A vertical structure micro LED device and a manufacturing method thereof

Abstract

This invention discloses a vertical structure Micro LED device and its manufacturing method. First, an aluminum metal layer and a passivation layer are deposited on the surface of the light-emitting epitaxial layer and the CMOS driving wafer, respectively, followed by atomic diffusion bonding under low temperature and low pressure in air. After removing the substrate, independent light-emitting mesa and anode are formed through two-step etching. Damage to the sidewalls is repaired, and a double passivation layer is deposited. Three layers of gradient ITO are deposited and etched to prepare a photonic crystal. Finally, a trench optical isolation layer is filled and imprinted to form a microlens array. This invention effectively solves the problems of bonding stress and oxidation. Through the synergistic effect of multi-dimensional optical structures, it significantly improves light extraction efficiency and beam directionality, eliminates pixel crosstalk, and is suitable for high-density micro-display manufacturing.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor wafer fabrication technology, specifically relating to a vertical structure Micro LED device and its manufacturing method. Background Technology

[0002] In recent years, Micro LED microdisplay arrays have been widely used in lighting and display fields due to their superior light-emitting performance, fast response time, low energy consumption, and long lifespan. Among them, the process of forming LED arrays by directly bonding LED epitaxial wafers to CMOS driving backplanes at the wafer level, removing the substrate, and photolithographically patterning can produce Micro LED microdisplay arrays with extremely high pixel density, while avoiding the delicate mass transfer process.

[0003] However, the vertical structure Micro LED fabrication method, which involves bonding first and then patterning, requires a high-performance wafer-level bonding process and is prone to generating brittle intermetallic compounds (IMCs), leading to increased interface resistance and decreased mechanical strength. In traditional eutectic bonding technology, the difference in the coefficients of thermal expansion between the Micro LED epitaxial wafer, the bonding metal layer, and the silicon-based CMOS driving circuit can easily generate significant interface stress, causing reliability issues in subsequent fabrication processes. Furthermore, the thick metal bonding layer can easily lead to severe heat dissipation problems during current conduction, resulting in wafer warping or even cracking.

[0004] Furthermore, during the miniaturization process, the sidewall effect becomes increasingly pronounced as the size of Micro LEDs decreases. When using inductively coupled plasma (ICP) dry etching for mesa isolation, high-energy ion bombardment generates amorphous layers and lattice defects on the GaN sidewalls, forming numerous nonradiative recombination centers. Without effective sidewall repair and passivation, this leads to a significant increase in leakage current and a sharp decline in luminous efficiency as the size decreases.

[0005] In terms of optical performance, due to the huge difference between the high refractive index of GaN material (n≈2.4) and the refractive index of air, most of the light generated inside the Micro LED is confined inside the device due to total internal reflection (TIR) ​​and cannot be emitted, resulting in low light extraction efficiency (LEE).

[0006] Therefore, there is an urgent need for a vertical structure Micro LED device and its manufacturing method that can achieve high-quality metal bonding at low temperature and low pressure, effectively repair sidewall damage, and significantly improve light extraction efficiency and directionality. Summary of the Invention

[0007] The first objective of this invention is to overcome the shortcomings of the prior art and provide a method for manufacturing a vertical structure Micro LED device, which can effectively reduce the thickness of wafer-level bonding metal, control the interlayer stress between GaN epitaxial wafer and silicon-based CMOS driving backplane, optimize the Micro LED structure, and improve the luminous performance of the device.

[0008] To achieve the above objectives, the technical solution adopted in this invention is a Micro LED microarray fabrication scheme that involves bonding followed by patterning, as detailed below:

[0009] A method for manufacturing a vertical structure Micro LED device includes the following steps:

[0010] S1. A growth substrate is provided, and an N-type semiconductor layer, a multiple quantum well active layer, and a P-type semiconductor layer are sequentially epitaxially grown on the surface of the growth substrate to form a light-emitting epitaxial layer; a first ITO layer, a first metal adhesion layer, a first metal functional layer, and a first surface passivation layer are sequentially deposited on the surface of the P-type semiconductor layer of the light-emitting epitaxial layer to obtain a first pre-bonding wafer.

[0011] S2. A silicon-based CMOS driver wafer is provided. A redistribution layer and metal pads are prepared on the surface of the silicon-based CMOS driver wafer. A second metal adhesion layer, a second metal functional layer and a second surface passivation layer are sequentially deposited on its surface to obtain a second pre-bonding wafer.

[0012] S3. The first pre-bonded wafer and the second pre-bonded wafer are subjected to low-temperature and low-pressure atomic diffusion bonding to obtain an atomically bonded wafer;

[0013] S4. Remove the growth substrate of the atomically bonded wafer to expose the N-type semiconductor layer of the light-emitting epitaxial layer, and obtain an epitaxial transfer wafer;

[0014] S5. Patterning the epitaxial transfer wafer: Perform a first etching, etching through the light-emitting epitaxial layer and stopping on the surface of the bonding metal layer to form a Micro LED mesa array; then perform a second etching in the trench region, etching through the bonding metal layer and stopping on the surface of the dielectric layer of the silicon-based CMOS driving wafer to form a micro-display array with independent anodes.

[0015] S6. Repair the sidewall damage of the micro display array, and deposit a sidewall passivation layer and an insulating protective layer sequentially on the sidewall and trench area of ​​the Micro LED mesa.

[0016] S7. Deposit a second ITO layer on the entire light-emitting surface of the epitaxial transfer wafer, and etch a photonic crystal structure on the surface of the second ITO layer.

[0017] S8. An optical isolation layer is filled in the trench area on the surface of the epitaxial transfer wafer, and a microlens array is formed in the mesa area of ​​the Micro LED using nanoimprint technology.

[0018] Furthermore, in steps S1 and S2, the materials of the first metal functional layer and the second metal functional layer are both aluminum metal layers, and the aluminum metal layer serves as both a light reflector and a bonding metal layer.

[0019] The materials of the first and second surface passivation layers are selected from one or more of Ti, Au, Ag, Pt, Pd, and Ru.

[0020] Furthermore, in step S3, the atomic diffusion bonding is carried out in an air environment, at low temperature and low pressure. By applying pressure, aluminum atoms diffuse through the surface passivation layer and recrystallize at the bonding interface to form Al-Al metal bonds. The low temperature is 150℃-400℃ and the low pressure is 0.5MPa-1.5MPa.

[0021] Furthermore, in step S5, the first etching is performed using ICP plasma etching, which utilizes a mixed gas of Cl2, BCl3 and Ar, and controls the etching to stop on the surface of the bonded metal layer by detecting changes in the characteristic spectral lines of Al or Ga.

[0022] The second etching process employs ICP-RIE etching, utilizing Cl2 and BC. l3 A mixture of Ar and CH4 gas is used to etch away the aluminum metal bonding layer in the trench region. The etching is stopped on the SiCN dielectric layer on the surface of the silicon-based CMOS driver wafer by detecting changes in the characteristic spectral lines of Al.

[0023] Further, in step S6, the sidewall damage repair and deposition process includes:

[0024] Wet etching of the Micro LED mesa sidewalls is performed using TMAH solution or hot phosphoric acid to selectively remove the amorphous layer and defect layer caused by dry etching.

[0025] An Al2O3 thin film was deposited as the sidewall passivation layer using atomic layer deposition (ALD) process;

[0026] A SiO2 thin film was deposited using a PECVD process as the insulating protective layer.

[0027] The sidewall passivation layer and the insulating protective layer form a double-layer passivation structure to enhance sidewall light reflection and provide electrical isolation.

[0028] Further, in step S7, the second ITO layer comprises, from bottom to top:

[0029] Bottom ITO layer: This is a highly doped ITO layer that forms an ohmic contact with the N-type semiconductor layer of the Micro LED;

[0030] The middle ITO layer is either a low sheet resistance, high carrier concentration ITO layer or a gallium-doped zinc oxide layer, serving as a current spreading layer.

[0031] Top ITO layer: This is an ITO layer with low defect density and high transmittance, serving as the substrate layer for fabricating photonic crystals.

[0032] Furthermore, the method for preparing the photonic crystal structure is as follows:

[0033] A two-dimensional triangular lattice hole array pattern is formed on the surface of the top ITO layer using photolithography.

[0034] The top ITO layer is etched to form air holes, which are either conical inclined holes or cylindrical vertical holes.

[0035] The period of the photonic crystal is in the range of 250nm-350nm, which matches the wavelength of the light emitted by the Micro LED.

[0036] Furthermore, in step S8, the optical isolation layer material is black polyimide, which fills the groove area between the Micro LED mesa and forms a bowl-shaped structure in the light-emitting mesa area after planarization treatment.

[0037] The formation process of the microlens array includes: spin-coating UV-curable adhesive, using a mold to imprint the curved lens shape on the corresponding position of the light-emitting platform, and demolding after curing; the microlens array is closely attached to the photonic crystal structure.

[0038] The second objective of this invention is to provide a vertical structure Micro LED device, which is manufactured using the above-described manufacturing method.

[0039] Furthermore, a quantum dot conversion layer is provided between the Micro LED light-emitting platform and the microlens array to achieve color conversion.

[0040] Compared with the prior art, the beneficial effects of the present invention are:

[0041] In the fabrication method of the Micro LED microdisplay array of the present invention, all process steps are compatible with existing CMOS processes, and the fabrication technology is mature and economically efficient. The first bonding wafer and the second bonding wafer are bonded by atomic diffusion, which avoids the formation of a brittle IMC layer in the bonding layer. The bonding temperature is low, the bonding strength is high, and the stability is good. The bonding metal layer of the atomic diffusion bonded sheet is relatively thin. From the GaN epitaxial layer to the bonding metal layer and then to the silicon-based CMOS wafer, the coefficient of thermal expansion of each layer gradually changes, which can effectively control the internal stress of the bonding structure and provide strong support for the subsequent patterning process. This composite bonding metal layer can realize ultra-low stress, all-metal high-reflectivity electrodes.

[0042] This invention integrates multiple optical enhancement methods. Among them, the aluminum mirror reflective layer can achieve a light reflectivity of over 95%, and the double-layer sidewall passivation layer enhances sidewall reflection by utilizing the difference in refractive index. Combined with the microlens array at the top and the optical isolation layer in the trench, it not only further focuses the outgoing light and improves the directionality of the light, but also completely eliminates light crosstalk between adjacent pixels, significantly improving the contrast and clarity of the micro-display array. The surface ITO photonic crystal layer effectively disrupts the total internal reflection condition of light inside GaN through the diffraction effect, coupling the confined waveguide mode into a vertical radiation mode, thereby improving the light extraction efficiency. Together, these methods improve the light extraction efficiency, enhance the directionality of the light, avoid light crosstalk, and greatly improve the luminous efficiency.

[0043] This invention addresses the challenge of simultaneously achieving low contact resistance and high transmittance with traditional single-layer ITO by designing a three-layer gradient ITO structure. The bottom layer, highly doped ITO, ensures a low-resistance ohmic contact with p-GaN, reducing the operating voltage. The middle layer, low-resistance ITO, enables uniform lateral current expansion, avoiding current congestion. The top layer, high-quality ITO, possesses extremely high transmittance and density, reducing light absorption and providing a superior substrate material for subsequent precision etching of the photonic crystal. These three layers work synergistically to maximize light output while ensuring excellent electrical performance. Attached Figure Description

[0044] Figure 1 This is a flowchart of the preparation method of the present invention.

[0045] Figure 2 This is a schematic diagram of the structure before atomic diffusion bonding in an embodiment of the present invention, wherein the upper part is the first pre-bonding wafer and the lower part is the second pre-bonding wafer.

[0046] Figure 3 This is a schematic diagram of the process structure for patterning and electrode fabrication of epitaxial transfer wafers in an embodiment of the present invention. It sequentially shows the etching steps for forming independent Micro LED mesa and anode, the deposition steps for sidewall passivation and insulating protective layers, and the three-layer ITO deposition and top photonic crystal etching steps.

[0047] Figure 4 This is a schematic diagram of the process structure for optical isolation and microlens fabrication in an embodiment of the present invention, showing the steps of filling the groove region with an optical isolation layer to form a bowl-shaped structure and forming a microlens array in the light-emitting mesa region using nanoimprint technology.

[0048] Figure 5 This is a schematic diagram of the second ITO layer of the present invention.

[0049] Figure 6 This is a schematic diagram of a photonic crystal structure.

[0050] The diagram is labeled as follows: 1. First pre-bonding wafer; 1-1. Growth substrate; 1-2. N-type semiconductor layer; 1-3. Multi-quantum well active layer; 1-4. P-type semiconductor layer; 1-5. First ITO layer; 1-6. First metal adhesion layer; 1-7. First metal functional layer; 1-8. First surface passivation layer; 2. Second pre-bonding wafer; 2-1. Silicon-based CMOS driver wafer; 2-2. Redistribution layer; 2-3. Metal pad; 2-4. Second metal adhesion layer; 2-5. Second metal functional layer; 2-6. Second surface passivation layer; 3. Bonding metal layer; 4. Micro LED light-emitting platform; 5. Trench; 6. Sidewall passivation layer; 7. Insulating protective layer; 8. Second ITO layer; 8-1. Bottom ITO layer; 8-2. Middle ITO layer; 8-3. Top ITO layer; 9. Photonic crystal structure; 10. Optical isolation layer; 11. Microlens array. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0052] The technical solution adopted in this invention is a Micro LED microarray fabrication method that involves bonding first and then patterning. Figure 1 This is a schematic flowchart of the fabrication method of Micro LED microarray in an embodiment of the present invention, including the following steps:

[0053] S1, a sapphire growth substrate 1-1 is provided, and an n-GaN layer (N-type semiconductor layer 1-2), a multiple quantum well active layer 1-3 (MQW), and a p-GaN layer (P-type semiconductor layer 1-4) are sequentially grown on the substrate surface using MOCVD process to form a GaN light-emitting epitaxial wafer. Then, a first ITO layer 1-5, a first metal adhesion layer 1-6, a first metal functional layer 1-7, and a first surface passivation layer 1-8 are sequentially deposited on the surface of the p-GaN layer to obtain a first pre-bonding wafer 1;

[0054] Figure 2 This illustrates the sequential deposition of the GaN epitaxial layer on the sapphire substrate in an embodiment of the present invention:

[0055] The first ITO layer 1-5 directly contacts the P-GaN layer to form an ohmic contact layer, and together with the first metal functional layer 1-7, constitutes the anode of the vertical structure Micro LED. The ITO transparent electrode serves as a light transmission and current spreading layer, realizing uniform longitudinal current flow and uniform lateral current distribution, and also acts as a stress buffer layer between the metal bonding layer and the Micro LED epitaxial layer.

[0056] The first ITO layer 1-5 was deposited using magnetron sputtering, with its thickness controlled between 20-80 nm to ensure good transmittance and lower contact resistance. The thickness of the first ITO layer 1-5 was co-designed with the thickness of the GaN epitaxial layer to achieve phase superposition between reflected and emitted light, enhancing the emitted light effect. Other transparent electrode materials that can be selected, such as IGZO and IGO, have higher carrier mobility and better etching controllability.

[0057] The first metal adhesion layer 1-6 is made of 5-20 nm Ti / TiW, which ensures strong adhesion between the first ITO layer 1-5 and the first metal functional layer 1-7 and acts as a diffusion barrier layer to prevent the diffusion of oxygen atoms from the first ITO layer 1-5 from causing oxidation of the first metal functional layer 1-7, thereby enhancing the stability of the reflection effect under thermal conditions.

[0058] The first metal functional layer 1-7 is made of aluminum metal. This functional layer can efficiently reflect the light emitted from the active area inward back to the Micro LED light-emitting surface. The aluminum metal reflector has a light reflectivity of up to 90%-92% in the visible light band, which can effectively improve the light extraction efficiency of the device. This functional layer can also serve as a metal bonding layer for the bonding structure. Through atomic diffusion and redistribution, a high-quality metal bonding structure can be achieved. The use of aluminum metal bonding layer can promote atomic diffusion under low temperature and low pressure conditions, forming a strong Al-Al metal bond with the lower bonding layer, forming a bonding interface with excellent mechanical strength, high thermal conductivity, and high electrical conductivity. This functional layer has strong plastic deformation capability. The yield strength and Young's modulus of the aluminum metal layer are much lower than those of GaN semiconductor material. It can effectively absorb and release thermal stress during the bonding process and subsequent light-emitting mesa processing, prevent interface stress caused by the difference in thermal expansion coefficients between the GaN epitaxial layer and the silicon-based driving backplane, and reduce the risk of bonding wafer warpage and breakage.

[0059] Aluminum layers 1-7 are deposited using magnetron sputtering to form the first functional metal layers. By controlling process parameters such as temperature, aluminum films with small grain size, high density, and low surface roughness (150-450 nm) are formed. If necessary, CMP (chemical vapor deposition) can be used to reduce wafer surface roughness, providing a good bonding structure surface for subsequent atomic diffusion bonding.

[0060] The first surface passivation layer 1-8 is made of titanium metal and is prepared with a thickness of 2-10 nm using magnetron sputtering. This passivation layer isolates the surface from air, effectively preventing oxidation of the first metal functional layers 1-7, and provides a diffusion channel for subsequent diffusion of aluminum atoms to the bonding interface. Alternatively, the surface passivation layer can be made of thin metal layers such as Au, Ag, Pt, Pd, or Ru, which can also achieve the functions of preventing oxidation and promoting diffusion.

[0061] S2. An RDL layer is fabricated on a silicon-based CMOS driver wafer 2-1. Metal pads are then fabricated within the RDL layer to form electrical connections. A dielectric material is deposited between the pads to planarize the wafer surface and reduce surface roughness. SiCN is the preferred dielectric layer, but other dielectric materials such as SiO2 and SiON can also be used. SiCN has a higher etch selectivity than metal bonding layers in subsequent etching processes, making it a superior etch stop layer in the etching of Micro LED mesa surfaces.

[0062] Figure 3 The image shows the sequential deposition of a second metal adhesion layer 2-4, a second metal functional layer 2-5, and a second surface passivation layer 2-6 on a silicon-based CMOS driver wafer 2-1.

[0063] The second metal adhesion layer 2-4 is preferably a titanium metal thin layer. Similar to the first metal adhesion layer 1-6, a titanium metal thin layer with a thickness of 2-10 nm is prepared by magnetron sputtering to improve the adhesion between the RDL layer and the second metal functional layer 2-5.

[0064] The second metal functional layer 2-5 is the same as the first metal functional layer 1-7, using an aluminum metal layer with a thickness between 200-600nm to compensate for the insufficient thickness of the first metal functional layer 1-7. It has stronger fluidity during the bonding process and can better fill the voids at the bonding interface under pressure, thereby improving the wafer bonding quality.

[0065] The material, thickness, and bonding process of the second surface passivation layer 2-6 are the same as those of the first surface passivation layer 1-8.

[0066] S3, the first pre-bonded wafer 1 and the second pre-bonded wafer 2 are subjected to low-temperature atomic diffusion bonding to obtain an atomic diffusion bonded wafer;

[0067] In an air environment, two wafers are pre-bonded without alignment. The surfaces of the pre-bonded wafers are heated to 250 °C and subjected to a pressure of 0.5-1.5 MPa to perform atomic diffusion bonding, followed by low-temperature annealing at 250 °C to form stable Al-Al metallic bonds. In this embodiment, the bonding pressure is 1 MPa to achieve low temperature and low pressure.

[0068] Both metal bonding layers have a passivation layer deposited on their surfaces, effectively preventing oxidation of the aluminum layer in air. This allows for high-quality bonding of the two wafer processes in air, significantly reducing production costs and equipment complexity in industrial applications. Simultaneously, the passivation layer provides diffusion channels for aluminum atoms during atomic diffusion bonding, enabling them to diffuse through the passivation layer under low temperature and pressure conditions and recrystallize at the wafer bonding interface. This avoids the need for high-temperature and high-pressure bonding conditions required in traditional hot-press bonding to break down the aluminum oxide layer and promote aluminum atom diffusion.

[0069] During atomic diffusion bonding, aluminum is used as the metal bonding layer material in both wafers. It does not form a solid solution with the surface passivation layer metal, thus avoiding the formation of metal bond compounds (IMC layers) at the bonding interface. This prevents the local temperature of the bonding metal layer 3 from becoming too high, reduces the resistance and interface brittleness of the bonding structure, and greatly enhances the reliability of the bonding structure.

[0070] The bonding process is carried out at temperatures between 150℃ and 400℃, below the melting point of aluminum, to avoid the formation of molten aluminum that could damage the surface passivation structure. The bonding pressure is between 0.5 and 1.5 MPa, applying pressure to ensure full contact between the bonding surfaces of the two wafers. The bonding time is 1-3 hours to promote full contact at the bonding interface. A post-bonding annealing process is essential; annealing at 150℃-400℃ for 2-4 hours promotes sufficient atomic diffusion, resulting in a high-quality bonded structure.

[0071] Ideally, after the bonding metal layer 3 is deposited on both wafers, the CMP process is used to reduce the surface roughness of the wafers and reduce the defect density of the wafer-level bonding structure.

[0072] The optimized bonding process employs surface activation bonding to achieve bonding between two wafers, reducing particulate contamination in a high vacuum environment and mitigating voids at the bonding interface.

[0073] S4, laser peeling is used to remove the sapphire substrate of the atomically bonded wafer to obtain an epitaxial transfer wafer;

[0074] Continue reading Figures 4-5 S5, perform the first photolithography and etching on the epitaxial transfer wafer to obtain a MicroLED mesa array, and perform the second photolithography and etching between the mesa arrays to obtain a microdisplay array with independent anodes;

[0075] A SiO2 layer with a thickness of 400-600 nm is deposited on the epitaxial transfer wafer as a hard mask layer for the subsequent two etching steps. Photolithography is performed on the hard mask surface, followed by spin-coating of photoresist, pre-baking, exposure, development, and post-baking to form a Micro LED mesa array pattern on the epitaxial transfer wafer surface. Then, the first etching is performed using ICP plasma etching, with Cl2 as the main etching gas, BCl3 as the sidewall passivation gas, and Ar as the auxiliary gas. A small amount of N2 is added to improve sidewall perpendicularity. During the etching process, the intensity changes of Al or Ga characteristic spectral lines are monitored to control the first etching to stop on the surface of the bonding metal layer 3.

[0076] A second etching process is then performed using ICP-RIE to etch the metal bonding layer. Cl2 is used as the primary etching gas, BCl3 as the sidewall passivation gas, and Ar as the auxiliary gas. A small amount of CH4 is added to enhance the selectivity for the etching stop layer SiCN. The RF bias power is 100W. The Cl-based gas has a high selectivity for both the Al-bonded metal layer 3 and the SiCN dielectric layer. By detecting the changes in the characteristic spectral lines of Al during the etching process, the etching can be precisely stopped at the SiCN dielectric layer, thereby protecting the underlying redistribution layer.

[0077] The advantage of this invention is that by reducing the distance 5 between the grooves 5 of the LED mesa, the number of LED light-emitting mesa per unit area can be greatly increased. Combined with the subsequent control of light crosstalk between each LED mesa, the spacing between the mesa can be further reduced while ensuring luminous efficiency, which significantly improves the PPI of the Micro LED chip and achieves high-density array distribution.

[0078] S6, selectively repair the sidewall damage of the microdisplay array by sequentially depositing a sidewall passivation layer 6 and an insulating protective layer 7 in the trench 5 region.

[0079] After removing the hard mask using HF solution, TMAH solution or hot phosphoric acid is used to selectively remove the amorphous and defective layers damaged during the dry etching process on the GaN sidewalls. The etching rate of this solution for the damaged sidewall sites is much higher than that for intact GaN crystals. During the isotropic etching process, the sidewalls of the LED mesa are gradually smoothed, and the damaged sidewall surface layers are removed, thereby reducing the sidewall surface state density and reducing nonradiative recombination.

[0080] The epitaxial transfer wafer undergoes standard cleaning. A dense insulating passivation layer is deposited across the entire wafer surface using the ALD method. This passivation layer, made of Al2O3 film with excellent passivation and anti-permeation properties, has a thickness of 10-30 nm. The insulating passivation layer exhibits excellent conformability, completely covering the entire LED sidewall and trench area, forming good electrical isolation. This passivation layer directly improves internal quantum efficiency and reduces non-radiative recombination, thereby significantly increasing luminous efficiency. Rapid thermal annealing at 200-400℃ for 1-5 minutes in an N2 atmosphere optimizes sidewall defects caused during the ALD process and improves the Al2O3 / GaN interface quality, further enhancing the passivation effect.

[0081] The second step involves using PECVD to deposit a 200 nm thick SiO2 protective layer on the entire wafer surface. Due to the difference in refractive index between the SiO2 protective layer and the Al2O3 passivation layer, the two work together to achieve better sidewall light reflection, reduce the internal loss of LED light emission, and significantly improve light extraction efficiency. At the same time, this protective layer can provide better mechanical support for the Al2O3 passivation layer.

[0082] Photolithography and etching expose the light-emitting area of ​​the Micro LED mesa. The above steps form a good double-layer passivation structure at the sidewall position. The goal of this passivation structure is to enhance the reflection of the beam on the sidewall and significantly improve the LED light extraction efficiency.

[0083] S7, deposit a second ITO layer 8 on the entire surface of the epitaxial transfer wafer. The ITO layer includes a three-layer structure, which serves as a bottom low-resistivity ohmic contact layer, a middle current diffusion layer, and a top ITO photonic crystal layer. Etch the surface of the top ITO layer 8-3 to prepare a photonic crystal structure 9.

[0084] The first step involves depositing a 10-30 nm thick bottom ITO layer 8-1 using reactive magnetron sputtering at a power of 100 W. The oxygen partial pressure is 0-1% O2 / Ar mixed gas, and the deposition rate is 0.3-0.5 nm / s, forming a highly doped ITO layer (In2O3:SnO2=90:10 wt%). This layer has a high carrier concentration and sacrificial transmittance. After annealing at 400℃ for 5 min, it can adhere well to the n-GaN surface, forming a low-resistivity ohmic contact layer.

[0085] The second step involves depositing a 100-150 nm thick central ITO layer 8-2 using optimized magnetron sputtering at 150 W power. The oxygen partial pressure is 0.5-1.5% O2 / Ar mixed gas, and the deposition rate is 0.4-0.6 nm / s, forming an optimized ITO layer (In2O3:SnO2=93:7 wt%) with a high carrier concentration (1.5 x 1021 cm⁻¹). -3With its low sheet resistance (8-12Ω / □) and high transmittance (greater than 95%), it can achieve good lateral current expansion and form a central current expansion layer.

[0086] Ideally, the central current spreading layer can be a deposited gallium-doped zinc oxide layer, which has better electrical stability and carrier mobility.

[0087] The third step involves depositing a 150-200 nm thick top ITO layer 8-3 using low-temperature, high-quality sputtering at 120 W power. The oxygen partial pressure is 2-4% O2 / Ar mixed gas, and the deposition rate is 0.2-0.4 nm / s, forming a high-quality ITO layer (In2O3:SnO2=95:5 wt%). This layer has extremely low defect density, high transmittance (>98%), and low carrier concentration, reducing carrier loss during the lateral current spread process. It can serve as a substrate layer for photonic crystal etching.

[0088] A two-dimensional triangular lattice hole array pattern is formed on the surface of the top ITO layer using photolithography (e.g., Figure 6 As shown, a photonic crystal structure 9 is formed with a period of 280 nm, matching the wavelength of blue light in the GaN layer. The selectable value is 250 nm-350 nm. With a duty cycle of 0.4 and an air hole depth of 150 nm, a significant photonic crystal effect is achieved. This structure is primarily formed in the top ITO layer 8-3. Conical tilted holes are preferred, with a sidewall tilt angle of 88°, within the range of 85°-90°. Cylindrical vertical holes are also an option. This structure couples the transversely diffracted light of the target wavelength to the vertical direction, greatly enhancing the light output. Together with the lower ITO layer, it forms a photoelectric co-design functional unit, working synergistically with the bonding layer mirror and the sidewall passivation layer 6 to significantly improve the light extraction efficiency of the Micro LED mesa.

[0089] S8, an optical isolation layer 10 is filled in the trench 5 region on the surface of the epitaxial transfer wafer. The optical isolation layer 10 forms a bowl-shaped structure in the light-emitting mesa region. UV-curable adhesive is spin-coated on the entire surface, and the layer is cured after being imprinted with a mold, forming a microlens array 11 in the entire light-emitting mesa region of the wafer.

[0090] Photoresist is spin-coated onto the entire epitaxial transfer wafer. During exposure and development, only the photoresist in the LED mesa area is retained, and post-baking hardens the photoresist. Black polyimide is then spin-coated, pre-baked, and chemically mechanically polished to remove the thicker polyimide layer, exposing the photoresist at the LED mesa location. The process is then stopped, and the photoresist is removed to expose the light-emitting mesa. The black polyimide completely fills the trench 5 area, effectively isolating adjacent pixels, eliminating light crosstalk, and providing excellent insulation to effectively prevent leakage. After subsequent planarization, a bowl-shaped structure is formed in the LED mesa area, providing a good carrier for subsequent lens substrate material filling. By controlling the sidewall tilt angle of the polyimide, the directionality of LED light emission is improved.

[0091] Next, a layer of NOA 63 UV-curable adhesive is spin-coated onto the entire surface of the epitaxial transfer wafer. After aligning the customized nanoimprint mold, it is placed on the surface of the epitaxial transfer wafer. The LED light-emitting platform is aligned with the aperture of the imprint mold. Pressure is applied to make the mold adhere to the wafer. The surface tension of the UV-curable adhesive is used to form a curved lens morphology. After curing, the mold is removed, forming a microlens array 11 on the entire wafer surface.

[0092] The microlens array 11 is closely attached to the lower photonic crystal layer, forming a refractive index gradient distribution of GaN, ITO, microlens, and air, thereby improving light extraction efficiency. At the same time, the microlens can significantly improve the directionality of light emission from each Micro LED mesa, and largely avoid light crosstalk between Micro LEDs.

[0093] In addition, before fabricating the microlens array 11, a quantum dot conversion layer can be spin-coated onto the surface of the Micro LED light-emitting platform 4 using quantum dot inkjet printing, thereby forming RGB three-color light emission.

Claims

1. A method for manufacturing a vertical structure Micro LED device, characterized in that, Includes the following steps: S1. A growth substrate (1-1) is provided, and an N-type semiconductor layer (1-2), a multi-quantum-well active layer (1-3), and a P-type semiconductor layer (1-4) are epitaxially grown sequentially on the surface of the growth substrate (1-1) to form a light-emitting epitaxial layer; A first ITO layer (1-5), a first metal adhesion layer (1-6), a first metal functional layer (1-7), and a first surface passivation layer (1-8) are sequentially deposited on the surface of the P-type semiconductor layer (1-4) of the light-emitting epitaxial layer to obtain a first pre-bonding wafer (1); S2. A silicon-based CMOS driver wafer (2-1) is provided. A redistribution layer (2-2) and a metal pad (2-3) are prepared on the surface of the silicon-based CMOS driver wafer (2-1). A second metal adhesion layer (2-4), a second metal functional layer (2-5), and a second surface passivation layer (2-6) are sequentially deposited on its surface to obtain a second pre-bonding wafer (2). S3. The first pre-bonded wafer (1) and the second pre-bonded wafer (2) are subjected to low-temperature and low-pressure atomic diffusion bonding to obtain an atomically bonded wafer; S4. Remove the growth substrate (1-1) of the atomically bonded wafer to expose the N-type semiconductor layer (1-2) of the light-emitting epitaxial layer, and obtain an epitaxial transfer wafer; S5. Patterning process of the epitaxial transfer wafer: First etching is performed, etching through the light-emitting epitaxial layer and stopping on the surface of the bonding metal layer (3) to form a Micro LED mesa array; Subsequently, a second etching is performed in the trench (5) region, which penetrates the bonding metal layer (3) and stops on the dielectric layer surface of the silicon-based CMOS driver wafer (2-1) to form a micro-display array with independent anodes; S6. Repair the sidewall damage of the micro display array, and deposit a sidewall passivation layer (6) and an insulating protective layer (7) sequentially on the sidewall and groove (5) area of ​​the Micro LED mesa; S7. Deposit a second ITO layer (8) on the entire light-emitting surface of the epitaxial transfer wafer, and etch a photonic crystal structure (9) on the surface of the second ITO layer (8). S8. An optical isolation layer (10) is filled in the trench (5) region on the surface of the epitaxial transfer wafer, and a microlens array (11) is formed in the Micro LED mesa region using nanoimprint technology.

2. The manufacturing method according to claim 1, characterized in that, In steps S1 and S2, the first metal functional layer (1-7) and the second metal functional layer (2-5) are both made of aluminum metal layer, which also serves as a light reflector and a bonding metal layer (3). The materials of the first surface passivation layer (1-8) and the second surface passivation layer (2-6) are selected from one or more of Ti, Au, Ag, Pt, Pd and Ru.

3. The manufacturing method according to claim 1, characterized in that, In step S3, the atomic diffusion bonding is carried out in an air environment, at low temperature and low pressure. By applying pressure, aluminum atoms diffuse through the surface passivation layer and recrystallize at the bonding interface to form Al-Al metal bonds. The low temperature is 150℃-400℃ and the low pressure is 0.5MPa-1.5MPa.

4. The manufacturing method according to claim 1, characterized in that, In step S5, the first etching is performed by ICP plasma etching, using a mixture of Cl2, BCl3 and Ar gas, and the etching is stopped on the surface of the bonded metal layer (3) by detecting changes in the characteristic spectral lines of Al or Ga. The second etching is performed using ICP-RIE etching, which uses a mixture of Cl2, BCl3, Ar and CH4 gases to etch and remove the aluminum metal bonding layer in the trench (5) region. The etching is stopped on the SiCN dielectric layer on the surface of the silicon-based CMOS driver wafer (2-1) by detecting changes in Al characteristic spectral lines.

5. The manufacturing method according to claim 1, characterized in that, In step S6, the sidewall damage repair and deposition process includes: Wet etching of the Micro LED mesa sidewalls is performed using TMAH solution or hot phosphoric acid to selectively remove the amorphous layer and defect layer caused by dry etching. An Al2O3 thin film was deposited as the sidewall passivation layer using atomic layer deposition (6); A SiO2 thin film was deposited using a PECVD process as the insulating protective layer (7); The sidewall passivation layer (6) and the insulating protective layer (7) form a double-layer passivation structure to enhance sidewall light reflection and provide electrical isolation.

6. The manufacturing method according to claim 1, characterized in that, In step S7, the second ITO layer (8) comprises, from bottom to top: Bottom ITO layer (8-1): This is a highly doped ITO layer that forms an ohmic contact with the N-type semiconductor layer (1-2) of the Micro LED; The middle ITO layer (8-2) is an ITO layer with low sheet resistance and high carrier concentration or a gallium-doped zinc oxide layer, which serves as a current spreading layer. Top ITO layer (8-3): This is an ITO layer with low defect density and high transmittance, serving as the substrate layer for preparing photonic crystals.

7. The manufacturing method according to claim 1, characterized in that, The method for preparing the photonic crystal structure (9) is as follows: A two-dimensional triangular lattice hole array pattern is formed on the surface of the top ITO layer (8-3) using photolithography. The top ITO layer (8-3) is etched to form air holes, which are either conical inclined holes or cylindrical vertical holes. The period of the photonic crystal is in the range of 250nm-350nm, which matches the wavelength of the light emitted by the Micro LED.

8. The manufacturing method according to claim 1, characterized in that, In step S8, the optical isolation layer material is black polyimide, which fills the groove area between the Micro LED mesa and forms a bowl-shaped structure in the light-emitting mesa area after planarization treatment. The formation process of the microlens array includes: spin-coating UV-curable adhesive, using a mold to imprint the curved lens shape on the corresponding position of the light-emitting platform, and demolding after curing; The microlens array is closely fitted to the photonic crystal structure.

9. A vertical structure Micro LED device, characterized in that, It is prepared by the manufacturing method described in any one of claims 1-8.

10. The vertical structure Micro LED device according to claim 9, characterized in that, A quantum dot conversion layer is also provided between the Micro LED light-emitting platform and the microlens array to achieve color conversion.

Images