System and method for fabricating a chip of a continuous deposition of superlattice and quantum well array

Abstract

This invention provides a fabrication system and method for continuous deposition of superlattice and quantum well array chips, relating to the field of chip fabrication. It includes multiple independent vacuum chambers arranged in series, connected to each other via vacuum channels with valves, and equipped with a substrate transfer mechanism. The multiple independent vacuum chambers, in the process sequence, include at least: a pre-vacuum chamber, a preheating and plasma cleaning chamber, a two-dimensional layer deposition chamber, a superlattice layer deposition chamber, a lower contact layer deposition chamber, a lower implantation layer deposition chamber, a light-emitting quantum well layer deposition chamber, an upper implantation layer deposition chamber, an upper contact layer deposition chamber, an impurity activation chamber, and a cooling chamber. By employing a streamlined fabrication system with multiple chambers in series, each thin film is deposited in an independent chamber, fundamentally avoiding cross-contamination of different target materials. Simultaneously, the multi-chamber continuous pipeline operation enables continuous substrate transfer fabrication, significantly reducing the process time per batch and adapting to industrial mass production requirements.

Description

Technical Field

[0001] This invention relates to the field of chip fabrication, and more particularly to a fabrication system and method for continuous deposition superlattice and quantum well array chips. Background Technology

[0002] Currently, the mainstream preparation technologies for superlattice and quantum well structure thin films in the semiconductor field are metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). Although both have excellent film quality, they have drawbacks such as expensive equipment, high process temperature (>1000℃), only suitable for small-sized single crystal substrates, high toxicity of raw materials, and complex control procedures, which make it impossible to achieve large-area, low-cost mass production.

[0003] Currently, MOCVD, MBE, and magnetron sputtering technologies all employ a single-cavity deposition mode to fabricate superlattice structures. Taking magnetron sputtering as an example, typically 2-3 targets are installed in a single cavity, along with corresponding RF, DC, or pulsed power supplies. The process for fabricating multilayer film devices is as follows: the substrate and the targets required for each film layer are placed in the same cavity. After vacuuming and heating the substrate, a process atmosphere is introduced and plasma is excited. The first target is bombarded to complete the deposition of the first semiconductor layer, and then the second target is bombarded to complete the deposition of the second semiconductor layer. The above operations are repeated, and patterning with a mask is used to complete the fabrication of a multilayer thin film structure for a semiconductor array chip.

[0004] However, in actual use, the above structure can cause the deposition of multiple thin films of different materials in the same cavity. The material deposited in the previous layer will be adsorbed on the cavity wall, baffle and other cavity structures, causing atomic cross-contamination of the subsequent film layers, which will affect the device performance, resulting in low device yield and high manufacturing cost. Furthermore, the sequential deposition of all film layers in the same cavity is time-consuming for a single batch and has low chip yield per unit time, which cannot meet the needs of industrial mass production. Finally, due to the limitations of cavity structure and film uniformity, the substrate must be placed on non-planar brackets such as butterfly or spherical shapes to alleviate the problem of uneven film thickness. The process is complex and difficult to adapt to the uniform film deposition requirements of large-area substrates.

[0005] Therefore, it is necessary to provide a new fabrication system and method for continuously deposited superlattices and quantum well array chips to solve the above-mentioned technical problems. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a fabrication system and method for continuously deposited superlattices and quantum well array chips.

[0007] The present invention provides a fabrication system for continuous deposition of superlattice and quantum well array chips, comprising: multiple independent vacuum cavities arranged in series, the cavities being connected to each other through vacuum channels with valves, and each cavity being provided with a substrate transfer mechanism; The plurality of independent vacuum chambers, in the order of process, include at least: a pre-vacuum chamber, a preheating and plasma cleaning chamber, a two-dimensional layer deposition chamber, a superlattice layer deposition chamber, a lower contact layer deposition chamber, a lower injection layer deposition chamber, a light-emitting quantum well layer deposition chamber, an upper injection layer deposition chamber, an upper contact layer deposition chamber, an impurity activation chamber, and a cooling chamber. Each deposition chamber is provided with at least one target chamber, and each target chamber is provided with a rectangular sputtering target. The sputtering target is equipped with any one of pulse, radio frequency or DC power supply. A substrate holder that can reciprocate left and right along the target arrangement direction is provided in the chamber.

[0008] Furthermore, a deposition carrier blocking layer cavity is provided between the deposition injection layer cavity and the deposition luminescent quantum well layer cavity.

[0009] Furthermore, the two-dimensional deposition layer cavity, the lower contact layer cavity, the lower injection layer cavity, the carrier blocking layer cavity, the upper injection layer cavity, and the upper contact layer cavity are each equipped with four target chambers, and each target chamber is equipped with four rectangular sputtering targets. The superlattice deposition layer cavity and the luminescent quantum well deposition layer cavity are equipped with three target chambers, and each target chamber is equipped with four rectangular sputtering targets, and a pulsed sputtering power supply is provided.

[0010] Another aspect of the present invention provides a method for fabricating a continuous deposition superlattice and quantum well array chip, the method comprising at least the following steps: S1. Substrate pretreatment: The substrate is sent into the pre-vacuum chamber to complete the pre-vacuuming, preheated to the substrate temperature T1 to remove surface impurities, and then sent into the preheating and plasma cleaning chamber, heated to the substrate temperature T2, and hydrogen gas is introduced to excite plasma to complete the substrate surface bombardment cleaning. S2, Two-dimensional material preparation: The cleaned substrate is sent into the two-dimensional layer deposition chamber under vacuum, the substrate temperature is controlled at T3, the process gas is introduced, and the target power supply is turned on to deposit graphene or hexagonal boron nitride two-dimensional layers. S3. Superlattice fabrication: The substrate is sent into the superlattice layer deposition cavity under vacuum environment, the substrate temperature is controlled at T4, and the sputtering power supplies of different targets are alternately turned on and n cycles are cycled to deposit a multilayer superlattice structure. The multilayer superlattice structure is any one of AlN / GaN superlattice, InGaN / GaN superlattice or AlGaN / GaN superlattice. S4. Lower contact layer preparation: The substrate is sent into the lower contact layer deposition chamber under vacuum, the substrate temperature is controlled at T5, argon and nitrogen are introduced, and the target power supply is turned on to deposit the N-type highly doped semiconductor lower contact layer. S5. Preparation of the lower implantation layer: The substrate is sent into the lower implantation layer deposition chamber under vacuum, the substrate temperature is controlled at T6, argon and nitrogen are introduced, and the target power supply is turned on to deposit the N-type low-doped semiconductor lower implantation layer. S6. Fabrication of the light-emitting layer and quantum well: The substrate is sent into the light-emitting quantum well layer deposition chamber under vacuum. The substrate temperature is controlled at T7. The sputtering power supplies of different targets are alternately turned on and m cycles are performed to deposit the InGaN / GaN multi-quantum-well light-emitting layer structure. S7. Preparation of upper implantation layer and upper contact layer: The substrate is sequentially fed into the upper implantation layer deposition chamber and the upper contact layer deposition chamber under vacuum. The substrate temperature is controlled at T8 and T9 respectively, and the P-type low-doped semiconductor upper implantation layer and the P-type high-doped semiconductor upper contact layer are deposited sequentially. S8. Activation and Cooling Discharge: The substrate is fed into the impurity activation chamber under vacuum and heated to the activation temperature T. jf The substrate is then kept at a constant temperature to activate the doped impurities, and then sent into a substrate cooling chamber to be cooled to room temperature in a controlled manner to complete the fabrication of the array chip. In all thin film deposition steps, the substrate moves back and forth with the support to achieve a uniform distribution of thin film thickness over a large area.

[0011] A further method involves adding a carrier blocking layer preparation step between steps S5 and S6. The carrier blocking layer preparation step is as follows: The substrate is fed into the carrier barrier layer deposition cavity, argon and nitrogen are introduced, the substrate temperature is controlled at T6-1, the target sputtering power supply is turned on to deposit the carrier barrier layer, and the substrate is allowed to move back and forth with the support to achieve a large area of ​​uniform film thickness distribution.

[0012] In a further method, the multi-quantum well structure in S6 has an InGaN material for the well layer, the emission wavelength is controlled by adjusting the In content, and the barrier layer is made of GaN material, with a bandgap wider than that of the well layer.

[0013] In a further method, the upper injection layer in S7 adopts a P-GaN / InGaN superlattice structure, which utilizes the polarization effect and band bending of the heterojunction interface to reduce the Mg activation energy and increase the hole concentration.

[0014] In a further method, the N-type dopant is either silicon or germanium, and the P-type dopant is either magnesium or zinc.

[0015] Compared with related technologies, the fabrication system and method for continuous deposition superlattice and quantum well array chips provided by this invention have the following advantages: 1. This invention employs a multi-cavity series-connected streamlined fabrication system, where each thin film is deposited in an independent cavity, fundamentally avoiding cross-contamination of different target materials and significantly improving device yield; at the same time, the multi-cavity continuous pipeline operation enables continuous substrate transfer fabrication, significantly shortening the process time per batch and significantly increasing chip yield per unit time, thus meeting the needs of industrial mass production.

[0016] 2. Based on the principle of pulsed magnetron sputtering, this invention can complete the epitaxial growth of multilayer semiconductor thin films in the low-temperature range without the need for high-temperature processes above 1000°C. It is compatible with low-melting-point amorphous substrates such as glass, ceramics, metals, and flexible materials, breaking through the limitation of traditional equipment that can only use small-sized single-crystal substrates. It can realize the mass production of large-area substrates and expand the application scenarios of the device.

[0017] 3. This invention directly controls the composition of each semiconductor layer by corresponding target material composition in the deposition chamber, eliminating the need for a real-time precise control system for multi-component gas flow and partial pressure required for MOCVD / MBE. This greatly simplifies the equipment structure and control program, and significantly reduces equipment investment and preparation costs.

[0018] 4. The multi-cavity system of the present invention integrates a deposition cavity, an impurity activation cavity, and a cooling cavity. After the thin film deposition is completed, the substrate can be directly transferred to the activation cavity to complete the impurity activation in a completely sealed environment with minimal vacuum disruption. There is no need to remove the substrate and expose it to the atmosphere, thus avoiding the impact of atmospheric pollution on device performance from the source. At the same time, it eliminates the need for multiple heating and cooling processes, reducing process energy consumption.

[0019] 5. This invention employs a low-temperature pulsed magnetron sputtering deposition process, which significantly reduces the substrate processing temperature, effectively suppresses atomic interdiffusion between adjacent thin film layers, maintains the designed clear interlayer interface structure, ensures the optoelectronic properties of the device, and further improves the device yield and performance stability.

[0020] 6. This invention configures multiple sets of rectangular targets in each deposition chamber, and is equipped with a substrate support that can reciprocate. During the deposition process, the distance, frequency and speed of the substrate's left and right reciprocating motion can be controlled, which greatly reduces the in-plane deviation of film thickness and composition. Without the need for special support structures such as butterfly or spherical shapes, film deposition with highly uniform thickness and composition can be achieved on large-area substrates, simplifying the process flow. Attached Figure Description

[0021] Figure 1 A schematic diagram of the cross-section of a light-emitting device array chip fabricated on a substrate provided by the present invention; Figure 2 A schematic diagram of the block structure of the multi-cavity fabrication system for the array chip thin film structure of superlattice and quantum well provided by the present invention; Figure 3This is a schematic diagram of the thin-film structure array chip of the superlattice light-emitting device provided by the present invention. Figure 4 for Figure 2 The diagram shows the structure of cavity 1 in the preparation system. Figure 5 for Figure 2 The diagram shows the structure of cavity 2 in the preparation system. Figure 6 for Figure 2 The diagram shows the structure of cavities 3, 5, 6, 8 and 9 in the preparation system shown. Figure 7 for Figure 2 A schematic diagram of the target spacing within the deposition chamber of the preparation system shown; Figure 8 for Figure 2 The diagram shows a schematic of the superlattice cavity deposited in the fabrication system. Figure 9 A schematic diagram of the thin film structure of the light-emitting device array chip with multiple superlattice layers and multiple quantum well layers provided by the present invention; Figure 10 for Figure 2 The diagram shows a schematic of the structure of the cavity for depositing the light-emitting quantum well layer in the fabrication system. Figure 11 for Figure 2 The diagram shows the structure of cavity 10 in the preparation system. Figure 12 for Figure 2 The diagram shows the structure of cavity 11 in the preparation system. Figure 13 for Figure 2 The thickness variations as a function of distance are shown in the following diagrams in the fabrication system: T1, T2, T3, T4 when only a single target is deposited in the deposition chamber, and T4 when multiple targets are deposited simultaneously and the substrate is moved back and forth. T A structural diagram. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Please refer to the following: Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 ,in, Figure 1 A schematic diagram of a cross-sectional view of a light-emitting device array chip fabricated on a substrate provided by the present invention; Figure 2 A schematic diagram of the block structure of the multi-cavity fabrication system for the array chip thin film structure of superlattice and quantum well provided by the present invention; Figure 3 This is a schematic diagram of the thin-film structure array chip of the superlattice light-emitting device provided by the present invention. Figure 4 for Figure 2 The diagram shows the structure of cavity 1 in the preparation system. Figure 5 for Figure 2 The diagram shows the structure of cavity 2 in the preparation system. Figure 6 for Figure 2 The diagram shows the structure of cavities 3, 5, 6, 8 and 9 in the preparation system shown. Figure 7 for Figure 2 A schematic diagram of the target spacing within the deposition chamber of the preparation system shown; Figure 8 for Figure 2 The diagram shows a schematic of the superlattice cavity deposited in the fabrication system. Figure 9 A schematic diagram of the thin film structure of the light-emitting device array chip with multiple superlattice layers and multiple quantum well layers provided by the present invention; Figure 10 for Figure 2 The diagram shows a schematic of the structure of the cavity for depositing the light-emitting quantum well layer in the fabrication system. Figure 11 for Figure 2 The diagram shows the structure of cavity 10 in the preparation system. Figure 12 for Figure 2 The diagram shows the structure of cavity 11 in the preparation system. Figure 13 for Figure 2 The thickness variations as a function of distance are shown in the following diagrams in the fabrication system: T1, T2, T3, T4 when only a single target is deposited in the deposition chamber, and T4 when multiple targets are deposited simultaneously and the substrate is moved back and forth. T A structural diagram.

[0024] In the various embodiments of the present invention, although the following embodiments prepare one-dimensional or two-dimensional light-emitting device array chips, in addition to the light-emitting devices mentioned above, the multi-cavity array chip fabrication system of the present invention can be used to prepare array chips of other microelectronic and optoelectronic thin film devices by flowing deposition, including but not limited to chips of LED lamps, photovoltaic devices, display devices and sensors.

[0025] This embodiment describes a fabrication system for continuous deposition of superlattices and quantum well array chips. The core design is a streamlined vacuum continuous deposition structure with multiple cascaded chambers, such as... Figure 1 , Figure 2As shown, the system includes multiple independent vacuum chambers arranged in series, which are connected to each other through vacuum channels with isolation valves. It is equipped with a substrate transfer mechanism, which enables the substrate to flow continuously in the vacuum environment between the chambers. Each thin film is deposited in an independent chamber, which avoids cross-contamination of different target materials from the source, and realizes continuous substrate preparation, which greatly improves mass production efficiency.

[0026] Multiple independent vacuum chambers, in the order of process, include at least: a pre-vacuum chamber, a preheating and plasma cleaning chamber, a two-dimensional layer deposition chamber, a superlattice layer deposition chamber, a lower contact layer deposition chamber, a lower injection layer deposition chamber, a light-emitting quantum well layer deposition chamber, an upper injection layer deposition chamber, an upper contact layer deposition chamber, an impurity activation chamber, and a cooling chamber.

[0027] Furthermore, each deposition chamber is equipped with at least one target chamber, and each target chamber contains a rectangular sputtering target. The sputtering target is equipped with any one of pulse, radio frequency, or DC power supply. A substrate holder that can reciprocate left and right along the target arrangement direction is set in the chamber. In this embodiment, the two-dimensional layer deposition chamber, the lower contact layer deposition chamber, the lower injection layer deposition chamber, the upper injection layer deposition chamber, and the upper contact layer deposition chamber are each equipped with four target chambers, and each target chamber contains four rectangular sputtering targets. The superlattice layer deposition chamber and the luminescent quantum well layer deposition chamber are equipped with three target chambers, and each target chamber contains four rectangular sputtering targets. The sputtering power supply for all sputtering targets is a pulsed power supply, based on the principle of pulsed magnetron sputtering, which is suitable for low-melting-point amorphous substrates such as glass, breaking through the substrate limitations of traditional high-temperature processes.

[0028] Furthermore, each cavity is equipped with at least one mechanical vacuum pump and molecular pump, which can extract gas molecules from the cavity or gas molecules introduced from the inlet and maintain the gas pressure inside the cavity.

[0029] This embodiment achieves highly uniform film deposition on large-area substrates through multi-target combination and substrate reciprocating motion. Specifically, each deposition chamber is equipped with four rectangular sputtering targets, each with a width of 120 mm and a spacing D of 120 mm between adjacent targets. During deposition, the substrate reciprocates approximately 200 mm in length, and the film thickness distribution is optimized by matching the target spacing. This enables highly uniform deposition on 1100 mm × 1300 mm glass substrates, and the film uniformity effect is comparable to... Figure 13 As shown, Figure 13The substrate contains four rectangular targets, each 120 mm wide and 1300 mm long. The distance between the substrate and the targets is between 50 and 150 mm, and the distance between adjacent targets is 120 mm. When only target 1 is activated for deposition, the film thickness on the substrate varies with position as shown by curve T1, exhibiting a bell-shaped distribution. The effective width of the film within 20% of the maximum thickness is approximately 1-2 times the width of a single target. When all four targets are activated for deposition simultaneously, the total film thickness curve T1 shows a different distribution. T The film thickness is a superposition of four curves: T1, T2, T3, and T4. The effective width of the film within 10% of the maximum thickness is approximately the width of four targets plus three times the target spacing. This significantly expands the usable area compared to single-target deposition, making it suitable for uniform film formation on large-area substrates.

[0030] Furthermore, as an optional structural design, a carrier blocking layer cavity can be added between the deposition injection layer cavity and the deposition luminescent quantum well layer cavity to deposit a carrier blocking layer, suppress carrier overflow, improve electron-hole recombination efficiency, and optimize the device's luminescence performance. Although not shown in the figures, a vacuum sputtering cleaning cavity can be added between the deposition injection layer cavity and the deposition carrier blocking layer cavity for plasma cleaning of the substrate surface to remove surface impurities and ensure the cleanliness of the film interface.

[0031] Furthermore, for the structure of the pre-evacuation chamber, see [link to relevant documentation]. Figure 4 The cavity has valve 2 on the left and valve 3 on the right. When valve 2 is opened, a substrate can be introduced. A heater is installed inside the cavity, and the distance between the substrate and the heater is 50mm. The top of the cavity has inlet 1, inlet 2 and inlet 3, which can be used to introduce hydrogen or hydrogen chloride. The bottom of the cavity has a vacuum pump interface.

[0032] Furthermore, for the structure of the preheating and plasma cleaning chamber, please refer to [link / reference needed]. Figure 5 The cavity is equipped with valves 5 and 6 on the left and right sides respectively. A heater is installed inside the cavity, and the distance between the substrate and the heater is 50mm. Four plasma sources are installed inside the cavity, and the bottom of each plasma source is connected to a plasma power supply. The distance D between adjacent plasma sources is 120mm, and the distance between the substrate and the plasma source is between 50-150mm. The top of the cavity is equipped with multiple air inlets, and the bottom is equipped with a vacuum pump interface.

[0033] Furthermore, the structures of the deposition two-dimensional layer cavity, the deposition lower contact layer cavity, the deposition lower injection layer cavity, the deposition upper injection layer cavity, the deposition upper contact layer cavity, and the deposition carrier barrier layer cavity are described in [reference needed]. Figure 6 The difference between these chambers is that the materials used for targets 1, 2, 3 and 4 are different. Valves are provided on both the left and right sides of the chamber. The chamber contains a heater and four sets of rectangular sputtering targets. The distance between the substrate and the heater is 50mm, and the distance between the substrate and the target is between 50-150mm. The top of the chamber has multiple air inlets, and the bottom has a vacuum pump interface.

[0034] Furthermore, for the structure of the deposited superlattice layer cavity, see [link to relevant documentation]. Figure 8 The cavity is equipped with multiple independent target chambers, each corresponding to a set of sputtering targets, and is equipped with an independent target cover and sputtering power supply, which can realize the alternating sputtering growth of different materials. Specifically, the target size is 1400mm long and 120mm wide. Four targets can be placed in one cavity, with a target spacing of 120mm and a target width of 120mm.

[0035] Furthermore, the structure of the deposited luminescent quantum well layer cavity is shown in [reference needed]. Figure 10 The cavity for depositing the luminescent quantum well layer has three independent target chambers, each corresponding to a set of sputtering targets, equipped with an independent target cover and pulse power supply. Valves 8 and 9 are respectively located on the left and right sides of the cavity, and an air inlet is located on the top, enabling the alternating sputtering growth of the quantum well barrier layer and the well layer.

[0036] Furthermore, the structure of the impurity activation chamber is described in [reference needed]. Figure 11 The cavity has a valve 10 on the left and a valve 11 on the right. The cavity contains a heater and a cooling plate. The distance Z2 between the substrate and the cooling plate is between 50-150mm. The top of the cavity has multiple air inlets and the bottom has a vacuum pump interface, which can introduce protective gas and achieve rapid heating and activation.

[0037] Furthermore, for the structure of the cooling chamber, please refer to [link / reference]. Figure 12 The cavity has valve 11 on the left and valve 12 on the right. The cavity is equipped with a cooling plate with cooling water circulation. The distance between the substrate and the cooling plate is between 50-150mm. The top of the cavity has multiple air inlets and the bottom has a vacuum pump interface, which can realize controllable gradient cooling of the substrate.

[0038] This embodiment describes a method for fabricating a continuous deposition superlattice and quantum well array chip. Based on the aforementioned system, the substrate temperature for all thin film deposition processes in this embodiment is within the low-temperature pulsed magnetron sputtering process range. While ensuring the crystallinity quality of each functional layer thin film, it effectively suppresses atomic interdiffusion between adjacent layers, maintains a clear interlayer interface structure, and adapts to the processing requirements of low-melting-point amorphous substrates such as glass. Those skilled in the art can adjust and determine the specific values ​​of each process temperature within this low-temperature range according to the material composition, designed thickness, and crystallization requirements of the target film layer. The specific steps include the following: S1. Substrate Pretreatment: A glass substrate with dimensions of 1100mm×1300mm is sent into the pre-vacuum chamber through valve 1 for pre-vacuuming. At the same time, the glass substrate is preheated to substrate temperature T1 (150℃) by a heater to remove adsorbed water vapor and organic impurities from the surface. After pre-vacuuming and preheating, the glass substrate is sent into the preheating and plasma cleaning chamber through valve 2. The temperature is further increased to substrate temperature T2, which is controlled within the process range of 200-600℃. Hydrogen gas is introduced and hydrogen plasma is excited by radio frequency power supply to perform hydrogen ion bombardment cleaning on the surface of the glass substrate. During the entire pretreatment process, the glass substrate moves back and forth from side to side to ensure uniform surface treatment.

[0039] S2. Two-dimensional material preparation: After cleaning, the gas and power sources of the preheating and plasma cleaning chambers are turned off. The glass substrate is sent into the two-dimensional layer deposition chamber under vacuum. The corresponding valves are closed and a vacuum is drawn. The temperature of the glass substrate is controlled at T3, and the temperature of T3 is controlled within the process range of 200-800℃. Argon, methane and hydrogen mixed process gases are introduced through multiple gas inlets to adjust the chamber pressure. The four-channel target plasma excitation power supply is turned on, and the graphene layer is deposited using PECVD, controlling the deposition thickness. During the deposition process, the glass substrate continuously moves back and forth to ensure the uniformity of film formation. In this embodiment, the two-dimensional material layer is graphene.

[0040] S3. Superlattice Fabrication: After the thickness of the two-dimensional material layer reaches the preset value, the glass substrate is pushed into the superlattice deposition cavity under vacuum. Process gas is introduced and the substrate temperature is controlled at T4. The temperature of T4 is controlled within the process range of 300-800℃. The sputtering power supply of target 4-1 in the superlattice deposition cavity is turned on, and the target 4-1 cover is turned on. The first layer a-1, which has a similar structure, is sputtered and grown on the two-dimensional material layer. When the thickness of layer a-1 reaches t... a-1 Then, turn off the target 4-1 shield and the sputtering power supply for target 4-1. Next, push the substrate above the target 4-2 chamber in the deposition superlattice cavity and maintain the substrate temperature at T4. Then, turn on the sputtering power supply for target 4-2 and the target 4-2 shield to sputter and grow a layer of b-1. When the thickness of layer b-1 reaches t... b-1 Then, turn off the target 4-2 shield and the sputtering power supply for target 4-2. Next, push the substrate back above the target 4-1 chamber in the deposition superlattice cavity. Then, turn on the sputtering power supply for target 4-1 in the deposition superlattice cavity and turn on the target 4-1 shield. Sputter-grow a layer of a-2. When the thickness of layer a-2 reaches t... a-2 Then, turn off the target 4-1 shield and the sputtering power supply for target 4-1. Next, push the substrate above the target 4-2 chamber in the deposition superlattice cavity and maintain the substrate temperature at T4. Then, turn on the sputtering power supply for target 4-2 and the target 4-2 shield, and sputter a layer of b-2. When the thickness of the b-2 layer reaches t... b-2Afterwards, the target 4-2 shield and its sputtering power supply are turned off. We can then repeatedly grow a double-layer superlattice in the deposition superlattice cavity for multiple cycles. By adjusting the film composition and thickness, we can obtain a superlattice film with reduced stress and defects, which is beneficial for the subsequent fabrication of light-emitting devices. The above description only uses targets 4-1 and 4-2 to deposit and grow the superlattice layer structure. We can also use target 4-3 or arrange additional targets in the same cavity to deposit and grow more material layers to form the desired superlattice structure. The generated superlattice structure is as follows: Figure 3 As shown, specifically, by Figure 3 As can be seen, the structure from bottom to top consists of a substrate, a two-dimensional layer, a superlattice layer a-1, a superlattice layer b-1, a superlattice layer an, a superlattice layer bn, a lower contact layer, a lower injection layer, a light-emitting layer, an upper injection layer, and an upper contact layer. In this embodiment, the multilayer superlattice structure is an AlN / GaN superlattice. During the deposition process, the glass substrate maintains a left-right reciprocating motion. By adjusting the distance, frequency, and speed of the left-right motion, the thickness and composition of the resulting superlattice thin film layer can be reduced as a function of distance, thereby increasing the uniformity of thickness and composition with respect to position or distance.

[0041] S4. Lower contact layer preparation: After superlattice deposition, the glass substrate is pushed into the lower contact layer deposition cavity under vacuum. After evacuation, argon and nitrogen are introduced to control the glass substrate temperature at T5. The temperature of T5 is controlled within the process range of 200-700℃. The pulse power supply is turned on to grow the N-type highly doped semiconductor lower contact layer. During the deposition process, the glass substrate maintains a left-right reciprocating motion to improve the film uniformity. In this embodiment, the N-type dopant is silicon.

[0042] S5. Preparation of the lower implantation layer: After the thickness of the lower contact layer reaches the preset value, the glass substrate is pushed into the deposition chamber of the lower implantation layer under vacuum. Argon and nitrogen are introduced, and the temperature of the glass substrate is controlled at T6. The temperature of T6 is controlled within the process range of 300-700℃. The pulse power supply is turned on to grow the N-type low-doped semiconductor lower implantation layer. During the deposition process, the glass substrate maintains a left-right reciprocating motion to improve the uniformity of film formation.

[0043] S6. Fabrication of the light-emitting layer and quantum well: After the current implantation layer thickness reaches the preset value, the glass substrate is pushed into the deposition cavity for the light-emitting quantum well layer under vacuum. Process gas is introduced and the substrate temperature is controlled at T7, which is within the process range of 300-800℃. After introducing the gas and controlling the substrate temperature to T7, the sputtering power supply of target 7-1 in the deposition cavity for the light-emitting quantum well layer is turned on, and the target 7-1 cover is turned on to sputter and grow the x-1 layer of the quantum well. When the thickness of the x-1 layer reaches t... x-1Then, turn off the target 7-1 shield and the sputtering power supply of target 7-1. Next, push the substrate above the target 7-2 chamber in the deposition cavity of the luminescent quantum well layer and maintain the substrate temperature at T7. Then, turn on the sputtering power supply of target 7-2 and the target 7-2 shield to sputter and grow the y-1 layer of the quantum well. When the thickness of the y-1 layer reaches t... y-1 Then, turn off the target 7-2 shield and the sputtering power supply for target 7-2. Next, push the substrate back above the target 7-1 chamber in the deposition cavity for the luminescent quantum well layer. Then, turn on the sputtering power supply for target 7-1 in the deposition cavity for the luminescent quantum well layer, turn on the target 7-1 shield, and sputter to grow the x-2 layer of the quantum well. When the thickness of the x-2 layer reaches t... x-2 Then, turn off the target 7-1 shield and the sputtering power supply of target 7-1. Next, push the substrate above the target 7-2 chamber in the deposition cavity of the luminescent quantum well layer, and maintain the substrate temperature at T7. Then, turn on the sputtering power supply of target 7-2 and the target 7-2 shield to sputter and grow the y-2 layer. When the thickness of the y-2 layer reaches t... y-2 Afterwards, turn off the target 7-2 shield and the sputtering power supply of target 7-2. We can then repeatedly deposit and grow the barrier layer and well layer of the quantum well in the cavity for m cycles of alternating sputtering to form an InGaN / GaN multi-quantum-well light-emitting layer structure. The formed multi-quantum-well light-emitting layer structure is described in [reference needed]. Figure 9 , specifically, by Figure 9 It can be seen that the structure, from bottom to top, consists of a substrate, a two-dimensional layer, a superlattice layer a-1, a superlattice layer b-1, a superlattice layer an, a superlattice layer bn, a lower contact layer, a lower injection layer, a quantum well x-1 layer, a quantum well y-1 layer, a light-emitting layer, a quantum well xm layer, a quantum well ym layer, an upper injection layer, and an upper contact layer.

[0044] Specifically, the multi-quantum-well structure is a sandwich-style alternating stacked structure. The well layer is an InGaN light-emitting layer with a thickness of about 3 nanometers. The band gap of the material can be controlled by adjusting the indium (In) content, thereby controlling the emission wavelength. The barrier layer is a GaN confinement layer with a thickness of 5 nm. Its band gap is larger than that of the well layer, which can form a quantum confinement effect on the charge carriers, confining electrons and holes within the well layer and improving the radiative recombination efficiency. When the thickness of the well layer is thin to the nanometer level, the movement of electrons and holes is confined to a two-dimensional plane, and the energy level splits, which can further improve the luminescence efficiency and the controllability of photon energy.

[0045] S7. Preparation of the upper implantation layer and upper contact layer: After the quantum well layer is prepared, the glass substrate is sequentially pushed into the upper implantation layer deposition cavity and the upper contact layer deposition cavity under vacuum. The substrate temperature is controlled at T8 and T9, respectively. The temperature of T8 is controlled within the process range of 300-700℃, and the temperature of T9 is controlled within the process range of 300-600℃. The P-type low-doped semiconductor upper implantation layer and the P-type high-doped semiconductor upper contact layer are grown sequentially. During the deposition of the two thin films, the glass substrate maintains a left-right reciprocating motion to improve the uniformity of film formation. In this embodiment, the P-type dopant is magnesium.

[0046] Specifically, in this embodiment, the upper injection layer adopts a P-GaN / InGaN superlattice structure, which utilizes polarization effect and band bending to reduce magnesium activation energy and improve hole concentration and injection efficiency.

[0047] S8. Activation and Cooling Discharge: After the upper contact layer thickness reaches the preset value, the glass substrate is pushed into the impurity activation chamber under vacuum. After evacuation, the distance between the glass substrate and the heater is adjusted to 50mm, and the distance between the glass substrate and the cooling plate is controlled between 50-150mm. The heater is turned on to heat the glass substrate to T10. The temperature of T10 is controlled within the process range of 300-1000℃. After nitrogen is introduced, the second heater is turned on to raise the temperature of the glass substrate to the activation temperature in a short time and maintain it for a predetermined time to activate the doped impurities in each layer. After activation, the glass substrate is pushed into the cooling chamber under vacuum. The cooling water of the cooling plate is turned on to controllably cool the glass substrate and its multilayer thin film structure to room temperature. Then, the material is discharged through valve 12 to complete the fabrication of the light-emitting device array chip.

[0048] Furthermore, as an optional optimized embodiment of the present invention, a carrier blocking layer preparation step can be added after the injection layer preparation is completed in S5 and before the light-emitting layer preparation in S6 of the above basic preparation method. At the same time, the production cost is reduced by replacing the photolithography process with mask patterning. The specific process is as follows: Specifically, after the deposition of the S5 injection layer is completed, the glass substrate is removed, and a mask with array device pattern is placed and clamped in a single cavity opening. This step is the only cavity opening operation in the entire process. Compared with the traditional process that requires cavity opening after each patterning layer is completed, this greatly reduces the frequency of substrate exposure to the atmosphere and significantly reduces the risk of contamination.

[0049] Specifically, after the mask is clamped, the substrate is sent into the added vacuum sputtering cleaning chamber, where plasma bombardment removes surface impurities that may be introduced during the opening process, ensuring the substrate surface is clean.

[0050] Specifically, after surface cleaning, the substrate is pushed into the deposition carrier blocking layer cavity, argon and nitrogen are introduced, and the temperature of the glass substrate is controlled at T6-1. The temperature of T6-1 is controlled within the process range of 200-600℃. The RF power supply is turned on to grow the carrier blocking layer of aluminum nitride. During the deposition process, the glass substrate is kept moving back and forth to improve the uniformity of film formation.

[0051] Specifically, after the carrier blocking layer is deposited, the substrate is sent into the cavity for depositing the light-emitting quantum well layer, and the subsequent fabrication process of S6-S8 is continued.

[0052] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or basic characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects. The scope of the invention is defined by the appended claims rather than the foregoing description. Therefore, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0053] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A system for the fabrication of a superlattice and quantum well array chip by continuous deposition, characterized in that, It includes multiple independent vacuum chambers arranged in series, which are connected to each other through vacuum channels with valves, and each chamber is provided with a substrate transfer mechanism. The plurality of independent vacuum chambers, in the order of process, include at least: a pre-vacuum chamber, a preheating and plasma cleaning chamber, a two-dimensional layer deposition chamber, a superlattice layer deposition chamber, a lower contact layer deposition chamber, a lower injection layer deposition chamber, a light-emitting quantum well layer deposition chamber, an upper injection layer deposition chamber, an upper contact layer deposition chamber, an impurity activation chamber, and a cooling chamber. Each deposition chamber is provided with at least one target chamber, and each target chamber is provided with a rectangular sputtering target. The sputtering target is equipped with any one of pulse, radio frequency or DC power supply. A substrate holder that can reciprocate left and right along the target arrangement direction is provided in the chamber.

2. The system for preparing a chip of continuously deposited superlattice and quantum well array of claim 1, wherein, A deposition carrier blocking layer cavity is provided between the deposition injection layer cavity and the deposition luminescent quantum well layer cavity.

3. The system for preparing a chip of continuously deposited superlattice and quantum well array of claim 2, wherein, The deposition two-dimensional layer cavity, the deposition lower contact layer cavity, the deposition lower injection layer cavity, the deposition carrier blocking layer cavity, the deposition upper injection layer cavity, and the deposition upper contact layer cavity are each equipped with four target chambers, and each target chamber is equipped with four rectangular sputtering targets. The deposition superlattice layer cavity and the deposition luminescent quantum well layer cavity are equipped with three target chambers, and each target chamber is equipped with four rectangular sputtering targets, and a pulsed sputtering power supply is provided.

4. A method for fabricating a continuous deposition superlattice and quantum well array chip, implemented based on the fabrication system according to any one of claims 1-2, the method comprising at least the following steps: S1. Substrate pretreatment: The substrate is sent into the pre-vacuum chamber to complete the pre-vacuuming, preheated to the substrate temperature T1 to remove surface impurities, and then sent into the preheating and plasma cleaning chamber, heated to the substrate temperature T2, and hydrogen gas is introduced to excite plasma to complete the substrate surface bombardment cleaning. S2, Two-dimensional material preparation: The cleaned substrate is sent into the two-dimensional layer deposition chamber under vacuum, the substrate temperature is controlled at T3, the process gas is introduced, and the target power supply is turned on to deposit graphene or hexagonal boron nitride two-dimensional layers. S3. Superlattice fabrication: The substrate is sent into the superlattice layer deposition cavity under vacuum environment, the substrate temperature is controlled at T4, and the sputtering power supplies of different targets are alternately turned on and n cycles are cycled to deposit a multilayer superlattice structure. The multilayer superlattice structure is any one of AlN / GaN superlattice, InGaN / GaN superlattice or AlGaN / GaN superlattice. S4. Lower contact layer preparation: The substrate is sent into the lower contact layer deposition chamber under vacuum, the substrate temperature is controlled at T5, argon and nitrogen are introduced, and the target power supply is turned on to deposit the N-type highly doped semiconductor lower contact layer. S5. Preparation of the lower implantation layer: The substrate is sent into the lower implantation layer deposition chamber under vacuum, the substrate temperature is controlled at T6, argon and nitrogen are introduced, and the target power supply is turned on to deposit the N-type low-doped semiconductor lower implantation layer. S6. Fabrication of the light-emitting layer and quantum well: The substrate is sent into the light-emitting quantum well layer deposition chamber under vacuum. The substrate temperature is controlled at T7. The sputtering power supplies of different targets are alternately turned on and m cycles are performed to deposit the InGaN / GaN multi-quantum-well light-emitting layer structure. S7. Preparation of upper implantation layer and upper contact layer: The substrate is sequentially fed into the upper implantation layer deposition chamber and the upper contact layer deposition chamber under vacuum. The substrate temperature is controlled at T8 and T9 respectively, and the P-type low-doped semiconductor upper implantation layer and the P-type high-doped semiconductor upper contact layer are deposited sequentially. S8. Activation and Cooling Discharge: The substrate is fed into the impurity activation chamber under vacuum and heated to the activation temperature T. jf The substrate is then kept at a constant temperature to activate the doped impurities, and then sent into a substrate cooling chamber to be cooled to room temperature in a controlled manner to complete the fabrication of the array chip. In all thin film deposition steps, the substrate moves back and forth with the support to achieve a uniform distribution of thin film thickness over a large area.

5. The preparation method according to claim 4, characterized in that, An additional carrier blocking layer preparation step is added between S5 and S6. The carrier blocking layer preparation step is as follows: The substrate is fed into the carrier barrier layer deposition cavity, argon and nitrogen are introduced, the substrate temperature is controlled at T6-1, the target sputtering power supply is turned on to deposit the carrier barrier layer, and the substrate is allowed to move back and forth with the support to achieve a large area of ​​uniform film thickness distribution.

6. The preparation method according to claim 4, characterized in that, The multi-quantum well structure in S6 uses InGaN material for the well layer, and the emission wavelength is controlled by adjusting the In content. The barrier layer uses GaN material, and its bandgap is larger than that of the well layer.

7. The preparation method according to claim 4, characterized in that, The upper injection layer in S7 adopts a P-GaN / InGaN superlattice structure, which utilizes the polarization effect and band bending of the heterojunction interface to reduce the Mg activation energy and increase the hole concentration.

8. The preparation method according to claim 4, characterized in that, The N-type dopant is either silicon or germanium, and the P-type dopant is either magnesium or zinc.

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