Display module, preparation method thereof and display device

Abstract

This application provides a display module and its fabrication method, as well as a display device, to solve the problem of poor circuit conductivity in the prior art. A display module includes a first substrate and a second substrate; a first wiring layer disposed between the first substrate and the second substrate; a flip-chip thin film layer disposed on the side of the first substrate facing away from the second substrate, including a conductive connection portion and a carrier substrate disposed on the side of the conductive connection portion near the substrate; a first groove and a second groove are provided on the surface of the first substrate on the side facing away from the second substrate; a dielectric layer fills the first groove, and the flip-chip thin film layer is at least partially in contact with the dielectric layer; the first surface of the flip-chip thin film layer includes a first sidewall on the side of the carrier substrate near the second region and a second sidewall on the side of the conductive connection portion near the second region; a conductive layer covers at least a portion of the surface of the flip-chip thin film layer facing away from the substrate, the first surface, and the surface of the first wiring layer exposed in the second groove, and the flip-chip thin film layer is electrically connected to the first wiring layer through the conductive layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display module, its manufacturing method, and a display device. Background Technology

[0002] With the development of display technology, the demand for optimized narrow bezels is constantly increasing due to the need to improve customer experience. Existing processes that combine substrate drilling with back-side bonding still suffer from poor circuit continuity. Summary of the Invention

[0003] In view of this, this application provides a display module and its manufacturing method, as well as a display device, to solve the problem of poor circuit continuity in the prior art.

[0004] To solve the above-mentioned technical problems, the following technical solutions are adopted in the embodiments of this application: In a first aspect, this application provides a display module, including a first region and a second region, the edges of the first region and the second region being connected, comprising: a substrate, including a first substrate and a second substrate, the first substrate and the second substrate being stacked; a flip-chip thin film layer disposed on the side of the first substrate away from the second substrate; a first groove located in the first region and a second groove located in the second region being disposed on the surface of the first substrate on the side of the first substrate away from the second substrate; a dielectric layer, the dielectric layer filling the first groove, the carrier substrate of the flip-chip thin film layer being at least partially in contact with the dielectric layer; a first wiring layer disposed within the substrate, a portion of the first wiring layer being exposed in the second groove; a conductive layer, covering at least a portion of the surface of the flip-chip thin film layer away from the substrate, the sidewall of the flip-chip thin film layer near the second groove, and the surface of the first wiring layer exposed in the second groove, the flip-chip thin film layer being electrically connected to the first wiring layer through the conductive layer; and a light-emitting functional layer disposed on the side of the first substrate away from the first substrate.

[0005] According to one embodiment of this application, the material of the conductive layer includes at least one of silver, gold, and copper.

[0006] According to one embodiment of this application, the conductive layer includes a plurality of conductive units and the orthographic projection of the plurality of conductive units on the substrate is spaced apart in a first direction; the width of the conductive units in the first direction is less than 30 μm.

[0007] According to one embodiment of this application, the flip-chip thin film layer includes a carrier substrate and a conductive connection portion. The carrier substrate is disposed on the side of the conductive connection portion near the first substrate. The orthographic projection of the conductive connection portion on the first substrate and the orthographic projection of the carrier substrate on the first substrate at least partially overlap. The first surface of the flip-chip thin film layer includes a first sidewall of the carrier substrate near the second groove and a second sidewall of the conductive connection portion near the second groove. The angle formed by the plane of the first sidewall and the plane of the substrate is a first angle. The first opening of the first angle points to the dielectric layer. The first angle is an acute angle.

[0008] According to one embodiment of this application, the second groove includes a third sidewall, which is close to the first groove. The plane containing the third sidewall and the plane containing the substrate form a second angle, and the second opening of the second angle points to the dielectric layer. The angle of the second angle is less than or equal to 60°. The orthographic projection of the first sidewall onto the second substrate near the edge of the second groove and the orthographic projection of the third sidewall onto the second substrate near the edge of the first groove at least partially coincide. The angle of the first angle is the same as the angle of the second angle.

[0009] According to one embodiment of this application, the orthographic projection of the conductive connection portion on the substrate is located within the orthographic projection range of the carrier substrate on the substrate; the end of the orthographic projection of the conductive connection portion near the carrier substrate on the substrate near the second groove coincides with the edge of the orthographic projection of the carrier substrate near the conductive connection portion on the substrate; the distance by which the conductive connection portion near the second groove is recessed into the carrier substrate is the first recess distance, which includes 20~70 μm.

[0010] According to one embodiment of this application, the first groove includes a fifth sidewall and a sixth sidewall, the sixth sidewall being close to the second groove, and the vertical distance between the contact point of the third sidewall and the portion of the first trace layer exposed in the second groove and the plane where the sixth sidewall is located includes 50-200 μm.

[0011] According to one embodiment of this application, the display module further includes an encapsulation layer, an array film layer, and a via. The array film layer is disposed on the side of the substrate away from the flip-chip thin film layer, the light-emitting functional layer is disposed on the side of the array film layer away from the substrate, and the encapsulation layer is disposed on the side of the light-emitting functional layer away from the array film layer. The encapsulation layer, the light-emitting functional layer, and the array film layer are stacked sequentially in a direction perpendicular to the substrate. The first wiring layer is electrically connected to the array film layer through the via.

[0012] Secondly, this application provides a method for fabricating a display module, comprising: setting a first substrate; setting a first wiring layer on one side of the first substrate; setting a second substrate on the side of the first wiring layer away from the first substrate; stacking the first substrate and the second substrate; and setting the first wiring layer within the substrate; performing patterning processing on the side of the first substrate away from the second substrate to form a first groove in a first region and a second groove in a second region; filling the first groove with a dielectric layer; setting a flip-chip thin film layer on the side of the first substrate away from the second substrate, wherein the flip-chip thin film layer is at least partially in contact with the dielectric layer; partially removing the surface of the flip-chip thin film layer near the second groove to form a sloped sidewall of the flip-chip thin film layer; and setting a conductive layer, wherein the flip-chip thin film layer is electrically connected to the first wiring layer through the conductive layer.

[0013] Thirdly, this application provides a display device, including any one of the display modules of claims 1 to 8.

[0014] The beneficial effects of this application are as follows: The display module provided by this application, by opening a first groove and a second groove on a first substrate and filling the first groove with a dielectric layer, allows the flip-chip thin film layer to adhere to the surface of the first substrate through the dielectric layer, effectively reducing the ramp height of the conductive layer and reducing the risk of silver paste disconnection; at the same time, the conductive layer and the dielectric layer do not contact each other, avoiding chemical reaction between the two and improving circuit stability.

[0015] Furthermore, the first angle formed by the plane of the first sidewall of the flip-chip thin film carrier substrate and the plane of the substrate, and the second angle formed by the plane of the third sidewall of the second groove and the plane of the substrate, are consistent. The angle of the second angle is less than or equal to 60°, which greatly reduces the ramp angle of the conductive layer, further reduces the possibility of the conductive layer breaking, and significantly improves the production yield and reliability of the display module. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Among them: Figure 1 This is a schematic diagram of the structure of a display module provided in an embodiment of this application; Figure 2 This is a schematic diagram of another display module provided in an embodiment of this application; Figure 3 This is a top view of a display module provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of another display module provided in an embodiment of this application; Figure 5 for Figure 1 A partially enlarged structural diagram of the area within the dashed box on the right; Figure 6 for Figure 1 Another enlarged structural diagram of the area within the dashed box on the left; Figure 7 for Figure 2 Another enlarged structural diagram of the area within the dashed box; Figure 8 A schematic flowchart illustrating a method for manufacturing a display module according to an embodiment of this application; Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0017] 1-Display device; 2-Display module; 21-First area; 22-Second area; 20 - Substrate; 201 - First substrate; 202 - Second substrate; 203 - Third substrate; 211 - First groove; D3 - Third depth; D4 - Fourth width; 2115 - Fifth sidewall; 2116 - Sixth sidewall; D2 - Second distance; 212 - Second groove; 2123 - Third sidewall; 2124 - Fourth sidewall; D5 - Fifth depth; D6 - Sixth width; D7 - Seventh distance; 30-Crystal-film layer; 301-Carrier substrate; 3011-First sidewall; α1-First included angle; 310-First opening; 302-Conductive connection; 3022-Second sidewall; α2-Second included angle; 320-Second opening; d1-First inward distance; d2-Second inward distance; 40 - Dielectric layer; 50 - Array film layer; 501 - First wiring layer; 503 - Through-hole; 60 - Conductive layer; 601 - Conductive unit; D1 - First width; 70 - First surface; 80 - Light-emitting functional layer; 90 - Encapsulation layer; X - First direction. Detailed Implementation

[0018] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0020] The existing technology uses a process of drilling holes in the substrate 20 and bonding on the back side to realize the electrical connection between the flip-chip thin film pads and the first trace layer 501 on the side of the substrate 20 away from the light-emitting layer through the conductive layer 60. However, due to the problem that the conductive layer 60 is prone to breakage, the circuit conduction is poor. With the continuous improvement of the market for display technology, there is an urgent need for a technical solution to solve the above problems.

[0021] According to one embodiment of this application, please refer to Figure 1 A display module 2 is provided, which includes a first region 21 and a second region 22, with the edges of the first region 21 and the second region 22 connected. The first region 21 can be an effective display area, which is composed of a pixel array and is an effective working area that can realize image display, light emission and touch sensing. The second region 22 can be a non-effective display area, located outside the effective display area, which does not participate in image display and can be used to arrange driving traces, bonding pins, packages and light-shielding borders.

[0022] According to one embodiment of this application, please refer to Figure 1 The display module 2 includes a substrate 20, a flip-chip thin film layer 30, a dielectric layer 40, a first wiring layer 501, a conductive layer 60, and a light-emitting functional layer 80. In this embodiment, the substrate 20 can be a first substrate 201 and a second substrate 202, which are stacked to provide support and insulation for the display module 2. The flip-chip thin film layer 30 is disposed on the side of the first substrate 201 away from the second substrate 202, and wiring is provided in the flip-chip thin film layer 30. A first groove 211 located in the first region 21 and a second groove located in the second region 22 are provided on the surface of the first substrate 201 on the side away from the second substrate 202. 212, the dielectric layer 40 fills the first groove 211, the flip-chip thin film layer 30 is at least partially in contact with the dielectric layer 40, the first wiring layer 501 is disposed in the substrate 20, a portion of the first wiring layer 501 is exposed in the second groove 212, the conductive layer 60 covers at least a portion of the surface of the flip-chip thin film layer 30 away from the substrate 20, the sidewall of the flip-chip thin film layer 30 near the second groove 212, and the surface of the first wiring layer 501 exposed in the second groove 212, the flip-chip thin film layer 30 is electrically connected to the first wiring layer 501 through the conductive layer 60, and the light-emitting functional layer 80 is disposed on the side of the second substrate 202 away from the first substrate 201, which is the core component for the display device 1 to realize display and light emission.

[0023] According to one embodiment of this application, please refer to Figure 1 and Figure 7 A first groove 211 and a second groove 212 are provided on the surface of the first substrate 201 on the side opposite to the second substrate 202. The first groove 211 is located in the first region 21, the second groove 212 is located in the second region 22, and the first groove 211 is located on the side of the second groove 212 away from the frame of the display device 1.

[0024] According to one embodiment of this application, please refer to Figure 7 The distance between the second groove 212 and the lower edge of the first region 21 is the seventh distance D7, which includes 10-100 μm. This setting can ensure the structural strength of the substrate 20.

[0025] According to one embodiment of this application, please refer to Figure 1 and Figure 7 The depth of the first groove 211 is the third depth D3, and the depth of the second groove 212 is the fifth depth D5. The range of the third depth D3 and the fifth depth D5 includes 5-10 μm, which does not affect the support and insulation function of the substrate 20.

[0026] According to one embodiment of this application, please refer to Figure 7 The opening width of the first groove 211 is the fourth width D4, and the opening width of the second groove 212 is the sixth width D6. The range of the fourth width D4 and the sixth width D6 includes 200-500 μm, and meets the requirement of partial exposure of the first wiring layer 501.

[0027] According to one embodiment of this application, please refer to Figure 1 The substrate 20 can also be a first substrate 201, a second substrate 202 and a third substrate 203, with the first substrate 201, the second substrate 202 and the third substrate 203 stacked in sequence. Alternatively, multiple substrates 20 can be provided to flexibly adapt to product requirements.

[0028] According to one embodiment of this application, please refer to Figure 1 The first surface 70 of the flip-chip thin film layer 30 includes a first sidewall 3011 of the carrier substrate 301 near the second groove 212 and a second sidewall 3022 of the conductive connection portion 302 near the second groove 212. Part of the first wiring layer 501 is exposed in the second groove 212. The conductive layer 60 covers at least part of the surface of the flip-chip thin film layer 30 away from the substrate 20, the first surface 70 and the surface of the first wiring layer 501 exposed in the second groove 212. The conductive layer 60 extends directly into the second groove 212 on the surface of the first substrate 201 away from the second substrate 202. The flip-chip thin film layer 30 is directly electrically connected to the first wiring layer 501 on the side away from the light-emitting functional layer 80 through the conductive layer 60, completely eliminating the bezel area occupied by the bending area, achieving a narrower bezel, and further improving the screen ratio and product appearance.

[0029] According to one embodiment of this application, please refer to Figure 1 and Figure 5The flip-chip thin film layer 30 includes a carrier substrate 301 and a conductive connection portion 302. The carrier substrate 301 is disposed on the side of the conductive connection portion 302 close to the first substrate 201. The carrier substrate 301 is attached to the first substrate 201. The orthographic projection of the conductive connection portion 302 on the first substrate 201 overlaps at least partially with the orthographic projection of the carrier substrate 301 on the first substrate 201. The carrier substrate 301 can be a flip-chip polyimide (COF PI) substrate, and the conductive connection portion 302 can be a flip-chip pad (COF Pad). The conductive connection portion 302 is disposed on the side of the carrier substrate 301 away from the substrate 20. The carrier substrate 301 can play a supporting role and insulate and protect the internal circuitry of the conductive connection portion 302. The conductive connection portion 302 is used to transmit signals with the pins or driver chip of the display module 2.

[0030] According to one embodiment of this application, please refer to Figure 3 Multiple conductive connection portions 302 can be provided on the side of the carrier substrate 301 away from the first substrate 201. Each conductive connection portion 302 is in contact with the corresponding conductive unit 601, and the multiple conductive connection portions 302 are spaced apart in the first direction X. The multiple conductive connection portions 302 are electrically connected to the first trace layer 501 through the multiple conductive units 601 to realize the conduction of different signal traces.

[0031] According to one embodiment of this application, please refer to Figure 1 The filling thickness of the dielectric layer 40 includes 5-10 μm. The surface of the dielectric layer 40 exposed in the first groove 211 is basically flat with the surface of the first substrate 201 on the side away from the second substrate 202, forming a flat bonding surface. This is beneficial for the carrier substrate 301 in the flip-chip thin film layer 30 to at least partially contact and tightly adhere to the surface of the first substrate 201 away from the second substrate 202. The conductive layer 60 is not easy to penetrate into the tiny gap between the carrier substrate 301 and the first substrate 201, and will not cause the conductive layer 60 to short circuit.

[0032] According to one embodiment of this application, please refer to Figure 1 Filling the dielectric layer 40 inside the first groove 211 helps to reduce the ramp height of the conductive layer 60 and reduce the risk of the conductive layer 60 breaking.

[0033] According to one embodiment of this application, please refer to Figure 1 The side of the carrier substrate 301 that is attached to the first substrate 201 and is close to the second groove 212 can extend beyond the dielectric layer 40 by a certain distance. This distance can be flexibly adjusted according to actual process requirements to further avoid the reaction between the conductive layer 60 and the dielectric layer 40 after contact, which would affect the conductivity of the wiring.

[0034] According to one embodiment of this application, the dielectric layer 40 may include at least one of acrylic adhesive, epoxy adhesive or silicone adhesive, and the dielectric layer 40 bonds the flip-chip thin film layer 30 to fix the position of the flip-chip thin film layer 30 on the first substrate 201.

[0035] According to one embodiment of this application, the conductive layer 60 can be achieved by electrohydrodynamic inkjet printing (EHD), microscale direct writing (UPD), or three-dimensional (3D) stretch printing, which is beneficial for forming a uniform and dense conductive layer 60 and improving product yield.

[0036] According to one embodiment of this application, the first wiring layer 501 is located inside the substrate 20. The first wiring layer 501 may be located only inside the second substrate 202 and partially exposed in the second groove 212 on the surface of the first substrate 201. Alternatively, the first wiring layer 501 may also be disposed in any plane in the thickness direction of the substrate 20 according to actual process requirements.

[0037] According to one embodiment of this application, the conductive layer 60 is made of at least one of silver, gold, and copper, which has high conductivity and ensures the response speed and display stability of the display module 2.

[0038] According to one embodiment of this application, please refer to Figure 3 The conductive layer 60 includes multiple conductive units 601. Every two conductive units 601 are spaced apart on the orthographic projection of the substrate 20 in the first direction X, so as to avoid short circuits between adjacent conductive units 601. The number and shape of the conductive units 601 can be flexibly adjusted according to actual process requirements.

[0039] According to one embodiment of this application, please refer to Figure 3 The width of the conductive unit 601 in the first direction X is a first width D1, which is less than 30 μm. The smaller the width of the conductive unit 601, the more beneficial it is to reduce the overall area occupied by the conductive layer 60, and the easier it is to realize the narrow bezel design of the product.

[0040] According to one embodiment of this application, please refer to Figure 5 The angle formed by the plane of the first sidewall 3011 and the plane of the substrate 20 is the first angle α1. The first opening 310 of the first angle α1 points to the dielectric layer 40. The first angle α1 is an acute angle. By setting the first sidewall 3011 of the carrier substrate 301 as a slope, the conductive layer 60 can achieve a smooth transition during the slope climbing process. The slope design increases the contact and adhesion performance between the conductive layer 60 and the first sidewall 3011, and avoids the conductive layer 60 from breaking.

[0041] According to one embodiment of this application, please refer to Figure 1 and Figure 5The second groove 212 includes a third sidewall 2123 and a fourth sidewall 2124. The third sidewall 2123 is close to the first groove 211. The angle formed by the plane of the third sidewall 2123 and the plane of the substrate 20 is a second angle α2. The second opening 320 of the second angle α2 points to the dielectric layer 40. The angle of the second angle α2 is less than or equal to 60°. The angle of the second angle α2 includes 60°, 55°, 48°, 32.3°, and 20°. The design of the second angle α2 also increases the contact and adhesion performance between the conductive layer 60 and the third sidewall 2123, further reducing the risk of the conductive layer 60 breaking.

[0042] According to one embodiment of this application, please refer to Figure 1 and Figure 5 The angles of the first included angle α1 and the second included angle α2 can be the same. The angles formed by the first sidewall 3011 and the plane where the first substrate 201 is located and the angles formed by the third sidewall 2123 and the plane where the first substrate 201 is located are the same, which simplifies the process complexity and can improve the product yield.

[0043] According to one embodiment of this application, please refer to Figure 2 The angles of the first included angle α1 and the second included angle α2 can also be different, and different included angles can meet different wiring requirements.

[0044] According to one embodiment of this application, the purpose of setting the first included angle α1 and the second included angle α2 is to reduce the ramp height of the conductive layer 60 and avoid the conductive layer 60 from being disconnected and affecting the wiring path. The first included angle α1 and the second included angle α2 can be flexibly designed according to actual process requirements.

[0045] According to one embodiment of this application, please refer to Figure 1 and Figure 5 The distance between the edge of the conductive connection portion 302 on the substrate 20 near the second groove 212 and the edge of the third sidewall 2123 on the substrate 20 near the first groove 211 is equal to the first inward distance d1. At this time, the edges of the first sidewall 3011 and the third sidewall 2123 on the substrate 202 near the first groove 211 coincide, which is beneficial to the continuous extension of the conductive layer 60. The conductive layer 60 covers at least part of the surface of the flip-chip thin film layer 30 away from the substrate 20, the first surface 70, the third sidewall 2123 and the first wiring layer 501 exposed on the surface of the second groove 212, realizing the electrical connection between the flip-chip thin film layer 30 and the first wiring layer 501.

[0046] According to one embodiment of this application, please refer to Figure 4 and Figure 5The distance between the edge of the conductive connection portion 302 on the substrate 20 near the second groove 212 and the edge of the third sidewall 2123 on the substrate 20 near the first groove 211 is greater than the first inward distance d1. At this time, there is a second inward distance d2 between the edge of the first sidewall 3011 near the second groove 212 and the edge of the third sidewall 2123 near the first groove 211. The conductive layer 60 covers at least part of the surface of the flip-chip thin film layer 30 away from the substrate 20, the first surface 70, the third sidewall 2123 and the first wiring layer 501 exposed on the surface of the second groove 212 and the second inward distance d2, which can flexibly adapt to the process requirements of different products.

[0047] According to one embodiment of this application, please refer to Figure 5 The first inward distance ranges from 20 to 70 μm. The carrier substrate 301 can support the conductive connection part 302, and the carrier substrate 301 plays an insulating and protective role. According to one embodiment of this application, please refer to Figure 1 The first sidewall 3011 is projected onto the second substrate 202 near the edge of the second groove 212, and the third sidewall 2123 is projected onto the second substrate 202 near the edge of the first groove 211. The first included angle α1 and the second included angle α2 are the same. At this time, the slope of the first sidewall 3011 relative to the substrate 20 and the slope of the third sidewall 2123 relative to the substrate 20 are the same and they are on the same plane. The conductive layer 60 has a continuous and gentle trend on the first sidewall 3011 and the third sidewall 2123, which improves the reliability of the wiring.

[0048] According to one embodiment of this application, please refer to Figure 2 The first sidewall 3011 is projected onto the second substrate 202 near the edge of the second groove 212, and the third sidewall 2123 is projected onto the second substrate 202 near the edge of the first groove 211. The angle of the first included angle α1 is smaller than the angle of the second included angle α2. At this time, the slope of the first sidewall 3011 relative to the substrate 20 is smaller than the slope of the third sidewall 2123 relative to the substrate 20. Under the same inward distance, the thickness of the carrier substrate 301 in the direction perpendicular to the substrate 20 is smaller, which reduces the discontinuity of the conductive layer 60 in the carrier substrate 301 and reduces the risk of the conductive layer 60 breaking.

[0049] According to one embodiment of this application, the first sidewall 3011 is projected onto the second substrate 202 near the edge of the second groove 212, and the third sidewall 2123 is projected onto the second substrate 202 near the edge of the first groove 211, and the angle of the first included angle α1 is greater than the angle of the second included angle α2. At this time, the slope of the first sidewall 3011 relative to the substrate 20 is greater than the slope of the third sidewall 2123 relative to the substrate 20. At this time, under the same inward distance, the smaller the horizontal distance between the conductive connection portion 302 and the first wiring layer 501, the more beneficial it is to achieve the wiring connection between the flip-chip thin film layer 30 and the first wiring layer 501 through the conductive layer 60.

[0050] According to one embodiment of this application, ultraviolet laser can be used to perform patterning processing of the first groove 211, the second groove 212, the first sidewall 3011, and the third sidewall.

[0051] According to one embodiment of this application, the display module 2 includes a process for setting a first groove 211, a first included angle α1 and a second included angle α2, which greatly reduces the discontinuity of the conductive layer 60 and ensures the continuity of the wiring.

[0052] According to one embodiment of this application, only the first groove 211 is provided on the display module 2, which reduces the discontinuity of the conductive layer 60 at the flip-chip thin film layer 30 and reduces the risk of the conductive layer 60 breaking.

[0053] According to one embodiment of this application, setting at least one of the first included angle α1 of the first sidewall 3011 and the second included angle α2 of the second sidewall 3022 is beneficial for the conductive layer 60 to contact and adhere to the relevant interface, and to prevent the conductive layer 60 from breaking.

[0054] According to one embodiment of this application, the above-mentioned design for reducing the breakage of the conductive layer 60 can exist alone or in combination, and can be flexibly adjusted according to actual process requirements.

[0055] According to one embodiment of this application, please refer to Figure 7 The first groove 211 includes a fifth sidewall 2115 and a sixth sidewall 2116. The sixth sidewall 2116 is close to the second groove 212. The vertical distance between the contact point of the third sidewall 2123 and the portion of the first wiring layer 501 exposed in the second groove 212 and the plane where the sixth sidewall 2116 is located is the second distance D2. The range of the second distance D2 includes 50-200 μm, which ensures sufficient structural strength between the substrate 20 and the groove, and reserves space for subsequent process flows.

[0056] According to one embodiment of this application, please refer to Figure 1The display module 2 also includes an encapsulation layer 90, an array film layer 50, and a via 503. The array film layer 50 is disposed on the side of the substrate 20 away from the flip-chip thin film layer 30. The light-emitting functional layer 80 is disposed on the side of the array film layer 50 away from the substrate 20. The encapsulation layer 90 is disposed on the side of the light-emitting functional layer 80 away from the array film layer 50. The encapsulation layer 90, the light-emitting functional layer 80, and the array film layer 50 are stacked sequentially in a direction perpendicular to the substrate 20. The first wiring layer 501 is electrically connected to the array film layer 50 through the via 503. The array film layer 50 includes a structure of switching devices and conductive lines, which can be used to provide driving signals for the light-emitting functional layer 80. The light-emitting functional layer 80 is disposed between the encapsulation layer 90 and the array film layer 50. Under the driving control of the array film layer 50, the light-emitting functional layer 80 realizes light emission and image display. The encapsulation layer 90 forms a sealed protection for the light-emitting functional layer 80 and the array film layer 50, thereby improving the reliability of the display module.

[0057] According to one embodiment of this application, please refer to Figure 1 The array film layer 50 and the first wiring layer 501 are electrically connected through a via 503. The via 503 can penetrate through the third substrate 203, and / or the via 503 can be partially located within the second substrate 202. The design of the via 503 enables the wiring of the first wiring layer 501 and the array film layer 50 to be connected, thereby achieving narrow bezel optimization.

[0058] According to one embodiment of this application, a method for preparing a display module 2 is also provided, please refer to... Figure 8 ,include: S101. A first substrate 201 is provided, a first wiring layer 501 is provided on one side of the first substrate 201, and a second substrate 202 is provided on the side of the first wiring layer 501 away from the first substrate 201. The first substrate 201 and the second substrate 202 are stacked, and the first wiring layer 501 is provided inside the substrate 20. The substrate 20 includes a first substrate 201 and a second substrate 202. The substrate 20 is made of polyimide. The substrate 20 plays a supporting, buffering, insulating and planarizing role. The first wiring layer 501 is used to transmit electrical signals to realize the conduction and shutdown control of the pixel circuit. An array film layer 50, a light-emitting functional layer 80 and an encapsulation layer 90 are stacked sequentially on the side of the second substrate 202 near the first substrate 201. The array film layer 50 includes the first wiring layer 501.

[0059] S102, patterning is performed on the side of the first substrate 201 away from the second substrate 202 to form a first groove 211 located in the first region 21 and a second groove 212 located in the second region 22; Laser processing is performed on the first substrate 201 to form a first groove 211 and a second groove 212, wherein the first wiring layer 501 is exposed to the second groove 212, and the second distance D2 between the first groove 211 and the second groove 212 ranges from 50 to 200 μm, which can ensure the structural strength supported by the substrate 20.

[0060] S103. Fill the first groove 211 with the dielectric layer 40; The filling thickness of the dielectric layer 40 is the same as the depth of the first groove 211, so as to avoid the influence of the morphology of the first groove 211 on the adhesion of the flip-chip thin film layer 30 to the first substrate 201.

[0061] S104. A flip-chip thin film layer 30 is disposed on the side of the first substrate 201 away from the second substrate 202, and the flip-chip thin film layer 30 is at least partially in contact with the dielectric layer 40. The flip-chip thin film layer 30 includes a carrier substrate 301 and a conductive connection portion 302. The carrier substrate 301 includes a flip-chip polyimide substrate, and the conductive connection portion 302 includes flip-chip bonding pads. The carrier substrate 301 plays a supporting role, and the conductive connection portion 302 is used to realize electrical connection between the pins of the display module 2 or the driver chip. The carrier substrate 301 is disposed on the side of the conductive connection portion 302 close to the first substrate 201, which can insulate and protect the internal circuit. The flip-chip thin film layer 30 is tightly bonded to the first substrate 201 through the dielectric layer 40.

[0062] S105. The surface of the flip-chip thin film layer 30 near the second groove 212 is partially removed using a laser to form a sloped sidewall of the flip-chip thin film layer 30. By sloping the surface, the flip-chip thin film layer 30 is brought closer to the second groove 212, which increases the contact adhesion performance of the conductive layer 60, slows down the sloping trend of the conductive layer 60, and avoids the conductive layer 60 from having a break.

[0063] S106. A conductive layer 60 is provided, and the flip-chip thin film layer 30 is electrically connected to the first wiring layer 501 through the conductive layer 60. The conductive layer 60 is made of at least one of gold, silver, and copper. The conductive layer 60 covers at least a portion of the surface of the flip-chip thin film layer 30 facing away from the substrate 20, the first surface 70, and the surface of the first wiring layer 501 exposed to the second groove 212. This enables a one-to-one electrical connection between the flip-chip thin film layer 30 facing away from the light-emitting functional layer 80 and the first wiring layer 50 facing away from the light-emitting functional layer 80 through the continuous extension of the conductive layer 60 to the second groove 212.

[0064] According to one embodiment of this application, please refer to Figure 1After the array process is completed, laser etching is used to perform patterning on the substrate 20 to form a second groove 212. The first wiring layer 501 is partially exposed in the second groove 212. The display module also includes a flip-chip thin film layer 30. The conductive layer 60 is used to realize the electrical connection between the flip-chip thin film layer 30 and the first wiring layer 501, completely eliminating the influence of the bending radius on the narrow bezel optimization.

[0065] According to one embodiment of this application, please refer to Figure 9 Furthermore, a display device 1 is provided, including any display module 2 in the single embodiment or the combined embodiment described above.

[0066] According to one embodiment of this application, the display device includes a display module, a power supply component, and a housing component. The display module further includes a control component, which is used for wiring and controlling the display module to display an image. The power supply component is used to supply power to the display module, and the housing component is used to house and fix the display module and the power supply component.

[0067] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0068] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other embodiments.

Claims

1. A display module comprising a first area and a second area, the first area edge and the second area edge being connected, characterized in that, include, The substrate includes a first substrate and a second substrate, wherein the first substrate and the second substrate are stacked together. A flip-chip thin film layer is disposed on the side of the first substrate opposite to the second substrate; A first groove located in the first region and a second groove located in the second region are provided on the surface of the first substrate on the side of the first substrate facing away from the second substrate; A dielectric layer that fills the first groove, wherein the flip-chip thin film layer is at least partially in contact with the dielectric layer; A first wiring layer is disposed within the substrate, with a portion of the first wiring layer exposed to the second groove; A conductive layer covers at least a portion of the surface of the flip-chip thin film layer facing away from the substrate, the sidewall of the flip-chip thin film layer near the second groove, and the surface of the first wiring layer exposed to the second groove, wherein the flip-chip thin film layer is electrically connected to the first wiring layer through the conductive layer; The light-emitting functional layer has a second substrate on the side opposite to the first substrate.

2. The display module according to claim 1, characterized in that, The conductive layer is made of at least one of silver, gold, and copper.

3. The display module according to claim 2, characterized in that, The conductive layer includes a plurality of conductive units, and the orthogonal projections of the plurality of conductive units on the substrate are spaced apart in a first direction; Preferably, the width of the conductive unit in the first direction is less than 30 μm.

4. The display module according to claim 1, characterized in that, The flip-chip thin film layer includes a carrier substrate and a conductive connection portion. The carrier substrate is disposed on the side of the conductive connection portion near the first substrate. The orthographic projection of the conductive connection portion on the first substrate at least partially overlaps with the orthographic projection of the carrier substrate on the first substrate. The first surface of the flip-chip thin film layer includes a first sidewall of the carrier substrate near the second groove and a second sidewall of the conductive connection portion near the second groove. The angle formed between the plane of the first sidewall and the plane of the substrate is a first angle. The first opening of the first angle points to the dielectric layer. The first angle is an acute angle.

5. The display module according to claim 4, characterized in that, The second groove includes a third sidewall, which is close to the first groove. The plane containing the third sidewall forms a second angle with the plane containing the substrate. The second opening of the second angle points to the dielectric layer. The angle of the second angle is less than or equal to 60°. Preferably, the orthographic projection of the first sidewall onto the second substrate near the edge of the second groove and the orthographic projection of the third sidewall onto the second substrate near the edge of the first groove at least partially overlap; Preferably, the angle of the first included angle is the same as the angle of the second included angle.

6. The display module according to claim 4, characterized in that, The orthographic projection of the conductive connection portion onto the substrate lies within the orthographic projection range of the carrier substrate onto the substrate; Preferably, the surface of the conductive connection near the carrier substrate at one end of its orthographic projection onto the substrate near the second groove and the surface of the carrier substrate near the conductive connection at the edge of its orthographic projection onto the substrate coincide; Preferably, the distance by which the conductive connection portion is recessed into the carrier substrate near the second groove is the first recess distance, which includes 20~70 μm.

7. The display module according to claim 5, characterized in that, The first groove includes a fifth sidewall and a sixth sidewall, the sixth sidewall being close to the second groove, and the vertical distance between the third sidewall and the contact point of the portion of the first trace layer exposed in the second groove and the plane containing the sixth sidewall is 50-200 μm.

8. The display module according to claim 1, characterized in that, The display module further includes an encapsulation layer, an array film layer, and a via. The array film layer is disposed on the side of the substrate away from the flip-chip thin film layer. The light-emitting functional layer is disposed on the side of the array film layer away from the substrate. The encapsulation layer is disposed on the side of the light-emitting functional layer away from the array film layer. The encapsulation layer, the light-emitting functional layer, and the array film layer are stacked sequentially in a direction perpendicular to the substrate. The first wiring layer is electrically connected to the array film layer through the via.

9. A method for manufacturing a display module, characterized by, include, A first substrate is provided, a first wiring layer is provided on one side of the first substrate, and a second substrate is provided on the side of the first wiring layer away from the first substrate. The first substrate and the second substrate are stacked, and the first wiring layer is disposed within the substrate. A patterning process is performed on the side of the first substrate away from the second substrate to form a first groove in the first region and a second groove in the second region; The first groove is filled using a dielectric layer; A flip-chip thin film layer is disposed on the side of the first substrate away from the second substrate, and the flip-chip thin film layer is at least partially in contact with the dielectric layer; Partially remove the surface of the flip-chip film layer near the second groove to form a sloping sidewall of the flip-chip film layer; A conductive layer is provided, and the flip-chip thin film layer is electrically connected to the first wiring layer through the conductive layer.

10. A display device, characterized by comprising: Includes any one of the display modules described in claims 1 to 8.

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