Method for bonding perovskite single crystal and CMOS chip, and electronic integrated device

Abstract

This invention belongs to the technical field of electronic packaging and heterogeneous integration. It discloses a bonding method for perovskite single crystals and CMOS chips, and an electronic integrated device. The bonding method includes: mixing a first material and a second material in an inert and anhydrous atmosphere to undergo a melting reaction, followed by cooling the melt to obtain an amorphous bonding material; the first material comprises an organic onium salt, and the second material comprises a metal halide; softening the amorphous bonding material and adding it to the interconnect windows of the CMOS to form a lattice bonding layer; aligning and bonding the perovskite single crystal and the CMOS; heating to soften and wet the lattice bonding layer, followed by cooling and shaping; the perovskite single crystal and the CMOS are interconnected through the lattice bonding layer. This invention can achieve bonding of perovskite single crystals and CMOS under low temperature and low pressure conditions without causing interface damage, and the bonded perovskite single crystal and CMOS exhibit good interconnect performance.

Description

Technical Field

[0001] This invention belongs to the technical field of electronic packaging and heterogeneous integration, and more specifically, relates to a bonding method between a perovskite single crystal and a CMOS chip, and an electronic integrated device. Background Technology

[0002] In recent years, halide perovskite materials have seen rapid development in the field of photoelectric detection. Compared with polycrystalline thin films, perovskite single crystals have advantages such as low defect density and superior carrier transport performance, showing significant advantages in achieving low dark current, low noise, and high sensitivity detection. Therefore, they are considered important candidate materials for next-generation high-performance detectors (especially X-ray detection and imaging devices).

[0003] In area array imaging and pixel-level detection applications, relying solely on the intrinsic properties of materials is insufficient to directly achieve system-level imaging capabilities. The detector and readout circuitry need to achieve pixel-level parallel acquisition, signal processing, and output to realize high spatial resolution, high frame rate, and consistent response under large-scale array conditions. CMOS readout circuitry offers advantages such as high integration, small pixel size, parallel readout, and on-chip processing. Therefore, integrating the detection material and CMOS readout circuitry at the pixel level / array level, tightly coupling detection and readout within the same system, is a crucial step in moving this type of detection technology from material performance to chip-level and engineering implementation.

[0004] However, despite the excellent probing potential of perovskite single crystals, many challenges remain regarding stable and repeatable bonding and interconnection schemes between perovskite single crystals and CMOS. The main reason is that perovskite materials are more sensitive to process temperature, pressure, and water / oxygen environments compared to traditional semiconductor materials and conventional interconnection packaging systems, making it difficult to directly adapt traditional packaging interconnection schemes. Especially in microarray applications with pixel pitches on the order of approximately 15 µm, to avoid perovskite single crystal cracking, interface damage, and ensure array interconnection consistency, the integrated interconnection process typically needs to be completed under relatively low temperature (no higher than 120 °C to prevent performance degradation) and low pressure (no higher than 0.5 MPa to prevent single crystal cracking), achieving micron-level alignment accuracy (e.g., alignment error no greater than ±1 µm).

[0005] Existing chip-level interconnect and packaging bonding technologies mainly include reflow soldering (solder reflow bonding), eutectic / transient liquid phase (TLP) bonding, metal diffusion bonding, thermocompression bonding, ultrasonic bonding, and conductive adhesive / anisotropic conductive film (ACF) flip-chip bonding. These technologies are widely used in conventional device packaging, but they often struggle to meet multiple requirements simultaneously in perovskite single-crystal to CMOS pixelation integration scenarios. For example, reflow soldering and eutectic / TLP bonding typically require high temperatures to achieve melt wetting or metallurgical bonding, which is difficult to adapt to temperature-sensitive perovskite single crystals and may exceed the back-end thermal budget of CMOS; metal diffusion bonding or thermocompression bonding often requires high pressure to obtain reliable contact, which can easily cause cracks, edge chipping or interface damage to brittle single crystals; although ultrasonic bonding can reduce some temperature requirements, its ultrasonic energy and local stress may have adverse effects on thin metal layers, microstructure and crystal integrity; conductive adhesive or ACF solutions can achieve electrical interconnection at relatively low temperatures, but there are still shortcomings in terms of controllability of conductive channels, curing shrinkage and thermal expansion mismatch, long-term electrothermal aging, and short circuit / crosstalk suppression and contact resistance consistency in fine-pitch arrays.

[0006] Therefore, how to achieve high-performance bonding between perovskite single crystals and CMOS chips under low temperature and low pressure environments is a technical problem that urgently needs to be solved. Summary of the Invention

[0007] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a bonding method for perovskite single crystal and CMOS chip and an electronic integrated device. The purpose is to achieve bonding of perovskite single crystal and CMOS chip under low temperature and low pressure environment without causing interface damage. The bonded perovskite single crystal and CMOS chip have good interconnect performance.

[0008] To achieve the above objectives, the present invention is proposed.

[0009] According to a first aspect of the present invention, a method for bonding a perovskite single crystal to a CMOS chip is provided, comprising: In an inert atmosphere and an anhydrous environment, a first material and a second material are mixed and heated to melt together to form a homogeneous melt. The melt is then cooled to obtain an amorphous bonding material with a melting temperature not exceeding 120°C. The first material comprises an organic onium salt, and the second material comprises a metal halide. The amorphous bonding material is heated to a softened state and then added to each interconnect window of the bonding surface of the CMOS chip to form a dot matrix bonding layer. The perovskite single crystal is aligned and bonded to the CMOS chip. The lattice adhesive layer is heated to soften and wet the perovskite single crystal, and then cooled and shaped to allow the perovskite single crystal and the CMOS chip to be interconnected through the lattice adhesive layer.

[0010] According to a second aspect of the present invention, an electronic integrated device is provided, comprising a bonded CMOS chip and a perovskite single crystal, wherein the CMOS chip and the perovskite single crystal are bonded by an amorphous bonding material, the amorphous bonding material being formed by mixing and melting a first material and a second material, wherein the first material comprises an organic onium salt and the second material comprises a metal halide.

[0011] In summary, compared with the prior art, the technical solutions conceived in this invention have the following main advantages: Firstly, this invention obtains an amorphous bonding material by mixing and melting a first material and a second material. The first material contains an organic onium salt, and the second material contains a metal halide. The amorphous bonding material obtained by mixing and melting the two materials belongs to the same chemical system as perovskite. Subsequently, it can be used as a bonding layer between perovskite single crystal and CMOS chip to avoid the bonding layer reacting with the perovskite single crystal and affecting the performance of the perovskite single crystal. Secondly, the two selected materials can undergo a melting reaction under off-chip heating, and the resulting amorphous bonding material exhibits structural characteristics of long-range disorder and short-range order. Long-range disorder manifests as macroscopic lattice disorder, thus ensuring a lower processing temperature. The melting temperature of the amorphous bonding material obtained in this invention does not exceed 120°C. During subsequent bonding of the perovskite single crystal to the CMOS chip, the softening temperature of the softening amorphous bonding material will not exceed 120°C, and the ambient pressure can not exceed 0.5 MPa, thereby meeting the low-temperature, low-pressure bonding requirements of perovskite single crystals and CMOS chips. Short-range order manifests as a certain arrangement order in the microscopic lattice, which is beneficial for charge transport. Interconnection between the perovskite single crystal and the CMOS chip based on the obtained amorphous bonding material ensures a low contact resistance between the two, resulting in good interconnection performance between the bonded perovskite single crystal and the CMOS chip. Thirdly, the amorphous bonding material obtained by this invention produces good wetting of the interface after softening at low temperature. Its surface active sites can form a strong chemical bonding network with the surface of perovskite single crystal, thereby enabling the construction of high-strength interface connection under low temperature conditions, improving bonding strength and integration yield. Fourth, the single crystal / amorphous interface between the amorphous bonding material obtained by this invention and the perovskite single crystal can form a natural heterostructure and band synergy effect, which is beneficial to optimize the carrier transport path, reduce the resistance fluctuation caused by the interface transport barrier or local contact discontinuity, thereby improving the electrical connection stability and electron transport efficiency. Fifth, the amorphous bonding material obtained by this invention has isotropic deformation and relatively slow-release stress response characteristics in terms of mechanics. Based on this amorphous bonding material, the bonding of perovskite single crystal and CMOS chip can be realized. It can buffer and release the interface thermal stress and mechanical stress under thermal cycling or external load, thereby reducing the risk of failure such as bonding interface cracking, debonding and contact degradation caused by thermal stress mismatch, and improving the long-term stability and reliability of the interface. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating the steps of a method for bonding perovskite single crystals to a CMOS chip according to an embodiment of the present invention. Figure 2 This is a flowchart of off-chip processing in one embodiment of the present invention; Figure 3 This is an on-chip processing flowchart of one embodiment of the present invention; Figure 4 This is a schematic diagram of the bonding structure in one embodiment of the present invention; Figure 5 This is the DSC curve of the amorphous bonding material obtained in one embodiment of the present invention; Figure 6 This is a schematic diagram of the shear strength test results of the bonding interface in one embodiment of the present invention; Figure 7 This is a comparison of the effects of using ACA adhesive and using the amorphous bonding material obtained in this invention as an intermediate layer on the electrical properties of perovskite single crystals in one embodiment. Figure 8 This is a comparison of the overall effects of traditional technical solutions and the present invention in perovskite single-crystal CMOS integration. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0014] This invention proposes a bonding method between perovskite single crystals and CMOS chips.

[0015] like Figure 1 The diagram shown is a flowchart illustrating the steps of a method for bonding perovskite single crystals to a CMOS chip according to an embodiment of the present invention. The following is in conjunction with... Figure 1 The method is described in detail.

[0016] S1. In an inert atmosphere and an anhydrous environment, the first material and the second material are mixed and heated to cause them to melt and react to form a homogeneous melt. The melt is then cooled to obtain an amorphous bonding material with a melting temperature not higher than 120°C. The first material contains an organic onium salt and the second material contains a metal halide.

[0017] like Figure 2 This is an off-chip processing flowchart in one embodiment of the present invention.

[0018] In this step, the first material selected contains an organic ononium salt, and the second material selected contains a metal halide. The amorphous binder material obtained by mixing and melting these two materials belongs to the same chemical system as perovskite. This binder material is subsequently used as the bonding layer between the perovskite single crystal and the CMOS chip, which avoids reactions between the binder layer and the perovskite single crystal that could affect its performance. Furthermore, the two selected materials can undergo a melting reaction upon heating, and the resulting amorphous binder material exhibits a structure characterized by long-range disorder and short-range order. The long-range disorder manifests as macroscopic lattice disorder, thereby ensuring a lower processing temperature. The melting temperature of the amorphous binder material obtained in this invention does not exceed 120°C. During the subsequent bonding of the perovskite single crystal to the CMOS chip, the processing temperature of the bonding environment can not exceed 120°C, and the environmental pressure can not exceed 0.5 MPa, thus meeting the low-temperature, low-pressure bonding requirements between the perovskite single crystal and the CMOS chip. Short-range order is characterized by a certain arrangement order of the crystal lattice at the microscopic level, which is conducive to charge transport. Based on the obtained amorphous bonding material, the interconnection between perovskite single crystal and CMOS chip can be realized, which can ensure that the contact resistance between the two is small. The bonded perovskite single crystal and CMOS chip have good interconnection performance.

[0019] Specifically, the first material includes any one or more of isopropyltriphenylphosphine bromide, dodecyltriphenylphosphine bromide, and ethyltriphenylphosphine bromide, and the second material includes bismuth bromide. The long-chain organic groups in the organic ononium salts are beneficial for regulating the softening behavior and interfacial stress buffering capacity of the material, thereby facilitating interfacial bonding during the subsequent low-temperature bonding process.

[0020] Specifically, the molar ratio of the first material and the second material can be adjusted within the range of (0.8:1) to (1.2:1). The specific gravity of the first material mainly affects the melting temperature of the resulting amorphous binder, while the specific gravity of the second material mainly affects the charge transport properties of the resulting amorphous binder. In one embodiment, to balance the melting temperature and charge transport properties, the molar ratio of the first material and the second material can be set to 1:1.

[0021] Specifically, after the first and second materials are mixed, they are heated to 100°C–160°C in an external environment and held at this temperature for 5–30 minutes to form a homogeneous melt. In one embodiment, the melt can be transferred to a pre-cooled substrate for cooling to obtain an amorphous binder material, which can be an amorphous sheet. The obtained amorphous material can be further ground into powder for easy storage and use in subsequent processes.

[0022] S2. After heating the amorphous bonding material to a softened state, add it to each interconnect window on the bonding surface of the CMOS chip to form a lattice bonding layer.

[0023] like Figure 3 The diagram shown is an on-chip processing flowchart of one embodiment of the present invention.

[0024] Specifically, the top layer of the CMOS chip with exposed metal electrodes is the bonding surface. These metal electrodes are exposed through interconnect windows in the top layer and need to be interconnected with the perovskite single crystal. In one embodiment, before forming a lattice adhesive layer on the bonding surface of the CMOS chip, the bonding surface is first cleaned and dried. The cleaning process includes removing organic matter and oxides, and the drying can be performed using vacuum drying at approximately 60°C.

[0025] Specifically, since the amorphous binder material in the aforementioned steps is solid after cooling, it needs to be reheated to a softened state before being added to the interconnect windows on the bonding surface of the CMOS chip to form a lattice binder layer. The softened state can be a flowable state, allowing for the removal of the required amount to form micro-lattices or micro-pillar arrays at each interconnect window via template transfer or molten lattice deposition. It is understood that since the melting temperature of the amorphous binder material is not higher than 120°C, the softening temperature is below 120°C; typically, heating the amorphous binder material to 60°C–90°C softens it. This softening temperature is below the CMOS thermistor threshold (typically 150°C), preventing chip performance degradation and thermal stress mismatch. In one embodiment, the thickness of the formed lattice binder layer ranges from 0.5 μm to 20 μm. In one embodiment, the CMOS chip is a detection signal readout circuit chip, and the amorphous bonding material forms a micro-matrix or micro-pillar array in the pixel electrode region of the detection chip. The amorphous bonding material corresponds to the pixel electrode in terms of spatial position and size.

[0026] S3. Align and bond the perovskite single crystal with the CMOS chip, heat to soften and wet the lattice adhesive layer, and then cool and shape it to allow the perovskite single crystal and the CMOS chip to be interconnected through the lattice adhesive layer.

[0027] In one embodiment, before aligning and bonding the perovskite single crystal to the CMOS chip, the bonding surfaces of the perovskite single crystal are mechanically polished and cleaned to obtain a low roughness and a clean interface. The process preferably avoids material damage caused by aqueous or strongly polar solvents.

[0028] Subsequently, using flip-chip alignment and bonding equipment, the perovskite single crystal and the CMOS chip are pixel-level aligned and bonded, ensuring that the bonding surface of the single crystal side contacts the micro-lattice adhesive layer on the CMOS side. In one embodiment, the perovskite single crystal and the CMOS chip are aligned and bonded. After bonding, the temperature is heated to 60°C to 80°C within a pressure range of 0.02 MPa to 0.2 MPa and held for 5 min to 20 min. This softens and wets the amorphous adhesive layer, and during cooling, it vitrifies / solidifies and solidifies, thereby forming a stable mechanical and electrical connection. Specifically, the pressure range can be set within a low pressure range of 0.02 MPa to 0.05 MPa.

[0029] In this invention, based on the prepared amorphous bonding material, the amorphous material is introduced between the perovskite single crystal and the CMOS chip as an interface bonding and electrical connection medium. After alignment and bonding, the amorphous material can be softened, wetted, and solidified in a low-temperature and low-pressure environment, thereby achieving a stable connection under relatively low temperature and low-pressure conditions, meeting the requirements of micro-area interconnection and pixelated array integration.

[0030] Overall, the present invention has the following effects: Low temperature and low pressure: Relying on the amorphous bonding material used in this invention as the bonding amorphous intermediate layer, it has the ability to activate at low temperature and rearrange the interface, and can realize the bonding interconnection between perovskite single crystal and CMOS chip under low temperature and low pressure conditions on the chip. For example, the temperature can be set to 80°C and the pressure can be set to 0.1 MPa, which significantly reduces the risk of thermal damage and interface failure. High reliability: The amorphous bonding material used in this invention has high chemical compatibility with the perovskite single crystal interface, and provides stress buffer for thermal expansion mismatch and external load, suppresses performance degradation caused by interface reaction / migration, and improves bonding strength and long-term reliability. Longitudinal conductivity and lateral isolation suppress crosstalk: The amorphous adhesive material of this invention serves as an intermediate layer, resulting in low interfacial contact resistance (≤1×10⁻⁶). -4 With a resistance of Ω·cm², stable vertical conduction can be achieved, and the horizontal isolation resistance between adjacent pixels is ≥10. 8 -10 9 Ω can achieve high lateral resistance isolation, meaning that the introduction of the amorphous layer will not cause leakage or crosstalk.

[0031] In summary, this invention can meet the requirements of high-precision alignment and fine-pitch pixelated array interconnection in micro-areas, which is beneficial for controlling the interface thickness and spatial distribution of interconnection areas. It can achieve micro-area-level interconnection accuracy (e.g., ±15 μm), thereby reducing the risks of open circuits, short circuits and crosstalk, and improving integration yield and device consistency.

[0032] In summary, this invention addresses the challenge of simultaneously achieving "low temperature, low pressure, inert and anhydrous conditions, and high-precision interconnection" in chip-level pixel integration of temperature-sensitive and brittle heterostructures such as halide perovskite single crystals. It proposes a low-temperature bonding scheme of "amorphous bonding-heterojunction synergy" centered on a low-melting-point amorphous binder material. This scheme achieves high-strength interface connections and stress buffering through off-chip fabrication and on-chip low-temperature softening and wetting. Furthermore, it utilizes single-crystal / amorphous heterostructures to optimize interface electrical connections and carrier transport, thereby improving integration yield, array consistency, and long-term reliability.

[0033] This invention also proposes an electronic integrated device comprising a bonded CMOS chip and a perovskite single crystal, wherein the CMOS chip and the perovskite single crystal are bonded together using an amorphous bonding material, such as... Figure 4 The diagram shows a bonding structure according to an embodiment of the present invention. The amorphous bonding material is formed by mixing and melting a first material and a second material. The first material contains an organic onium salt, and the second material contains a metal halide. For example, a CMOS chip can be a readout circuit chip for detecting signals, and the integrated electronic device can be a detector or an optoelectronic device.

[0034] The technical effects of this invention have also been verified through experiments.

[0035] like Figure 5 The figure shows the DSC curve of the amorphous adhesive material obtained in one embodiment of the present invention. It can be seen that its melting temperature is 97.8℃, which is not higher than 120℃, and it has the characteristic of low-temperature melting.

[0036] like Figure 6 The diagram shows the shear strength test results of the bonding interface in one embodiment of the present invention. It can be seen that the bonding structure obtained by the technical solution of the present invention, after 100 thermal cycles and 168 hours of continuous placement in a high temperature and high humidity environment, shows a small decrease in the shear strength of the interface compared with its initial state, thus verifying that the bonding technology proposed in the present invention can achieve long-term stability and reliability of the interface.

[0037] like Figure 7The figure shows a comparison of the effects of using ACA adhesive and the amorphous bonding material obtained in this invention as intermediate layers on the electrical properties of perovskite single crystals in one embodiment. It can be seen that compared with using ACA adhesive as intermediate layer, the use of amorphous bonding material as intermediate layer in this invention has a smaller impact on the IV characteristic curve of perovskite single crystals (i.e., original single crystal devices). In other words, the introduction of amorphous bonding material as intermediate layer for bonding in this invention has a smaller impact on the electrical properties of perovskite single crystals.

[0038] like Figure 8 The diagram shows a comparison of the overall performance of traditional technical solutions and the present invention in perovskite single-crystal CMOS integration. Compared with traditional bonding methods, the present invention outperforms traditional methods in several key indicators and achieves the best overall performance.

[0039] Based on this invention, a bonding method is proposed: using an amorphous molten bonding material system with a composition similar to perovskite as the integration / bonding medium, under the premise of meeting the requirements of low temperature, low pressure, inert and anhydrous and high precision interconnection, the pixel-based integration of perovskite single crystal and CMOS is realized, thereby overcoming the technical problem of the difficulty in stable integration of perovskite single crystal and CMOS in the prior art, and promoting the development of perovskite single crystal detectors towards chip and array applications.

[0040] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that the terms "in one embodiment," "for example," and "again" are intended to illustrate the present invention and are not intended to limit the present invention.

[0041] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for bonding a perovskite single crystal to a CMOS chip, characterized in that, include: In an inert atmosphere and an anhydrous environment, a first material and a second material are mixed and heated to melt together to form a homogeneous melt. The melt is then cooled to obtain an amorphous bonding material with a melting temperature not exceeding 120°C. The first material comprises an organic onium salt, and the second material comprises a metal halide. The amorphous bonding material is heated to a softened state and then added to each interconnect window of the bonding surface of the CMOS chip to form a dot matrix bonding layer. The perovskite single crystal is aligned and bonded to the CMOS chip. The lattice adhesive layer is heated to soften and wet the perovskite single crystal, and then cooled and shaped to allow the perovskite single crystal and the CMOS chip to be interconnected through the lattice adhesive layer.

2. The bonding method as described in claim 1, characterized in that, The first material includes any one or more of isopropyltriphenylphosphine bromide, dodecyltriphenylphosphine bromide, and ethyltriphenylphosphine bromide, and the second material includes bismuth bromide.

3. The bonding method as described in claim 1, characterized in that, The molar ratio of the first material to the second material is in the range of (0.8:1) to (1.2:1).

4. The bonding method as described in claim 1, characterized in that, After a uniform melt is formed, it is transferred to a pre-cooled substrate for cooling to obtain an amorphous bonding material, which is an amorphous sheet.

5. The bonding method as described in claim 1, characterized in that, Before forming a dot matrix bonding layer on the bonding surface of the CMOS chip, the bonding surface of the CMOS chip is first cleaned and dried.

6. The bonding method as described in claim 1, characterized in that, The softening temperature range used to heat the amorphous adhesive material to a softened state is 60°C to 90°C.

7. The bonding method as described in claim 1, characterized in that, After aligning and bonding the perovskite single crystal with the CMOS chip, the temperature is heated to 60°C to 90°C within a pressure range of 0.02 MPa to 0.2 MPa and held for 5 min to 20 min to soften and wet the lattice adhesive layer.

8. The bonding method as described in claim 1, characterized in that, The thickness of the formed lattice adhesive layer ranges from 0.5 μm to 20 μm.

9. An electronic integrated device, characterized in that, The invention includes a bonded CMOS chip and a perovskite single crystal, wherein the CMOS chip and the perovskite single crystal are bonded by an amorphous bonding material, wherein the amorphous bonding material is formed by mixing and melting a first material and a second material, wherein the first material contains an organic onium salt and the second material contains a metal halide.

10. The electronic integrated device as claimed in claim 9, characterized in that, The electronic integrated device is a detector or an optoelectronic device.

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