Array substrate and display panel

Abstract

This application relates to an array substrate and a display panel. The array substrate includes a substrate and a driving circuit layer. The driving circuit layer includes multiple pixel circuits, including a first color pixel circuit, a second color pixel circuit, and a third color pixel circuit. The first color pixel circuit and the second color pixel circuit are adjacent to each other, and the third color pixel circuit and the second color pixel circuit are adjacent to each other. The second color pixel circuit and the third color pixel circuit are symmetrical about a second center line. The driving circuit layer also includes a first trace, a second trace, and a third trace. The first trace corresponds to the first color pixel circuit, and the second trace and the third trace are adjacent and located between the second color pixel circuit and the third color pixel circuit. The second trace and the third trace have the same signal and are interconnected. In this way, the trace layout can be simplified, the wiring space occupied can be reduced, the equivalent conductive cross-sectional area can be increased, and the resistance and voltage drop of a single trace can be significantly reduced, thereby improving the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered the most promising next-generation display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0003] Among related technologies, OLED display panels still suffer from poor display performance. Summary of the Invention

[0004] Based on this, this application provides an array substrate and a display panel that can improve the display effect.

[0005] According to one aspect of this application, an array substrate is provided, including a substrate and a driving circuit layer disposed on one side of the substrate;

[0006] The driving circuit layer includes multiple pixel circuits, each including at least one first color pixel circuit, at least one second color pixel circuit, and at least one third color pixel circuit. The first color pixel circuit and the second color pixel circuit are adjacent to each other, and the third color pixel circuit and the second color pixel circuit are adjacent to each other. The second color pixel circuit and the adjacent third color pixel circuit are symmetrical about a second center line. The second center line is parallel to a first direction.

[0007] The driving circuit layer further includes a first trace, a second trace, and a third trace, all extending along the first direction; the first trace corresponds to the first color pixel circuit; the second trace and the third trace are adjacent and located between the second color pixel circuit and the third color pixel circuit, the second trace corresponds to the second color pixel circuit, the third trace corresponds to the third color pixel circuit, and the signals of the second trace and the third trace are the same and interconnected.

[0008] In some embodiments, the second color pixel circuit and the adjacent first color pixel circuit are symmetrical about a first center line; the first center line is parallel to the first direction; the first trace is located on the side of the first color pixel circuit away from the second color pixel circuit;

[0009] Optionally, the second trace and the third trace are arranged in the same layer and made of the same material, and the second trace and the third trace are merged.

[0010] In some embodiments, the plurality of pixel circuits includes a plurality of first color pixel circuits, a plurality of second color pixel circuits, and a plurality of third color pixel circuits;

[0011] A plurality of first color pixel circuits are arranged along the first direction to form at least one first color pixel circuit column; a plurality of second color pixel circuits are arranged along the first direction to form at least one second color pixel circuit column; a plurality of third color pixel circuits are arranged along the first direction to form at least one third color pixel circuit column;

[0012] The first color pixel circuit column is adjacent to the second color pixel circuit column; the third color pixel circuit column is adjacent to the second color pixel circuit column; the second color pixel circuit column and the adjacent third color pixel circuit column are symmetrical about the second center line;

[0013] The second trace and the third trace are located between the second color pixel circuit column and the third color pixel circuit column;

[0014] Optionally, the second color pixel circuit column and the adjacent first color pixel circuit column are symmetrical about the first center line; the first trace is located on the side of the first color pixel circuit column away from the second color pixel circuit column;

[0015] Optionally, a plurality of first color pixel circuits are arranged along the first direction to form a plurality of first color pixel circuit columns; the plurality of first color pixel circuit columns are arranged along a second direction intersecting the first direction;

[0016] Multiple second-color pixel circuits are arranged along the first direction to form multiple second-color pixel circuit columns; multiple second-color pixel circuit columns are arranged along the second direction;

[0017] Multiple third-color pixel circuits are arranged along the first direction to form multiple columns of third-color pixel circuits; multiple columns of third-color pixel circuits are arranged along the second direction;

[0018] Each of the first color pixel circuit columns, each of the second color pixel circuit columns, and each of the third color pixel circuit columns are arranged sequentially along the second direction.

[0019] In some embodiments, the driving circuit layer further includes a connection portion extending along a first direction, the connection portion being located between the second trace and the third trace, and connecting the second trace and the third trace;

[0020] Optionally, the connecting portion is disposed in the same layer and with the same material as the second trace; and the connecting portion is disposed in the same layer and with the same material as the third trace;

[0021] Optionally, the second trace and the third trace are symmetrical about the second center line; the connecting portion is symmetrical about the second center line;

[0022] Optionally, the second trace, the third trace, and the connecting portion are integrally formed;

[0023] Optionally, the sum of the dimensions of the second trace, the third trace, and the connecting portion along the second direction is greater than the dimension of the first trace along the second direction; the second direction intersects the first direction;

[0024] Optionally, the dimension of the first trace along the second direction is 1 to 3 μm;

[0025] Optionally, the dimension of the second trace along the second direction is 1 to 3 μm;

[0026] Optionally, the dimension of the third trace along the second direction is 1 to 3 μm;

[0027] Optionally, the sum of the dimensions of the second trace, the third trace, and the connecting portion along the second direction is between 6 and 10 μm;

[0028] Optionally, the first trace and the second trace are arranged in the same layer and made of the same material.

[0029] In some embodiments, the driving circuit layer includes a first reference signal line extending along a second direction; the second direction intersects the first direction; at least one of the first trace, the second trace, and the third trace is connected to the first reference signal line;

[0030] Optionally, the driving circuit layer includes multiple first traces arranged along a second direction; the first reference signal line is connected to multiple pixel circuits and to at least some of the first traces; at least some of the first traces are connected to the corresponding first color pixel circuit.

[0031] In some embodiments, the driving circuit layer further includes a second reference signal line extending along the second direction; the first reference signal line is connected to a portion of the first trace; the second reference signal line is connected to a plurality of the pixel circuits and to other portions of the first traces.

[0032] In some embodiments, a portion of the first trace is not connected to the first reference signal line, nor to the second reference signal line or the pixel circuit; the signal of a portion of the first trace is a low-level signal.

[0033] In some embodiments, the driving circuit layer includes a plurality of second traces and a plurality of third traces; the plurality of second traces are arranged along a second direction, the plurality of third traces are arranged along a second direction, and the second direction intersects with the first direction;

[0034] At least some of the second traces are connected to the circuit corresponding to the second color pixel; at least some of the third traces are connected to the circuit corresponding to the third color pixel.

[0035] Optionally, the signals of at least some of the second traces are the same as the signals of at least some of the first traces;

[0036] Optionally, the signals of the second trace and the third trace are both reference signals or power signals.

[0037] In some embodiments, the driving circuit layer further includes a plurality of first power signal lines extending along the first direction and a second power signal line extending along the second direction; the first power signal lines are connected to the pixel circuit; the second power signal lines are connected to the plurality of first power signal lines, at least a portion of the second traces, and at least a portion of the third traces;

[0038] Optionally, the signals on the first power signal line and the second power signal line are high-level signals;

[0039] Optionally, the plurality of first power signal lines include a first color power signal line, a second color power signal line, and a third color power signal line; the first color power signal line is connected to the first color pixel circuit; the second color power signal line is connected to the second color pixel circuit; and the third color power signal line is connected to the third color pixel circuit.

[0040] Optionally, the second power signal line is connected to the plurality of first power signal lines, a portion of the second traces, and a portion of the third traces;

[0041] Some of the second traces are not connected to the plurality of first power signal lines, and are not connected to the second power signal lines and the pixel circuit; some of the third traces are not connected to the plurality of first power signal lines, and are not connected to the second power signal lines and the pixel circuit; some of the second traces and some of the third traces are both low-level signals.

[0042] In some embodiments, the driving circuit layer further includes a plurality of first data lines extending along the first direction;

[0043] The plurality of first data lines include a first color data line, a second color data line, and a third color data line; the first color data line is connected to the first color pixel circuit; the second color data line is connected to the second color pixel circuit; and the third color data line is connected to the third color pixel circuit.

[0044] Optionally, the first color power signal line is located between the first trace and the first color data line; the second color power signal line is located between the second trace and the second color data line; the third color power signal line is located between the third trace and the third color data line; the first color data line and the second color data line are arranged adjacent to each other.

[0045] Optionally, the first color data line and the second color data line are symmetrical about the first center line, and the first center line is parallel to the first direction;

[0046] Optionally, the first color power signal line and the second color power signal line are symmetrical about the first center line;

[0047] Optionally, the second color power signal line and the third color power signal line are symmetrical about the second center line;

[0048] Optionally, the second color data line and the third color data line are symmetrical about the second center line.

[0049] According to another aspect of this application, a display panel is provided, comprising an array substrate according to any one of the above embodiments.

[0050] The aforementioned array substrate, by symmetrically placing the second color pixel circuit and the adjacent third color pixel circuit about the second center line, allows the second trace corresponding to the second color pixel circuit to be located between the second color pixel circuit and the third color pixel circuit, and the third trace corresponding to the third color pixel circuit to be located between the second color pixel circuit and the third color pixel circuit. In other words, the second and third traces with the same signal are placed adjacent to each other, so that the second and third traces do not need to be spaced and are interconnected. This simplifies the trace layout, reduces the space occupied by wiring, and increases the equivalent conductive cross-sectional area, significantly reducing the resistance and voltage drop of a single trace, so that the pixel circuit can better drive the sub-pixels to emit light, thereby improving the display effect. Attached Figure Description

[0051] Figure 1 This is a top view of the array substrate in some embodiments of this application.

[0052] Figure 2 This is a cross-sectional view of the array substrate in some embodiments of this application.

[0053] Figure 3 This is a schematic diagram showing the distribution of the first trace, second trace, third trace, first power signal line, and first data line in the array substrate in some embodiments of this application.

[0054] Figure 4 This is a schematic diagram showing the distribution of the first reference signal line, the second reference signal line, the first trace, the second trace, the third trace, the first power signal line, and the first data line in the array substrate in some embodiments of this application.

[0055] Figure 5 for Figure 4 A magnified view of a portion of the array substrate at point A.

[0056] Figure 6 This is a schematic diagram showing the distribution of the first reference signal line, second reference signal line, first trace, second trace, third trace, first power signal line, first data line, and second power signal line in the array substrate in some embodiments of this application.

[0057] Figure 7 for Figure 6 A magnified view of a portion of the array substrate at point B.

[0058] Figure 8 This is a schematic diagram of the structure of the display panel in some embodiments of this application.

[0059] Explanation of reference numerals in the attached figures:

[0060] 1. Display panel;

[0061] 10. Array substrate;

[0062] 11. Substrate; 12. Driving circuit layer; 121. Pixel circuit; 121a. First color pixel circuit; 121b. Second color pixel circuit; 121c. Third color pixel circuit; S1. First center line; S2. Second center line; 1221. First trace; 1222. Second trace; 1223. Third trace; 123. Connector; 124. First reference signal line; 125. Second reference signal line; 126. First power signal line; 126a. First color power signal line; 126b. Second color power signal line; 126c. Third color power signal line; 127. Second power signal line; 128. First data line; 128a. First color data line; 128b. Second color data line; 128c. Third color data line;

[0063] X, the first direction; Y, the second direction. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0066] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intermediate elements. Furthermore, when a layer is referred to as being "below" another layer, it can be directly below it. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers.

[0067] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0068] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0069] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0070] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0071] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0072] Firstly, see Figures 1 to 3 As shown, this application embodiment provides an array substrate 10, including a substrate 11 and a driving circuit layer 12 disposed on one side of the substrate 11; the driving circuit layer 12 includes a plurality of pixel circuits 121, the plurality of pixel circuits 121 including at least one first color pixel circuit 121a, at least one second color pixel circuit 121b, and at least one third color pixel circuit 121c, the first color pixel circuit 121a and the second color pixel circuit 121b are adjacent, the third color pixel circuit 121c and the second color pixel circuit 121b are adjacent; the second color pixel circuit 121b and the adjacent third color pixel circuit 121c are about a second center line. S2 is symmetrical; the second center line S2 is parallel to the first direction X; the driving circuit layer 12 also includes a first trace 1221, a second trace 1222 and a third trace 1223, all extending along the first direction X; the first trace 1221 corresponds to the first color pixel circuit 121a; the second trace 1222 and the third trace 1223 are adjacent and located between the second color pixel circuit 121b and the third color pixel circuit 121c, the second trace 1222 corresponds to the second color pixel circuit 121b; the third trace 1223 corresponds to the third color pixel circuit 121c; the signals of the second trace 1222 and the third trace 1223 are the same and interconnected.

[0073] Specifically, substrate 11 can provide buffering, protection, or support for the display device. Substrate 11100 can be a flexible substrate 11, and the material of flexible substrate 11 can be polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a mixture of the above materials. Substrate 11 can also be a rigid substrate formed of materials such as glass.

[0074] The driving circuit layer 12 may include an active layer located on one side of the substrate 11, and multiple metal layers stacked on the side of the active layer opposite to the substrate 11. The second trace 1222 and the third trace 1223 may be located on the same metal layer, and the signals of the second trace 1222 and the third trace 1223 are the same. The signal of the first trace 1221 may be the same as the signals of the second trace 1222 and the third trace 1223, or the signal of the first trace 1221 may be different from the signals of the second trace 1222 and the third trace 1223. The driving circuit layer 12 includes a plurality of pixel circuits 121, which include at least one first color pixel circuit 121a, at least one second color pixel circuit 121b, and at least one third color pixel circuit 121c. The first color pixel circuit 121a is used to drive the first color sub-pixel to emit first color light; the second color pixel circuit 121b is used to drive the second color sub-pixel to emit second color light; and the third color pixel circuit 121c is used to drive the third color sub-pixel to emit third color light. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0075] The first trace 1221 corresponds to the first color pixel circuit 121a; the second trace 1222 corresponds to the second color pixel circuit 121b; and the third trace 1223 corresponds to the third color pixel. It should be noted that the correspondence between any of the above traces and pixel circuits 121 can be understood as the trace being the closest to the pixel circuit 121, or in other words, the trace being connected to the pixel circuit 121. The distribution of these traces varies depending on the structure and distribution of the corresponding pixel circuits 121.

[0076] In this embodiment, by symmetrically positioning the second color pixel circuit 121b and the adjacent third color pixel circuit 121c about the second center line S2, the second trace 1222 corresponding to the second color pixel circuit 121b is located between the second color pixel circuit 121b and the third color pixel circuit 121c, and the third trace 1223 corresponding to the third color pixel circuit 121c is located between the second color pixel circuit 121b and the third color pixel circuit 121c. That is, the second trace 1222 and the third trace 1223 with the same signal are placed next to each other. In this way, the second trace 1222 and the third trace 1223 do not need to be spaced apart, and the second trace 1222 and the third trace 1223 are connected to each other. This simplifies the wiring layout, reduces the space occupied by wiring, and increases the equivalent conductive cross-sectional area, significantly reducing the resistance and voltage drop of a single trace, so that the pixel circuit 121 can better drive the sub-pixels to emit light, thereby improving the display effect.

[0077] In some of these embodiments, see Figure 1 and Figure 3As shown, the second color pixel circuit 121b and the adjacent first color pixel circuit 121a are symmetrical about the first center line S1; the first center line S1 is parallel to the first direction X; the first trace 1221 is located on the side of the first color pixel circuit 121a away from the second color pixel circuit 121b.

[0078] This allows the overall pixel unit (including the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel) and the wiring layout to form a regular and symmetrical structure, resulting in a more balanced distribution of electrical parameters. This effectively reduces signal crosstalk and power supply deviation, making the overall wiring clearer and more orderly. It ensures independent and stable driving of each color pixel, further optimizes space utilization, reduces parasitic resistance and capacitance, improves pixel response consistency and image uniformity, and enhances the reliability of the array substrate and display quality. In addition, by placing the first trace on the side of the first color pixel circuit away from the second color pixel circuit, interference with the second and third traces is avoided. At the same time, the symmetrical structure reduces the difficulty of process alignment and improves the precision of photolithography and etching.

[0079] Optional, see below Figure 3 As shown, the second routing 1222 and the third routing 1223 are set in the same layer and made of the same material, and the second routing 1222 and the third routing 1223 are merged.

[0080] In this way, the second trace 1222 and the third trace 1223 form a parallel conductive structure, which effectively increases the cross-sectional area of ​​the overall conductive path, reduces the resistance and signal voltage drop of a single trace, ensures the stability and driving capability of signal transmission, and thus helps to improve the display effect.

[0081] In some of these embodiments, see Figures 1 to 3 As shown, the plurality of pixel circuits 121 include a plurality of first color pixel circuits 121a, a plurality of second color pixel circuits 121b, and a plurality of third color pixel circuits 121c; the plurality of first color pixel circuits 121a are arranged along the first direction X to form at least one first color pixel circuit column; the plurality of second color pixel circuits 121b are arranged along the first direction X to form at least one second color pixel circuit column; the plurality of third color pixel circuits 121c are arranged along the first direction X to form at least one third color pixel circuit column; the first color pixel circuit column is adjacent to the second color pixel circuit column; the third color pixel circuit column is adjacent to the second color pixel circuit column; the second color pixel circuit column and the adjacent third color pixel circuit column are symmetrical about the second center line S2; the second trace 1222 and the third trace 1223 are located between the second color pixel circuit column and the third color pixel circuit column.

[0082] Thus, by placing the first color pixel circuit column adjacent to the second color pixel circuit column, and the third color pixel circuit column adjacent to the second color pixel circuit column, and making the second color pixel circuit column and the adjacent third color pixel circuit column symmetrical about the second center line S2, the second trace 1222 and the third trace 1223 can be located between the second color pixel circuit column and the third color pixel circuit column. That is, the second trace 1222 and the third trace 1223 with the same signal are concentrated between the second color pixel circuit column and the third color pixel circuit column. The second trace 1222 and the third trace 1223 are directly connected without the need to reserve an insulation gap. This simplifies the wiring layout, reduces the space occupied by wiring, increases the equivalent conductive cross-sectional area, significantly reduces the resistance and voltage drop of a single trace, ensures the stability of signal transmission and the uniformity of driving capability, and thus helps to improve the display effect.

[0083] Optionally, see Figure 1 and Figure 3 As shown, the second color pixel circuit column and the adjacent first color pixel circuit column are symmetrical about the first center line S1; the first trace 1221 is located on the side of the first color pixel circuit column away from the second color pixel circuit column.

[0084] Optionally, see Figure 1 As shown, multiple first color pixel circuits 121a are arranged along a first direction X to form multiple first color pixel circuit columns; multiple first color pixel circuit columns are arranged along a second direction Y intersecting the first direction X; multiple second color pixel circuits 121b are arranged along the first direction X to form multiple second color pixel circuit columns; multiple second color pixel circuit columns are arranged along the second direction Y; multiple third color pixel circuits 121c are arranged along the first direction X to form multiple third color pixel circuit columns; multiple third color pixel circuit columns are arranged along the second direction Y; each first color pixel circuit column, each second color pixel circuit column, and each third color pixel circuit column are arranged sequentially along the second direction Y.

[0085] In this way, a first-color pixel circuit column, a second-color pixel circuit column, and a third-color pixel circuit column arranged sequentially along the second direction Y can form a repeating unit. Multiple first-color pixel circuit columns, multiple second-color pixel circuit columns, and multiple third-color pixel circuit columns can form multiple repeating units. Multiple repeating units are arranged sequentially along the second direction Y. Within a repeating unit, the second-color pixel circuit column and the first-color pixel circuit column are symmetrical about the first center line S1, and the second-color pixel circuit column and the third-color pixel circuit column are symmetrical about the second center line S2. However, there is no symmetrical relationship between the pixel circuit 121 columns in different repeating units. This makes the structure of the pixel circuit 121 of the same color and the distribution of the corresponding wiring consistent, reduces the brightness difference of sub-pixels of the same color, reduces the probability of vertical stripes, and improves the display effect.

[0086] In some of these embodiments, see Figure 3 , Figure 4 As shown, the driving circuit layer 12 also includes a connection portion 123 extending along the first direction X. The connection portion 123 is located between the second trace 1222 and the third trace 1223, and connects the second trace 1222 and the third trace 1223.

[0087] Thus, by providing a connecting portion 123 extending along the first direction X between the second trace 1222 and the third trace 1223, the second trace 1222 and the third trace 1223 can be stably connected in the extension direction, forming a parallel conductive structure. This effectively increases the cross-sectional area of ​​the overall conductive path, reduces the resistance and signal voltage drop of a single trace, and ensures the stability and driving capability of signal transmission, thereby improving the display effect.

[0088] Optionally, the connecting part 123 and the second wiring 1222 are made of the same material and layer; and the connecting part 123 and the third wiring 1223 are made of the same material and layer.

[0089] Thus, by using the same layer and material for the connection portion 123, the second trace 1222, and the third trace 1223, the connection portion 123, the second trace 1222, and the third trace 1223 can be formed simultaneously in the same process, without the need for additional mask, photolithography, and etching processes. This effectively simplifies the fabrication process of the array substrate 10 and reduces production difficulty and manufacturing costs. Furthermore, the use of the same layer and material enables the connection portion 123 and the traces to form a uniform, tightly bonded integrated conductive structure, reducing contact resistance and avoiding problems such as poor conductivity or increased parasitic parameters caused by interlayer alignment deviations or differences in material properties. This ensures a low-resistance, stable, and reliable electrical connection between the second trace 1222 and the third trace 1223, improves signal transmission consistency, and ultimately guarantees the driving stability of the pixel circuit 121 and the uniformity of the displayed image.

[0090] Optionally, see Figure 1 and Figure 3 As shown, the second trace 1222 and the third trace 1223 are symmetrical about the second center line S2; the connecting part 123 is symmetrical about the second center line S2.

[0091] Thus, by making the second trace 1222 and the third trace 1223 symmetrical about the second center line S2, and the connection portion 123 symmetrical about the second center line S2, the driving circuit layer 12 can maintain a symmetrical distribution in terms of trace layout, conductive cross-section and electrical parameters, making the signal transmission path, resistance distribution and electric field distribution more balanced, effectively avoiding problems such as signal deviation and uneven voltage drop caused by asymmetrical structure; in addition, it can also improve the alignment accuracy and process stability of the array substrate 10 in photolithography, etching and other processes, reduce the impact of process deviation on electrical performance, ensure the driving consistency of adjacent pixel circuits 121, and thus improve the brightness and color uniformity of the display panel 1.

[0092] Optionally, the second wiring 1222, the third wiring 1223 and the connecting part 123 are integrally formed.

[0093] Optionally, the sum of the dimensions of the second trace 1222, the third trace 1223, and the connecting portion 123 along the second direction Y is greater than the dimension of the first trace 1221 along the second direction Y.

[0094] In other words, the cross-sectional area of ​​the conductive path of the second trace 1222, the third trace 1223 and the connecting part 123 is relatively large, which can reduce the overall resistance of the second trace 1222, the third trace 1223 and the connecting part 123, thereby reducing the voltage drop, ensuring the stability of signal transmission and the uniformity of driving capability, and improving the display effect.

[0095] Optionally, the dimension of the first trace 1221 along the second direction Y is 1 to 3 μm. Specifically, the dimension of the first trace 1221 along the second direction Y can be 1 μm, 2 μm, 3 μm, or any value between 1 μm and 3 μm.

[0096] Optionally, the dimension of the second trace 1222 along the second direction Y is 1 to 3 μm. Specifically, the dimension of the second trace 1222 along the second direction Y can be 1 μm, 2 μm, 3 μm, or any value between 1 μm and 3 μm.

[0097] Optionally, the dimension of the third trace 1223 along the second direction Y is 1 to 3 μm. Specifically, the dimension of the third trace 1223 along the second direction Y can be 1 μm, 2 μm, 3 μm, or any value between 1 μm and 3 μm.

[0098] Optionally, the sum of the dimensions of the second trace 1222, the third trace 1223, and the connecting portion 123 along the second direction Y is between 6 and 10 μm. Specifically, the sum of the dimensions of the second trace 1222, the third trace 1223, and the connecting portion 123 along the second direction Y can be any value of 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, or 6 to 10 μm.

[0099] Optionally, the first wiring 1221 and the second wiring 1222 are set on the same layer and made of the same material.

[0100] In some of these embodiments, see Figure 1 , Figure 4 and Figure 5 As shown, the driving circuit layer 12 includes a first reference signal line 124 extending along the second direction Y; the second direction Y intersects the first direction X; at least one of the three traces 1221, 1222 and 1223 is connected to the first reference signal line 124.

[0101] Specifically, the first reference signal line 124 can be connected to multiple pixel circuits 121.

[0102] Thus, the first reference signal line 124 forms a regular cross layout with at least one of the first trace 1221, the second trace 1222 and the third trace 1223, realizing multi-point equipotential compensation, improving the voltage drop unevenness problem of the far-end pixel circuit 121, enhancing the stability and reliability of the driving signal, and thus improving the brightness and color uniformity of the display screen.

[0103] Optionally, see Figure 1 , Figure 4 and Figure 5 As shown, the driving circuit layer 12 includes multiple first traces 1221, which are arranged along the second direction Y; the first reference signal line 124 is connected to multiple pixel circuits 121 and to at least some of the first traces 1221, and at least some of the first traces 1221 are connected to the corresponding first color pixel circuit 121a.

[0104] Thus, by connecting the first reference signal line 124 extending along the second direction Y to multiple pixel circuits 121 and at least a portion of the first traces 1221, a unified and stable reference potential supply path can be formed, providing a consistent reference level for multiple pixel circuits 121, effectively reducing driving errors caused by potential fluctuations, and improving the consistency of the operating states of each pixel circuit 121. Furthermore, by extending the first reference signal line 124 along the second direction Y, it can form a regular cross layout with multiple first traces 1221, achieving multi-point equipotential compensation, improving the uneven voltage drop problem of the far-end pixel circuits 121, enhancing the stability and reliability of the driving signal, and thereby improving the brightness and color uniformity of the displayed image.

[0105] Optionally, see Figure 1 , Figure 4 and Figure 6 As shown, the driving circuit layer 12 also includes a second reference signal line 125 extending along the second direction Y; the first reference signal line 124 is connected to a portion of the first traces 1221; the second reference signal line 125 is connected to a plurality of pixel circuits 121 and to other portions of the first traces 1221.

[0106] Thus, by connecting the first reference signal line 124 and the second reference signal line 125 extending along the second direction Y to correspondingly connect a portion of the first trace 1221, partitioned power supply and reference potential supply to the first trace 1221 can be achieved. The first reference signal line 124 and the second reference signal line 125 cooperate with each other to distribute the trace load, reduce the resistance voltage drop of a single signal line, and enable the pixel circuits 121 in different areas to obtain a stable and balanced potential reference, thereby improving driving consistency and thus improving the display effect.

[0107] In some of these embodiments, see Figure 1 , Figure 4 and Figure 6 As shown, some of the first traces 1221 are not connected to the first reference signal line 124, nor to the second reference signal line 125 and the pixel circuit 121; the signal of some of the first traces 1221 is a low-level signal.

[0108] In other words, some of the first traces 1221 act as low-level signal lines, which allows low-level signals to be transmitted from the edge area or through some of the first traces 1221 in the display area. This reduces the voltage drop of the low-level signal lines, improves the display effect, and reduces power consumption.

[0109] In some of these embodiments, see Figure 1 , Figure 3 , Figure 4 and Figure 6As shown, the driving circuit layer 12 includes multiple second traces 1222 and multiple third traces 1223; the multiple second traces 1222 are arranged along the second direction Y, and the multiple third traces 1223 are arranged along the second direction Y, which intersects with the first direction X; at least some of the second traces 1222 are connected to the corresponding second color pixel circuit 121b; at least some of the third traces 1223 are connected to the corresponding third color pixel circuit 121c.

[0110] Thus, by arranging multiple second traces 1222 and multiple third traces 1223 along the second direction Y intersecting the first direction X, and connecting them respectively to the second and third color pixel circuits 121c, independent driving and signal control of the different color pixel circuits 121 can be achieved, improving the precision of array driving. In addition, each second and third color pixel circuit 121c can obtain a stable and uniform driving signal, effectively improving the brightness and color consistency of sub-pixels in different areas and enhancing the display effect.

[0111] Optionally, the signals of at least some of the second traces 1222 are the same as the signals of at least some of the first traces 1221.

[0112] Optionally, the signals of the second trace 1222 and the third trace 1223 are both reference signals or power signals.

[0113] In some of these embodiments, see Figure 1 , Figure 6 and Figure 7 As shown, the driving circuit layer 12 also includes a plurality of first power signal lines 126 extending along the first direction X and a second power signal line 127 extending along the second direction Y. The first power signal lines 126 are connected to the pixel circuit 121; the second power signal lines 127 are connected to the plurality of first power signal lines 126, at least some of the second traces 1222 and at least some of the third traces 1223.

[0114] Thus, by connecting the second power signal line 127 extending along the second direction Y to multiple first power signal lines 126 extending along the first direction X, at least some of the second traces 1222 and at least some of the third traces 1223, a unified and stable common power supply network can be formed, realizing potential balancing and collaborative compensation of multiple power supply lines, effectively reducing the resistance voltage drop of the remote power supply lines, improving the consistency of the power supply potential of each pixel circuit 121, thereby helping to improve the consistency of screen display.

[0115] Optionally, the signals of the first power signal line 126 and the second power signal line 127 are high-level signals.

[0116] Optionally, see Figure 1 and Figure 6As shown, the multiple first power signal lines 126 include a first color power signal line 126a, a second color power signal line 126b, and a third color power signal line 126c; the first color power signal line 126a is connected to the first color pixel circuit 121a; the second color power signal line 126b is connected to the second color pixel circuit 121b; and the third color power signal line 126c is connected to the third color pixel circuit 121c.

[0117] Thus, by setting multiple first power signal lines 126 extending along the first direction X, and configuring corresponding first color, second color, and third color power signal lines 126c according to the sub-pixel colors, each color power signal line independently supplies power to the corresponding pixel circuit 121. This enables power supply separation and precise control of different color pixel circuits 121, avoiding mutual interference and drag between different color pixels in terms of power supply, effectively reducing power supply crosstalk and potential fluctuations, and allowing each pixel circuit 121 to obtain a more stable and uniform driving voltage. This reduces brightness differences and color shifts caused by uneven power supply, and improves the consistency of screen display.

[0118] Optionally, see Figure 1 , Figure 6 and Figure 7 As shown, the second power signal line 127 is connected to multiple first power signal lines 126, a portion of the second traces 1222, and a portion of the third traces 1223; the portion of the second traces 1222 is not connected to the multiple first power signal lines 126, nor to the second power signal line 127 and the pixel circuit 121; the portion of the third traces 1223 is not connected to the multiple first power signal lines 126, nor to the second power signal line 127 and the pixel circuit 121; both the portion of the second traces 1222 and the portion of the third traces 1223 are low-level signals.

[0119] In this way, by simultaneously connecting multiple first power signal lines 126 and some second and third traces 1223 through the second power signal line 127, a power supply network is constructed, realizing potential balance and current sharing of multiple power supplies, effectively reducing the overall power supply voltage drop, and improving the power supply stability of each pixel circuit 121; the second traces 1222 and third traces 1223 of some unconnected first power signal lines 126, second power signal lines 127 and pixel circuits 121 are all set to low level, which can form a shielding layer, suppress crosstalk and noise between signal lines, reduce the impact of parasitic capacitance on signal transmission, thereby improving the display effect and reducing power consumption.

[0120] In some of these embodiments, see Figure 1 , Figure 3 , Figure 4 and Figure 6As shown, the driving circuit layer 12 also includes multiple first data lines 128 extending along the first direction X; the multiple first data lines 128 include a first color data line 128a, a second color data line 128b, and a third color data line 128c; the first color data line 128a is connected to the first color pixel circuit 121a; the second color data line 128b is connected to the second color pixel circuit 121b; and the third color data line 128c is connected to the third color pixel circuit 121c.

[0121] Thus, by setting a first color data line 128a, a second color data line 128b, and a third color data line 128c that extend along the first direction X and are distinguished by color, and each corresponding to a pixel circuit 121 that drives its respective color, independent transmission and precise control of data signals for each sub-pixel can be achieved, avoiding data crosstalk between sub-pixels of different colors. Moreover, the independent data lines can provide stable and pure data signals for each pixel circuit 121, effectively improving grayscale display accuracy and color reproduction accuracy, making the image richer in layers and the colors purer.

[0122] Optionally, see Figure 1 , Figure 3 , Figure 4 and Figure 6 As shown, the first color power signal line 126a is located between the first trace 1221 and the first color data line 128a; the second color power signal line 126b is located between the second trace 1222 and the second color data line 128b; the third color power signal line 126c is located between the third trace 1223 and the third color data line 128c; the first color data line 128a and the second color data line 128b are arranged adjacent to each other.

[0123] In this way, by arranging the power signal lines of each color between the corresponding traces and data lines, and setting the first color data line 128a and the second color data line 128b adjacent to each other, the power supply lines and data transmission lines can be arranged in an orderly and close manner, shortening the power supply and signal access path of the pixel circuit 121, reducing parasitic resistance and parasitic capacitance, and reducing signal delay and voltage drop.

[0124] Optionally, see Figure 1 , Figure 3 , Figure 4 and Figure 6 As shown, the first color data line 128a and the second color data line 128b are symmetrical about the first center line S1.

[0125] Thus, by symmetrically arranging the first color data line 128a and the second color data line 128b about the first center line S1, the two data lines can maintain a high degree of consistency in terms of trace length, line width spacing, and parasitic parameters, effectively balancing signal transmission delay and impedance characteristics, and avoiding data deviation and brightness unevenness caused by asymmetrical wiring. In addition, the distribution of the first color data line 128a and the second color data line 128b is more in line with the symmetrical arrangement of the first color pixel circuit 121a and the second color pixel circuit 121b, optimizing the space utilization of the array substrate 10.

[0126] Optionally, see Figure 1 , Figure 3 , Figure 4 and Figure 6 As shown, the first color power signal line 126a and the second color power signal line 126b are symmetrical about the first center line S1.

[0127] In this way, by symmetrically setting the first color power signal line 126a and the second color power signal line 126b about the first center line S1, the two power supply lines maintain a high degree of consistency in terms of trace length, line width, impedance and parasitic parameters. This can provide a balanced and synchronous power supply potential to the corresponding pixel circuits 121 on both sides, effectively reducing the brightness deviation and driving difference caused by power supply asymmetry, improving the display effect and reducing power consumption.

[0128] Optionally, see Figure 1 , Figure 3 , Figure 4 and Figure 6 As shown, the second color power signal line 126b and the third color power signal line 126c are symmetrical about the second center line S2.

[0129] Thus, by symmetrically arranging the second color power signal line 126b and the third color power signal line 126c about the second center line S2, the two power supply lines can maintain a high degree of consistency in length, impedance, parasitic parameters and current distribution, providing a balanced and stable power supply potential for the corresponding pixel circuit 121, avoiding brightness and color deviation caused by power supply asymmetry, improving display effect and reducing power consumption.

[0130] Optionally, see Figure 1 , Figure 3 , Figure 4 and Figure 6 As shown, the second color data line 128b and the third color data line 128c are symmetrical about the second center line S2.

[0131] Thus, by symmetrically arranging the second color data line 128b and the third color data line 128c about the second center line S2, the two data lines maintain a high degree of consistency in electrical parameters such as trace length, line width, impedance, and parasitic capacitance. This ensures that the data signal transmission delay and driving strength are synchronously balanced, avoiding display deviations between adjacent pixels due to wiring differences and improving the display effect. In addition, the distribution of data lines corresponding to different color sub-pixels is adapted to the arrangement of pixel circuits 121 corresponding to different color sub-pixels, which is beneficial for precise alignment of photolithography and etching in the process, reducing process errors and improving the yield and reliability of the array substrate 10.

[0132] Secondly, see Figure 8 As shown, this application embodiment provides a display panel 1 based on the array substrate 10 of any of the above embodiments. This improves the display effect of the display panel 1.

[0133] The display panel 1 can be used in mobile phones, computers, wearable products or other devices with display functions.

[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, Includes a substrate and a driving circuit layer disposed on one side of the substrate; The driving circuit layer includes multiple pixel circuits, each including at least one first color pixel circuit, at least one second color pixel circuit, and at least one third color pixel circuit. The first color pixel circuit and the second color pixel circuit are adjacent to each other, and the third color pixel circuit and the second color pixel circuit are adjacent to each other. The second color pixel circuit and the adjacent third color pixel circuit are symmetrical about a second center line. The second center line is parallel to a first direction. The driving circuit layer further includes a first trace, a second trace, and a third trace, all extending along the first direction; the first trace corresponds to the first color pixel circuit; the second trace and the third trace are adjacent and located between the second color pixel circuit and the third color pixel circuit, the second trace corresponds to the second color pixel circuit, the third trace corresponds to the third color pixel circuit, and the signals of the second trace and the third trace are the same and interconnected.

2. The array substrate according to claim 1, characterized in that, The second color pixel circuit and the adjacent first color pixel circuit are symmetrical about the first center line; the first center line is parallel to the first direction; the first trace is located on the side of the first color pixel circuit away from the second color pixel circuit; Optionally, the second trace and the third trace are arranged in the same layer and made of the same material, and the second trace and the third trace are merged.

3. The array substrate according to claim 1, characterized in that, The plurality of pixel circuits includes a plurality of first color pixel circuits, a plurality of second color pixel circuits, and a plurality of third color pixel circuits; Multiple first color pixel circuits are arranged along the first direction to form at least one first color pixel circuit column; Multiple second-color pixel circuits are arranged along the first direction to form at least one second-color pixel circuit column; Multiple third color pixel circuits are arranged along the first direction to form at least one third color pixel circuit column; The first color pixel circuit column is adjacent to the second color pixel circuit column; the third color pixel circuit column is adjacent to the second color pixel circuit column; the second color pixel circuit column and the adjacent third color pixel circuit column are symmetrical about the second center line; The second trace and the third trace are located between the second color pixel circuit column and the third color pixel circuit column; Optionally, the second color pixel circuit column and the adjacent first color pixel circuit column are symmetrical about the first center line; the first center line is parallel to the first direction; the first trace is located on the side of the first color pixel circuit column away from the second color pixel circuit column; Optionally, a plurality of first color pixel circuits are arranged along the first direction to form a plurality of first color pixel circuit columns; Multiple columns of the first color pixel circuits are arranged along a second direction intersecting the first direction; Multiple second-color pixel circuits are arranged along the first direction to form multiple columns of second-color pixel circuits; Multiple columns of second-color pixel circuits are arranged along the second direction; Multiple third-color pixel circuits are arranged along the first direction to form multiple columns of third-color pixel circuits; Multiple columns of the third color pixel circuits are arranged along the second direction; Each of the first color pixel circuit columns, each of the second color pixel circuit columns, and each of the third color pixel circuit columns are arranged sequentially along the second direction.

4. The array substrate according to claim 1, characterized in that, The driving circuit layer further includes a connection portion extending along a first direction, the connection portion being located between the second trace and the third trace, and connecting the second trace and the third trace; Optionally, the connecting portion is disposed in the same layer and with the same material as the second trace; and the connecting portion is disposed in the same layer and with the same material as the third trace; Optionally, the second trace and the third trace are symmetrical about the second center line; the connecting portion is symmetrical about the second center line; Optionally, the second trace, the third trace, and the connecting portion are integrally formed; Optionally, the sum of the dimensions of the second trace, the third trace, and the connecting portion along the second direction is greater than the dimension of the first trace along the second direction; the second direction intersects the first direction; Optionally, the dimension of the first trace along the second direction is 1 to 3 μm; Optionally, the dimension of the second trace along the second direction is 1 to 3 μm; Optionally, the dimension of the third trace along the second direction is 1 to 3 μm; Optionally, the sum of the dimensions of the second trace, the third trace, and the connecting portion along the second direction is between 6 and 10 μm; Optionally, the first trace and the second trace are arranged in the same layer and made of the same material.

5. The array substrate according to claim 1, characterized in that, The driving circuit layer includes a first reference signal line extending along a second direction; the second direction intersects the first direction; at least one of the first trace, the second trace, and the third trace is connected to the first reference signal line; Optionally, the driving circuit layer includes multiple first traces arranged along a second direction; the first reference signal line is connected to multiple pixel circuits and to at least some of the first traces, and at least some of the first traces are connected to the corresponding first color pixel circuit.

6. The array substrate according to claim 5, characterized in that, The driving circuit layer also includes a second reference signal line extending along the second direction; the first reference signal line is connected to a portion of the first trace; the second reference signal line is connected to a plurality of the pixel circuits and to other portions of the first trace.

7. The array substrate according to claim 6, characterized in that, Some of the first traces are not connected to the first reference signal line, nor to the second reference signal line or the pixel circuit; the signal of some of the first traces is a low-level signal.

8. The array substrate according to claim 1, characterized in that, The driving circuit layer includes multiple second traces and multiple third traces; the multiple second traces are arranged along a second direction, and the multiple third traces are arranged along a second direction, the second direction intersecting with the first direction; At least some of the second traces are connected to the circuit corresponding to the second color pixel; at least some of the third traces are connected to the circuit corresponding to the third color pixel. Optionally, the signals of at least some of the second traces are the same as the signals of at least some of the first traces; Optionally, the signals of the second trace and the third trace are both reference signals or power signals.

9. The array substrate according to claim 8, characterized in that, The driving circuit layer further includes a plurality of first power signal lines extending along the first direction and a second power signal line extending along the second direction; the first power signal lines are connected to the pixel circuit; the second power signal lines are connected to the plurality of first power signal lines, at least a portion of the second traces, and at least a portion of the third traces; Optionally, the signals on the first power signal line and the second power signal line are high-level signals; Optionally, the plurality of first power signal lines include a first color power signal line, a second color power signal line, and a third color power signal line; the first color power signal line is connected to the first color pixel circuit; the second color power signal line is connected to the second color pixel circuit; and the third color power signal line is connected to the third color pixel circuit. Optionally, the second power signal line is connected to the plurality of first power signal lines, a portion of the second traces, and a portion of the third traces; Some of the second traces are not connected to the plurality of first power signal lines, nor to the second power signal lines or the pixel circuit; some of the third traces are not connected to the plurality of first power signal lines, nor to the second power signal lines or the pixel circuit; some of the second traces and some of the third traces are both low-level signals.

10. The array substrate according to claim 9, characterized in that, The driving circuit layer also includes multiple first data lines extending along the first direction; The plurality of first data lines include a first color data line, a second color data line, and a third color data line; the first color data line is connected to the first color pixel circuit; the second color data line is connected to the second color pixel circuit; and the third color data line is connected to the third color pixel circuit. Optionally, the first color power signal line is located between the first trace and the first color data line; the second color power signal line is located between the second trace and the second color data line; the third color power signal line is located between the third trace and the third color data line; the first color data line and the second color data line are arranged adjacent to each other. Optionally, the first color data line and the second color data line are symmetrical about the first center line, and the first center line is parallel to the first direction; Optionally, the first color power signal line and the second color power signal line are symmetrical about the first center line; Optionally, the second color power signal line and the third color power signal line are symmetrical about the second center line; Optionally, the second color data line and the third color data line are symmetrical about the second center line.

11. A display panel, characterized in that, The array substrate according to any one of claims 1 to 10.

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