Display panel and its manufacturing method, display device

Abstract

This application provides a display panel and its fabrication method, as well as a display device, solving the problem in the prior art where the carrier transport performance of different color sub-pixels is poor, resulting in the corresponding microcavity length not meeting requirements. This application provides a display panel including a substrate and multiple light-emitting devices, the multiple light-emitting devices being located on one side of the substrate; the multiple light-emitting devices include a first light-emitting device and a second light-emitting device, the first light-emitting device including a first carrier transport layer and a first light-emitting layer, the first light-emitting layer being located on the side of the first carrier transport layer facing away from the substrate; the second light-emitting device includes a stacked second carrier transport layer, a third carrier transport layer, and a second light-emitting layer, the third carrier transport layer being located on the side of the second carrier transport layer facing away from the substrate. This solution can improve the electrical performance of the light-emitting devices while optimizing the corresponding optical microcavity length.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to display panels and their manufacturing methods, and display devices. Background Technology

[0002] In the field of top-emitting quantum dot display panel technology, in order to achieve high color gamut and high resolution display, it is necessary to optimize the optical microcavity of sub-pixels with different emission colors to improve the luminous efficiency and color purity of each sub-pixel.

[0003] In related technologies, adjusting the thickness of the carrier transport layer is often used to fine-tune the cavity length of sub-pixels. However, this approach can negatively impact the carrier transport performance of the device. Furthermore, sub-pixels of different emission colors exhibit varying sensitivities to photosensitive materials. Therefore, there is a lack of technical solutions that can simultaneously achieve precise optical microcavity control while ensuring excellent electrical performance and luminous efficiency for each color of sub-pixel. Thus, optimizing the optical microcavity length for sub-pixels of different emission colors in top-emitting quantum dot display panels, without compromising carrier transport performance, has become a pressing technical problem in this field. Summary of the Invention

[0004] In view of this, the present application provides a display panel and its manufacturing method and display device, which solves the problem in the prior art that the carrier transport performance of different color sub-pixels is poor and causes the corresponding microcavity length to not meet the requirements.

[0005] This application provides a display panel, including a substrate and a plurality of light-emitting devices, the plurality of light-emitting devices being located on one side of the substrate; the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device, the first light-emitting device including a first carrier transport layer and a first light-emitting layer, the first light-emitting layer being located on the side of the first carrier transport layer facing away from the substrate; the second light-emitting device including a stacked second carrier transport layer, a third carrier transport layer and a second light-emitting layer, the third carrier transport layer being located on the side of the second carrier transport layer facing away from the substrate; the first carrier transport layer is cured under a first trigger condition, the second carrier transport layer is cured under the first trigger condition, the third carrier transport layer is cured under a second trigger condition, and the first carrier transport layer, the second carrier transport layer and the third carrier transport layer have the same function.

[0006] A second aspect of this application provides a display panel, including a substrate and a plurality of light-emitting devices, the plurality of light-emitting devices being located on one side of the substrate; each light-emitting device includes a first common layer; the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device, the first light-emitting device including a first light-emitting layer located on the side of the first common layer facing away from the substrate; the second light-emitting device includes a stacked third carrier transport layer and a second light-emitting layer, the third carrier transport layer being located on the side of the first common layer facing away from the substrate; the first common layer is cured under a first trigger condition, the third carrier transport layer is cured under a second trigger condition, and the first common layer and the third carrier transport layer have the same function.

[0007] A third aspect of this application provides a method for manufacturing a display panel, comprising: A first electrode and a second electrode are fabricated on one side of the substrate; A pixel defining layer is formed on the side of the first electrode and the second electrode away from the substrate. The pixel defining layer has a plurality of pixel openings, including a first pixel opening and a second pixel opening. A first common layer is formed on the side of the pixel defining layer opposite to the substrate; A second light-emitting device is obtained by fabricating a third carrier transport layer and a second light-emitting layer in the second pixel opening and on the side of the first common layer away from the substrate. A first light-emitting layer is prepared in the first pixel opening and on the side of the first common layer opposite to the substrate to obtain a first light-emitting device.

[0008] A fourth aspect of this application provides a display device comprising a display panel as described in any of the preceding claims, or a display panel prepared by the preparation method described above.

[0009] According to the display panel provided in the embodiments of this application, by setting the first light-emitting device to contain only a single-layer carrier transport layer (first carrier transport layer), and the second light-emitting device to contain a double-layer carrier transport layer (second and third carrier transport layers), and the third carrier transport layer is cured under a second triggering condition (such as light illumination) while the first and second carrier transport layers are cured under a first triggering condition (such as heating), different light-emitting devices can adopt different curing methods and layer structures. This allows for independent optimization of the thickness and material of the carrier transport layer for light-emitting devices of different colors, avoiding damage to the performance of specific color devices by a uniform structure, ensuring excellent electrical performance and luminous efficiency of each color sub-pixel, and facilitating the adjustment of the microcavity length of different color sub-pixels to better meet design requirements. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0011] Figure 2 This is a schematic diagram of the light-emitting structure in the first light-emitting device provided in the embodiments of this application.

[0012] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0013] Figure 4 This is a schematic diagram of the light-emitting structure in the second light-emitting device provided in the embodiments of this application.

[0014] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0015] Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0016] Figure 7 This is a planar schematic diagram of the first light-emitting device provided in an embodiment of this application.

[0017] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0018] Figure 9 This is a planar schematic diagram of the second light-emitting device provided in an embodiment of this application.

[0019] Figure 10 This is a schematic diagram of the structure of the first electrode provided in an embodiment of this application.

[0020] Figure 11 A comparative structural diagram of the first electrode and the second electrode provided in the embodiments of this application.

[0021] Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0022] Figure 13 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0023] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0024] Figure 15 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0025] Figure 16 A comparative structural diagram of the first electrode, second electrode, and third electrode provided in the embodiments of this application.

[0026] Figure 17 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0027] Figure 18 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application.

[0028] Figure 19 This is a schematic diagram of the structure of a display panel during the manufacturing process, as provided in an embodiment of this application.

[0029] Figure 20 This is a schematic diagram of the structure of a display panel during the manufacturing process, as provided in an embodiment of this application.

[0030] Figure 21 This is a schematic diagram of the structure of a display panel during the manufacturing process, as provided in an embodiment of this application.

[0031] Figure 22 This is a schematic diagram of the structure of a display panel during the manufacturing process, as provided in an embodiment of this application.

[0032] Figure 23 This is a schematic diagram of the structure of a display panel during the manufacturing process, as provided in an embodiment of this application.

[0033] Figure label: 100 - Display panel; 10 - Substrate; 20 - First light-emitting device; 21 - First carrier transport layer; 22 - First light-emitting layer; 221 - First central region; 222 - First edge region; 23 - First electrode; 231 - First conductive layer; 232 - First reflective layer; 233 - First inorganic layer; 234 - Second conductive layer; 24 - First light-emitting functional layer; 30-Second light-emitting device; 31-Second carrier transport layer; 32-Third carrier transport layer; 33-Second light-emitting layer; 331-Second central region; 332-Second edge region; 34-Second electrode; 341-Third conductive layer; 342-Second reflective layer; 343-Second inorganic layer; 344-Fourth conductive layer; 35-Second light-emitting functional layer; 40 - Third light-emitting device; 41 - Fourth carrier transport layer; 42 - Fifth carrier transport layer; 43 - Third light-emitting layer; 44 - Third electrode; 441 - Fifth conductive layer; 442 - Third reflective layer; 443 - Third inorganic layer; 444 - Sixth conductive layer; 50 - Pixel boundary layer; 51 - First pixel opening; 52 - Second pixel opening; 53 - Third pixel opening; 60 - First common layer; 70 - Fourth electrode. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0036] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0037] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0038] In the field of top-emission quantum dot display panels, to achieve full-color display, it is typically necessary to construct optical microcavities that meet design requirements for sub-pixels emitting different colors to improve luminous efficiency and color purity. A common approach in related technologies is to design a multi-layered luminescent functional layer structure and adjust the thickness of the hole transport layer to achieve microcavity length adjustment for different wavelengths. This approach works by using a solution method to form a uniformly thick luminescent functional layer, and then introducing a photolithographically oriented hole transport layer with adjustable thickness to compensate for the differences in optical cavity length between sub-pixels of different colors.

[0039] However, to achieve precise optical microcavity length, this approach requires a relatively thick photolithographic hole transport layer. The inherent charge transport characteristics of this organic material impair the device's carrier transport performance, leading to increased driving voltage and decreased luminous efficiency. Furthermore, the negative impact of introducing photolithographic materials on the performance of blue quantum dot materials is particularly pronounced, resulting in significantly lower luminous efficiency for blue photonic pixels compared to other colors.

[0040] To overcome the above contradictions, this application proposes a different technical approach, namely, by adopting differentiated carrier transport layer structures between sub-pixels of different emitting colors, it is possible to ensure that the electrical performance and luminous efficiency of each color sub-pixel are not affected by the carrier transport performance. At the same time, it is possible to perform precise optical microcavity optimization on sub-pixels of different emitting colors, so that the length of each microcavity meets the design requirements.

[0041] Please see Figures 1 to 4 This application provides a display panel 100, including a substrate 10 and a plurality of light-emitting devices. The plurality of light-emitting devices are located on one side of the substrate 10. The plurality of light-emitting devices include a first light-emitting device 20 and a second light-emitting device 30. The first light-emitting device 20 includes a first carrier transport layer 21 and a first light-emitting layer 22, with the first light-emitting layer 22 located on the side of the first carrier transport layer 21 facing away from the substrate 10. The second light-emitting device 30 includes a stacked second carrier transport layer 31, a third carrier transport layer 32, and a second light-emitting layer 33, with the third carrier transport layer 32 located on the side of the second carrier transport layer 31 facing away from the substrate 10. The first carrier transport layer 21 is cured under a first trigger condition, the second carrier transport layer 31 is cured under the first trigger condition, and the third carrier transport layer 32 is cured under a second trigger condition. The first carrier transport layer 21, the second carrier transport layer 31, and the third carrier transport layer 32 have the same function.

[0042] like Figure 1 As shown, the first light-emitting device 20 specifically includes a first electrode 23, a first light-emitting functional layer 24, and a fourth electrode 70. The second light-emitting device 30 specifically includes a second electrode 34, a second light-emitting functional layer 35, and a fourth electrode 70. Optionally, the first electrode 23 and the second electrode 34 can be anodes, and the fourth electrode 70 can be cathodes. The first light-emitting functional layer 24 is located between the first electrode 23 and the fourth electrode 70. The second light-emitting functional layer 35 is located between the second electrode 34 and the fourth electrode 70. Optionally, the first electrode 23 and the second electrode 34 can be cathodes, and the fourth electrode 70 can be anodes.

[0043] Figure 2 The specific structure of the first light-emitting functional layer 24 is shown in the figure. In this embodiment, the first carrier transport layer 21 and the first light-emitting layer 22 of the first light-emitting device 20 are located in the first light-emitting functional layer 24. Please refer to [link to relevant documentation]. Figure 2 The first light-emitting functional layer 24 specifically includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the substrate 10. Optionally, in this embodiment, the first carrier transport layer 21 may be an electron blocking layer EBL, and the first light-emitting layer 22 may be a light-emitting material layer EML.

[0044] For example, the first light-emitting functional layer 24 specifically includes a hole injection layer HIL, a hole transport layer HTL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along the direction away from the substrate 10. Optionally, in this embodiment, the first carrier transport layer 21 may be a hole transport layer HTL, and the first light-emitting layer 22 may be a light-emitting material layer EML.

[0045] For example, the first light-emitting functional layer 24 specifically includes an electron injection layer EIL, an electron transport layer ETL, a hole blocking layer HBL, a light-emitting material layer EML, a hole transport layer HTL, and a hole injection layer HIL stacked along a direction away from the substrate 10. Optionally, in this embodiment, the first carrier transport layer 21 may be a hole blocking layer HBL, and the first light-emitting layer 22 may be a light-emitting material layer EML.

[0046] For example, the first light-emitting functional layer 24 specifically includes an electron injection layer EIL, an electron transport layer ETL, a light-emitting material layer EML, a hole transport layer HTL, and a hole injection layer HIL stacked along a direction away from the substrate 10. Optionally, in this embodiment, the first carrier transport layer 21 may be an electron transport layer ETL, and the first light-emitting layer 22 may be a light-emitting material layer EML.

[0047] Figure 4 The diagram illustrates the specific structure of the second light-emitting functional layer 35. In this embodiment, the second carrier transport layer 31, the third carrier transport layer 32, and the second light-emitting layer 33 of the second light-emitting device 30 are located within this second light-emitting functional layer 35. Please refer to [link to documentation]. Figure 4 The second light-emitting functional layer 35 specifically includes a hole injection layer HIL, a hole transport layer HTL-1 and a hole transport layer HTL-2, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL, stacked along a direction away from the substrate 10. Optionally, in this embodiment, the second carrier transport layer 31 can be the hole transport layer HTL-1, the third carrier transport layer 32 can be the hole transport layer HTL-2, and the second light-emitting layer 33 can be the light-emitting material layer EML.

[0048] For example, as explained above, the second carrier transport layer 31 can be an electron blocking layer, and the third carrier transport layer 32 can be an electron blocking layer; or, the second carrier transport layer 31 can be a hole blocking layer, and the third carrier transport layer 32 can be a hole blocking layer; or, the second carrier transport layer 31 can be an electron transport layer, and the third carrier transport layer 32 can be an electron transport layer.

[0049] Please see Figure 3 In order to clearly show the specific locations of the first carrier transport layer 21 and the first light-emitting layer 22 in the first light-emitting device 20, and the second carrier transport layer 31, the third carrier transport layer 32 and the second light-emitting layer 33 in the second light-emitting device 30, other specific film layer refinement structures shown in the above figures are omitted in this figure, and only the part of the structure required for the core inventive point is retained.

[0050] Optionally, the first light-emitting layer 22 includes a first quantum dot, and the second light-emitting layer 33 includes a second quantum dot. The quantum dot material can achieve high color purity luminescence, and its emission wavelength can be precisely controlled by adjusting the size of the quantum dot. Optionally, the first quantum dot is, for example, a blue light-emitting quantum dot, and the second quantum dot is, for example, a red light-emitting quantum dot. The first light-emitting layer 22 is provided with one carrier transport layer (first carrier transport layer 21), and the second light-emitting layer 33 is provided with two carrier transport layers (second carrier transport layer 31 and third carrier transport layer 32).

[0051] Optionally, the first carrier transport layer 21 is cured under the first triggering condition, the second carrier transport layer 31 is cured under the first triggering condition, and the third carrier transport layer 32 is cured under the second triggering condition. The first carrier transport layer 21, the second carrier transport layer 31, and the third carrier transport layer 32 have the same function, for example, they are all hole transport layers and can all transport holes. The only difference is that the material properties of the carrier transport layers obtained under different triggering conditions are different.

[0052] For example, the first triggering condition includes heating treatment, and the second triggering condition includes light irradiation treatment. Correspondingly, the first carrier transport layer 21 and the second carrier transport layer 31 can be thermally cross-linked hole transport layers, and the third carrier transport layer 32 can be photocross-linked hole transport layers. In this embodiment, it is mainly considered that the photocross-linked hole transport layer would affect the light emission of the first light-emitting device 20 (blue light-emitting device). Therefore, the first carrier transport layer 21 (thermally cross-linked hole transport layer) is only provided in the first light-emitting device 20, while the second light-emitting device 30 (red light-emitting device) is provided with both the second carrier transport layer 31 (thermally cross-linked hole transport layer) and the third carrier transport layer 32 (photocross-linked hole transport layer).

[0053] Optionally, the thickness range of the first carrier transport layer 21 and the second carrier transport layer 31 can be set to be greater than or equal to 20 nm and less than or equal to 60 nm (e.g., 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, etc.). Optionally, the thickness of the first carrier transport layer 21 and the second carrier transport layer 31 can be greater than or equal to 30 nm and less than or equal to 50 nm (e.g., 30 nm, 40 nm, 50 nm, etc.). The thickness range of the third carrier transport layer 32 can be set to be greater than or equal to 10 nm and less than or equal to 80 nm (e.g., 10 nm, 28 nm, 46 nm, 64 nm, 80 nm, etc.).

[0054] Optionally, the thickness of the third carrier transport layer 32 is greater than or equal to 10 nm and less than or equal to 30 nm (e.g., 10 nm, 20 nm, 30 nm, etc.). This thickness range ensures that the third carrier transport layer 32 can provide stable hole transport performance, while leaving sufficient space for optical microcavity adjustment. Furthermore, the thinner thickness of the third carrier transport layer 32 helps reduce the impact of the etching solution on the sidewalls of the third carrier transport layer 32 during the development process of the third carrier transport layer 32 or the second light-emitting layer. The specific thickness of each film layer in light-emitting devices of different colors can be set according to the following table.

[0055] In this embodiment, the first light-emitting device 20 is configured to contain only a single-layer carrier transport layer (first carrier transport layer 21), and the second light-emitting device 30 is configured to contain a double-layer carrier transport layer (second carrier transport layer 31 and third carrier transport layer 32). The third carrier transport layer 32 is cured under a second triggering condition (such as light illumination), while the first carrier transport layer 21 and the second carrier transport layer 31 are cured under a first triggering condition (such as heating). This allows different light-emitting devices to adopt different curing methods and layer structures, thereby enabling independent optimization of the thickness and material of the carrier transport layer for light-emitting devices of different colors. This avoids damage to the performance of specific color devices by a uniform structure, ensuring excellent electrical performance and luminous efficiency of each color sub-pixel. At the same time, it facilitates the adjustment of the microcavity length of different color sub-pixels, enabling them to better meet design requirements.

[0056] In one embodiment, see Figure 5 The orthographic projection of the third carrier transport layer 32 onto the substrate 10 lies within the orthographic projection range of the second light-emitting layer 33 onto the substrate 10. The second light-emitting layer 33 covers at least a portion of the sidewalls of the third carrier transport layer 32.

[0057] Optionally, the display panel 100 further includes a pixel defining layer 50. The pixel defining layer 50 is located on one side of the substrate 10. The pixel defining layer 50 has a plurality of pixel openings. The plurality of pixel openings includes a first pixel opening 51 and a second pixel opening 52. At least a portion of the first carrier transport layer 21 and at least a portion of the first light-emitting layer 22 are located within the first pixel opening 51, and at least a portion of the second carrier transport layer 31, at least a portion of the third carrier transport layer 32, and at least a portion of the second light-emitting layer 33 are located within the second pixel opening 52. The distance from the end of the third carrier transport layer 32 away from the substrate 10 to the substrate 10 is less than the distance from the surface of the pixel defining layer 50 away from the substrate 10 to the substrate 10.

[0058] Optionally, a portion of the second light-emitting layer 33 is in direct contact with the second carrier transport layer 31 located on the sidewall of the pixel defining layer 50.

[0059] Optionally, the sidewalls of the third carrier transport layer 32 are arc-shaped, and the increase in the spacing between the sidewalls of the third carrier transport layer 32 and the sidewalls of the pixel boundary layer 50 increases along a direction perpendicular to and away from the sidewalls of the pixel boundary layer 50.

[0060] In this embodiment, the positional relationship between the third carrier transport layer 32 and the second light-emitting layer 33, as well as the structure of the pixel defining layer 50, are defined in detail. The orthographic projection of the third carrier transport layer 32 onto the substrate 10 lies within the orthographic projection range of the second light-emitting layer 33 onto the substrate 10. The second light-emitting layer 33 covers at least a portion of the sidewalls of the third carrier transport layer 32. This covering structure ensures that the third carrier transport layer 32 is completely surrounded by the second light-emitting layer 33, preventing the edges of the third carrier transport layer 32 from being exposed to the external environment, thereby reducing carrier leakage channels and providing a certain degree of isolation and protection for the third carrier transport layer 32. Furthermore, it can effectively prevent the etching solution used in the fabrication of the light-emitting device in subsequent processes from affecting the third carrier transport layer 32.

[0061] Optionally, the display panel 100 further includes a pixel defining layer 50. The pixel defining layer 50 is located on one side of the substrate 10. The pixel defining layer 50 has a plurality of pixel openings. The plurality of pixel openings includes a first pixel opening 51 and a second pixel opening 52. At least a portion of the first carrier transport layer 21 and at least a portion of the first light-emitting layer 22 are located within the first pixel opening 51. At least a portion of the second carrier transport layer 31, at least a portion of the third carrier transport layer 32, and at least a portion of the second light-emitting layer 33 are located within the second pixel opening 52. The distance from the end of the third carrier transport layer 32 away from the substrate 10 to the substrate 10 is less than the distance from the surface of the pixel defining layer 50 away from the substrate 10 to the substrate 10. This means that the third carrier transport layer 32 is completely contained within the pixel opening and does not exceed the height of the pixel defining layer 50, thereby simplifying subsequent patterning processes. In addition, the orthographic projection of the third carrier transport layer 32 on the substrate 10 can be located within the orthographic projection range of the second light-emitting layer 33 on the substrate 10, which can effectively avoid the influence of the etching solution used in the fabrication process of the light-emitting device in subsequent processes on the third carrier transport layer 32.

[0062] Optionally, a portion of the second light-emitting layer 33 directly contacts the third carrier transport layer 32 located on the sidewall of the pixel defining layer 50. This facilitates the stable adhesion of the second light-emitting layer 33 to the third carrier transport layer 32 and prevents film peeling. The sidewall of the third carrier transport layer 32 is arc-shaped, and the increase in the distance between the sidewall of the third carrier transport layer 32 and the sidewall of the pixel defining layer 50 increases along a direction perpendicular to and away from the sidewall of the pixel defining layer 50. This arc-shaped sidewall design helps to form a smooth contour during the development process, reduces photoresist residue, and improves pattern accuracy. For example, during the development process, the third carrier transport layer 32, as a photocrosslinked hole transport material, is cured in the ultraviolet irradiation area, and the uncured area is dissolved. The gradual curvature of the arc-shaped sidewall helps the developer penetrate evenly and avoids residue formation at the root of the sidewall.

[0063] In one embodiment, see Figure 6 and Figure 7 The first light-emitting layer 22 located within the first pixel opening 51 includes a first central region 221 and a first edge region 222. The first edge region 222 surrounds at least a portion of the first central region 221. The thickness of the first edge region 222 is greater than the thickness of the first central region 221.

[0064] Optionally, the thickness of the first light-emitting layer 22 located on the sidewall of the pixel defining layer 50 is less than the thickness of the first central region 221.

[0065] Optionally, the second light-emitting layer 33 located within the second pixel opening 52 includes a second central region 331 and a second edge region 332. The second edge region 332 surrounds at least a portion of the second central region 331. The thickness of the second edge region 332 is greater than the thickness of the second central region 331.

[0066] Optionally, the thickness of the second light-emitting layer 33 located on the sidewall of the pixel defining layer 50 is less than the thickness of the second central region 331.

[0067] In this embodiment, the thickness distribution of the light-emitting layer within the pixel opening is described in detail. The first light-emitting layer 22 located within the first pixel opening 51 includes a first central region 221 and a first edge region 222. The first edge region 222 surrounds at least a portion of the first central region 221. The thickness of the first edge region 222 is greater than the thickness of the first central region 221. This thickness difference originates from the edge accumulation effect during the drying or film formation process of the light-emitting layer inside the pixel opening, i.e., the solution accumulates at the corners of the opening due to surface tension, forming a thicker film layer.

[0068] For example, when using inkjet printing, the quantum dot solution exhibits different solvent evaporation rates at the sidewalls of the pixel defining layer 50 due to differences in contact angle, causing solute to migrate towards the edges and forming a thickness gradient. The thickness of the first light-emitting layer 22 located on the sidewalls of the pixel defining layer 50 is less than the thickness of the first central region 221. This indicates that the first light-emitting layer 22 has a thinner coverage on the sidewalls of the pixel defining layer 50, which helps to avoid excessively thick film layers at the sidewalls, thus preventing optical interference or color crosstalk.

[0069] Similarly, such as Figure 8 and Figure 9 As shown, the second light-emitting layer 33 located within the second pixel opening 52 includes a second central region 331 and a second edge region 332. The second edge region 332 surrounds at least a portion of the second central region 331. The thickness of the second edge region 332 is greater than the thickness of the second central region 331. The thickness of the second light-emitting layer 33 located on the sidewall of the pixel defining layer 50 is less than the thickness of the second central region 331. This design makes the thickness distribution of the light-emitting layer within the pixel opening more uniform, which is beneficial for improving luminous efficiency and reducing crosstalk between pixels.

[0070] In one embodiment, see Figure 8 and Figure 10 The first light-emitting device 20 further includes a first electrode 23. The first electrode 23 is located between the first carrier transport layer 21 and the substrate 10. The first electrode 23 includes a first conductive layer 231, a first reflective layer 232, a first inorganic layer 233, and a second conductive layer 234 stacked together. The second conductive layer 234 is located on the side of the first inorganic layer 233 closer to the first carrier transport layer 21. The first conductive layer 231 and the second conductive layer 234 are electrically connected.

[0071] Optionally, the thickness of the first conductive layer 231 is greater than or equal to 15 nm (e.g., it can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.), and / or the thickness of the second conductive layer 234 is greater than or equal to 15 nm (e.g., it can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.).

[0072] Optionally, please refer to Figure 8 and Figure 11 The second light-emitting device 30 further includes a second electrode 34. The second electrode 34 is located between the second carrier transport layer 31 and the substrate 10. The second electrode 34 includes a stacked third conductive layer 341, a second reflective layer 342, a second inorganic layer 343, and a fourth conductive layer 344. The fourth conductive layer 344 is located on the side of the second inorganic layer 343 near the second carrier transport layer 31. The third conductive layer 341 and the fourth conductive layer 344 are electrically connected.

[0073] Optionally, such as Figure 11 As shown, the thickness of the first inorganic layer 233 is less than the thickness of the second inorganic layer 343.

[0074] Optionally, the thickness of the third conductive layer 341 is greater than or equal to 15 nm (e.g., it can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.), and / or the thickness of the fourth conductive layer 344 is greater than or equal to 15 nm (e.g., it can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.).

[0075] In this embodiment, an electrode structure is introduced to achieve precise adjustment of the optical microcavity. The first light-emitting device 20 also includes a first electrode 23. The first electrode 23 is located between the first carrier transport layer 21 and the substrate 10. The first electrode 23 includes a stacked first conductive layer 231, a first reflective layer 232, a first inorganic layer 233, and a second conductive layer 234. The second conductive layer 234 is located on the side of the first inorganic layer 233 closer to the first carrier transport layer 21. The first conductive layer 231 and the second conductive layer 234 are electrically connected.

[0076] Optionally, the thickness of the first conductive layer 231 is greater than or equal to 15 nm (e.g., 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.), and the thickness of the second conductive layer 234 is greater than or equal to 15 nm (e.g., 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.), and can be made of transparent indium tin oxide (ITO). This thickness setting ensures reliable electrical connection and etching resistance of the conductive layers, preventing the first electrode 23 (e.g., the anode) from disconnecting. The first reflective layer 232 is, for example, silver or aluminum, with a reflectivity greater than 90%, used to reflect the light emitted by the light-emitting layer in the direction of light emission.

[0077] Optionally, the first inorganic layer 233 is a silicon nitride layer. The first inorganic layer 233 is located between the first conductive layer 231 and the second conductive layer 234, forming a sandwich structure. This structure allows the first inorganic layer 233 in the first electrode 23 to provide compensation for the optical cavity length, and since the first inorganic layer 233 does not participate in carrier transport, it will not have a negative impact on the electrical performance of the device.

[0078] Similarly, the second light-emitting device 30 also includes a second electrode 34. The second electrode 34 is located between the second carrier transport layer 31 and the substrate 10. The second electrode 34 includes a stacked third conductive layer 341, a second reflective layer 342, a second inorganic layer 343, and a fourth conductive layer 344. The fourth conductive layer 344 is located on the side of the second inorganic layer 343 near the second carrier transport layer 31.

[0079] For example, the third conductive layer 341 is electrically connected to the fourth conductive layer 344. The thickness of the third conductive layer 341 is greater than or equal to 15 nm, and the thickness of the fourth conductive layer 344 is greater than or equal to 15 nm (e.g., it can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.), and it can be made of transparent ITO material. This thickness setting ensures reliable electrical connection and etching resistance of the conductive layers, avoiding the possibility of disconnection of the second electrode 34 (e.g., it can be an anode). The second reflective layer 342 is, for example, silver or aluminum, with a reflectivity greater than 90%, used to reflect the light emitted by the light-emitting layer in the light-emitting direction.

[0080] Optionally, such as Figure 11 As shown, the thickness of the first inorganic layer 233 is less than the thickness of the second inorganic layer 343. This thickness difference is used to compensate for the cavity length difference between sub-pixels of different emission colors due to different emission wavelengths. For the blue sub-pixel (first light-emitting device 20), the required cavity length is shorter, so the thickness of the first inorganic layer 233 is thinner; for the red sub-pixel (second light-emitting device 30), the required cavity length is longer, so the thickness of the second inorganic layer 343 is thicker.

[0081] In one embodiment, the first inorganic layer 233 satisfies at least one of the following conditions: a refractive index greater than or equal to 1.6 and less than or equal to 2.1 (e.g., it can be 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, etc.), and a light transmittance greater than or equal to 90% in the wavelength range of 440 nm to 680 nm.

[0082] Optionally, the second inorganic layer 343 satisfies at least one of the following conditions: a refractive index greater than or equal to 1.6 and less than or equal to 2.1 (e.g., it can be 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, etc.), and a light transmittance greater than or equal to 90% in the wavelength range of 440 nm to 680 nm.

[0083] This optical property ensures that the inorganic layer has high transmittance in the visible light band, while its refractive index matches that of the adjacent conductive layer (such as ITO, with a refractive index of approximately 1.8), which helps reduce interface reflection. The materials of the first inorganic layer 233 and the second inorganic layer 343 are, for example, silicon nitride (SiNx) or silicon oxide (SiOx). Silicon nitride has high transmittance and a suitable refractive index in the visible light band, and also possesses good insulating properties, making it suitable as an optical compensation layer. Furthermore, silicon nitride exhibits better film uniformity and surface roughness than ITO; using silicon nitride as a planarization layer can repair surface roughness caused by anodic etching and prevent anodic disconnection.

[0084] In one embodiment, see Figure 12The plurality of light-emitting devices also includes a third light-emitting device 40. The third light-emitting device 40 includes a fourth carrier transport layer 41, a fifth carrier transport layer 42, and a third light-emitting layer 43 stacked together. The fourth carrier transport layer 41 is cured under a first triggering condition, and the fifth carrier transport layer 42 is cured under a second triggering condition. The fourth carrier transport layer 41 and the fifth carrier transport layer 42 have the same function as the first carrier transport layer 21.

[0085] Optionally, such as Figure 13 As shown, the thickness of the third carrier transport layer 32 is greater than or equal to the thickness of the fifth carrier transport layer 42.

[0086] Optionally, the third light-emitting layer 43 includes a third quantum dot.

[0087] Optionally, the thickness of the fifth carrier transport layer 42 is greater than or equal to 10 nm and less than or equal to 80 nm (e.g., it can be 10 nm, 28 nm, 46 nm, 64 nm, 80 nm, etc.).

[0088] Optionally, the thickness of the fifth carrier transport layer 42 is greater than or equal to 10 nm and less than or equal to 30 nm (e.g., it can be 10 nm, 20 nm, 30 nm, etc.). This thickness range ensures that the fifth carrier transport layer 42 can provide stable hole transport performance, while leaving sufficient space for optical microcavity adjustment. In addition, the thinner thickness of the fifth carrier transport layer 42 helps to reduce the influence of the etching solution on the sidewalls of the third carrier transport layer 32 during the development of the fifth carrier transport layer 42 or the third light-emitting layer.

[0089] In this embodiment, the plurality of light-emitting devices further includes a third light-emitting device 40. The third light-emitting device 40 includes a stacked fourth carrier transport layer 41, a fifth carrier transport layer 42, and a third light-emitting layer 43. The fourth carrier transport layer 41 is cured under a first triggering condition, and the fifth carrier transport layer 42 is cured under a second triggering condition. The fourth carrier transport layer 41 and the fifth carrier transport layer 42 have the same function as the first carrier transport layer 21, for example, they are both hole transport layers.

[0090] For example, the fourth carrier transport layer 41, the first carrier transport layer, and the second carrier transport layer are a single common layer.

[0091] It is understandable that the required remaining cavity lengths of the second and third light-emitting devices can be calculated by using the thickness of the common layer or the thickness of the first carrier transport layer of the first light-emitting device (blue light-emitting device) as a reference, and then compensated within the thickness of the anode according to the total cavity length of different light-emitting devices.

[0092] Optionally, the third light-emitting layer 43 includes a third quantum dot, such as a green light-emitting quantum dot. Quantum dot materials can achieve high color purity luminescence, and their emission wavelength can be precisely controlled by adjusting the quantum dot size. The first triggering condition includes heat treatment, and the second triggering condition includes light irradiation.

[0093] Optionally, such as Figure 13 As shown, the thickness of the third carrier transport layer 32 is greater than or equal to the thickness of the fifth carrier transport layer 42. This thickness difference is used to finely adjust the microcavity length of different color subpixels. The aforementioned thickness range ensures that the fifth carrier transport layer 42 can provide stable hole transport performance, while leaving sufficient space for optical microcavity adjustment in the fifth carrier transport layer 42.

[0094] In one embodiment, see Figure 14 The orthographic projection of the fifth carrier transport layer 42 onto the substrate 10 lies within the orthographic projection range of the third light-emitting layer 43 onto the substrate 10. The third light-emitting layer 43 covers at least a portion of the sidewalls of the fifth carrier transport layer 42. This effectively avoids the influence of the etching solution used in the fabrication of the light-emitting device in subsequent processes on the fifth carrier transport layer 42.

[0095] Optionally, the display panel 100 further includes a pixel defining layer 50. The pixel defining layer 50 is located on one side of the substrate 10. The pixel defining layer 50 has a plurality of pixel openings. The plurality of pixel openings include a first pixel opening 51, a second pixel opening 52, and a third pixel opening 53. At least a portion of the first carrier transport layer 21 and at least a portion of the first light-emitting layer 22 are located within the first pixel opening 51. At least a portion of the second carrier transport layer 31, at least a portion of the third carrier transport layer 32, and at least a portion of the second light-emitting layer 33 are located within the second pixel opening 52. At least a portion of the fourth carrier transport layer 41, at least a portion of the fifth carrier transport layer 42, and at least a portion of the third light-emitting layer 43 are located within the second pixel opening 52. The distance from the end of the third carrier transport layer 32 away from the substrate 10 to the substrate 10 is less than the distance from the surface of the pixel defining layer 50 away from the substrate 10 to the substrate 10; and / or, the distance from the end of the fifth carrier transport layer 42 away from the substrate 10 to the substrate 10 is less than the distance from the surface of the pixel defining layer 50 away from the substrate 10 to the substrate 10.

[0096] Optionally, a portion of the second light-emitting layer 33 is in direct contact with the second carrier transport layer 31 located on the sidewall of the pixel defining layer 50; and / or, a portion of the third light-emitting layer 43 is in direct contact with the fourth carrier transport layer 41 located on the sidewall of the pixel defining layer 50.

[0097] Optionally, the sidewalls of the fifth carrier transport layer 42 are arc-shaped. Along a direction perpendicular to and away from the sidewalls of the pixel defining layer 50, the increase in the distance between the sidewalls of the fifth carrier transport layer 42 and the sidewalls of the pixel defining layer 50 becomes larger.

[0098] In this embodiment, the positional relationship between the fifth carrier transport layer 42 and the third light-emitting layer 43, as well as the structure of the pixel defining layer 50, are defined in detail. The orthographic projection of the fifth carrier transport layer 42 onto the substrate 10 lies within the orthographic projection range of the third light-emitting layer 43 onto the substrate 10. The third light-emitting layer 43 covers at least a portion of the sidewalls of the fifth carrier transport layer 42. This covering structure ensures that the fifth carrier transport layer 42 is completely surrounded by the third light-emitting layer 43, preventing the edges of the fifth carrier transport layer 42 from being exposed to the external environment, thereby reducing carrier leakage channels and providing a certain degree of isolation and protection for the fifth carrier transport layer 42. Furthermore, it can effectively prevent the etching solution used in the fabrication of subsequent light-emitting devices from affecting the fifth carrier transport layer 42.

[0099] For example, multiple light-emitting devices are prepared in the order of preparation of the second light-emitting device, the third light-emitting device, and the first light-emitting device.

[0100] Optionally, the display panel 100 further includes a pixel defining layer 50. The pixel defining layer 50 is located on one side of the substrate 10. The pixel defining layer 50 has a plurality of pixel openings. The plurality of pixel openings include a first pixel opening 51, a second pixel opening 52, and a third pixel opening 53. At least a portion of the first carrier transport layer 21 and at least a portion of the first light-emitting layer 22 are located within the first pixel opening 51. At least a portion of the second carrier transport layer 31, at least a portion of the third carrier transport layer 32, and at least a portion of the second light-emitting layer 33 are located within the second pixel opening 52. At least a portion of the fourth carrier transport layer 41, at least a portion of the fifth carrier transport layer 42, and at least a portion of the third light-emitting layer 43 are located within the third pixel opening 53.

[0101] For example, the distance from the end of the third carrier transport layer 32 away from the substrate 10 to the substrate 10 is less than the distance from the surface of the pixel defining layer 50 away from the substrate 10 to the substrate 10; and / or, the distance from the end of the fifth carrier transport layer 42 away from the substrate 10 to the substrate 10 is less than the distance from the surface of the pixel defining layer 50 away from the substrate 10 to the substrate 10. This means that the third carrier transport layer 32 and the fifth carrier transport layer 42 are completely contained within the pixel opening and do not exceed the height of the pixel defining layer 50, thereby simplifying subsequent patterning processes.

[0102] Optionally, a portion of the second light-emitting layer 33 is in direct contact with the second carrier transport layer 31 located on the sidewall of the pixel defining layer 50; and / or, a portion of the third light-emitting layer 43 is in direct contact with the fourth carrier transport layer 41 located on the sidewall of the pixel defining layer 50. This facilitates the stable adhesion of the second and third light-emitting layers 33 to the sidewall of the pixel defining layer 50, preventing film detachment. It also helps to avoid further etching of the second and fourth carrier transport layers 31 by the etching solution.

[0103] Optionally, such as Figure 14 As shown, the sidewalls of the fifth carrier transport layer 42 are arc-shaped. Along a direction perpendicular to and away from the sidewalls of the pixel defining layer 50, the increase in the distance between the sidewalls of the fifth carrier transport layer 42 and the sidewalls of the pixel defining layer 50 increases. This arc-shaped sidewall design facilitates the formation of a smooth contour during development, reduces photoresist residue, and improves pattern accuracy. For example, during development, the fifth carrier transport layer 42, as a photocrosslinked hole transport material, solidifies in the ultraviolet irradiation area, and the unsolidified areas dissolve. The gradual curvature of the arc-shaped sidewalls helps the developer penetrate evenly, avoiding residue formation at the root of the sidewalls.

[0104] In one embodiment, see Figure 15 The distance between the edge of the orthographic projection of the third carrier transport layer 32 on the substrate 10 and the edge of the orthographic projection of the second light-emitting layer 33 on the substrate 10 is the first distance D1. The distance between the edge of the orthographic projection of the fifth carrier transport layer 42 on the substrate 10 and the edge of the orthographic projection of the third light-emitting layer 43 on the substrate 10 is the second distance D2. The first distance D1 is greater than the second distance D2.

[0105] In this embodiment, the edge spacing relationship between the third carrier transport layer 32 and the fifth carrier transport layer 42 and their respective light-emitting layers is further defined. According to the aforementioned size relationship, this indicates that the edge of the photosensitive hole transport layer (third carrier transport layer 32) in the second light-emitting device 30 is farther from the edge of the light-emitting layer, while the edge of the photosensitive hole transport layer (fifth carrier transport layer 42) in the third light-emitting device 40 is closer to the edge of the light-emitting layer. This spacing difference can be used to adjust the precision of the optical microcavities of different color sub-pixels. For the red light device (second light-emitting device 30), since a longer optical cavity length is required, the edge of the photosensitive hole transport layer is appropriately farther from the edge of the light-emitting layer, which helps to reduce cavity length deviation caused by edge effects; for the green light device (third light-emitting device 40), since the cavity length is shorter, the photosensitive hole transport layer is closer to the edge of the light-emitting layer, allowing for more precise control of the microcavity.

[0106] It is understandable that when multiple light-emitting devices are fabricated in the order of the second light-emitting device, the third light-emitting device, and the first light-emitting device, the third carrier transport layer 32 corresponding to the second light-emitting device will be further etched by the etching used to fabricate the third light-emitting device and the first light-emitting device. This results in the edge of the photosensitive hole transport layer (third carrier transport layer 32) in the second light-emitting device 30 being farther from the edge of the light-emitting layer, while the edge of the photosensitive hole transport layer (fifth carrier transport layer 42) in the third light-emitting device 40 is closer to the edge of the light-emitting layer.

[0107] In one embodiment, see Figure 15 and Figure 16 The third light-emitting device 40 also includes a third electrode 44. The third electrode 44 is located between the fourth carrier transport layer 41 and the substrate 10. The third electrode 44 includes a fifth conductive layer 441, a third reflective layer 442, a third inorganic layer 443, and a sixth conductive layer 444 stacked together. The sixth conductive layer 444 is located on the side of the third inorganic layer 443 near the fourth carrier transport layer 41. The fifth conductive layer 441 and the sixth conductive layer 444 are electrically connected.

[0108] Optionally, the thickness of the fifth conductive layer 441 is greater than or equal to 15 nm (e.g., it can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.), and / or the thickness of the sixth conductive layer 444 is greater than or equal to 15 nm (e.g., it can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.). This avoids the possibility of the third electrode 44 (e.g., it can be an anode) being disconnected.

[0109] Optionally, the second light-emitting device 30 further includes a second electrode 34. The second electrode 34 is located between the second carrier transport layer 31 and the substrate 10. The second electrode 34 includes a stacked third conductive layer 341, a second reflective layer 342, a second inorganic layer 343, and a fourth conductive layer 344. The fourth conductive layer 344 is located on the side of the second inorganic layer 343 closest to the second carrier transport layer 31. The third conductive layer 341 and the fourth conductive layer 344 are electrically connected. The thickness of the third inorganic layer 343 is less than the thickness of the second inorganic layer 343.

[0110] Optionally, the first light-emitting device 20 further includes a first electrode 23. The first electrode 23 is located between the first carrier transport layer 21 and the substrate 10. The first electrode 23 includes a first conductive layer 231, a first reflective layer 232, a first inorganic layer 233, and a second conductive layer 234 stacked together. The second conductive layer 234 is located on the side of the first inorganic layer 233 closer to the first carrier transport layer 21. The first conductive layer 231 and the second conductive layer 234 are electrically connected. The thickness of the first inorganic layer 233 is less than the thickness of the third inorganic layer 443.

[0111] Optionally, the thickness of the second conductive layer 234 is less than the thickness of the sixth conductive layer 444, and / or the thickness of the sixth conductive layer 444 is less than the thickness of the fourth conductive layer 344.

[0112] In this embodiment, an electrode structure is introduced to achieve precise adjustment of the optical microcavity. The third light-emitting device 40 also includes a third electrode 44. The third electrode 44 is located between the fourth carrier transport layer 41 and the substrate 10. The third electrode 44 includes a stacked fifth conductive layer 441, a third reflective layer 442, a third inorganic layer 443, and a sixth conductive layer 444. The sixth conductive layer 444 is located on the side of the third inorganic layer 443 near the fourth carrier transport layer 41. The fifth conductive layer 441 and the sixth conductive layer 444 are electrically connected.

[0113] Optionally, the thickness of the fifth conductive layer 441 is greater than or equal to 15 nm, and the thickness of the sixth conductive layer 444 is greater than or equal to 15 nm, and they can be made of transparent ITO material. This thickness setting ensures reliable electrical connection and etching resistance of the conductive layers. The third reflective layer 442 is, for example, silver or aluminum, with a reflectivity greater than 90%, and is used to reflect the light emitted by the light-emitting layer in the direction of light emission.

[0114] Optionally, the third inorganic layer 443 is a silicon nitride layer. The third inorganic layer 443 is located between the fifth conductive layer 441 and the sixth conductive layer 444, forming a sandwich structure. This structure allows the third inorganic layer 443 in the third electrode 44 to provide compensation for the optical cavity length, and since the third inorganic layer 443 does not participate in carrier transport, it will not have a negative impact on the electrical performance of the device.

[0115] Similarly, the second light-emitting device 30 also includes a second electrode 34. The first light-emitting device 20 also includes a first electrode 23. The specific structures of the first electrode 23 and the second electrode 34 have been described in the above embodiment. For details, please refer to the above embodiment. The specific structure is similar to that of the third electrode 44, and will not be repeated here.

[0116] Optionally, such as Figure 16 As shown, the thickness of the third inorganic layer 443 is less than the thickness of the second inorganic layer 343. This thickness difference is used to compensate for the cavity length difference between sub-pixels of different emission colors caused by different emission wavelengths. For the green sub-pixel (third light-emitting device 40), the required cavity length is shorter, so the thickness of the third inorganic layer 443 is thinner; for the red sub-pixel (second light-emitting device 30), the required cavity length is longer, so the thickness of the second inorganic layer 343 is thicker.

[0117] Optionally, the thickness of the first inorganic layer 233 is less than the thickness of the third inorganic layer 443. This thickness difference is used to compensate for the cavity length difference between sub-pixels of different emission colors due to different emission wavelengths. For the blue sub-pixel (first light-emitting device 20), the required cavity length is shorter, so the thickness of the first inorganic layer 233 is thinner; for the green sub-pixel (third light-emitting device 40), the required cavity length is longer, so the thickness of the third inorganic layer 443 is thicker.

[0118] Optionally, the thickness of the second conductive layer 234 is less than the thickness of the sixth conductive layer 444, and / or the thickness of the sixth conductive layer 444 is less than the thickness of the fourth conductive layer 344. This thickness difference stems from the varying degrees to which the anodes of different color sub-pixels are exposed during subsequent etching processes, resulting in different conductive layer losses. The anode structure of the red pixel is the thickest, and its top conductive layer experiences the least etching loss, thus the fourth conductive layer 344 has the largest final thickness; the green pixel is next, and the blue pixel has the smallest. This differentiated design ensures the consistency of the electrode structure of each sub-pixel throughout the overall process. The first conductive layer 231, the third conductive layer 341, and the fifth conductive layer 441 are all transparent conductive oxides such as ITO, each with a thickness of 15 nm. Because they are located below the reflective layer, they are not affected by etching, thus maintaining a consistent thickness. The electrode thicknesses in different color light-emitting devices can be set according to the following table.

[0119] In one embodiment, the third inorganic layer 443 satisfies at least one of the following conditions: a refractive index greater than or equal to 1.6 and less than or equal to 2.1 (e.g., it can be 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, etc.), and a light transmittance greater than or equal to 90% in the wavelength range of 440 nm to 680 nm.

[0120] This optical property ensures that the inorganic layer has high transmittance in the visible light band, while its refractive index matches that of the adjacent conductive layer (such as ITO, with a refractive index of approximately 1.8), which helps reduce interface reflection. The material of the third inorganic layer 443 is, for example, silicon nitride (SiNx) or silicon oxide (SiOx). Silicon nitride has high transmittance and a suitable refractive index in the visible light band, and also has good insulating properties, making it suitable as an optical compensation layer. In addition, silicon nitride has better film uniformity and surface roughness than ITO. Using silicon nitride as a planarization layer can repair the surface roughness caused by anodic etching and avoid anodic disconnection.

[0121] In one embodiment, see Figure 17The display panel 100 includes a first common layer 60. The first common layer 60 is an integrated layer structure and is also reused as a first carrier transport layer 21 and a second carrier transport layer 31. That is, the first carrier transport layer 21 and the second carrier transport layer 31 are a single common layer.

[0122] Optionally, the first common layer 60 includes at least one of a hole transport layer, an electron blocking layer, an electron transport layer, and a hole blocking layer.

[0123] Optionally, the first common layer 60 includes thermally crosslinked groups. The thermally crosslinked groups include at least one of aliphatic polyamines, alicyclic polyamines, aromatic polyamines, phenols, and acid anhydrides.

[0124] Optionally, the third carrier transport layer 32 includes a photocrosslinking group. The photocrosslinking group includes at least one of azide, diazo, and benzophenone.

[0125] In this embodiment, the display panel 100 includes a first common layer 60. The first common layer 60 is an integrated layer structure and is reused as both a first carrier transport layer 21 and a second carrier transport layer 31. This means that the first light-emitting device 20 and the second light-emitting device 30 share the same hole transport layer, which is located above the substrate 10 and covers the entire display area. The first common layer 60 includes at least one of a hole transport layer, an electron blocking layer, an electron transport layer, and a hole blocking layer. Preferably, the first common layer 60 is a hole transport layer.

[0126] Exemplarily, the first common layer 60 includes thermally crosslinked groups. The thermally crosslinked groups include at least one of aliphatic polyamines, alicyclic polyamines, aromatic polyamines, phenolic compounds, and acid anhydrides. Upon heating, the thermally crosslinked groups undergo a crosslinking reaction to form an insoluble network structure, thereby ensuring the stability of the first common layer 60 in subsequent solution processing. The third carrier transport layer 32 includes photocrosslinked groups. The photocrosslinked groups include at least one of azide, diazo, and benzophenone. Under ultraviolet light irradiation, the photocrosslinked groups undergo a crosslinking reaction, causing the third carrier transport layer 32 to solidify in specific regions, facilitating pattern formation through a development process. The thickness of the first common layer 60 (600) is preferably 30 nm.

[0127] In one embodiment, the microcavity length of the first light-emitting device 20 includes at least one of a first-order microcavity length, a second-order microcavity length, a third-order microcavity length, and a fourth-order microcavity length.

[0128] Optionally, the microcavity length of the second light-emitting device 30 includes at least one of the following: first-order microcavity length, second-order microcavity length, third-order microcavity length, and fourth-order microcavity length.

[0129] Optionally, the thickness of the first light-emitting layer 22 is less than the thickness of the second light-emitting layer 33.

[0130] For example, sub-pixels of different colors can choose different microcavity orders to balance luminous efficiency and color purity. For instance, blue light can use a first-order microcavity (approximately 90 nm), red light can use a third-order microcavity (approximately 460 nm), and green light can use a second-order microcavity (approximately 220 nm). The thickness of the first luminescent layer 22 is less than the thickness of the second luminescent layer 33. This thickness difference stems from the optimal film thickness conditions for different luminescent materials; for example, the film thickness for blue quantum dots is typically 15 nm, and for red quantum dots it is 20 nm. Specific settings can be made according to the table below.

[0131] Please see Figure 17 The second aspect of this application provides a display panel 100. The display panel 100 includes a substrate 10 and a plurality of light-emitting devices. The plurality of light-emitting devices are located on one side of the substrate 10. Each light-emitting device includes a first common layer 60. The plurality of light-emitting devices includes a first light-emitting device 20 and a second light-emitting device 30. The first light-emitting device 20 includes a first light-emitting layer 22. The first light-emitting layer 22 is located on the side of the first common layer 60 facing away from the substrate 10. The second light-emitting device 30 includes a stacked third carrier transport layer 32 and a second light-emitting layer 33. The third carrier transport layer 32 is located on the side of the first common layer 60 facing away from the substrate 10. The first common layer 60 is cured under a first trigger condition, and the third carrier transport layer 32 is cured under a second trigger condition. The first common layer 60 and the third carrier transport layer 32 have the same function.

[0132] In this embodiment, the first common layer 60 serves as a shared hole transport layer covering the entire display area, the first light-emitting device 20 contains only a single light-emitting layer, while the second light-emitting device 30 includes an additional third carrier transport layer 32. This structure simplifies the manufacturing process while providing differentiated adjustment capabilities for the microcavities of different color sub-pixels. Compared to the previous embodiment, this embodiment omits the intermediate second carrier transport layer 31, directly using the first common layer 60 as the common foundation for the first carrier transport layer 21 and the second carrier transport layer 31, further reducing the number of process steps and film layers.

[0133] It should be noted that the embodiments provided in the second aspect can be combined with the embodiments provided in the first aspect in whole or in part, and will not be elaborated further here.

[0134] Please see Figure 18 The third aspect of this application provides a method for preparing a display panel 100, comprising steps S1-S5.

[0135] S1. A first electrode 23 and a second electrode 34 are prepared on one side of the substrate 10.

[0136] S2. A pixel defining layer 50 is formed on the side of the first electrode 23 and the second electrode 34 facing away from the substrate 10. The pixel defining layer 50 has a plurality of pixel openings. The plurality of pixel openings includes a first pixel opening 51 and a second pixel opening 52.

[0137] S3. A first common layer 60 is prepared on the side of the pixel defining layer 50 away from the substrate 10.

[0138] S4. In the second pixel opening 52, a third carrier transport layer 32 and a second light-emitting layer 33 are prepared on the side of the first common layer 60 away from the substrate 10 to obtain the second light-emitting device 30.

[0139] S5. A first light-emitting layer 22 is prepared in the first pixel opening 51 and on the side of the first common layer 60 away from the substrate 10 to obtain a first light-emitting device 20.

[0140] In one embodiment, fabricating a first common layer 60 on the side of the pixel defining layer 50 facing away from the substrate 10 includes: fabricating a first common material layer on the side of the pixel defining layer 50 facing away from the substrate 10; and subjecting the first common material layer to a heat treatment to obtain the first common layer 60.

[0141] Optionally, in the second pixel opening 52, and on the side of the first common layer 60 facing away from the substrate 10, a third carrier transport layer 32 and a second light-emitting layer 33 are fabricated, including: in the second pixel opening 52, and on the side of the first common layer 60 facing away from the substrate 10, a third carrier transport material layer and a second light-emitting material layer are sequentially fabricated. The third carrier transport material layer and the second light-emitting material layer are irradiated with ultraviolet light. The third carrier transport material layer and the second light-emitting material layer are patterned to obtain the third carrier transport layer 32 and the second light-emitting layer 33. Since the third carrier transport layer 32 can be removed by photolithography, quantum dot material of the second light-emitting layer is prevented from remaining in the pixel openings of other light-emitting devices, thus avoiding color mixing or cross-contamination.

[0142] In step S1, as Figure 19 As shown, the fabrication process of the first electrode 23 and the second electrode 34 includes: sequentially depositing a first conductive layer 231 (e.g., ITO), a first reflective layer 232 (e.g., Ag), a first inorganic layer 233 (e.g., SiNx), and a second conductive layer 234 (e.g., ITO) using sputtering or evaporation methods. The deposition sequence of the second electrode 34 is similar. A patterned structure is formed using conventional photolithography and etching processes. The etching process includes wet etching or dry etching, wherein wet etching uses ITO etching solution, and dry etching uses chlorine-containing gas.

[0143] For example, in step S2, as Figure 20As shown, a pixel defining layer 50 is formed on the side of the first electrode 23 and the second electrode 34 facing away from the substrate 10. The pixel defining layer 50 can be an organic photoresist material, and a first pixel opening 51, a second pixel opening 52, and a possible third pixel opening 53 are formed by coating, exposure, and development processes.

[0144] For example, in step S3, as Figure 21 As shown, a first common layer 60 is prepared on the side of the pixel defining layer 50 facing away from the substrate 10. This step includes: coating the pixel defining layer 50 and the exposed surfaces of the first electrode 23 and the second electrode 34 with a thermally cross-linked hole transport material solution, spin-coating to form a film, and then heating it at 180°C for 30 minutes to allow the thermally cross-linked groups to undergo a cross-linking reaction, forming an insoluble first common layer 60. The first common layer 60 after heat treatment exhibits excellent solvent resistance and can withstand solvent erosion in subsequent solution processing.

[0145] For example, in step S4, as Figure 22 As shown, a third carrier transport layer 32 and a second light-emitting layer 33 are fabricated in the second pixel opening 52, on the side of the first common layer 60 facing away from the substrate 10. The specific steps include: firstly, a photocrosslinked hole transport material is coated on the surface of the first common layer 60; then, the area of ​​the second pixel opening 52 is irradiated with ultraviolet light through a mask, causing the photocrosslinked material in that area to undergo a crosslinking reaction. Next, a second light-emitting material (red quantum dot solution) is coated without cleaning, and then irradiated with ultraviolet light again, causing the second light-emitting material to also undergo partial crosslinking and solidify. Finally, the uncured material is removed using a developer to obtain the third carrier transport layer 32 and the second light-emitting layer 33. During the development process, the third carrier transport layer 32 is crosslinked in the ultraviolet-irradiated area and is not dissolved, while the unirradiated area is removed by the developer, forming a pattern. The formation of the arc-shaped sidewalls is due to the difference in erosion rate of the crosslinked edges by the developer.

[0146] For example, in step S5, as Figure 23 As shown, a first light-emitting layer 22 is formed in the first pixel opening 51 and on the side of the first common layer 60 facing away from the substrate 10. The specific steps include: coating a first light-emitting material (blue quantum dot solution) onto the surface of the first common layer 60, and curing it by ultraviolet light irradiation or baking to form the first light-emitting layer 22. Since the first light-emitting device 20 does not require a photocrosslinked hole transport layer, only a single light-emitting layer is needed. This step does not require additional photoresist patterning; the first light-emitting layer 22 can be defined within the first pixel opening 51 by inkjet printing or coating with a mask.

[0147] It is understandable that multiple light-emitting devices are fabricated in the order of the second, third, and first light-emitting devices. Since the third carrier transport layer 32 in the second light-emitting device can be removed by photolithography, it avoids the quantum dot material of the second light-emitting layer remaining in the pixel openings of the other light-emitting devices, thus preventing color mixing or cross-contamination. Similarly, the fifth carrier transport layer in the third light-emitting device can be removed by photolithography, preventing the quantum dot material of the third light-emitting layer remaining in the pixel openings of the other light-emitting devices, thus preventing color mixing or cross-contamination. Finally, the first light-emitting device is fabricated to avoid the influence of the remaining red and green quantum dots on the blue quantum dots, thereby improving the display quality of the display panel.

[0148] It should be noted that the embodiments provided in the third aspect can be combined with the embodiments provided in the first aspect and / or the second aspect in whole or in part, which will not be elaborated further here.

[0149] A fourth aspect of this application provides a display device, including a display panel 100 as described in any of the preceding claims, or a display panel 100 prepared by the preparation method described above.

[0150] Optionally, the display device can be a quantum dot light-emitting diode display, an organic light-emitting diode display, a liquid crystal display backlight module, an illumination device, etc. This display device has the advantages of high color gamut, high brightness, high resolution, and long lifespan.

[0151] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0152] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A display panel, characterized in that, include: substrate; Multiple light-emitting devices are located on one side of the substrate; The plurality of light-emitting devices include a first light-emitting device and a second light-emitting device. The first light-emitting device includes a first carrier transport layer and a first light-emitting layer, with the first light-emitting layer located on the side of the first carrier transport layer facing away from the substrate. The second light-emitting device includes a stacked second carrier transport layer, a third carrier transport layer, and a second light-emitting layer, with the third carrier transport layer located on the side of the second carrier transport layer facing away from the substrate. The first carrier transport layer is cured under a first trigger condition, the second carrier transport layer is cured under the first trigger condition, and the third carrier transport layer is cured under a second trigger condition. The first, second, and third carrier transport layers have the same function.

2. The display panel according to claim 1, characterized in that, The first triggering condition includes heating treatment, and the second triggering condition includes light irradiation treatment; Preferably, the first light-emitting layer comprises a first quantum dot, and the second light-emitting layer comprises a second quantum dot; Preferably, the thickness of the third carrier transport layer is greater than or equal to 10 nm and less than or equal to 80 nm; Preferably, the thickness of the third carrier transport layer is greater than or equal to 10 nm and less than or equal to 30 nm.

3. The display panel according to claim 1, characterized in that, The orthographic projection of the third carrier transport layer on the substrate is located within the orthographic projection range of the second light-emitting layer on the substrate, and the second light-emitting layer covers at least a portion of the sidewalls of the third carrier transport layer; Preferably, the display panel further includes a pixel defining layer located on one side of the substrate. The pixel defining layer has a plurality of pixel openings, including a first pixel opening and a second pixel opening. At least a portion of the first carrier transport layer and at least a portion of the first light-emitting layer are located within the first pixel opening. At least a portion of the second carrier transport layer, at least a portion of the third carrier transport layer, and at least a portion of the second light-emitting layer are located within the second pixel opening. The distance from the end of the third carrier transport layer away from the substrate to the substrate is less than the distance from the surface of the pixel defining layer away from the substrate to the substrate. Preferably, a portion of the second light-emitting layer is in direct contact with the second carrier transport layer located on the sidewall of the pixel defining layer; Preferably, the sidewall of the third carrier transport layer is arc-shaped, and the increase in the distance between the sidewall of the third carrier transport layer and the sidewall of the pixel boundary layer increases along a direction perpendicular to and away from the sidewall of the pixel boundary layer.

4. The display panel according to claim 3, characterized in that, The first light-emitting layer located within the first pixel opening includes a first central region and a first edge region, the first edge region surrounds at least a portion of the first central region, and the thickness of the first edge region is greater than the thickness of the first central region; Preferably, the thickness of the first light-emitting layer located on the sidewall of the pixel defining layer is less than the thickness of the first central region; Preferably, the second light-emitting layer located within the second pixel opening includes a second central region and a second edge region, the second edge region surrounding at least a portion of the second central region, and the thickness of the second edge region being greater than the thickness of the second central region; Preferably, the thickness of the second light-emitting layer located on the sidewall of the pixel defining layer is less than the thickness of the second central region.

5. The display panel according to claim 1, characterized in that, The first light-emitting device further includes a first electrode, which is located between the first carrier transport layer and the substrate; the first electrode includes a stacked first conductive layer, a first reflective layer, a first inorganic layer and a second conductive layer, the second conductive layer is located on the side of the first inorganic layer near the first carrier transport layer, and the first conductive layer and the second conductive layer are electrically connected. Preferably, the thickness of the first conductive layer is greater than or equal to 15 nm, and / or the thickness of the second conductive layer is greater than or equal to 15 nm; Preferably, the second light-emitting device further includes a second electrode, which is located between the second carrier transport layer and the substrate; the second electrode includes a stacked third conductive layer, a second reflective layer, a second inorganic layer and a fourth conductive layer, the fourth conductive layer is located on the side of the second inorganic layer near the second carrier transport layer, and the third conductive layer is electrically connected to the fourth conductive layer; Preferably, the thickness of the first inorganic layer is less than the thickness of the second inorganic layer; Preferably, the thickness of the third conductive layer is greater than or equal to 15 nm, and / or the thickness of the fourth conductive layer is greater than or equal to 15 nm.

6. The display panel according to claim 5, characterized in that, The first inorganic layer satisfies at least one of the following conditions: The refractive index is greater than or equal to 1.6 and less than or equal to 2.1; Light transmittance in the wavelength range of 440nm to 680nm is greater than or equal to 90%; Preferably, the second inorganic layer satisfies at least one of the following conditions: The refractive index is greater than or equal to 1.6 and less than or equal to 2.1; The light transmittance in the wavelength range of 440nm to 680nm is greater than or equal to 90%.

7. The display panel according to claim 1, characterized in that, The plurality of light-emitting devices further includes a third light-emitting device, which includes a fourth carrier transport layer, a fifth carrier transport layer, and a third light-emitting layer stacked together. The fourth carrier transport layer is solidified under the first triggering condition, and the fifth carrier transport layer is solidified under the second triggering condition. The fourth carrier transport layer and the fifth carrier transport layer have the same function as the first carrier transport layer. Preferably, the thickness of the third carrier transport layer is greater than or equal to the thickness of the fifth carrier transport layer; Preferably, the third light-emitting layer comprises a third quantum dot; Preferably, the thickness of the fifth carrier transport layer is greater than or equal to 10 nm and less than or equal to 80 nm; Preferably, the thickness of the fifth carrier transport layer is greater than or equal to 10 nm and less than or equal to 30 nm.

8. The display panel according to claim 7, characterized in that, The orthographic projection of the fifth carrier transport layer on the substrate is located within the orthographic projection range of the third light-emitting layer on the substrate, and the third light-emitting layer covers at least a portion of the sidewalls of the fifth carrier transport layer; Preferably, the display panel further includes a pixel defining layer located on one side of the substrate. The pixel defining layer has a plurality of pixel openings, including a first pixel opening, a second pixel opening, and a third pixel opening. At least a portion of the first carrier transport layer and at least a portion of the first light-emitting layer are located within the first pixel opening. At least a portion of the second carrier transport layer, at least a portion of the third carrier transport layer, and at least a portion of the second light-emitting layer are located within the second pixel opening. At least a portion of the fourth carrier transport layer, at least a portion of the fifth carrier transport layer, and at least a portion of the third light-emitting layer are located within the third pixel opening. The distance from the end of the third carrier transport layer away from the substrate to the substrate is less than the distance from the surface of the pixel defining layer away from the substrate to the substrate; and / or, the distance from the end of the fifth carrier transport layer away from the substrate to the substrate is less than the distance from the surface of the pixel defining layer away from the substrate to the substrate. Preferably, a portion of the second light-emitting layer is in direct contact with the second carrier transport layer located on the sidewall of the pixel defining layer; And / or, part of the third light-emitting layer is in direct contact with the fourth carrier transport layer located on the sidewall of the pixel defining layer; Preferably, the sidewall of the fifth carrier transport layer is arc-shaped, and the increase in the distance between the sidewall of the fifth carrier transport layer and the sidewall of the pixel boundary layer increases along a direction perpendicular to and away from the sidewall of the pixel boundary layer.

9. The display panel according to claim 7, characterized in that, The distance between the edge of the orthographic projection of the third carrier transport layer on the substrate and the edge of the orthographic projection of the second light-emitting layer on the substrate is a first distance, and the distance between the edge of the orthographic projection of the fifth carrier transport layer on the substrate and the edge of the orthographic projection of the third light-emitting layer on the substrate is a second distance, wherein the first distance is greater than the second distance.

10. The display panel according to claim 7, characterized in that, The third light-emitting device further includes a third electrode, which is located between the fourth carrier transport layer and the substrate; the third electrode includes a stacked fifth conductive layer, a third reflective layer, a third inorganic layer and a sixth conductive layer, the sixth conductive layer is located on the side of the third inorganic layer close to the fourth carrier transport layer, and the fifth conductive layer and the sixth conductive layer are electrically connected; Preferably, the thickness of the fifth conductive layer is greater than or equal to 15 nm, and / or the thickness of the sixth conductive layer is greater than or equal to 15 nm; Preferably, the second light-emitting device further includes a second electrode located between the second carrier transport layer and the substrate; the second electrode includes a stacked third conductive layer, a second reflective layer, a second inorganic layer and a fourth conductive layer, the fourth conductive layer being located on the side of the second inorganic layer near the second carrier transport layer, and the third conductive layer being electrically connected to the fourth conductive layer; the thickness of the third inorganic layer is less than the thickness of the second inorganic layer; Preferably, the first light-emitting device further includes a first electrode, which is located between the first carrier transport layer and the substrate; the first electrode includes a stacked first conductive layer, a first reflective layer, a first inorganic layer and a second conductive layer, the second conductive layer is located on the side of the first inorganic layer near the first carrier transport layer, and the first conductive layer and the second conductive layer are electrically connected; the thickness of the first inorganic layer is less than the thickness of the third inorganic layer. Preferably, the thickness of the second conductive layer is less than the thickness of the sixth conductive layer, and / or the thickness of the sixth conductive layer is less than the thickness of the fourth conductive layer.

11. The display panel according to claim 10, characterized in that, The third inorganic layer satisfies at least one of the following conditions: The refractive index is greater than or equal to 1.6 and less than or equal to 2.1; The light transmittance in the wavelength range of 440nm to 680nm is greater than or equal to 90%.

12. The display panel according to claim 1, characterized in that, The display panel includes a first common layer, which is an integrated layer structure and is reused as both the first carrier transport layer and the second carrier transport layer. Preferably, the first common layer includes at least one of a hole transport layer, an electron blocking layer, an electron transport layer, and a hole blocking layer; Preferably, the first common layer includes thermally crosslinked groups, which include at least one of aliphatic polyamines, alicyclic polyamines, aromatic polyamines, phenolic compounds, and acid anhydrides; Preferably, the third carrier transport layer includes a photocrosslinking group, which includes at least one of azide, diazo and benzophenone.

13. The display panel according to claim 1, characterized in that, The microcavity length of the first light-emitting device includes at least one of the following: first-order microcavity length, second-order microcavity length, third-order microcavity length, and fourth-order microcavity length. Preferably, the microcavity length of the second light-emitting device includes at least one of a first-order microcavity length, a second-order microcavity length, a third-order microcavity length, and a fourth-order microcavity length; Preferably, the thickness of the first light-emitting layer is less than the thickness of the second light-emitting layer.

14. A display panel, characterized in that, include: substrate; A plurality of light-emitting devices are located on one side of the substrate; each light-emitting device includes a first common layer; the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device, the first light-emitting device including a first light-emitting layer located on the side of the first common layer facing away from the substrate; the second light-emitting device includes a stacked third carrier transport layer and a second light-emitting layer, the third carrier transport layer located on the side of the first common layer facing away from the substrate; the first common layer is cured under a first trigger condition, the third carrier transport layer is cured under a second trigger condition, and the first common layer and the third carrier transport layer have the same function.

15. A method for manufacturing a display panel, characterized in that, include: A first electrode and a second electrode are fabricated on one side of the substrate; A pixel defining layer is formed on the side of the first electrode and the second electrode away from the substrate. The pixel defining layer has a plurality of pixel openings, including a first pixel opening and a second pixel opening. A first common layer is formed on the side of the pixel defining layer opposite to the substrate; A second light-emitting device is obtained by fabricating a third carrier transport layer and a second light-emitting layer in the second pixel opening and on the side of the first common layer away from the substrate. A first light-emitting layer is prepared in the first pixel opening and on the side of the first common layer opposite to the substrate to obtain a first light-emitting device.

16. The preparation method according to claim 15, characterized in that, The step of fabricating a first common layer on the side of the pixel defining layer opposite to the substrate includes: A first common material layer is prepared on the side of the pixel defining layer opposite to the substrate; The first common material layer is subjected to heat treatment to obtain the first common layer; Preferably, the step of fabricating a third carrier transport layer and a second light-emitting layer in the second pixel opening, and on the side of the first common layer opposite to the substrate, includes: In the second pixel opening, and on the side of the first common layer away from the substrate, a third carrier transport material layer and a second light-emitting material layer are sequentially prepared. The third carrier transport material layer and the second light-emitting material layer are irradiated with ultraviolet light; The third carrier transport material layer and the second light-emitting material layer are patterned to obtain the third carrier transport layer and the second light-emitting layer.

17. A display device, characterized in that, It includes the display panel according to any one of claims 1 to 14, or the display panel prepared by the preparation method according to claim 15 or 16.

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