Display device, electronic device, and method for manufacturing the display device

Abstract

This application discloses a display device, an electronic device, and a method for manufacturing the display device. The display device includes: a substrate including a light-emitting region and a non-light-emitting region; a dam structure located in the light-emitting region of the substrate, wherein the dam structure includes a first dam layer, a second dam layer, and a third dam layer defining an overhang structure; and a light-emitting element located on the dam structure, including an anode electrode, a light-emitting layer, and a cathode electrode, wherein the third dam layer includes: a first upper conductive layer located on the second dam layer and including a first tip protruding beyond the side surface of the second dam layer; and a second upper conductive layer located on the first upper conductive layer and including a second tip overlapping the first tip, and an undercut defined between the first tip and the second tip.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0012253, filed on January 31, 2025, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a display device, an electronic device using the display device, and a method for manufacturing the display device. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are already used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, or organic light-emitting diode (OLED) displays. Among these flat panel displays, the light-emitting display element can include a light-emitting element that enables each pixel in the display panel to emit its own light, thereby displaying images without the use of a backlight unit to provide light to the display panel. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device capable of providing high-resolution images, an electronic device using the display device, and a method for manufacturing the display device.

[0005] Embodiments of this disclosure are used to reduce the resistance of a display device by increasing the contact area between the dam structure and the cathode electrode in a high-resolution display device.

[0006] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of this disclosure.

[0007] Details of other embodiments are included in the detailed description and accompanying drawings.

[0008] In embodiments of this disclosure, the display device includes: a substrate including a light-emitting region and a non-light-emitting region; a dam structure located in the light-emitting region of the substrate, wherein the dam structure includes a first dam layer, a second dam layer, and a third dam layer defining an overhang structure; and a light-emitting element located on the dam structure, including an anode electrode, a light-emitting layer, and a cathode electrode, wherein the third dam layer includes: a first upper conductive layer located on the second dam layer and including a first tip protruding beyond the side surface of the second dam layer; and a second upper conductive layer located on the first upper conductive layer and including a second tip overlapping the first tip, and an undercut defined between the first tip and the second tip.

[0009] In an embodiment, the first tip may include: a first surface facing the second embankment; a second surface opposite to the first surface; and a first inclined surface connecting the first surface and the second surface, wherein the first inclined angle formed by the first surface and the first inclined surface may be an acute angle.

[0010] In an embodiment, the second tip may include: a third surface facing the first upper conductive layer; a fourth surface opposite to the third surface; and a second inclined surface connecting the third surface and the fourth surface, wherein the second inclined angle formed by the third surface and the second inclined surface may be an acute angle and may be greater than the first inclined angle.

[0011] In an embodiment, the undercut may be defined between the first inclined surface and the second tip, and the cathode electrode may contact and cover the first and second tips.

[0012] In an embodiment, the second dam layer, the first upper conductive layer, and the second upper conductive layer may comprise materials that are different from each other.

[0013] In an embodiment, the first upper conductive layer may include a transparent conductive oxide containing tin, and the tin content in the first upper conductive layer is more than about 18% and less than about 30%.

[0014] In an embodiment, the second dam layer may include aluminum, and the second upper conductive layer may include titanium.

[0015] In an embodiment, the display device may further include: a first element insulating layer located between the dam structure and the anode electrode; and a second element insulating layer covering the edge of the anode electrode and contacting the first element insulating layer, wherein the light-emitting opening is defined in the second element insulating layer, and the first element insulating layer and the second element insulating layer overlap with the first tip and the second tip.

[0016] In an embodiment, the light-emitting layer may completely cover the second element insulating layer, the light-emitting layer overlaps with the first tip and the second tip in a direction perpendicular to the substrate, and the light-emitting layer may not contact the first tip of the first upper conductive layer.

[0017] In an embodiment, in a plan view, the third embankment layer may have a shape configured to form a conductive pattern surrounding the light-emitting opening.

[0018] In an embodiment, the third dam layer may further include: a third upper conductive layer located on the second upper conductive layer and including a third tip overlapping the first tip and the second tip; and a fourth upper conductive layer located on the third upper conductive layer and including a fourth tip overlapping the first tip, the second tip and the third tip, wherein the first upper conductive layer and the third upper conductive layer may comprise the same material as each other, and the second upper conductive layer and the fourth upper conductive layer may comprise the same material as each other.

[0019] In embodiments of this disclosure, a method for manufacturing a display device includes: forming a first dam layer, a second dam layer, and a third dam layer of a dam structure on a substrate; forming a first tip and a second tip of the third dam layer respectively by performing different etching processes; and forming a light-emitting element and an element inorganic layer on the dam structure.

[0020] In an embodiment, the third dam layer may include a first upper conductive layer and a second upper conductive layer comprising different materials from each other. The first upper conductive layer may include a transparent conductive oxide comprising tin, and the first upper conductive layer may have a first tip that protrudes from the side surface of the second dam layer by performing a wet etching process.

[0021] In one embodiment, the second upper conductive layer may include titanium, and the second upper conductive layer may have a second tip that protrudes beyond the side surface of the second embankment layer, formed by performing a dry etching process.

[0022] In embodiments of this disclosure, an electronic device includes: a display device including a substrate, the substrate including a light-emitting region and a non-light-emitting region; and at least one selected from a processor, a memory, and a power module connected to the display device, wherein the display device includes: a dam structure located in the light-emitting region of the substrate, wherein the dam structure includes a first dam layer, a second dam layer, and a third dam layer defining an overhang structure; and a light-emitting element located on the dam structure and including an anode electrode, a light-emitting layer, and a cathode electrode, wherein the third dam layer includes: a first upper conductive layer located on the second dam layer and including a first tip protruding beyond the side surface of the second dam layer; and a second upper conductive layer located on the first upper conductive layer and including a second tip overlapping the first tip, and an undercut defined between the first tip and the second tip.

[0023] According to an embodiment, a display device capable of providing high-resolution images and reducing the resistance of the display device by increasing the contact area between the dam structure and the cathode electrode, an electronic device using the display device, and a method for manufacturing the display device can be provided.

[0024] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those skilled in the art upon which they pertain by referring to the claims. Attached Figure Description

[0025] The above and other features of the embodiments of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a perspective view of a display device according to an embodiment;

[0027] Figure 2 This is a cross-sectional view of a display device according to an embodiment;

[0028] Figure 3 It is a diagram. Figure 2 A plan view of the display layer;

[0029] Figure 4 The diagram shows the settings. Figure 3 A plan view showing the arrangement of multiple pixels in the display area;

[0030] Figure 5 The diagram is along Figure 4 A cross-sectional view of an example of the display layer, taken by line X1-X1';

[0031] Figure 6 Is with Figure 5 A magnified cross-sectional view of the display element layer overlapping the first light-emitting region in the image;

[0032] Figure 7 yes Figure 6 An enlarged cross-sectional view of region "A" in the image;

[0033] Figure 8 The diagram is along Figure 4 A cross-sectional view of an example of the display layer, taken by line X3-X3';

[0034] Figure 9 The illustration is along another embodiment. Figure 4 A cross-sectional view of an example of the display layer, taken by line X5-X5';

[0035] Figure 10 yes Figure 9 An enlarged cross-sectional view of region "C";

[0036] Figure 11 The illustration is for manufacturing. Figure 5 A flowchart of an embodiment of a method for displaying a display element layer;

[0037] Figure 12 It is used to describe Figure 11 A cross-sectional view of process S100;

[0038] Figures 13 to 17 It is used to describe Figure 11 A cross-sectional view of process S200;

[0039] Figures 18 to 21 It is used to describe Figure 11 A cross-sectional view of process S300;

[0040] Figure 22 This is a block diagram of an electronic device according to an embodiment; and

[0041] Figure 23 The illustrations are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0042] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0043] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on that other element or layer, or there may be an intermediary element or layer between them. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings herein.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to an element “a” followed by reference to an element “the” in a claim includes one such element and multiple such elements. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” is not to be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or variations thereof, or “including” and / or variations thereof, when used in this specification, indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0046] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to also cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” of the other elements will be oriented to be “up” of the other elements. Thus, depending on the specific orientation of the drawing, the term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented to be “above” the other elements. Thus, the terms “below” or “under” can cover both “up” and “down” orientations.

[0047] Features of the various embodiments of this disclosure can be combined or integrated with each other in whole or in part, and can be operated and driven by each other in various technical ways. Embodiments can be implemented independently of each other, or they can be implemented together in a coexisting relationship.

[0048] Given the measurements discussed and the errors associated with the measured values ​​of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include stated values ​​and refer to a range of acceptable deviations from that particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant art and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] The embodiments described herein are illustrated with cross-sectional views that are schematic illustrations of preferred embodiments. Therefore, variations in the illustrated shapes will be expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape, for example, resulting from manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the present claims.

[0051] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 This is a perspective view of a display device according to an embodiment.

[0053] refer to Figure 1 Embodiments of display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). In embodiments, for example, display device 10 can be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. In another embodiment, for example, display device 10 can be applied to wearable devices such as smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs).

[0054] In an embodiment, the display device 10 may be formed into a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a predetermined curvature, or may be formed at right angles. The planar shape of the display device 10 is not limited to a quadrilateral and may be formed similar to other polygons, circles, or ellipses. Here, the third direction DR3 may be a direction perpendicular to the first direction DR1 and the second direction DR2, and may be the thickness direction of the display device 10.

[0055] In an embodiment, the display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0056] Display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DDA containing pixels of the displayed image and a non-display area NDA located around the display area DDA.

[0057] The display area DDA can emit light from multiple light-emitting areas or multiple light-emitting openings, which will be described later. In embodiments, for example, the display panel 100 may include pixel circuitry containing switching elements, an element insulating layer defining the light-emitting areas or light-emitting openings, and self-emissive elements. In embodiments, for example, the self-emissive element may include, but is not limited to, organic light-emitting diodes (LEDs) including organic light-emitting layers, quantum dot LEDs including quantum dot light-emitting layers, inorganic LEDs including inorganic semiconductors, or micro LEDs. In the accompanying drawings, for ease of illustration, embodiments where the self-emissive element is an organic light-emitting diode are primarily shown.

[0058] The non-display area NDA can be an area located outside the display area DDA. The non-display area NDA can be defined as the edge area of ​​the main area MA of the display panel 100.

[0059] The sub-region SBA can be a region extending from one side of the main region MA. The sub-region SBA can include a flexible material that can be bent, folded, or rolled. In an embodiment, for example, when the sub-region SBA is bent, the sub-region SBA can overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA can include a display driver 200 and pad portions connected to the circuit board 300. In another embodiment, the sub-region SBA can be omitted, and the display driver 200 and pad portions can be located in the non-display area NDA.

[0060] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic welding method. In one embodiment, for example, the display driver 200 can be located in a sub-region SBA and can overlap with the main region MA in the thickness direction by bending the sub-region SBA. In another embodiment, for example, the display driver 200 can be mounted on a circuit board 300.

[0061] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip-on-film.

[0062] Touch driver 400 can be mounted on circuit board 300. Touch driver 400 can be connected to and drive a touch sensor layer for sensing touch. Figure 2 (in the "TSL").

[0063] Figure 2 This is a cross-sectional view of a display device according to an embodiment.

[0064] refer to Figure 2 An embodiment of the display panel 100 may include a display layer DPL, a touch sensor layer TSL, and a color filter layer CFL. The display layer DPL may include a substrate SUB, a transistor layer TFTL, a display element layer EML, and a thin film encapsulation layer TFEL.

[0065] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. In embodiments, for example, the substrate SUB may include, but is not limited to, a polymer resin such as polyimide (PI). In another embodiment, the substrate SUB may include a glass material or a metal material.

[0066] The transistor layer TFTL can be located on the substrate SUB. The transistor layer TFTL can be located in the portion overlapping the display area DDA, the non-display area NDA, and the sub-area SBA. The transistor layer TFTL can include multiple transistors ( Figure 5 (TFT in the text).

[0067] The display element layer (EML) may be located on the transistor layer (TFTL). The display element layer (EML) may be located in the portion overlapping with the display area (DDA). The display element layer (EML) may include, but is not limited to, at least one selected from organic light-emitting diodes (LEDs) including organic light-emitting layers, quantum dot LEDs including quantum dot light-emitting layers, inorganic LEDs including inorganic semiconductors, and micro LEDs.

[0068] A thin-film encapsulation layer (TFEL) may be located on the display element layer (EML). The TFEL may be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The TFEL may cover the top and side surfaces of the display element layer (EML) and protect it from external oxygen and moisture. The TFEL may include at least one inorganic film and at least one organic film for encapsulating the display element layer (EML). In some embodiments, the TFEL may be omitted.

[0069] The touch sensor layer (TSL) may be located on the thin-film encapsulation layer (TFEL). The touch sensor layer (TSL) may be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The touch sensor layer (TSL) may sense the user's touch using either mutual capacitance or self-capacitance methods. In some embodiments, the touch sensor layer (TSL) may be omitted.

[0070] The color filter layer (CFL) can be located on the touch sensor layer (TSL). The CFL can be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The CFL absorbs a portion of the light introduced from the outside of the display device 10 to reduce reflected light caused by external light. Therefore, the CFL effectively prevents color distortion caused by the reflection of external light.

[0071] In embodiments where the color filter layer CFL is directly disposed on the touch sensor layer TSL, the display device 10 may not include a separate substrate for the color filter layer CFL. Therefore, the display device 10 can have a relatively small thickness. In some embodiments, the color filter layer CFL may also be omitted.

[0072] In an embodiment, such as Figure 2 As shown, the portion of the display panel 100 that overlaps with the sub-region SBA can be bent. With a portion of the display panel 100 bent, the display driver 200, circuit board 300, and touch driver 400 can overlap with the main region MA on the third-direction DR3.

[0073] When a portion of the display panel 100 is bent, the bending protection layer BPL can protect the underlying structure overlapping with the sub-region SBA from bending stress.

[0074] Figure 3 It is a diagram. Figure 2 The plan view of the display layer.

[0075] refer to Figure 3An embodiment of the display layer DPL may include multiple pixels PX located in the portion overlapping with the display area DDA, and multiple power lines VL, multiple scan lines SL, multiple emission control lines EDL, and multiple data lines DL connected to the multiple pixels PX.

[0076] Multiple scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects the first direction DR1. The scan lines SL can be arranged along the second direction DR2. The scan lines SL can sequentially supply scan signals to multiple pixels PX.

[0077] The emission control lines (EDLs) can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The emission control lines (EDLs) can be arranged along the second direction DR2. The emission control lines (EDLs) can sequentially supply light emission signals to multiple pixels (PXs).

[0078] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to multiple pixels PX. The data voltage can determine the brightness of each of the multiple pixels PX.

[0079] The power line VL may include a main power line VL1 and a secondary power line VL2. At least one of a first power supply voltage (high potential voltage) and a second power supply voltage (low potential voltage) can be transmitted to the secondary power line VL2 through the main power line VL1, which overlaps with the non-display area NDA. In the following, the main power line VL1 and the secondary power line VL2 may be collectively referred to as power line VL.

[0080] The non-display area NDA may surround the display area DDA. The non-display area NDA may include a scan driver 211 and a transmit control driver 213.

[0081] The scan driver 211 can be located outside one side of the display area DDA or on one side of the non-display area NDA. The scan driver 211 may include multiple scan transistors that generate scan signals based on scan control signals.

[0082] The emission control driver 213 can be located on the outside of the display area DDA or on the other side of the non-display area NDA. The emission control driver 213 may include multiple emission control transistors that generate light emission signals based on emission control signals.

[0083] The display layer DPL included in the embodiment may include a display driver 200 and a plurality of pad electrodes PDs located in the portion overlapping with the sub-region SBA. The plurality of pad electrodes PDs may be spaced apart from each other in the first direction DR1, and each pad electrode PD may be connected to a different line.

[0084] Figure 4 The diagram shows the settings. Figure 3 A plan view showing the arrangement of multiple pixels in the display area.

[0085] refer to Figure 4 According to an embodiment, pixel PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 located in the portion overlapping with the display area DDA. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be spaced apart from each other.

[0086] Pixel PX may include a light-emitting region EA. The light-emitting region EA may be the portion from which light is emitted. In an embodiment, for example, a first sub-pixel SP1 may include a first light-emitting region EA1, a second sub-pixel SP2 may include a second light-emitting region EA2, and a third sub-pixel SP3 may include a third light-emitting region EA3.

[0087] In one embodiment, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can emit light of different colors. For example, in one embodiment, the first light-emitting region EA1 can emit red light, the second light-emitting region EA2 can emit green light, and the third light-emitting region EA3 can emit blue light. However, the colors of the light emitted by the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are not limited to these, and in another embodiment, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can emit light of the same color as each other.

[0088] In an embodiment, the light-emitting region EA may be defined by a light-emitting opening OP. The light-emitting opening OP may be defined by a second element insulating layer (described later). Figure 5 The term "DIL2" is used to define this.

[0089] In a plan view (or when viewed on a third-direction DR3), the anode contact hole ACTH can be located in the portion overlapping with the light-emitting region EA. In a plan view, the anode contact hole ACTH can also be located inside the light-emitting region EA. For ease of illustration, Figure 4 An embodiment is shown in which the anode contact hole ACTH is located in the upper portion of the light-emitting region EA, but this disclosure is not limited thereto. The detailed structure of the anode contact hole ACTH will be described later.

[0090] The display device 10 according to an embodiment may include a non-emitting region NLA located in the portion overlapping with the display area DDA. The non-emitting region NLA can effectively prevent color mixing of light emitted from the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3.

[0091] In the plan view, the dike structure ( Figure 5 The "BN" in the diagram can be located in the portion overlapping with the non-luminous region NLA. In the plan view, the third dam layer BN3 included in the dam structure BN can have a shape with a conductive pattern surrounding the luminous region EA or the luminous opening OP. In the plan view, the third dam layers BN3 surrounding the first to third luminous regions EA1, EA2, and EA3 can be spaced apart from each other.

[0092] Furthermore, the first dam layer BN1 included in the dam structure BN can be formed entirely in the portion overlapping with the non-luminescent region NLA. In a plan view, the first dam layer BN1 can electrically connect the third dam layer BN3 surrounding the first to third luminescent regions EA1, EA2, and EA3.

[0093] Figure 5 The diagram is along Figure 4 A cross-sectional view of the display layer, taken by line X1-X1', and Figure 6 Is with Figure 5 An enlarged cross-sectional view of the display element layer overlapping the first light-emitting region in the image. Figure 5 The diagram illustrates the cross-sectional structure of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 located in the portion overlapping with the display area DDA of the display device 10.

[0094] refer to Figure 5 and Figure 6 In an embodiment of the display device 10, the transistor layer TFTL may be located on the substrate SUB. The substrate SUB may correspondingly include a light-emitting region EA and a non-light-emitting region NLA. The transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a transistor TFT, a gate insulating layer GI, a first insulating layer ILD1, a capacitor electrode CPE, a second insulating layer ILD2, a first connection electrode CNE1, a first via layer VIA1, a second connection electrode CNE2, a second via layer VIA2, and a third insulating layer ILD3.

[0095] The first buffer layer BF1 may be located on the substrate SUB. The first buffer layer BF1 may include an inorganic membrane capable of preventing the penetration of air or moisture. In an embodiment, for example, the first buffer layer BF1 may include a plurality of inorganic membranes stacked alternately.

[0096] The lower metal layer BML may be located on the first buffer layer BF1. The lower metal layer BML may include a conductive metal and may be formed as (or defined as) a single layer or multiple layers made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof.

[0097] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic membrane capable of preventing the penetration of air or moisture. In an embodiment, for example, the second buffer layer BF2 may include a plurality of inorganic membranes stacked alternately.

[0098] The transistor TFT can be disposed on the second buffer layer BF2 and can constitute a pixel circuit. In an embodiment, for example, the transistor TFT can be a driving transistor or a switching transistor of the pixel circuit.

[0099] A transistor TFT may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0100] The active layer ACT can be located on the second buffer layer BF2. The active layer ACT can overlap with the gate electrode GE on the third-direction DR3 and can be insulated from the gate electrode GE through the gate insulating layer GI. The drain electrode DE and the source electrode SE can be portions formed by making a portion of the active layer ACT conductive.

[0101] A gate insulating layer GI can be disposed on the active layer ACT. The gate insulating layer GI can cover the active layer ACT and the second buffer layer BF2, and can insulate the active layer ACT and the gate electrode GE from each other. The gate insulating layer GI can be provided with a contact hole through which the first connection electrode CNE1 passes.

[0102] The gate electrode GE can be located on the gate insulating layer GI. The gate insulating layer GI can be disposed between the gate electrode GE and the active layer ACT.

[0103] The gate electrode GE may include a conductive metal and may be formed as, for example, at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, or a single layer or multiple layers made therefrom.

[0104] A first insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first insulating layer ILD1 may be provided with a contact hole through which a first connecting electrode CNE1 passes. The contact hole of the first insulating layer ILD1 may connect to the contact hole of the gate insulating layer GI and the contact hole of the second insulating layer ILD2.

[0105] The capacitor electrode CPE can be located on the first insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE on the third-direction DR3. The capacitor electrode CPE and the gate electrode GE can form a capacitor.

[0106] The second insulating layer ILD2 may cover the capacitor electrode CPE and the first insulating layer ILD1. The second insulating layer ILD2 may be provided with a contact hole through which the first connecting electrode CNE1 passes. The contact hole of the second insulating layer ILD2 may be connected to the contact hole of the first insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0107] The first connection electrode CNE1 may be located on the second insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole defined or formed in the first insulating layer ILD1, the second insulating layer ILD2 and the gate insulating layer GI, and may contact the drain electrode DE of the transistor TFT.

[0108] The first via layer VIA1 can be located on the first connecting electrode CNE1 and the second insulating layer ILD2. The first via layer VIA1 can planarize the underlying structure. The first via layer VIA1 can be provided with contact holes through which the second connecting electrode CNE2 passes.

[0109] The first through-hole layer VIA1 may include an organic insulating material. In an embodiment, for example, the first through-hole layer VIA1 may include at least one selected from acrylic resin, polyimide, polyamide, benzocyclobutene, and phenolic resin.

[0110] The second connecting electrode CNE2 may be located on the first via layer VIA1. The second connecting electrode CNE2 may be located in the portion overlapping with the light-emitting region EA. The second connecting electrode CNE2 may be inserted into a contact hole defined or formed in the first via layer VIA1 and may be in contact with the first connecting electrode CNE1.

[0111] The second via layer VIA2 can be located on the first via layer VIA1. The second via layer VIA2 can planarize the step formed by the second connecting electrode CNE2.

[0112] The second through-hole layer VIA2 may include an organic material. In an embodiment, for example, the second through-hole layer VIA2 may include at least one selected from acrylic resin, silicone resin, silicone acrylic resin, epoxy resin, polyimide, polyamide, benzocyclobutene, and phenolic resin.

[0113] The third insulating layer ILD3 can be located on the second via layer VIA2. The third insulating layer ILD3 can help prevent degassing caused by the organic material of the second via layer VIA2 from penetrating into the display element layer EML.

[0114] The third insulating layer ILD3 may include an inorganic insulating material. In an embodiment, for example, the third insulating layer ILD3 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0115] The display element layer (EML) can be disposed on the transistor layer (TFTL). The display element layer (EML) may include a barrier structure (BN), an insulating layer (DIL), a light-emitting element (ED), and an inorganic layer (IO).

[0116] The dam structure BN can be disposed on the third insulating layer ILD3. The dam structure BN can be located in the portion that overlaps with the light-emitting region EA and / or the light-emitting opening OP.

[0117] The embankment structure BN can help form the first to third light-emitting elements ED1, ED2 and ED3 respectively in the portions overlapping with the first to third light-emitting regions EA1, EA2 and EA3, and can also help to electrically connect the cathode electrode CE and the cathode auxiliary electrode AX that are spaced apart from each other in the first to third light-emitting regions EA1, EA2 and EA3.

[0118] The dike structure BN may include a first dike layer BN1, a second dike layer BN2, and a third dike layer BN3. The first dike layer BN1, the second dike layer BN2, and the third dike layer BN3 may be stacked sequentially on a third-direction DR3.

[0119] The first insulating layer BN1 can be located on the third insulating layer ILD3. The first insulating layer BN1 can cover the third insulating layer ILD3 in the portion where it overlaps with the luminescent region EA and the non-luminescent region NLA.

[0120] The first dam layer BN1 can be completely formed in the portion that overlaps with the luminescent region EA and the non-luminescent region NLA, and can help to apply a low potential voltage to the cathode electrode CE.

[0121] The first dam layer BN1 may include an etch-resistant conductive metal. In an embodiment, for example, the first dam layer BN1 may include titanium (Ti).

[0122] The second dam layer BN2 can be configured to contact the first dam layer BN1 in the portion overlapping with the light-emitting region EA. Multiple second dam layers BN2 can be formed, and these multiple second dam layers BN2 can be spaced apart from each other in the first direction DR1. In other words, the multiple second dam layers BN2 can be located in the portions overlapping with the first to third light-emitting regions EA1, EA2, and EA3, respectively, and each second dam layer BN2 can be formed as an island-shaped conductive pattern.

[0123] The second dam layer BN2 located in the portion overlapping with the first light-emitting region EA1, the second dam layer BN2 located in the portion overlapping with the second light-emitting region EA2, and the second dam layer BN2 located in the portion overlapping with the third light-emitting region EA3 can be electrically connected through the first dam layer BN1.

[0124] The second dam layer BN2 may include a metal with high electrical conductivity. In an embodiment, for example, the second dam layer BN2 may include aluminum (Al).

[0125] The second diaphragm layer BN2 can be formed into a predetermined shape during the manufacturing process of the display device 10 by using a wet etching process with a phosphoric acid etchant. This manufacturing process will be described later.

[0126] The third dam layer BN3 can be configured to contact the second dam layer BN2. Multiple third dam layers BN3 can be formed, and these multiple third dam layers BN3 can be spaced apart from each other in the first direction DR1. In other words, the multiple third dam layers BN3 can be located in the portions overlapping the first to third light-emitting regions EA1, EA2, and EA3, respectively, and each third dam layer BN3 can be formed as an island-shaped conductive pattern.

[0127] In an embodiment, the third dam layer BN3 located in the portion overlapping with the first light-emitting region EA1, the third dam layer BN3 located in the portion overlapping with the second light-emitting region EA2, and the third dam layer BN3 located in the portion overlapping with the third light-emitting region EA3 can be electrically connected through the second dam layer BN2 and the first dam layer BN1.

[0128] In an embodiment, the third dam layer BN3 may include a first upper conductive layer BN31 and a second upper conductive layer BN32. The first upper conductive layer BN31 may be configured to contact the second dam layer BN2, and the second upper conductive layer BN32 may be disposed on the first upper conductive layer BN31.

[0129] The first upper conductive layer BN31 can be configured to contact the second embankment layer BN2 in the portion that overlaps with the light-emitting region EA.

[0130] In an embodiment, such as Figure 6As shown, the width Wbn31 of the first upper conductive layer BN31 in the first direction DR1 can be greater than the width Wbn2 of the second dam layer BN2 in the first direction DR1. Furthermore, the thickness of the first upper conductive layer BN31 in the third direction DR3 can be less than the thickness of the second dam layer BN2 in the third direction DR3.

[0131] The first upper conductive layer BN31 may have a first tip 1 that protrudes beyond the first side surface 2c of the second dam layer BN2 in the first direction DR1. The first side surface 2c of the second dam layer BN2 and the first tip 1 of the first upper conductive layer BN31 may form or jointly define an undercut, and therefore, the dam structure BN may have an overhang structure.

[0132] The first upper conductive layer BN31 may include a transparent conductive oxide (TCO) containing tin (Sn). In embodiments, for example, the first upper conductive layer BN31 may include at least one selected from Sn-IGZO, Sn-IZO, Sn-ITGZO, and Sn-ZnO. In embodiments, the first upper conductive layer BN31 may not include ITO.

[0133] The tin (Sn) content included in the first upper conductive layer BN31 can range from approximately 18% to approximately 30%. For example, when the tin (Sn) content included in the first upper conductive layer BN31 is less than 18%, the first upper conductive layer BN31 may not include the first tip 1 because a portion of the first upper conductive layer BN31 is removed by the phosphoric acid etchant used when forming the second dam layer BN2. In other words, when the tin (Sn) content included in the first upper conductive layer BN31 is less than 18%, the first upper conductive layer BN31 can have a shape similar to that of the second dam layer BN2. Furthermore, when the tin (Sn) content included in the first upper conductive layer BN31 is greater than 30%, it may be difficult to form the first upper conductive layer BN31 itself because a deposition target cannot be formed.

[0134] During the manufacturing process of the display device 10, the first upper conductive layer BN31 can be formed by a wet etching process. Figure 6 The shape is shown in the figure. However, the etchant used in the wet etching process to form the first upper conductive layer BN31 and the etchant used in the wet etching process to form the second diaphragm layer BN2 can be different from each other. In an embodiment, for example, the etchant used in the wet etching process to form the first upper conductive layer BN31 can be an etchant that is selective for etching aluminum (Al). In other words, the etchant used in the wet etching process to form the first upper conductive layer BN31 can include any etchant that does not etch aluminum (Al).

[0135] The second upper conductive layer BN32 can be configured to contact the first upper conductive layer BN31 in the portion that overlaps with the light-emitting region EA.

[0136] The second upper conductive layer BN32 may have a second tip 2 that protrudes beyond the first side surface 2c of the second embankment layer BN2 in the first direction DR1. The second tip 2 of the second upper conductive layer BN32 may cover the first tip 1 of the first upper conductive layer BN31 and overlap with the first tip 1 of the first upper conductive layer BN31 in the third direction DR3.

[0137] The second upper conductive layer BN32 may include an etch-resistant conductive metal. In an embodiment, for example, the second upper conductive layer BN32 may include titanium (Ti).

[0138] During the manufacturing process of the display device 10, the second upper conductive layer BN32 can be formed by a dry etching process. Figure 6 The shape shown is illustrated. The manufacturing process will be described later.

[0139] Since the display device 10 according to the embodiment includes a first tip 1 of a first upper conductive layer BN31 and a second tip 2 of a second upper conductive layer BN32, the first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3 spaced apart from each other can be formed during the manufacturing process of the display device 10 without the need to use a separate fine metal mask.

[0140] Furthermore, since the display device 10 according to the embodiment includes a first tip 1 of the first upper conductive layer BN31 and a second tip 2 of the second upper conductive layer BN32, the contact area between the cathode electrode CE and the cathode auxiliary electrode AX and the dam structure BN can be increased. A detailed description will be provided later.

[0141] The component insulating layer DIL may include a first component insulating layer DIL1 and a second component insulating layer DIL2.

[0142] The first element insulating layer DIL1 may be located on the third dam layer BN3. The first element insulating layer DIL1 may cover the second upper conductive layer BN32 and may be configured to overlap with the first tip 1 of the first upper conductive layer BN31 and the second tip 2 of the second upper conductive layer BN32 on the third-direction DR3.

[0143] The first element, the insulating layer DIL1, can separate and insulate the dam structure BN and the anode electrode AE ​​from each other, so that the dam structure BN and the anode electrode AE ​​do not come into contact with each other.

[0144] The first element insulating layer DIL1 may include an inorganic insulating material. In an embodiment, for example, the first element insulating layer DIL1 may include at least one selected from silicon nitride, silicon oxide, and silicon oxynitride.

[0145] The second insulating layer DIL2 can be located on the first insulating layer DIL1. The second insulating layer DIL2 can define a light-emitting opening OP and expose the anode electrode AE ​​in the portion overlapping with the light-emitting opening OP. In other words, the second insulating layer DIL2 can be configured to surround the light-emitting opening OP and cover the edge of the anode electrode AE. In the portion overlapping with the non-light-emitting region NLA, the first insulating layer DIL1 and the second insulating layer DIL2 can be in contact with each other.

[0146] The second element insulating layer DIL2 may include an inorganic insulating material. In an embodiment, for example, the second element insulating layer DIL2 may include at least one selected from silicon nitride, silicon oxide, and silicon oxynitride.

[0147] In an embodiment, for example, where the first element insulating layer DIL1 and the second element insulating layer DIL2 are made of the same material as each other, the first element insulating layer DIL1 and the second element insulating layer DIL2 can be integrally formed as a single, indivisible part.

[0148] The light-emitting element ED can be located on the embankment structure BN. The light-emitting element ED can overlap with the embankment structure BN, the first element insulating layer DIL1, and the second element insulating layer DIL2 on the third-direction DR3.

[0149] The display device 10 according to the embodiment can be applied to high-resolution electronic devices. Therefore, it may be desirable to include a plurality of light-emitting elements ED in the display device 10 while ensuring appropriate separation distances within a narrow area. Accordingly, in the display device 10 according to the embodiment, by forming the light-emitting elements ED on the embankment structure BN, a plurality of light-emitting elements ED can be effectively placed within a narrow area.

[0150] The light-emitting element ED may include a first light-emitting element ED1 disposed in a first light-emitting region EA1, a second light-emitting element ED2 disposed in a second light-emitting region EA2, and a third light-emitting element ED3 disposed in a third light-emitting region EA3. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may be spaced apart from each other.

[0151] The first light-emitting element ED1 may include an anode electrode AE, a first light-emitting layer EL1, a cathode electrode CE, and a cathode auxiliary electrode AX; the second light-emitting element ED2 may include an anode electrode AE, a second light-emitting layer EL2, a cathode electrode CE, and a cathode auxiliary electrode AX; and the third light-emitting element ED3 may include an anode electrode AE, a third light-emitting layer EL3, a cathode electrode CE, and a cathode auxiliary electrode AX.

[0152] The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can emit light of different colors. In an embodiment, for example, the first light-emitting element ED1 can emit red light, the second light-emitting element ED2 can emit green light, and the third light-emitting element ED3 can emit blue light. The color of the light emitted by the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can be determined by the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, respectively.

[0153] The anode electrode AE ​​can be located on the first element insulating layer DIL1. The anode electrode AE ​​can be located in the portion that overlaps with the light-emitting region EA and / or the light-emitting opening OP.

[0154] The anode electrode AE ​​can be a stacked film structure in which layers of materials with high work functions, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and reflective material layers such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), or mixtures thereof are stacked. In embodiments, for example, the anode electrode AE ​​can have a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, and ITO / Ag / ITO, but is not limited thereto.

[0155] The first to third light-emitting layers EL1, EL2, and EL3 can be located on the anode electrode AE. The first to third light-emitting layers EL1, EL2, and EL3 can be located in the portion overlapping with the light-emitting region EA and the non-light-emitting region NLA. The first to third light-emitting layers EL1, EL2, and EL3 can overlap with the embankment structure BN, the first element insulating layer DIL1, and the second element insulating layer DIL2 on the third-direction DR3.

[0156] The first to third light-emitting layers EL1, EL2 and EL3 can contact the anode electrode AE ​​in the portion overlapping with the light-emitting opening OP, and can completely cover the second element insulating layer DIL2 in the portion overlapping with the non-light-emitting region NLA.

[0157] In some embodiments, the first to third light-emitting layers EL1, EL2, and EL3 may cover a portion of the third dam layer BN3 and may contact a portion of the first element insulating layer DIL1. The first to third light-emitting layers EL1, EL2, and EL3 may not contact the first tip 1 of the first upper conductive layer BN31.

[0158] The first luminescent layer EL1 can be located in the portion overlapping with the first luminescent region EA1, the second luminescent layer EL2 can be located in the portion overlapping with the second luminescent region EA2, and the third luminescent layer EL3 can be located in the portion overlapping with the third luminescent region EA3. The first luminescent layer EL1, the second luminescent layer EL2, and the third luminescent layer EL3 can be spaced apart from each other in the portions overlapping with the non-luminescent region NLA.

[0159] Since the display device 10 according to the embodiment includes a first tip 1 of a first upper conductive layer BN31 and a second tip 2 of a second upper conductive layer BN32, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, which are spaced apart from each other, can be formed during the manufacturing process of the display device 10 without the need for a separate fine metal mask. This manufacturing process will be described later.

[0160] The first to third light-emitting layers EL1, EL2, and EL3 can be organic light-emitting layers comprising or made of organic materials. The first to third light-emitting layers EL1, EL2, and EL3 can include any commonly used materials.

[0161] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can emit light of different colors. In an embodiment, for example, the first light-emitting layer EL1 can emit red light, the second light-emitting layer EL2 can emit green light, and the third light-emitting layer EL3 can emit blue light, but this disclosure is not limited thereto.

[0162] The cathode electrode CE can be located on the first to third light-emitting layers EL1, EL2, and EL3. The cathode electrode CE can be located in the portion overlapping the light-emitting region EA and the non-light-emitting region NLA. The cathode electrode CE can completely cover the first to third light-emitting layers EL1, EL2, and EL3.

[0163] The cathode electrode CE can contact the dam structure BN, and therefore can be electrically connected to the dam structure BN. In an embodiment, for example, the cathode electrode CE can contact the first tip 1 of the first upper conductive layer BN31 and the second tip 2 of the second upper conductive layer BN32.

[0164] The cathode electrode CE comprises a highly conductive metal and a transparent conductive oxide, allowing light generated in the first to third light-emitting layers EL1, EL2, and EL3 to be emitted. In embodiments, for example, the cathode electrode CE may comprise a material layer with a low work function, such as Li, Ca, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, Ba, or compounds thereof (e.g., LiF or BaF2) or mixtures thereof (e.g., mixtures of Ag and Mg), or a multilayer structure such as LiF / Ca or LiF / Al.

[0165] In an embodiment, the cathode electrode CE located in the portion overlapping with the first light-emitting region EA1, the cathode electrode CE located in the portion overlapping with the second light-emitting region EA2, and the cathode electrode CE located in the portion overlapping with the third light-emitting region EA3 can be spaced apart from each other. The cathode electrodes CE in the first to third light-emitting regions EA1, EA2, and EA3 that are spaced apart from each other can be electrically connected through the dike structure BN. In an embodiment, the cathode electrodes CE in the first to third light-emitting regions EA1, EA2, and EA3 that are spaced apart from each other can contact the third dike layer BN3 in the first to third light-emitting regions EA1, EA2, and EA3 that are spaced apart from each other, and can be electrically connected to each other through the second dike layer BN2 and the first dike layer BN1 that are electrically connected to the third dike layer BN3.

[0166] Since the display device 10 according to the embodiment includes a first tip 1 of a first upper conductive layer BN31 and a second tip 2 of a second upper conductive layer BN32, cathode electrodes CE, which are spaced apart from each other, can be formed in the first to third light-emitting regions EA1, EA2, and EA3 without the need for a separate fine metal mask. This manufacturing process will be described later.

[0167] The cathode auxiliary electrode AX can be located on the cathode electrode CE. The cathode auxiliary electrode AX can be located in the portion overlapping the luminescent region EA and the non-luminescent region NLA. The cathode auxiliary electrode AX can completely cover the cathode electrode CE. The cathode auxiliary electrode AX helps to electrically connect the cathode electrode CE.

[0168] In an embodiment, the cathode auxiliary electrode AX can be integrally formed with the cathode electrode CE into a single, inseparable part. In this case, the cathode auxiliary electrode AX can be referred to as the cathode electrode CE.

[0169] The cathode auxiliary electrode AX may include a transparent conductive oxide (TCO). In embodiments, for example, the cathode auxiliary electrode AX may include at least one selected from indium zinc oxide (IZO) and indium tin oxide (ITO).

[0170] In an embodiment, the cathode auxiliary electrode AX located in the portion overlapping with the first light-emitting region EA1, the cathode auxiliary electrode AX located in the portion overlapping with the second light-emitting region EA2, and the cathode auxiliary electrode AX located in the portion overlapping with the third light-emitting region EA3 can be spaced apart from each other. The cathode auxiliary electrodes AX in the first to third light-emitting regions EA1, EA2, and EA3 that are spaced apart from each other can be electrically connected through the dike structure BN. In an embodiment, the cathode auxiliary electrodes AX in the first to third light-emitting regions EA1, EA2, and EA3 that are spaced apart from each other can contact the third dike layer BN3 in the first to third light-emitting regions EA1, EA2, and EA3, and can be electrically connected to each other through the second dike layer BN2 and the first dike layer BN1 that are electrically connected to the third dike layer BN3.

[0171] Generally, as the contact area between the cathode electrode CE and / or the auxiliary cathode electrode AX and the dam structure BN increases, the display device 10 can have a reduced resistance. For example, when the contact area between the cathode electrode CE and / or the auxiliary cathode electrode AX and the dam structure BN decreases below a certain range, the display device 10 may cause poor reliability issues such as poor power supply or reduced brightness.

[0172] Accordingly, since the display device 10 according to the embodiment is formed such that the first upper conductive layer BN31 and the second upper conductive layer BN32 respectively include a first tip 1 and a second tip 2, and a step is formed between the first tip 1 and the second tip 2, the contact area between the cathode electrode CE and / or the cathode auxiliary electrode AX and the dam structure BN can be increased. The detailed structure of the first tip 1 and the second tip 2 will be described later.

[0173] The inorganic layer I / O can be located on the light-emitting element (ED). The inorganic layer I / O can completely cover the light-emitting element (ED) and prevent oxygen or moisture from penetrating into the light-emitting element (ED).

[0174] The inorganic layer IO of the component may include an inorganic insulating material. In an embodiment, for example, the inorganic layer IO of the component may include at least one selected from silicon nitride, silicon oxide, and silicon oxynitride.

[0175] The inorganic layer IO may include a first inorganic layer IO1, a second inorganic layer IO2, and a third inorganic layer IO3. The first inorganic layer IO1 may be disposed on a first light-emitting element ED1 in a first light-emitting region EA1, the second inorganic layer IO2 may be disposed on a second light-emitting element ED2 in a second light-emitting region EA2, and the third inorganic layer IO3 may be disposed on a third light-emitting element ED3 in a third light-emitting region EA3. The first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3 may be spaced apart from each other in the portion overlapping with the non-light-emitting region NLA.

[0176] In an embodiment, such as Figure 5 As shown, the first element inorganic layer IO1, the second element inorganic layer IO2, and the third element inorganic layer IO3 can be formed in the same layer as each other (or directly on the same layer as each other). However, during the manufacturing process of the display device 10, the first element inorganic layer IO1 can be formed after the first light-emitting element ED1, the second element inorganic layer IO2 can be formed after the second light-emitting element ED2, and the third element inorganic layer IO3 can be formed after the third light-emitting element ED3. This manufacturing process will be described later.

[0177] The thin-film encapsulation layer TFEL can be located on the display element layer EML. The thin-film encapsulation layer TFEL can include an organic encapsulation layer TFE1 and an inorganic encapsulation layer TFE3.

[0178] According to an embodiment, the organic encapsulation layer TFE1 can be located on the inorganic layer IO of the component. In an embodiment, for example, the organic encapsulation layer TFE1 can be in complete contact with and cover the first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3.

[0179] The organic encapsulation layer TFE1 can be planarized according to the contour of the underlying structure (or a stepped structure). The organic encapsulation layer TFE1 can fill the space between the cathode auxiliary electrode AX and the first dam layer BN1 in the portion that overlaps with the non-light-emitting region NLA.

[0180] The organic encapsulation layer TFE1 may include polymeric materials. In embodiments, for example, the organic encapsulation layer TFE1 may include at least one selected from acrylic resins, silicone resins, epoxy resins, silicone acrylic resins, polyimides, and polyethylene.

[0181] The inorganic encapsulation layer TFE3 can be located on top of the organic encapsulation layer TFE1. The inorganic encapsulation layer TFE3 can protect the underlying structure from moisture and oxygen penetration. In another embodiment, the inorganic encapsulation layer TFE3 can also be omitted.

[0182] The inorganic encapsulation layer TFE3 may include an inorganic insulating material. In an embodiment, for example, the inorganic encapsulation layer TFE3 may include at least one selected from silicon nitride, silicon oxide, and silicon oxynitride.

[0183] Figure 7 yes Figure 6 An enlarged cross-sectional view of region "A" in the image.

[0184] Apart from Figures 1 to 6 In addition to referencing Figure 7 According to the embodiment, the first upper conductive layer BN31 may include a first tip 1 that protrudes from the first side surface 2c of the second embankment layer BN2 in the first direction DR1, and the cross section of the first tip 1 may have a regular conical shape or a trapezoidal shape.

[0185] Since the first upper conductive layer BN31 according to the embodiment comprises tin (Sn) in the range of approximately 18% to approximately 30%, the first upper conductive layer BN31 can have a low etching rate when formed by performing a wet etching process during manufacturing. Accordingly, the first upper conductive layer BN31 can be formed as Figure 7 The shape shown is illustrated. The manufacturing process will be described later.

[0186] The first tip 1 may include a first surface 3a, a second surface 3b, and a first inclined surface 3c. The first surface 3a of the first tip 1 may be a surface facing the second embankment layer BN2, the second surface 3b may be a surface opposite to the first surface 3a, and the first inclined surface 3c may be a surface connecting the first surface 3a and the second surface 3b. The first inclined surface 3c may have a shape that is inclined between the direction opposite to the first direction DR1 and the third direction DR3.

[0187] In an embodiment, the first tilt angle θa formed by the first surface 3a and the first inclined surface 3c included in the first tip 1 can be an acute angle, and the second tilt angle θb formed by the second surface 3b and the first inclined surface 3c included in the first tip 1 can be an obtuse angle. Since the first upper conductive layer BN31 is formed during manufacturing using a wet etching process, the first tilt angle θa and the second tilt angle θb included in the first tip 1 can be formed as follows: Figure 7 The shape shown in the image.

[0188] In an embodiment, the second tip 2 of the second upper conductive layer BN32 may cover the first tip 1 of the first upper conductive layer BN31. As described above, the first tip 1 and the second tip 2 may overlap each other on the third-direction DR3.

[0189] An undercut can be formed between the second tip 2 of the second upper conductive layer BN32 and the first tip 1 of the first upper conductive layer BN31. According to an embodiment, the display device 10 can increase the contact area between the cathode electrode CE and / or the cathode auxiliary electrode AX and the third embankment layer BN3 by forming an undercut between the first tip 1 and the second tip 2 to include a stepped portion.

[0190] In an embodiment, the cathode electrode CE and / or the cathode auxiliary electrode AX may contact the first inclined surface 3c of the first tip 1, and the cathode auxiliary electrode AX may contact the first surface 3a. In an embodiment, as... Figure 7 As shown, the cathode electrode CE can completely fill the undercut, but this disclosure is not limited thereto.

[0191] Since the second upper conductive layer BN32 according to the embodiment contains titanium (Ti), the second upper conductive layer BN32 can be formed by performing a dry etching process during manufacturing. Accordingly, the second upper conductive layer BN32 may have a second tip 2 that protrudes beyond the first side surface 2c of the second embankment layer BN2 in the first direction DR1, and the cross-section of the second tip 2 may have a regular tapered or trapezoidal shape.

[0192] In an embodiment, the second tip 2 included in the second upper conductive layer BN32 may include a third surface 4a, a fourth surface 4b, and a second inclined surface 4c. The third surface 4a of the second tip 2 may be a surface facing the first upper conductive layer BN31, the fourth surface 4b may be a surface opposite to the third surface 4a, and the second inclined surface 4c may be a surface connecting the third surface 4a and the fourth surface 4b. The second inclined surface 4c may have a shape that is inclined between the first direction DR1 and the third direction DR3.

[0193] In an embodiment, the first tilt angle θc formed by the third surface 4a and the second tilt surface 4c included in the second tip 2 may be an acute angle, and the second tilt angle θd formed by the fourth surface 4b and the second tilt surface 4c included in the second tip 2 may be an obtuse angle.

[0194] In an embodiment, the first tip 1 and the second tip 2 may have different structures due to being executed in different processes. In an embodiment, the first tilt angle θc included in the second tip 2 may be greater than the first tilt angle θa included in the first tip 1. In the display device 10 according to an embodiment, the first upper conductive layer BN31 and the second upper conductive layer BN32 comprise different materials and are formed by different processes, such that the first tilt angle θc included in the second tip 2 is greater than the first tilt angle θa included in the first tip 1.

[0195] In an embodiment, the cathode electrode CE may contact the second inclined surface 4c and / or the third surface 4a of the second tip 2.

[0196] In an embodiment, the first element insulating layer DIL1 can completely cover the fourth surface 4b of the second upper conductive layer BN32.

[0197] Figure 8 The diagram is along Figure 4 A cross-sectional view of the display layer, taken by line X3-X3'. Figure 8 The diagram illustrates the cross-sectional structure of the display element layer EML overlapping the anode contact hole ACTH. In the following text, any repetitive detailed descriptions of elements identical or similar to those described above will be omitted, and the characteristics of the display element layer EML overlapping the anode contact hole ACTH will be primarily described.

[0198] Apart from Figures 1 to 7 In addition to referencing Figure 8 In this embodiment, the anode contact hole ACTH may overlap with the light-emitting region EA.

[0199] In one embodiment, the anode contact hole ACTH may be located in the portion overlapping with the light-emitting opening OP defined by the second element insulating layer DIL2. The anode contact hole ACTH may be formed through the first element insulating layer DIL1, the dam structure BN, and the third insulating layer ILD3, and the second connection electrode CNE2 may be exposed in the portion overlapping with the anode contact hole ACTH.

[0200] In one embodiment, the first upper conductive layer BN31 and the second upper conductive layer BN32 of the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 can be configured to surround the anode contact hole ACTH. In such an embodiment, a first tip 1 included in the first upper conductive layer BN31 and a second tip 2 included in the second upper conductive layer BN32 can be configured to surround the anode contact hole ACTH.

[0201] In an embodiment, the first element insulating layer DIL1 may be disposed between the anode electrode AE ​​and the first upper conductive layer BN31 and the second upper conductive layer BN32 of the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3. In an embodiment, the anode electrode AE ​​may be covered along the steps formed by the first element insulating layer DIL1. Accordingly, the anode electrode AE ​​may include steps (or may have a stepped structure) in the portion overlapping with the anode contact hole ACTH.

[0202] In the portion overlapping with the anode contact hole ACTH, the anode electrode AE ​​and the second connecting electrode CNE2 can contact and be electrically connected. (Reference) Figure 5 The anode electrode AE ​​can be electrically connected to the transistor TFT via the second connection electrode CNE2.

[0203] In one embodiment, the first light-emitting layer EL1 may cover the portion overlapping with the anode contact hole ACTH along the steps formed by the anode electrode AE. Accordingly, in another embodiment, the first light-emitting layer EL1 may include steps in the portion overlapping with the anode contact hole ACTH.

[0204] In one embodiment, the cathode electrode CE may cover the portion overlapping the anode contact hole ACTH along the steps formed by the anode electrode AE. Accordingly, in another embodiment, the cathode electrode CE may include steps in the portion overlapping the anode contact hole ACTH.

[0205] In one embodiment, the cathode auxiliary electrode AX may cover the portion overlapping the anode contact hole ACTH along the steps formed by the anode electrode AE. Accordingly, in another embodiment, the cathode auxiliary electrode AX may include steps in the portion overlapping the anode contact hole ACTH.

[0206] In an embodiment, the first element inorganic layer IO1 may cover the portion overlapping with the anode contact hole ACTH along the steps formed by the anode electrode AE. Accordingly, in an embodiment, the first element inorganic layer IO1 may include steps in the portion overlapping with the anode contact hole ACTH. However, this specification is not limited thereto, and the first element inorganic layer IO1 may not include steps in the portion overlapping with the anode contact hole ACTH. Any repeated detailed descriptions thereof will be omitted.

[0207] For ease of illustration and description, the structure and features of the anode contact hole ACTH overlapping the first light-emitting region EA1 are illustrated and described. However, the structure and features of the anode contact hole ACTH overlapping the second light-emitting region EA2 and the third light-emitting region EA3 can be the same as those of the anode contact hole ACTH overlapping the first light-emitting region EA1.

[0208] Figure 9 The illustration is along another embodiment. Figure 4 A cross-sectional view of the display layer, taken by line X5-X5', and Figure 10 yes Figure 9 An enlarged cross-sectional view of region "C".

[0209] Apart from Figures 1 to 8 In addition to referencing Figure 9 and Figure 10 The dam structure BN in the display device 30 according to the embodiment may include a first dam layer BN1, a second dam layer BN2 and a third dam layer BN3, and the third dam layer BN3 may include a first upper conductive layer BN31, a second upper conductive layer BN32, a third upper conductive layer BN33 and a fourth upper conductive layer BN34.

[0210] The first upper conductive layer BN31 and the second upper conductive layer BN32 included in the display device 30 may have the same structure and features as the first upper conductive layer BN31 and the second upper conductive layer BN32 included in the display device 10. (Hereinafter, omissions will be omitted.) Figure 9 and Figure 10 The description will not repeat any repeated details of elements in the display device 30 that are the same as or similar to those described above, and will mainly describe the differences.

[0211] The third upper conductive layer BN33 included in the display device 30 can be configured to contact the second upper conductive layer BN32 in the portion that overlaps with the light-emitting region EA.

[0212] The third upper conductive layer BN33 may have a third tip 3 that protrudes from the first side surface 2c of the second embankment layer BN2 in the first direction DR1. The third tip 3 of the third upper conductive layer BN33 may overlap with the first tip 1 and the second tip 2 in the third direction DR3.

[0213] The third upper conductive layer BN33 may comprise the same material as the first upper conductive layer BN31. In embodiments, for example, the third upper conductive layer BN33 may comprise a transparent conductive oxide (TCO) containing tin (Sn), and the tin (Sn) content may range from about 18% to about 30%. In embodiments, for example, the third upper conductive layer BN33 may comprise Sn-IGZO, Sn-IZO, Sn-ITGZO, Sn-ZnO, etc. In embodiments, the third upper conductive layer BN33 may not include ITO.

[0214] During the manufacturing process of the display device 30, the third upper conductive layer BN33 can be formed into the shape shown in the present illustration by a wet etching process. The etchant used in the wet etching process for forming the third upper conductive layer BN33 can be the same as the etchant used in the wet etching process for forming the first upper conductive layer BN31.

[0215] In an embodiment, the third tip 3 included in the third upper conductive layer BN33 may include a first surface 5a, a second surface 5b, and a first inclined surface 5c. The first surface 5a of the third tip 3 may be a surface facing the second upper conductive layer BN32, the second surface 5b may be a surface opposite to the first surface 5a, and the first inclined surface 5c may be a surface connecting the first surface 5a and the second surface 5b. The first inclined surface 5c may have a shape that is inclined between the first direction DR1 and the third direction DR3.

[0216] The third tip 3 can have a regular conical or trapezoidal shape. Specifically, the first inclination angle θe formed by the first surface 5a and the first inclined surface 5c included in the third tip 3 can be an acute angle, and the second inclination angle θf formed by the second surface 5b and the first inclined surface 5c included in the third tip 3 can be an obtuse angle.

[0217] In an embodiment, an undercut may be formed between the fourth tip 4 of the fourth upper conductive layer BN34 and the third tip 3 of the third upper conductive layer BN33. The display device 30 according to the embodiment can increase the contact area between the cathode electrode CE and / or the cathode auxiliary electrode AX and the third diaphragm layer BN3 by forming an undercut between the third tip 3 and the fourth tip 4 to include a stepped portion.

[0218] In an embodiment, the cathode electrode CE and / or the cathode auxiliary electrode AX may contact the first inclined surface 5c of the third tip 3. In an embodiment, as... Figure 9 As shown, the cathode electrode CE can completely fill the undercut between the third tip 3 and the fourth tip 4, but this disclosure is not limited thereto.

[0219] The fourth upper conductive layer BN34 can be configured to contact the third upper conductive layer BN33 in the portion that overlaps with the light-emitting region EA.

[0220] The fourth upper conductive layer BN34 may have a fourth tip 4 that protrudes beyond the first side surface 2c of the second dam layer BN2 in the first direction DR1. The fourth tip 4 of the fourth upper conductive layer BN34 may overlap with the first tip 1, the second tip 2 and the third tip 3 in the third direction DR3.

[0221] The fourth upper conductive layer BN34 may comprise the same material as the second upper conductive layer BN32. In embodiments, for example, the fourth upper conductive layer BN34 may comprise an etch-resistant conductive metal and may comprise titanium (Ti).

[0222] During the manufacturing process of the display device 30, the fourth upper conductive layer BN34 can be formed by a dry etching process. Figure 9 The shape shown in the figure. The fourth tip 4 can have a regular conical shape or a trapezoidal shape.

[0223] In an embodiment, the fourth tip 4 included in the fourth upper conductive layer BN34 may include a third surface 6a, a fourth surface 6b, and a second inclined surface 6c. The third surface 6a of the fourth tip 4 may be a surface facing the third upper conductive layer BN33, the fourth surface 6b may be a surface opposite to the third surface 6a, and the second inclined surface 6c may be a surface connecting the third surface 6a and the fourth surface 6b. The second inclined surface 6c may have a shape that is inclined between the first direction DR1 and the third direction DR3.

[0224] In an embodiment, the first tilt angle θg formed by the third surface 6a and the second tilt surface 6c included in the fourth tip 4 may be an acute angle, and the second tilt angle θh formed by the fourth surface 6b and the second tilt surface 6c included in the fourth tip 4 may be an obtuse angle.

[0225] In embodiments, the third tip 3 and the fourth tip 4 may have different structures due to being executed in different processes. In embodiments, for example, the first tilt angle θg included in the fourth tip 4 may be greater than the first tilt angle θe included in the third tip 3. In the display device 30 according to an embodiment, the third upper conductive layer BN33 and the fourth upper conductive layer BN34 may include different materials and be formed by different processes, such that the first tilt angle θg included in the fourth tip 4 has a larger value than the first tilt angle θe included in the third tip 3.

[0226] The first element insulating layer DIL1 can completely cover the fourth surface 6b of the fourth upper conductive layer BN34.

[0227] Since the third dam layer BN3 includes a first tip 1, a second tip 2, a third tip 3 and a fourth tip 4, the display device 30 can include a first light-emitting element ED1, a second light-emitting element ED2 and a third light-emitting element ED3 spaced apart from each other during the manufacturing process without the need for a separate fine metal mask.

[0228] Furthermore, since the third dam layer BN3 includes a first tip 1, a second tip 2, a third tip 3, and a fourth tip 4, the display device 30 can increase the contact area between the cathode electrode CE and the cathode auxiliary electrode AX and the dam structure BN. Correspondingly, the resistance of the display device 30 can be reduced.

[0229] Figure 11 The illustration is for manufacturing. Figure 5 A flowchart of an embodiment of a method for displaying a display element layer.

[0230] Apart from Figures 1 to 10 In addition to referencing Figure 11 The method S1 for manufacturing a display element layer EML included in the display device 10 according to the embodiment may include a process S100 of forming a first dam layer, a second dam layer and a third dam layer with a dam structure on a substrate, a process S200 of forming a first tip and a second tip of the third dam layer by performing different etching processes, and a process S300 of forming a light-emitting element and an element inorganic layer on the dam structure.

[0231] Figure 12 It is used to describe Figure 11 The cross-sectional view of process S100.

[0232] Reference Figure 12 S100 describes the process of forming a first dam layer, a second dam layer, and a third dam layer on a substrate to form a dam structure.

[0233] First, multiple second connection electrodes CNE2 are formed on the first via layer VIA1, and the second via layer VIA2, the third insulating layer ILD3, the dam structure BN, and the first element insulating layer DIL1 are completely formed.

[0234] In this process, the dike structure BN may include a first dike layer BN1, a second dike layer BN2 and a third dike layer BN3 stacked in sequence, and the third dike layer BN3 may include a first upper conductive layer BN31 and a second upper conductive layer BN32.

[0235] In this process, the first upper conductive layer BN31 and the second upper conductive layer BN32 of the second dam layer BN2 and the third dam layer BN3 can comprise different materials. In an embodiment, for example, the first upper conductive layer BN31 and the second upper conductive layer BN32 can comprise materials having greater etch resistance than the second dam layer BN2. Any repeated detailed descriptions thereof will be omitted.

[0236] Although not illustrated in the accompanying drawings, a transistor layer TFTL, including a third insulating layer ILD3, a first via layer VIA1, and a second via layer VIA2, can be disposed on the substrate SUB, and the detailed structure of the transistor layer TFTL is similar to... Figure 5The structures shown in the diagram are the same.

[0237] Next, an anode electrode AE ​​and a second element insulating layer DIL2 are formed on the first element insulating layer DIL1. In this process, the anode electrode AE ​​can be formed by a deposition process and a patterning process including at least one of the materials described above for forming the anode electrode AE, and the second element insulating layer DIL2 can be formed by a deposition process and a patterning process including at least one of the inorganic insulating materials described above.

[0238] Figures 13 to 17 It is used to describe Figure 11 The cross-sectional view of process S200.

[0239] Reference Figures 13 to 17 The process S200 describes the formation of the first and second tips of the third embankment by performing different etching processes.

[0240] First, photoresist PR1 is formed on the anode electrode AE ​​and the second element insulating layer DIL2, and a first etching process is performed. In this process, multiple photoresist PR1s can be formed, and the photoresist PR1s can completely cover the anode electrode AE ​​and the second element insulating layer DIL2.

[0241] In such a process, the first etching process can be performed as a dry etching process. In embodiments, for example, the dry etching process can be performed using reactive ion etching (RIE) processes employing reactive gases such as CHF3, CH3F, CH2F2, CHF6, CF4, C2F6, and C3F6, and sputtering gases such as Ar and O2 / Ar. In such embodiments, an inductively coupled plasma (ICP) source or a capacitively coupled plasma (CCP) source can be used as the plasma source.

[0242] Through this process, the first element insulating layer DIL1 and the second upper conductive layer BN32, which do not overlap with the photoresist PR1, can be removed in one step. Accordingly, a temporary opening TOP can be formed in the portion that does not overlap with the photoresist PR1, and the first upper conductive layer BN31 can be exposed in the portion that overlaps with the temporary opening TOP.

[0243] Next, a second etching process is performed using the current photoresist PR1. This second etching process can be performed as a wet etching process. In such a process, the etchant can include any etchant specifically designed to etch transparent conductive oxides (TCOs) and exhibiting etching selectivity for aluminum (Al). In embodiments, for example, the etchant used in this process can include oxalic acid, inorganic acids, etc.

[0244] In this process, the first upper conductive layer BN31, which does not overlap with the photoresist PR1, can be removed, and the second dam layer BN2 can be exposed in the portion overlapping with the temporary opening TOP. Through this process, the first upper conductive layer BN31 can have a regular conical or trapezoidal shape. Any repeated detailed descriptions thereof will be omitted.

[0245] Next, a third etching process is performed using the current photoresist PR1. This third etching process can be performed as a wet etching process. The etchant used in this process may include phosphoric acid. In embodiments, for example, the etchant composition may include approximately 40% to approximately 60% phosphoric acid, approximately 2% to approximately 9% nitric acid, and approximately 5% to approximately 15% acetic acid.

[0246] In this process, the second dam layer BN2, which does not overlap with the photoresist PR1, can be completely removed, and the first dam layer BN1 can be exposed in the portion that overlaps with the temporary opening TOP.

[0247] In this process, the second embankment layer BN2 can have a higher etching rate than the first upper conductive layer BN31 and the second upper conductive layer BN32. Accordingly, the first side surface 2c of the second embankment layer BN2 can be formed to be recessed in the first direction DR1 than the first upper conductive layer BN31 and the second upper conductive layer BN32.

[0248] In this process, tin (Sn) included in the first upper conductive layer BN31 at a content of approximately 18% and less than approximately 30% can react with phosphate (PO4) included in the phosphoric acid etching solution. - Adsorption provides etch resistance. As a result, the first upper conductive layer BN31 does not react with the etch solution of the third etching process and can maintain the shape of the first tip 1 protruding from the first side surface 2c of the second embankment layer BN2 in the first direction DR1.

[0249] Furthermore, the titanium (Ti) included in the second upper conductive layer BN32 of the third dam layer BN3 and the first dam layer BN1 can provide resistance to wet etchants. Accordingly, the second upper conductive layer BN32 does not react with the etch solution of the third etching process and can maintain the shape of the second tip tip2 protruding from the first side surface 2c of the second dam layer BN2 in the first direction DR1, and the first dam layer BN1 can be retained without being removed.

[0250] Through this process, an undercut can be formed between the first side surface 2c of the second embankment layer BN2 and the third embankment layer BN3, and the embankment structure BN can have an overhanging structure. Although not illustrated in the accompanying drawings, the photoresist PR1 can be removed by performing an ashing process.

[0251] The display device 10 according to the embodiment can be easily manufactured by performing a first etching process, a second etching process, and a third etching process using the same photoresist PR1.

[0252] Figures 18 to 21 It is used to describe Figure 11 The cross-sectional view of process S300.

[0253] Reference Figures 18 to 21 The process S300 describes the formation of light-emitting elements and inorganic layers of elements on the embankment structure.

[0254] First, a first light-emitting element ED1 is formed by depositing a first light-emitting layer EL1, a cathode electrode CE, and a cathode auxiliary electrode AX on the anode electrode AE.

[0255] In this process, the formation of the first luminescent layer EL1 can be performed using a thermal deposition process. The formation of the first luminescent layer EL1 can be performed through full-surface deposition without the need for a separate fine metal mask.

[0256] Accordingly, in this process, the material forming the first light-emitting layer EL1 can be formed not only on the anode electrode AE ​​overlapping the first light-emitting region EA1, but also on the anode electrode AE ​​located in the portion overlapping the second light-emitting region EA2 and the third light-emitting region EA3. The first light-emitting layers EL1 located in the portions overlapping the first to third light-emitting regions EA1, EA2 and EA3 can be spaced apart from each other.

[0257] Alternatively, the material forming the first light-emitting layer EL1 can also be formed on the first diaphragm layer BN1. The material forming the first light-emitting layer EL1 on the anode electrode AE ​​and the material forming the first light-emitting layer EL1 on the first diaphragm layer BN1 can be spaced apart from each other. The material forming the first light-emitting layer EL1 temporarily located on the first diaphragm layer BN1 can be referred to as an organic patterned ELP.

[0258] In this process, the formation of the cathode electrode CE can be performed using either thermal deposition or sputtering. The formation of the cathode electrode CE can achieve a higher step coverage than the formation of the first light-emitting layer EL1. Therefore, the cathode electrode CE can completely cover the first light-emitting layer EL1.

[0259] In this process, the formation of the cathode electrode CE can be performed through full-surface deposition without the need for a separate fine metal mask. Accordingly, the material forming the cathode electrode CE can be formed not only on the first light-emitting layer EL1 overlapping the first light-emitting region EA1, but also on the portion of the first light-emitting layer EL1 overlapping the second light-emitting region EA2 and the third light-emitting region EA3. The cathode electrodes CE located in the portions overlapping the first to third light-emitting regions EA1, EA2, and EA3 can be spaced apart from each other.

[0260] Furthermore, the material forming the cathode electrode CE can be formed not only on the first light-emitting layer EL1, but also on the organic pattern ELP. The materials forming the cathode electrode CE on the first light-emitting layer EL1 and the materials forming the cathode electrode CE on the organic pattern ELP can be spaced apart from each other. The material forming the cathode electrode CE temporarily formed on the first diaphragm layer BN1 can be referred to as the electrode pattern CEP.

[0261] In this process, the cathode electrode CE can contact and cover the first tip 1 of the first upper conductive layer BN31 and the second tip 2 of the second upper conductive layer BN32. Since the display device 10 according to the embodiment includes the first tip 1 of the first upper conductive layer BN31 and the second tip 2 of the second upper conductive layer BN32, the contact area between the cathode electrode CE and the dam structure BN can be increased, thereby reducing the resistance of the display device 10. Any repeated detailed description will be omitted.

[0262] The process of forming the cathode auxiliary electrode AX can be performed by sputtering. The process of forming the cathode auxiliary electrode AX can have a higher step coverage than the process of forming the cathode electrode CE. Therefore, the cathode auxiliary electrode AX can completely cover the cathode electrode CE. In embodiments, for example, the cathode electrode CE and the cathode auxiliary electrode AX can be integrally formed as a single, inseparable part.

[0263] In this process, the formation of the cathode auxiliary electrode AX can be performed through full-surface deposition without the need for a separate fine metal mask. Accordingly, the material forming the cathode auxiliary electrode AX can be formed not only on the cathode electrode CE overlapping the first light-emitting region EA1, but also on the cathode electrode CE located in the portions overlapping the second and third light-emitting regions EA2 and EA3. The cathode auxiliary electrodes AX located in the portions overlapping the first to third light-emitting regions EA1, EA2, and EA3 can be spaced apart from each other.

[0264] Furthermore, the material forming the cathode auxiliary electrode AX can be formed not only on the cathode electrode CE, but also on the electrode pattern CEP. The materials forming the cathode auxiliary electrode AX on the cathode electrode CE and the materials forming the cathode auxiliary electrode AX on the electrode pattern CEP can be spaced apart from each other. The material forming the cathode auxiliary electrode AX temporarily formed on the first embankment layer BN1 can be referred to as the auxiliary electrode pattern AXP.

[0265] In this process, the material forming the cathode auxiliary electrode AX can cover the first tip 1 of the first upper conductive layer BN31 and the second tip 2 of the second upper conductive layer BN32, and can contact the first tip 1 of the first upper conductive layer BN31.

[0266] Next, an inorganic layer IO is formed on the cathode auxiliary electrode AX. The inorganic layer IO can completely cover the cathode auxiliary electrode AX with a uniform thickness along the contour of the underlying structure.

[0267] In such a process, the formation of the inorganic layer IO of the component can be achieved by a film-forming process (e.g., deposition process) of at least one of the inorganic insulating materials described above.

[0268] Next, photoresist PR2 is formed in the portion overlapping with and around the first light-emitting region EA1, and photoresist PR2 is used as a mask to perform a fourth etching process. In an embodiment, for example, dry etching and wet etching processes may be performed alternately in the fourth etching process.

[0269] In this process, the materials that do not overlap with the photoresist PR2, forming the first light-emitting layer EL1, the cathode electrode CE, the cathode auxiliary electrode AX, and the element inorganic layer IO, can all be removed. Accordingly, the anode electrode AE ​​overlapping with the second light-emitting region EA2 and the anode electrode AE ​​overlapping with the third light-emitting region EA3 can be exposed again, and the element inorganic layer IO can be formed in the form of the first element inorganic layer IO1.

[0270] In this process, the first element inorganic layer IO1 can be spaced apart from the first embankment layer BN1 on the third-direction DR3. This may be due to the removal of the organic pattern ELP, electrode pattern CEP, and auxiliary electrode pattern AXP by the fourth etching process.

[0271] In this way, a first light-emitting element ED1 and a first element inorganic layer IO1 can be formed in the portion that overlaps with the first light-emitting region EA1.

[0272] Next, by repeating the above process, a second light-emitting layer EL2, a cathode electrode CE, a cathode auxiliary electrode AX, and an inorganic element layer IO are formed on the anode electrode AE ​​that overlaps with the second light-emitting region EA2. Through this process, a second light-emitting element ED2 and a second element inorganic layer IO2 that overlap with the second light-emitting region EA2 can be formed.

[0273] Furthermore, by repeating the above process, a third light-emitting layer EL3, a cathode electrode CE, a cathode auxiliary electrode AX, and an inorganic element layer IO are formed on the anode electrode AE ​​that overlaps with the third light-emitting region EA3. Through this process, a third light-emitting element ED3 and a third element inorganic layer IO3 that overlap with the third light-emitting region EA3 can be formed.

[0274] Therefore, it can form Figure 5 The diagram shows the display element layer (EML).

[0275] Return to reference Figures 1 to 21 Since the display device 10 according to the embodiment includes a first tip 1 of a first upper conductive layer BN31 and a second tip 2 of a second upper conductive layer BN32, a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3 spaced apart from each other can be formed in the portions overlapping the first to third light-emitting regions EA1, EA2, and EA3, respectively, without the need for a separate fine metal mask. Accordingly, the display device 10 according to the embodiment can be easily manufactured.

[0276] In addition, the display device 10 according to the embodiment can effectively provide a high-resolution display device by providing a dam structure BN in the portion overlapping with the light-emitting area EA and forming a first light-emitting element ED1, a second light-emitting element ED2 and a third light-emitting element ED3 on the dam structure BN.

[0277] Furthermore, the display device 10 according to the embodiment can increase the contact area between the cathode electrode CE and / or the cathode auxiliary electrode AX and the dam structure BN by forming a first tip 1 and a second tip 2 with regular conical shapes without using a separate mask. Accordingly, the resistance of the display device 10 according to the embodiment can be reduced.

[0278] Figure 22 This is a block diagram of an electronic device according to an embodiment.

[0279] Apart from Figures 1 to 21 In addition to referencing Figure 22The display device 10 or 30 according to the embodiments can be applied to various electronic devices 1. The electronic device 1 according to the embodiments may include the display device 10 or 30 described above, and may further include modules or devices with additional functions in addition to the display device 10 or 30.

[0280] The electronic device 1 according to the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0281] Display module 11 may include a display device corresponding to one of the above embodiments.

[0282] The processor 12 may include at least one selected from a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0283] Data information used for the operation of processor 12 or display module 11 can be stored in memory 13. When processor 12 executes the application stored in memory 13, image data signals and / or input control signals can be transmitted to display module 11, and display module 11 can process the provided signals and output image information through the display screen.

[0284] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power for the operation of the electronic device 1.

[0285] At least one of the aforementioned components of electronic device 1 may be included in the display device according to the above embodiments. Additionally, some of the aforementioned modules may be included within the display device, while others may be provided separately from the display device. In an embodiment, for example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided within electronic device 1 as other devices besides the display device.

[0286] Figure 23 The illustrations are schematic diagrams of electronic devices according to various embodiments.

[0287] refer to Figure 23The various electronic devices 1 to which the display device 10 or 30 is applied according to the embodiments may include not only image display electronic devices such as smartphones 1_1a, tablet PCs 1_1b, laptop computers 1_1c, televisions (TVs) 1_1d, and desktop monitors 1_1e, but also wearable electronic devices including display modules such as smart glasses 1_2a, head-mounted displays 1_2b, and smartwatches 1_2c, as well as vehicle electronic devices 1_3 including display modules such as in-vehicle mirror displays, central information displays (CIDs) installed on the instrument panel, central dashboard, or instrument panel of a vehicle.

[0288] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the concept of the invention to those skilled in the art.

[0289] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: The substrate includes light-emitting and non-light-emitting areas; A dam structure, located in the light-emitting region of the substrate, wherein the dam structure includes a first dam layer, a second dam layer, and a third dam layer defining a cantilever structure; and A light-emitting element is located on the embankment structure and includes an anode electrode, a light-emitting layer, and a cathode electrode. The third embankment layer includes: A first upper conductive layer, located on the second dam layer and including a first tip protruding beyond the side surface of the second dam layer; and A second upper conductive layer is located on the first upper conductive layer and includes a second tip that overlaps with the first tip. The undercut is defined between the first tip and the second tip.

2. The display device according to claim 1, wherein The first tip includes: The first surface faces the second embankment layer; A second surface, opposite to the first surface; and A first inclined surface connects the first surface and the second surface, and The first tilt angle formed by the first surface and the first tilted surface is an acute angle.

3. The display device according to claim 2, wherein The second tip includes: The third surface faces the first upper conductive layer; A fourth surface, opposite to the third surface; and A second inclined surface connects the third and fourth surfaces. The second tilt angle formed by the third surface and the second tilted surface is an acute angle, and The second tilt angle is greater than the first tilt angle.

4. The display device according to claim 3, wherein The undercut is defined between the first inclined surface and the second tip, and The cathode electrode contacts and covers the first tip and the second tip.

5. The display device according to claim 1, wherein The second dam layer, the first upper conductive layer, and the second upper conductive layer comprise different materials from each other.

6. The display device of claim 5, wherein, The first upper conductive layer comprises a transparent conductive oxide containing tin, and The tin content in the first upper conductive layer is more than 18% and less than 30%.

7. The display device of claim 6, wherein, The second dam layer comprises aluminum, and The second upper conductive layer comprises titanium.

8. The display device according to claim 1, further comprising: The first element insulating layer is located between the dam structure and the anode electrode; as well as A second insulating layer covers the edge of the anode electrode and contacts the first insulating layer, wherein the light-emitting opening is defined within the second insulating layer. Wherein, the first element insulating layer and the second element insulating layer overlap with the first tip and the second tip.

9. The display device of claim 8, wherein, The light-emitting layer completely covers the insulating layer of the second element. The light-emitting layer overlaps with the first tip and the second tip in a direction perpendicular to the substrate, and The light-emitting layer does not contact the first tip of the first upper conductive layer.

10. The display device of claim 8, wherein, In the plan view, the third embankment layer has a shape configured to form a conductive pattern surrounding the light-emitting opening.

11. The display device according to claim 1, wherein The third levee layer further includes: A third upper conductive layer, located on the second upper conductive layer and including a third tip overlapping the first tip and the second tip; and A fourth upper conductive layer, located on the third upper conductive layer and including a fourth tip overlapping the first tip, the second tip, and the third tip. The first upper conductive layer and the third upper conductive layer comprise the same material as each other, and The second upper conductive layer and the fourth upper conductive layer comprise the same material as each other.

12. A method for manufacturing a display device, the method comprising: A first dam layer, a second dam layer, and a third dam layer of a dam structure are formed on a substrate; The first and second tips of the third embankment are formed by performing different etching processes; as well as Light-emitting elements and an inorganic layer of the elements are formed on the embankment structure.

13. The method of claim 12, wherein, The third dam layer includes a first upper conductive layer and a second upper conductive layer, which are made of different materials from each other. The first upper conductive layer comprises a transparent conductive oxide containing tin, and The first upper conductive layer has a first tip that protrudes beyond the side surface of the second embankment layer, formed by performing a wet etching process.

14. The method of claim 13, wherein, The second upper conductive layer comprises titanium, and The second upper conductive layer has a second tip that protrudes beyond the side surface of the second embankment layer, formed by performing a dry etching process.

15. An electronic device comprising: The display device according to any one of claims 1 to 11; as well as At least one of a processor, memory, and power module is connected to the display device.

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