Display device

Abstract

According to embodiments of the present disclosure, a display device is provided, comprising: a substrate including an active region for displaying an image and a curved region located on one side of the active region and having curvature; at least one first connecting line, the at least one first connecting line being directly disposed on the upper surface of the substrate in the curved region; a first planarization layer disposed on the at least one first connecting line; and at least one second connecting line disposed on the first planarization layer and passing through the first planarization layer to connect to the at least one first connecting line.

Description

Technical Field

[0001] This disclosure relates to display devices. Background Technology

[0002] Display devices are used in various electronic devices, such as televisions, mobile phones, laptops, and tablets.

[0003] Examples of display devices include self-emissive organic light-emitting diode (OLED) display devices and liquid crystal display (LCD) devices that require a separate light source.

[0004] The bezel area of ​​a display device is a factor that reduces aesthetics and immersion due to its visibility to users. Recently, narrow-bezel displays with reduced bezel areas where images are not displayed have become a focus. Summary of the Invention

[0005] Research is underway to reduce the bezel area of ​​a display device that is visible to the user by using a flexible substrate to bend the non-active area of ​​a display panel and hiding the pad area of ​​the non-active area on the back surface of the active area. Connecting lines for electrically connecting the active area to the pad area can be provided in the bent area of ​​the display panel, and an organic material can be provided to cover the connecting lines.

[0006] Due to the curvature of the curved areas of the display panel, tensile stress can be applied to the connecting lines in the curved areas, and therefore cracks may appear in the connecting lines in the curved areas. In particular, the greatest tensile stress can be applied to the connecting lines in the areas of the curved areas with the greatest curvature (i.e., the areas with the smallest radius of curvature), and cracks may appear in the connecting lines.

[0007] This disclosure aims to provide a display device that can prevent cracks from appearing in the connecting lines within the bending area of ​​the display panel.

[0008] This disclosure also aims to provide a display device that can reduce the production energy required for production and reduce greenhouse gas emissions.

[0009] The purpose of this disclosure is not limited to the above purposes, and those skilled in the art will be able to clearly understand other purposes not described based on the following description.

[0010] According to embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate including an active region for displaying an image and a curved region located on one side of the active region and having curvature; at least one first connecting line, the at least one first connecting line being directly disposed on the upper surface of the substrate in the curved region; a first planarization layer disposed on the at least one first connecting line; and at least one second connecting line disposed on the first planarization layer and passing through the at least one first planarization layer and connected to the at least one first connecting line.

[0011] According to embodiments of this disclosure, by removing the intermediate substrate layer of the substrate in the minimum radius of curvature region of the curved area of ​​the display panel and directly arranging the connecting lines on the upper surface of the upper substrate layer of the substrate, the tensile stress applied to the connecting lines can be reduced, thereby preventing cracks from appearing in the connecting lines.

[0012] According to embodiments of this disclosure, since the defect rate of the display device caused by cracks in the bending region is low, the production energy required to produce the display device can be reduced, and greenhouse gas emissions can be reduced.

[0013] The effects of this disclosure are not limited to those described above, and those skilled in the art will be able to clearly understand other effects not described based on the following detailed description. Attached Figure Description

[0014] Figure 1 This is a plan view of a display device according to one embodiment of the present disclosure.

[0015] Figure 2 It is along Figure 1 A cross-sectional view of the display device in line II-II.

[0016] Figure 3 It is along Figure 1 A cross-sectional view of the display device shown in line III-III.

[0017] Figure 4 yes Figure 3 A magnified view of region IV in the image.

[0018] Figure 5 This is a cross-sectional view of the curved region of a display panel according to one embodiment of the present disclosure.

[0019] Figure 6 This is a cross-sectional view showing a portion of a curved region of a display panel according to one embodiment of the present disclosure. Detailed Implementation

[0020] The advantages and features of this disclosure, as well as the methods for implementing them, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. These embodiments are provided only to make this disclosure complete and to fully inform those skilled in the art of the scope of this disclosure.

[0021] Since the shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings used to describe embodiments of this disclosure are illustrative, this disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same parts. Furthermore, in describing this disclosure, detailed descriptions of related known technologies are omitted where it is determined that such detailed descriptions might unnecessarily obscure the essential points of this disclosure. When terms such as "comprising," "having," or "consisting of" are used herein, additional parts may be added unless "only" is used. When a part is represented in the singular, it includes multiple parts unless specifically stated otherwise.

[0022] When interpreting a component, even without a separate explicit description of the tolerance margin, the component is interpreted as including the tolerance margin.

[0023] When describing positional relationships, for example, when using "on top of," "above," "below," "next to," etc. to describe the positional relationship between two parts, one or more other parts can be positioned between the two parts unless "immediately adjacent," "directly," or "near" is used.

[0024] When describing temporal relationships, the use of terms such as "after," "following," "then," and "before" can include non-continuous cases unless "immediately following" or "directly" is used.

[0025] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. The terms are used only to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the first component described below can be a second component.

[0026] In the description of the components of this disclosure, terms such as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used. These terms are used only for the purpose of distinguishing one component from another, and the nature, order, sequence, etc., of the corresponding components are not limited by the terms.

[0027] When a particular component is described as being “connected,” “coupled,” “linked,” or “attached” to other components, that particular component may be directly connected, coupled, linked, or attached to other components. However, it should be understood that, unless otherwise specifically stated, another component may be inserted between components that may be indirectly connected, coupled, linked, or attached.

[0028] When a component or layer is described as "in contact" or "overlapping" with other components or layers, the component or layer may be in direct contact or directly overlap with other components or layers. However, it should be understood that, unless otherwise specifically stated, another component may be inserted between components that may be in indirect contact or overlap with each other.

[0029] It should be understood that "at least one" includes any combination of one or more of the associated components. For example, "at least one of the first component, the second component, and the third component" may include not only the first component, the second component, or the third component, but also any combination of two or more of the first component, the second component, and the third component.

[0030] The terms “first direction,” “second direction,” “third direction,” “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted as merely a geometric relationship in which the relationship between them is perpendicular, but can refer to a wider range of directions within which the configuration of this disclosure can be functionally effective.

[0031] Features of various embodiments of this disclosure may be coupled or combined in part or in whole, various technical interactions and drives are possible, and embodiments may be implemented independently of each other or together in an associated relationship.

[0032] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a plan view of a display device according to one embodiment of the present disclosure.

[0034] Reference Figure 1 According to one embodiment of this disclosure, the display device 100 may include a display panel PNL, a polarizing plate POL, a chip-on-film (COF) assembly, a printed circuit board, etc. A data driver chip may be mounted on the COF assembly. A timing controller and a power supply may be mounted on the printed circuit board.

[0035] The display panel PNL may include an active area AA and an active area NAA. The active area AA and the active area NAA can be areas of the substrate. The active area AA is the area where the image is displayed. The active area NAA is the area where no image is displayed and is located outside the active area AA.

[0036] The active region AA is the area where multiple pixels are arranged. Each pixel can include multiple sub-pixels. The non-active region NAA is the area where gate drivers and various lines are arranged.

[0037] The active region AA includes multiple data lines and multiple gate lines arranged to intersect each other. The multiple gate lines may extend, for example, in a first direction DR1, and the multiple data lines may extend, for example, in a second direction DR2.

[0038] A non-active region NAA can be configured to surround an active region AA. For example, when the active region AA has a quadrilateral shape, the non-active region NAA can be configured to be positioned above, below, to the left, and to the right of the active region AA.

[0039] The gate driver (not shown) can be located, for example, in the non-active region NAA positioned to the left and right of the active region AA.

[0040] The non-active region NAA, located below the active region AA, includes: a pad region PA where the chip-on-film (COF) and a printed circuit board (not shown) are joined, a link region LA, and a curved region BA defined between the link region LA and the pad region PA. The pad region PA may include multiple pads connected to the chip-on-film (COF).

[0041] The curved area BA of the non-active region NAA of the display panel PNL can be bent at a predetermined curvature. Because the curved area BA of the display panel PNL is bent, the pad area PA of the non-active region NAA can be positioned below the active region AA. Therefore, the lower bezel area of ​​the display device 100 can be reduced.

[0042] A touch sensor can be disposed on the active area AA of the display panel PNL. The touch sensor can be, for example, of mutual capacitance type. The touch sensor may include, for example, multiple first touch lines extending in a first direction DR1 and multiple second touch lines extending in a second direction DR2.

[0043] A polarizing plate (POL) can be installed on the display panel PNL to prevent external light reflection.

[0044] Figure 2 It is along Figure 1 A cross-sectional view of the display device in line II-II. Figure 2 A sub-pixel of a display device according to an embodiment of the present disclosure is shown schematically.

[0045] Reference Figure 2The display device according to embodiments of the present disclosure may include a display panel PNL, a first back plate BP1 supporting the display panel PNL, and a polarizing plate POL disposed on the display panel PNL. The display panel PNL may include a substrate 101, a first thin-film transistor 120, a storage capacitor 130, a second thin-film transistor 140, a light-emitting element 160, and a touch sensor 186.

[0046] Substrate 101 may include an insulating material. Substrate 101 may include a flexible polymer material. Substrate 101 may have a multilayer structure. For example, substrate 101 may include a lower substrate layer 101a, an upper substrate layer 101c, and an intermediate substrate layer 101b disposed between the lower substrate layer 101a and the upper substrate layer 101c. The lower substrate layer 101a and the upper substrate layer 101c may include polymer materials such as polyimide (PI). The intermediate substrate layer 101b may be formed of an inorganic insulating material such as silicon oxide or silicon nitride. Substrate 101 may be a flexible substrate.

[0047] The first backplate BP1 can be disposed below the substrate 101. The first backplate BP1 can be attached to the lower surface of the substrate 101 by an adhesive layer. The first backplate BP1 can be formed of a polymer material such as polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), etc.

[0048] A first buffer layer 105 may be disposed on the substrate 101. The first buffer layer 105 may be disposed over the entire active region AA of the substrate 101. The first buffer layer 105 may include an insulating material. For example, the first buffer layer 105 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride. The first buffer layer 105 may have a multilayer structure.

[0049] A light-shielding layer 109 may be provided on the first buffer layer 105. The light-shielding layer 109 may include a metallic material. For example, the light-shielding layer 109 may include a metallic material such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W).

[0050] A second buffer layer 112 covering the light-shielding layer 109 can be provided on the first buffer layer 105. The second buffer layer 112 may include an insulating material. For example, the second buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride. The second buffer layer 112 may have a multilayer structure.

[0051] A driving circuit can be positioned in each sub-pixel. The driving circuit can generate a driving current supplied to the light-emitting element. The driving circuit can be electrically connected to signal lines. For example, signal lines may include a gate line GL for applying a gate signal, a data line DL for applying a data signal, and a power supply line for supplying power voltage. For example, the driving circuit may include a first thin-film transistor 120, a second thin-film transistor 140, and a storage capacitor 130.

[0052] The first thin-film transistor 120 can be electrically connected to the light-emitting element 160. The first thin-film transistor 120 may include a first semiconductor pattern 121, a first gate insulating layer 122, a first gate electrode 123, a first source electrode 124, and a first drain electrode 125. The first semiconductor pattern 121 may be disposed on the second buffer layer 112.

[0053] The first semiconductor pattern 121 may include a semiconductor material. For example, the first semiconductor pattern 121 may include a polycrystalline semiconductor material. For example, the first semiconductor pattern 121 may include low-temperature polycrystalline silicon (LTPS).

[0054] A first gate insulating layer 122 may be positioned on a first semiconductor pattern 121. The first gate insulating layer 122 may extend outward from the first semiconductor pattern 121. For example, the first gate insulating layer 122 may extend along the upper surface of the second buffer layer 112. The first gate insulating layer 122 may include an insulating material. For example, the first gate insulating layer 122 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon nitride.

[0055] The first gate electrode 123 may be positioned on the first gate insulating layer 122. The first gate electrode 123 may include a conductive material. For example, the first gate electrode 123 may include metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The first gate electrode 123 may be electrically insulated from the first semiconductor pattern 121 through the first gate insulating layer 122. The first gate electrode 123 may overlap with the first channel region of the first semiconductor pattern 121.

[0056] The first interlayer insulating layer 114 may be positioned on the first gate electrode 123. The first interlayer insulating layer 114 may extend outward from the first gate electrode 123. The first interlayer insulating layer 114 may extend along the upper surface of the first gate insulating layer 122. The first interlayer insulating layer 114 may include an insulating material. For example, the first interlayer insulating layer 114 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon nitride.

[0057] The first source electrode 124 and the first drain electrode 125 can be electrically connected to the first semiconductor layer 121.

[0058] The storage capacitor 130 may include a first storage electrode 131 and a second storage electrode 132. For example, the first storage electrode 131 may be positioned on the same layer as the first gate electrode 123. For example, the first storage electrode 131 may be formed of the same material as the first gate electrode 123. The first storage electrode 131 may be disposed near the first gate electrode 123 on the first gate insulating layer 122. The second storage electrode 132 may be disposed overlapping the first storage electrode 131 on the first interlayer insulating layer 114.

[0059] The first storage electrode 131 and the second storage electrode 132 may include conductive materials. For example, the first storage electrode 131 and the second storage electrode 132 may include metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0060] The separating insulating layer 116 may cover the second storage electrode 132 and may be disposed on the first interlayer insulating layer 114. The separating insulating layer 116 may include an insulating material. For example, the separating insulating layer 116 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon nitride. For example, the separating insulating layer 116 may have a multilayer structure including silicon oxide and silicon nitride.

[0061] The second thin-film transistor 140 may be electrically connected to the first thin-film transistor 120. For example, the second thin-film transistor 140 may include a second semiconductor pattern 141, a second gate insulating layer 142, a second gate electrode 143, a second source electrode 145, and a second drain electrode 146.

[0062] The second semiconductor pattern 141 may include a semiconductor material. The second semiconductor pattern 141 may include a material different from the first semiconductor pattern 121. For example, the second semiconductor pattern 141 may include an oxide semiconductor such as IGZO. The second semiconductor pattern 141 may be positioned on a layer different from the first semiconductor pattern 121. The second semiconductor pattern 141 may be positioned on the separation insulating layer 116. Therefore, damage to the second semiconductor pattern 141 due to the process of forming the first semiconductor pattern 121 can be prevented.

[0063] A second gate insulating layer 142 may be disposed on the second semiconductor pattern 141. The second gate insulating layer 142 may extend outward from the second semiconductor pattern 141. For example, the second gate insulating layer 142 may extend along the upper surface of the separation insulating layer 116. The second gate insulating layer 142 may include an insulating material. For example, the second gate insulating layer 142 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon nitride.

[0064] The second gate electrode 143 may be disposed on the second gate insulating layer 142. For example, the second gate electrode 143 may overlap with the second channel region of the second semiconductor pattern 141. The second gate electrode 143 may include a conductive material. For example, the second gate electrode 143 may include metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). For example, the second gate electrode 143 may be formed of the same material as the first gate electrode 123. The second gate electrode 143 may be insulated from the second semiconductor pattern 141 through the second gate insulating layer 142.

[0065] The second interlayer insulating layer 118 can be positioned on the second gate electrode 143. The second interlayer insulating layer 118 can extend outward from the second gate electrode 143. The second interlayer insulating layer 118 can extend along the upper surface of the separating insulating layer 116. The second interlayer insulating layer 118 can include an insulating material. For example, the second interlayer insulating layer 118 can include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon nitride. For example, the second interlayer insulating layer 118 can have a multilayer structure including silicon oxide and silicon nitride.

[0066] The first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may be disposed on the second interlayer insulating layer 118. The first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may include conductive materials. For example, the first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may include metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). For example, the first source electrode 124, the first drain electrode 125, the second source electrode 145, and the second drain electrode 146 may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0067] The first source electrode 124 and the first drain electrode 125 can be electrically connected to the first semiconductor layer 121. For example, the first source electrode 124 and the first drain electrode 125 can be in direct contact with the first semiconductor pattern 121 through contact holes passing through the second interlayer insulating layer 118, the second gate insulating layer 142, the separation insulating layer 116, the first interlayer insulating layer 114, and the first gate insulating layer 122.

[0068] The second source electrode 145 and the second drain electrode 146 can be electrically connected to the second semiconductor layer 141. For example, the second source electrode 145 and the second drain electrode 146 can be in direct contact with the second semiconductor pattern 141 through contact holes passing through the second interlayer insulating layer 118 and the second gate insulating layer 142.

[0069] The second thin-film transistor 140 can be disposed on the storage capacitor 130. For example, the second semiconductor pattern 141 of the second thin-film transistor 140 can overlap with the storage capacitor 130. Light passing through the substrate 101 and traveling toward the second semiconductor pattern 141 can be blocked by the storage capacitor 130. Therefore, changes in the characteristics of the second thin-film transistor 140 due to external light can be prevented. The storage capacitor 130 can be electrically connected to the second drain electrode 146 of the second thin-film transistor 140. For example, the second drain electrode 146 can be in direct contact with the first storage electrode 131 through contact holes passing through the second interlayer insulating layer 118, the second gate insulating layer 142, the separation insulating layer 116, and the first interlayer insulating layer 114.

[0070] The light-emitting element 160 can be disposed on the driving circuit. For example, the first thin-film transistor 120, the second thin-film transistor 140 and the storage capacitor 130 of each sub-pixel can be positioned between the substrate 101 and the light-emitting element 160.

[0071] The first planarization layer 150 and the second planarization layer 154 may be sequentially stacked between the driving circuit and the light-emitting element 160. The first planarization layer 150 and the second planarization layer 154 may cover the steps caused by the driving circuit to provide a flat surface. For example, the first planarization layer 150 and the second planarization layer 154 may include an organic insulating material.

[0072] A pixel contact electrode 152 may be disposed on the first planarization layer 150. A light-emitting element 160 may be disposed on the second planarization layer 154. The light-emitting element 160 may include a first electrode 161, a light-emitting layer 165, and a second electrode 167. The light-emitting element 160 may be electrically connected to the first drain electrode 125 of the first thin-film transistor 120 via the pixel contact electrode 152. The pixel contact electrode 152 may include a conductive material. For example, the pixel contact electrode 152 may include a metallic material such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W). For example, the pixel contact electrode 152 may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0073] A dam layer 156 may be disposed on the second planarization layer 154. The dam layer 156 may include an organic insulating material. For example, the dam layer 156 may be formed of a photosensitive acrylic or polyimide organic material. The dam layer 156 may cover the edge of the first electrode 161. The dam layer 156 may have an opening that exposes a portion of the first electrode 161. The light-emitting layer 165 of the light-emitting element 160 and the second electrode 167 may be stacked on the portion of the first electrode 161 exposed through the dam layer 156. The light-emitting area may be defined by the portion of the first electrode 161 exposed through the opening of the dam layer 156. The first electrode 161 may include a conductive material. The first electrode 161 may have high reflectivity. For example, the first electrode 161 may include a metallic material such as aluminum (Al) or silver (Ag). The first electrode 161 may have a multilayer structure. For example, the first electrode 161 may have a structure in which a metal such as aluminum (Al) or silver (Ag) is disposed between transparent conductive materials such as ITO and IZO.

[0074] The light-emitting layer 165 may extend onto the embankment layer 156. The light-emitting layer 165 may include a light-emitting material layer 163. For example, the light-emitting material layer 163 may include an organic light-emitting material. The light-emitting layer 165 may have a multilayer structure. For example, the light-emitting layer 165 may include at least one of a first light-emitting common layer 162 positioned between the first electrode 161 and the light-emitting material layer 163 and a second light-emitting common layer 164 positioned between the light-emitting material layer 163 and the second electrode 167. For example, the first light-emitting common layer 162 may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL). The second light-emitting common layer 164 may include at least one of an electron transport layer (ETL) and an electron injection layer (EIL).

[0075] For example, when subpixels of each pixel emit light of a different color, the luminescent material layer 163 of each subpixel can be separated from the luminescent material layers 163 of adjacent subpixels. The luminescent material layer 163 of each subpixel can be formed individually using a fine metal mask (FMM). The end portions of the luminescent material layer 163 can be positioned on the embankment layer 156.

[0076] For example, spacer 158 can be disposed on the dam layer 156. Spacer 158 can prevent damage to the dam layer 156 and damage to the light-emitting material layer 163 through contact with the FMM. For example, spacer 158 can be formed of photosensitive acrylic or polyimide organic materials. Dam layer 156 and spacer 158 can be formed simultaneously by a single photolithography process, but are not limited thereto. Dam layer 156 and spacer 158 can also be formed by separate processes.

[0077] The first common light-emitting layer 162 and the second common light-emitting layer 164 of the light-emitting layer 165 can extend along the surface of the embankment layer 156. The first common light-emitting layer 162 and the second common light-emitting layer 164 of the light-emitting layer 165 can cover the upper surface and side surface of the spacer portion 158. For example, the first common light-emitting layer 162 and the second common light-emitting layer 164 can be jointly disposed in adjacent sub-pixels. For example, each of the first common light-emitting layer 162 and the second common light-emitting layer 164 can be jointly disposed in all pixels of the active region AA.

[0078] The second electrode 167 can be commonly disposed in adjacent sub-pixels. For example, the second electrode 167 can be commonly disposed in all pixels in the active region AA. The second electrode 167 may include a conductive material. For example, the second electrode 167 may be a transparent electrode formed of a transparent conductive material such as ITO and IZO.

[0079] The encapsulation portion 170 can be positioned on the light-emitting element 160. The encapsulation portion 170 can prevent damage to the light-emitting element 160 due to external impact and moisture. The encapsulation portion 170 can have a multi-layer structure. For example, the encapsulation portion 170 may include a first encapsulation layer 172, a second encapsulation layer 174, and a third encapsulation layer 176 stacked sequentially. For example, the first encapsulation layer 172 and the third encapsulation layer 176 may include inorganic insulating materials, while the second encapsulation layer 174 may include organic insulating materials.

[0080] The encapsulation portion 170 can extend outward from the active region AA. At least one dam structure can be provided in the non-active region NAA. For example, the dam structure can be positioned on the first planarization layer 150. For example, the dam structure can include at least one organic insulating material. For example, the dam structure can include a first layer formed of the same material as the second planarization layer 154 and a second layer formed of the same material as the dam layer 156. The dam structure can have a closed-loop shape surrounding the active region AA of the substrate 101. Since the flow of the fluid second encapsulation layer 174 can be blocked by the dam structure, the second encapsulation layer 174 can be positioned only on the portion of the substrate 101 defined by the dam structure. The third encapsulation layer 176 can be in direct contact with the first encapsulation layer 172 outside the second encapsulation layer 174.

[0081] A touch sensor 186 can be disposed on the package portion 170. The touch sensor 186 may include a bridge electrode 183, a first touch electrode 184, and a second touch electrode 185. The bridge electrode 183, the first touch electrode 184, and the second touch electrode 185 may be disposed at a position overlapping with the embankment layer 156. Light emitted from each light-emitting element 160 may not be blocked by the bridge electrode 183, the first touch electrode 184, and the second touch electrode 185.

[0082] A touch buffer layer 181 may be provided between the package 170 and the touch sensor 186. The touch buffer layer 181 can prevent damage to the package 170 and the light-emitting element 160 during the process of forming the first touch electrode 184, the bridge electrode 183, and the second touch electrode 185. For example, the upper surface of the package 170 may be covered by the touch buffer layer 181. For example, the touch buffer layer 181 may extend to the non-active region NAA. The touch buffer layer 181 may include an insulating material. For example, the touch buffer layer 181 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon nitride.

[0083] A bridge electrode 183 may be disposed on the touch buffer layer 181. A touch insulating layer 182 may be disposed on the bridge electrode 183. The touch insulating layer 182 may extend along the upper surface of the touch buffer layer 181. For example, the touch insulating layer 182 may extend to the non-active region NAA. For example, the touch insulating layer 182 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, and silicon nitride oxide.

[0084] A first touch electrode 184 and a second touch electrode 185 can be disposed on the touch insulating layer 182. A bridge electrode 183 can electrically connect adjacent first touch electrodes 184. Adjacent first touch electrodes 184 can be connected to the bridge electrode 183 through contact holes passing through the touch insulating layer 182. The bridge electrode 183 and the first touch electrodes 184 can form a first touch electrode line. The second touch electrode 185 can form a second touch electrode line.

[0085] The bridge electrode 183, the first touch electrode 184, and the second touch electrode 185 may include conductive materials. For example, the bridge electrode 183, the first touch electrode 184, and the second touch electrode 185 may include metallic materials such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W). For example, the bridge electrode 183, the first touch electrode 184, and the second touch electrode 185 may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0086] A touch protection layer 190 can be provided on the touch sensor 186. The touch protection layer 190 can prevent damage to the touch sensor 186 due to external impacts and moisture. The touch protection layer 190 may include an insulating material. For example, the touch protection layer 190 may include an organic insulating material. For example, the touch protection layer 190 may be formed of a photosensitive acrylic-based or polyimide-based organic material. The touch protection layer 190 may extend into the non-active area (NAA).

[0087] A cover layer 195 may be provided on the touch protection layer 190. For example, the cover layer 195 may include an organic insulating material. For example, the cover layer 195 may be formed of an acrylic, polyimide, epoxy, or silane resin. The touch protection layer 190 may extend into the non-active area NAA. The cover layer 195 may extend into the non-active area NAA.

[0088] A polarizing plate (POL) can be provided on the cover layer 195. The polarizing plate POL can be attached to the upper surface of the cover layer 195 via an adhesive layer. The polarizing plate POL is a circular polarizing plate and can improve the outdoor visibility of the display device by preventing internal reflections caused by external light. Depending on the configuration of the display panel PNL, the polarizing plate POL can be omitted.

[0089] Figure 3 It is along Figure 1 A cross-sectional view of the display device shown in line III-III. Figure 3 This is a cross-sectional view showing the unfolded state of the curved region BA of the display panel PNL.

[0090] Reference Figure 3 The first backplate BP1 can be disposed below the substrate 101 in the linking area LA of the display panel PNL. The second backplate BP2 can be disposed below the substrate 101 in the pad area PA of the display panel PNL. The first backplate BP1 and the second backplate BP2 can be attached to the lower surface of the substrate 101 by an adhesive layer. The first backplate BP1 and the second backplate BP2 can be formed of polymer materials such as polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), etc. The backplate may not be disposed in the bending area BA of the display panel PNL. The area between the first backplate BP1 and the second backplate BP2 can be the bending area BA of the display panel PNL.

[0091] The substrate 101 may include a lower substrate layer 101a, an intermediate substrate layer 101b, and an upper substrate layer 101c. The lower substrate layer 101a and the upper substrate layer 101c may be formed of a polymer material. The intermediate substrate layer 101b may be formed of an inorganic material. The intermediate substrate layer 101b of the substrate 101 may have a patterned shape. A portion of the intermediate substrate layer 101b of the substrate 101 can be removed from the bending region BA of the display panel PNL. The intermediate substrate layer 101b of the substrate 101 may include an opening 101p positioned in the bending region BA. The opening 101p of the intermediate substrate layer 101b of the substrate 101 may have a predetermined width in a second direction DR2. In the bending region BA of the display panel PNL, the opening 101p of the intermediate substrate layer 101b of the substrate 101 may extend in a first direction DR1. The opening 101p of the intermediate substrate layer 101b of the substrate 101 may have a predetermined length in the first direction DR1. The intermediate substrate layer 101b of substrate 101 may include a first intermediate substrate layer 101b1 and a second intermediate substrate layer 101b2 spaced apart from each other by the width of the opening 101p. The thickness of the upper substrate layer 101c may be less than the thickness of the lower substrate layer 101a. The upper substrate layer 101c contacts the lower substrate layer 101a at the opening 101p.

[0092] The first buffer layer 105, the second buffer layer 112, the first gate insulating layer 122, the first interlayer insulating layer 114, the separation insulating layer 116, the second gate insulating layer 142, and the second interlayer insulating layer 118 can be disposed on the substrate 101 in the link area LA and the pad area PA of the display panel PNL.

[0093] However, the first buffer layer 105, the second buffer layer 112, the first gate insulating layer 122, the first interlayer insulating layer 114, the separation insulating layer 116, the second gate insulating layer 142, and the second interlayer insulating layer 118, which are formed of easily crackable inorganic insulating materials, cannot be disposed in the curved area BA of the display panel PNL.

[0094] The first signal line 133, the second signal line 134, and the third signal line 144 can be disposed in the link area LA of the display panel PNL. The first signal line 133 can be disposed between the first gate insulating layer 122 and the first interlayer insulating layer 114. The first signal line 133 can be formed in the same layer as the first gate electrode 123 using the same materials and the same process. The second signal line 134 can be disposed between the first interlayer insulating layer 114 and the separation insulating layer 116. The second signal line 134 can be formed in the same layer as the first source electrode 124 and the first drain electrode 125 using the same materials and the same process. The third signal line 144 can be disposed between the second gate insulating layer 142 and the second interlayer insulating layer 118. The third signal line 144 can be formed in the same layer as the second gate electrode 143 using the same materials and the same process.

[0095] Alternatively, the link contact electrode CNE can be disposed on the second interlayer insulating layer 118 in the link area LA of the display panel PNL. The link contact electrode CNE can be formed in the same layer as the second source electrode 145 and the second drain electrode 146 using the same materials and the same process.

[0096] The first connection line CNL1 can be disposed on the substrate 101 in the curved region BA of the display panel PNL. The first connection line CNL1 can be directly disposed on the upper surface of the substrate 101. The opening 101p of the intermediate substrate layer 101b of the substrate 101 can be disposed below the first connection line CNL1. A portion of the first connection line CNL1 can overlap with the opening 101p of the intermediate substrate layer 101b of the substrate 101. The first connection line CNL1 can, for example, extend to a predetermined length in the second direction DR2. The length of the first connection line CNL1 can be greater than the width of the opening 101p of the intermediate substrate layer 101b of the substrate 101. The first connection line CNL1 can be formed in the same layer as the second source electrode 145 and the second drain electrode 146 using the same material and the same process.

[0097] Figure 3 A single first connection line CNL1 is shown, but multiple first connection lines CNL1 can be provided on the substrate 101 within the curved region BA of the display panel PNL. The opening 101p of the intermediate substrate layer 101b of the substrate 101 can extend in a direction intersecting with the multiple first connection lines CNL1. For example, the opening 101p of the intermediate substrate layer 101b can be formed in the shape of a line intersecting with the multiple first connection lines CNL1.

[0098] A first planarization layer 150 covering the link contact electrode CNE and the first connection line CNL1 can be disposed on the second interlayer insulating layer 118. The first planarization layer 150 extending from the active region AA of the display panel PNL can be continuously disposed in the link region LA, the bending region BA, and the pad region PA of the display panel PNL. The first planarization layer 150 can be directly disposed on the upper surface of the substrate 101 in the bending region BA of the display panel PNL.

[0099] The second connection line CNL2 can be disposed on the first planarization layer 150 and in the link area LA, bending area BA, and pad area PA of the display panel PNL. The second connection line CNL2 can include a first portion CNL21 disposed in the link area LA and bending area BA of the display panel PNL and a second portion CNL22 disposed in the bending area BA and pad area PA of the display panel PNL.

[0100] One end of the first portion CNL21 of the second connection line CNL2 can be connected to the link contact electrode CNE in the link region LA, and the other end of the first portion CNL21 of the second connection line CNL2 can be connected to the first connection line CNL1 in the bending region BA. One end of the second portion CNL22 of the second connection line CNL2 can be connected to the first connection line CNL1 in the bending region BA, and the other end of the second portion CNL22 of the second connection line CNL2 can be connected to the pad in the pad region PA. The second connection line CNL2 can be formed in the same layer as the pixel contact electrode 152 using the same materials and the same process.

[0101] Figure 3 A second connection line CNL2 is shown, but multiple second connection lines CNL2 can be provided on the substrate 101 in the curved area BA of the display panel PNL.

[0102] A second planarization layer 154 covering the second interconnect CNL2 can be formed on the first planarization layer 150. The second planarization layer 154, extending from the active region AA, can be continuously formed in the link region LA, the bend region BA, and the pad region PA. The second planarization layer 154 can protect the first interconnect CNL1 and the second interconnect CNL2 from external impacts and moisture.

[0103] A dam layer 156 can be provided on the second planarization layer 154 in the link region LA, bending region BA, and pad region PA of the display panel PNL. A touch buffer layer 181 and a touch insulating layer 182 can be provided on the dam layer 156 in the link region LA of the display panel PNL. The end portions of the touch buffer layer 181 and the touch insulating layer 182 can be positioned within the link region LA. In one embodiment, a spacer portion 158 can be further provided on the dam layer 156 in the link region LA, bending region BA, and pad region PA of the display panel PNL. The touch buffer layer 181 and the touch insulating layer 182 can be provided on the spacer portion 158. The dam layer 156 and the spacer portion 158 can be provided in the bending region BA so that the position of the neutral plane in the bending region BA of the display panel PNL moves upward from the substrate 101 and reduces the tensile stress applied to the first connection line CNL1 and the second connection line CNL2. The dike layer 156 and the spacer 158 can protect the first connecting line CNL1 and the second connecting line CNL2 from external impact and moisture.

[0104] A touch protection layer 190 can be disposed on the touch buffer layer 181 and the touch insulating layer 182. The touch protection layer 190 can cover the end portions of the touch buffer layer 181 and the touch insulating layer 182. A partition wall 190D can be disposed on a portion of the dam layer 156. Multiple partition walls 190D can be disposed in the link region LA, but are not limited thereto. The partition wall 190D can be disposed in the bending region BA. The partition wall 190D can act as a dam to prevent the organic material forming the cap layer 195 from flowing to the outside of the display panel PNL during the process of forming the cap layer 195 disposed on the touch protection layer 190. The partition wall 190D can have a closed-loop shape surrounding the active region AA of the substrate 101. The partition wall 190D can be formed in the same layer as the touch protection layer 190 using the same material and the same process.

[0105] A cover layer 195 can be provided on the touch protection layer 190 in the link area LA of the display panel PNL. The cover layer 195 can contact the partition wall 190D.

[0106] A polarizing plate POL can be provided on the cover layer 195. The polarizing plate POL can be attached to the upper surface of the cover layer 195 by an adhesive layer.

[0107] A microcoating layer MCL can be provided in the link area LA, bending area BA, and pad area PA of the display panel PNL. The microcoating layer MCL can be provided on the dam layer 156. The microcoating layer MCL can be formed by a photocurable resin. For example, the microcoating layer MCL can be formed by a photocurable acrylic resin. The microcoating layer MCL can move the position of the neutral plane in the bending area BA upward from the substrate 101 and reduce the tensile stress applied to the first connection line CNL1 and the second connection line CNL2. The microcoating layer MCL can protect the first connection line CNL1 and the second connection line CNL2 from external impact and moisture.

[0108] Figure 4 yes Figure 3 A magnified view of region IV in the image.

[0109] Reference Figure 4 The intermediate substrate layer 101b of the substrate 101 may include an opening 101p positioned in the curved region BA of the display panel PNL. The upper substrate layer 101c of the substrate 101 may include a groove 101g at a position corresponding to the opening 101p of the intermediate substrate layer 101b.

[0110] In a portion of the curved region BA of the display panel PNL, the first connecting line CNL1 can be directly disposed on the upper surface of the upper substrate layer 101c. The first portion CNL21 and the second portion CNL22 of the second connecting line CNL2 can pass through the first planarization layer 150 and can be respectively connected to the two ends of the first connecting line CNL1.

[0111] The first connecting line CNL1 can be directly disposed on the upper surface of the upper substrate layer 101c with a length greater than the width of the groove 101g of the upper substrate layer 101c. A portion of the first connecting line CNL1 can be disposed within the groove 101g of the upper substrate layer 101c, and the remaining portion of the first connecting line CNL1 can be disposed outside the groove 101g of the upper substrate layer 101c. The middle portion of the first connecting line CNL1 can be disposed within the groove 101g of the upper substrate layer 101c, and the end portions on both sides of the first connecting line CNL1 can be disposed outside the groove 101g of the upper substrate layer 101c.

[0112] In this embodiment, the neutral surface can be positioned in the upper part of the upper substrate layer 101c, and instead of using the second connecting line CNL2 throughout the entire bending region BA, the first connecting line CNL1 can be directly disposed on the upper surface of the upper substrate layer 101c in a portion of the bending region BA. This allows the first connecting line CNL1 to be positioned close to the neutral surface and reduces the tensile stress applied to the first connecting line CNL1. Furthermore, by arranging a portion of the first connecting line CNL1 in the groove 101g of the upper substrate layer 101c, a portion of the first connecting line CNL1 can be positioned even closer to the neutral surface, thereby further reducing the tensile stress applied to that portion of the first connecting line CNL1.

[0113] Figure 5 This is a schematic cross-sectional view of the curved area of ​​a display panel according to one embodiment of the present disclosure.

[0114] Reference Figure 5 The second backplate BP2 can be coupled to the first backplate BP1 via a fixing member FM to keep the curved area of ​​the display panel in a curved state. The lower surfaces of the second backplate BP2 and the first backplate BP1 can face each other. The fixing member FM can be, for example, foam tape.

[0115] The curvature of the substrate 101 in the curved region BA of the display panel PNL can vary depending on the location. The substrate 101 can have a small curvature at locations adjacent to the first backplate BP1 and the second backplate BP2, but a large curvature at locations away from the first backplate BP1 and the second backplate BP2. The substrate 101 can have a large radius of curvature at locations adjacent to the first backplate BP1 and the second backplate BP2, but a small radius of curvature at locations away from the first backplate BP1 and the second backplate BP2. The maximum tensile stress can be applied to the first connecting line CNL1 in the region of maximum curvature of the substrate 101, i.e., in the region of minimum radius of curvature.

[0116] In this embodiment, in order to reduce the maximum tensile stress applied to the first interconnect line CNL1, the opening 101p of the intermediate substrate layer 101b of the substrate 101 is designed to be positioned at the point where the substrate 101 has a minimum radius of curvature r. mnThe portion of point P (the point of minimum radius of curvature) (referred to as the "region of minimum radius of curvature") is located within this region. Therefore, the groove 101g of the upper substrate layer 101c can also be positioned within the region of minimum radius of curvature of the substrate 101. Here, the region of minimum radius of curvature of the substrate 101 can be a region ranging from -15° to +15° relative to the virtual line connecting the point P of minimum radius of curvature to the center of curvature. The width of the opening 101p of the intermediate substrate layer 101b of the substrate 101 is preferably greater than the region of minimum radius of curvature of the substrate 101.

[0117] According to this embodiment, by removing the intermediate substrate layer of the substrate in the minimum radius of curvature region of the curved area of ​​the display panel and directly arranging the first connecting line on the upper surface of the upper substrate layer of the substrate, the tensile stress applied to the first connecting line can be reduced, thereby preventing cracks from appearing in the first connecting line.

[0118] Figure 6 This is a cross-sectional view showing a portion of a curved region of a display panel according to one embodiment of the present disclosure.

[0119] Reference Figure 6 The intermediate substrate layer 101b of the substrate 101 may include an opening 101p' located in the curved region BA of the display panel PNL. The upper substrate layer 101c of the substrate 101 may include a groove 101g' at a position corresponding to the opening 101p' of the intermediate substrate layer 101b.

[0120] In a portion of the curved region BA of the display panel PNL, the first connecting line CNL1 can be directly disposed on the upper surface of the upper substrate layer 101c. The first portion CNL21 and the second portion CNL22 of the second connecting line CNL2 can pass through the first planarization layer 150 and can be respectively connected to the two ends of the first connecting line CNL1.

[0121] The width of the opening 101p' in the intermediate substrate layer 101b of substrate 101 and the width of the groove 101g' in the upper substrate layer 101c can be greater than the length of the first connecting line CNL1. The first connecting line CNL1 can be directly disposed on the upper surface of the upper substrate layer 101c with a length smaller than the width of the groove 101g' in the upper substrate layer 101c. The entire first connecting line CNL1 can be disposed within the groove 101g' in the upper substrate layer 101c.

[0122] In this embodiment, the neutral surface can be positioned above the upper substrate layer 101c, and instead of using the second connecting line CNL2 throughout the entire bending region BA, the first connecting line CNL1 can be directly disposed on the upper surface of the upper substrate layer 101c within a portion of the bending region BA. This allows the first connecting line CNL1 to be positioned close to the neutral surface and reduces the tensile stress applied to the first connecting line CNL1. Furthermore, by arranging the entire first connecting line CNL1 within the groove 101g' of the upper substrate layer 101c, the entire first connecting line CNL1 can be positioned even closer to the neutral surface, thereby further reducing the tensile stress applied to the entire first connecting line CNL1.

[0123] Even in this embodiment, the opening 101p' of the intermediate substrate layer 101b and the groove 101g' of the upper substrate layer 101c can be positioned in the region of minimum radius of curvature of the substrate 101.

[0124] According to this embodiment, by removing the intermediate substrate layer of the substrate in the minimum radius of curvature region of the curved area of ​​the display panel and directly arranging the first connecting line on the upper surface of the upper substrate layer of the substrate, the tensile stress applied to the first connecting line can be reduced, thereby preventing cracks from appearing in the first connecting line.

[0125] Meanwhile, when the position of the second back plate BP2, which is coupled to the first back plate BP1 via the fixing member FM, changes due to errors in the attachment process, the minimum radius of curvature area of ​​the substrate 101 may change.

[0126] According to this embodiment, since the width of the opening in the middle substrate layer of the substrate and the width of the groove in the upper substrate layer of the substrate are formed to be greater than the length of the first connecting line, even if the minimum radius of curvature of the substrate 101 changes due to errors in the attachment process, it can be ensured that the tensile stress applied to the first connecting line is reduced.

[0127] The display device according to various embodiments of the present disclosure can be described as follows.

[0128] According to embodiments of the present disclosure, a display device is provided, comprising: a substrate including an active region for displaying an image and a curved region located on one side of the active region and having curvature; at least one first connecting line, the at least one first connecting line being directly disposed on the upper surface of the substrate in the curved region; a first planarization layer disposed on the at least one first connecting line; and at least one second connecting line disposed on the first planarization layer and passing through the first planarization layer to connect to the at least one first connecting line.

[0129] According to some embodiments of this disclosure, at least one second connecting line may have a first portion connected to one side of at least one first connecting line and a second portion connected to the other side of at least one first connecting line.

[0130] According to some embodiments of the present disclosure, the substrate may include a lower substrate layer, an intermediate substrate layer and an upper substrate layer, and the intermediate substrate layer may include an opening disposed below at least one first connection line.

[0131] According to some embodiments of the present disclosure, the upper substrate layer may include a groove overlapping the opening of the intermediate substrate layer, and a portion of at least one first connecting line may be disposed within the groove of the upper substrate layer, and the remaining portion of at least one first connecting line may be disposed outside the groove of the upper substrate layer.

[0132] According to some embodiments of the present disclosure, the upper substrate layer may include a groove that overlaps with the opening of the intermediate substrate layer, and at least one first connecting line may be disposed within the groove of the upper substrate layer.

[0133] According to some embodiments of this disclosure, the opening in the intermediate substrate layer may be located at a position overlapping with the minimum radius of curvature region within the curved region of the substrate.

[0134] According to some embodiments of this disclosure, at least one first connection line may include multiple first connection lines, and the opening in the intermediate substrate layer may extend in a direction intersecting with the multiple first connection lines.

[0135] According to some embodiments of this disclosure, the lower substrate layer and the upper substrate layer may be formed of polymeric materials, and the intermediate substrate layer may be formed of inorganic materials.

[0136] According to some embodiments of this disclosure, the upper substrate layer is directly disposed on the lower substrate layer at the opening.

[0137] According to embodiments of the present disclosure, a display device is provided, comprising: a substrate including a curved region, the substrate including a lower substrate layer, an intermediate substrate layer and an upper substrate layer, the intermediate substrate layer including an opening, and the upper substrate layer contacting the lower substrate layer at the opening; a first connecting line, the first connecting line being directly disposed on the upper surface of the upper substrate layer in the curved region; a first planarization layer, the first planarization layer being disposed on the first connecting line; and a second connecting line, the second connecting line being disposed on the first planarization layer and passing through the first planarization layer and connected to the first connecting line.

[0138] According to some embodiments of this disclosure, the substrate further includes a link region in a non-active region that does not display an image, and a pad region including a plurality of pads, and a curved region between the link region and the pad region.

[0139] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in this specification are not intended to limit the technical spirit of the present disclosure, but rather to describe it, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Thus, it should be understood that the above embodiments are illustrative and not restrictive in all respects.

Claims

1. A display device, comprising: A substrate, the substrate including an active region for displaying an image and a curved region located on one side of the active region and having curvature; At least one first connecting line is disposed on the upper surface of the substrate in the bending region; A first planarization layer is disposed on the at least one first connection line; as well as At least one second connection line is disposed on the first planarization layer and passes through the first planarization layer to connect to the at least one first connection line.

2. The display device according to claim 1, wherein The at least one second connecting line has a first portion connected to one side of the at least one first connecting line and a second portion connected to the other side of the at least one first connecting line.

3. The display device according to claim 1, wherein The substrate includes a lower substrate layer, a middle substrate layer, and an upper substrate layer, and The intermediate substrate layer includes an opening disposed below the at least one first connection line.

4. The display device according to claim 3, wherein, The upper substrate layer includes a groove that overlaps with the opening of the intermediate substrate layer, and A portion of the at least one first connecting line is disposed within the groove of the upper substrate layer, and the remaining portion of the at least one first connecting line is disposed outside the groove of the upper substrate layer.

5. The display device according to claim 3, wherein, The upper substrate layer includes a groove that overlaps with the opening of the intermediate substrate layer, and The entire at least one first connecting line is disposed within the groove of the upper substrate layer.

6. The display device according to claim 3, wherein, The opening in the intermediate substrate layer is located at a position where it overlaps with the region of minimum radius of curvature within the curved region of the substrate.

7. The display device according to claim 6, wherein, The region of minimum radius of curvature of the substrate is a region ranging from -15° to +15° relative to a virtual line connecting the point of minimum radius of curvature of the substrate to the center of curvature. The width of the opening in the intermediate substrate layer of the substrate is greater than the width corresponding to the minimum radius of curvature region of the substrate.

8. The display device according to claim 3, wherein, The at least one first connecting line includes multiple first connecting lines, and The opening in the intermediate substrate layer extends in the direction intersecting with the plurality of first connecting lines.

9. The display device according to claim 3, wherein, The lower substrate layer and the upper substrate layer are formed of polymer materials, and the intermediate substrate layer is formed of inorganic materials.

10. The display device according to claim 1, wherein, The at least one second connection line is disposed in the same layer as the pixel contact electrode, which is disposed on the first planarization layer in the active region.

11. The display device according to claim 1, wherein, The at least one first connection line is disposed in the same layer as the source and drain electrodes of the thin-film transistor disposed below the first planarization layer in the active region.

12. The display device according to claim 5, wherein, The width of the opening in the intermediate substrate layer is greater than the length of the at least one first connecting line.

13. The display device according to claim 9, wherein, The inorganic insulating material includes silicon oxide or silicon nitride, and the polymer material includes polyimide.

14. The display device according to claim 3, wherein, At the opening, the upper substrate layer is directly disposed on the lower substrate layer.

15. The display device according to claim 3, further comprising: A second planarization layer is disposed on the at least one second connection line; A dike layer, wherein the dike layer is disposed on the second planarization layer; as well as A microcoating layer is disposed on the dam layer and is formed of a photocurable acrylic resin.

16. A display device, comprising: A substrate including a curved region, the substrate including a lower substrate layer, an intermediate substrate layer and an upper substrate layer, the intermediate substrate layer including an opening, and the upper substrate layer contacting the lower substrate layer at the opening; A first connecting line is directly disposed on the upper surface of the upper substrate layer in the bending region; A first planarization layer is disposed on the first connection line; as well as The second connecting line is disposed on the first planarization layer and passes through the first planarization layer to connect to the first connecting line.

17. The display device according to claim 16, wherein, The substrate also includes a link region in a non-active region that does not display an image, and a pad region including a plurality of pads, and the curved region is between the link region and the pad region.

18. The display device according to claim 16, wherein, The substrate is configured such that the neutral surface of the curved region is in the upper part of the upper substrate layer.

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