Perovskite / crystalline silicon tandem solar cell and preparation method thereof

Abstract

This invention provides a perovskite / crystalline silicon tandem solar cell and its fabrication method. A composite tunneling layer is formed between the perovskite top cell and the crystalline silicon bottom cell, consisting of an N-type doped polycrystalline silicon layer and a P-type doped amorphous silicon layer. The P-type doped amorphous silicon layer, fabricated using a low-temperature process, reduces physical damage to the crystalline silicon bottom cell caused by traditional TCO processes and high-temperature processes, improves interfacial contact, and the resulting composite tunneling structure also achieves better bandgap matching, increasing the device's open-circuit voltage and fill factor, thereby further improving the cell's photoelectric conversion efficiency and stability.

Description

Technical Field

[0001] This invention relates to the field of perovskite tandem solar cell technology, specifically to a perovskite / crystalline silicon tandem solar cell and its fabrication method. Background Technology

[0002] Solar energy is a promising new clean energy source with advantages such as abundant resources and low cost. Currently, photovoltaic (PV) cells are one of the most efficient ways to convert solar energy into electricity, and monocrystalline silicon and polycrystalline silicon solar cells have relatively mature industrialization technologies. In recent years, perovskite / crystalline silicon tandem technology has become one of the research hotspots in the field of photovoltaic technology, attracting widespread attention. The development of this technology is of great significance for improving the photoelectric conversion efficiency of solar cells and reducing manufacturing costs, thereby promoting the further development and application of solar power generation technology. The theoretical effective photoelectric conversion efficiency of crystalline silicon / perovskite tandem solar cells is as high as 40% or more, far exceeding that of crystalline silicon solar cells. The basic principle of perovskite / crystalline silicon tandem technology is to stack perovskite materials and crystalline silicon materials together to form a heterojunction. By utilizing the wide bandgap, high absorption coefficient, and high carrier mobility of perovskite materials, and the stability and good electron transport performance of crystalline silicon materials, the photoelectric conversion efficiency of solar cells can be improved.

[0003] In two-terminal perovskite / crystalline silicon tandem solar cells, the top and bottom cells must be electrically interconnected via a tunneling recombination junction (TRJ). The TRJ layer allows holes generated by the top cell to recombine efficiently with electrons generated by the bottom cell, and its performance directly determines the contact resistance, fill factor (FF), and overall current matching of the tandem solar cell.

[0004] Currently, mainstream tandem solar cells in the industry primarily use transparent conductive oxide (TCO, such as ITO or IZO) thin films as composite tunneling layers. However, this TCO-based interconnection solution faces numerous insurmountable technical bottlenecks in actual mass production:

[0005] First, there is severe plasma bombardment damage. TCO thin films are usually prepared using magnetron sputtering, and the physical bombardment of high-energy ions can severely damage the passivation layer on the surface of the bottom cell (especially the amorphous silicon passivation layer), leading to a sharp increase in the interface defect state density and a significant decrease in the open-circuit voltage of the bottom cell.

[0006] Secondly, there is the issue of optical parasitic absorption loss. TCO materials exhibit a significant free carrier absorption effect in the near-infrared band, which consumes photons that should be transmitted to the bottom cell, resulting in a decrease in the short-circuit current of the bottom cell and severely limiting the upper limit of the current matching of the tandem cell.

[0007] To circumvent the aforementioned drawbacks of introducing a TCO layer, the industry has attempted to construct composite junctions through direct contact between silicon-based thin films (e.g., by directly contacting N-type doped amorphous silicon with N-type doped polycrystalline silicon). However, this TCO-free direct interconnect structure faces severe problems of "parasitic diodes" and "high contact resistance." Due to the inherent network disorder of amorphous silicon (a-Si) materials, its effective doping efficiency is lower than that of conventional crystalline materials. When N-type polycrystalline silicon with conventional doping concentration forms a composite tunneling layer with P-type amorphous silicon, the Fermi levels of both are difficult to enter degenerate states, resulting in a significant increase in the width of the depletion layer at the interface. Under illumination conditions, this wide depletion region interface easily forms a reverse-biased parasitic diode, which not only fails to achieve quantum tunneling recombination of charge carriers but also generates a huge series resistance, causing voltage losses on the order of hundreds of millivolts, ultimately leading to a precipitous drop in the efficiency of the tandem solar cell.

[0008] In summary, the industry urgently needs a novel crystalline silicon / perovskite tandem solar cell and its fabrication method that features a simplified process, low optical loss, and excellent electrical ohmic contact, in order to completely solve the practical problems existing in the current composite tunneling structure, such as sputtering damage, parasitic absorption, and reverse diode effect. Summary of the Invention

[0009] To address the severe sputtering damage and optical parasitic absorption loss issues associated with introducing a TCO layer as a composite tunneling layer in traditional perovskite / crystalline silicon solar cells, this invention provides a perovskite / crystalline silicon solar cell and its fabrication method. The composite tunneling layer consists of an N-type doped polycrystalline silicon layer and a P-type doped amorphous silicon layer placed between the perovskite top cell and the crystalline silicon bottom cell. The P-type doped amorphous silicon layer, fabricated using a low-temperature process, reduces the physical damage to the crystalline silicon bottom cell caused by traditional TCO processes and high-temperature processes, improves interfacial contact, and the resulting composite tunneling structure also achieves better bandgap matching, increasing the device's open-circuit voltage and fill factor, thereby further enhancing the cell's photoelectric conversion efficiency and stability.

[0010] To achieve the above objectives, the present invention provides the following specific solution:

[0011] A method for fabricating a perovskite / crystalline silicon tandem solar cell includes the following steps: providing an N-type silicon substrate, sequentially fabricating a tunneling layer, a first N-type doped polycrystalline silicon layer, and a second N-type doped polycrystalline silicon layer on one side; fabricating an intrinsic amorphous silicon layer on the other side of the N-type silicon substrate, forming a first P-type doped amorphous silicon layer and a second P-type doped amorphous silicon layer on the surfaces of the intrinsic amorphous silicon layer and the second N-type doped polycrystalline silicon layer, respectively, and forming a composite tunneling layer on the surface of the second N-type doped polycrystalline silicon layer and the second P-type doped amorphous silicon layer.

[0012] In this embodiment, the first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer can be prepared individually or simultaneously using plasma-enhanced chemical vapor deposition (PECVD). Silicon source gas, dopant gas, and carrier gas are introduced to form the first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer on the intrinsic amorphous silicon layer and the second N-type doped polycrystalline silicon layer, respectively, with thicknesses of 10nm-15nm and 2nm-5nm.

[0013] Specifically, the first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer can be prepared separately. The first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer are formed on the intrinsic amorphous silicon layer and the second N-type doped polycrystalline silicon layer using PECVD, with doping concentrations of 10⁻⁶ and 10⁻⁶, respectively. 15 ~10 17 cm -3 and 10 17 ~10 21 cm -3 .

[0014] Preferably, the first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer can be fabricated simultaneously. The first P-type doped amorphous silicon layer may include lightly doped and heavily doped regions disposed on the intrinsic amorphous silicon layer. After the lightly doped region is fabricated on the intrinsic amorphous silicon layer using PECVD, the heavily doped region and the second P-type doped amorphous silicon layer are formed on the lightly doped region and the second N-type doped polycrystalline silicon layer using double-sided PECVD. The thickness of the heavily doped region and the second P-type doped amorphous silicon layer is 2-5 nm, and the thickness of the lightly doped region is 10-13 nm. The doping concentration of the heavily doped region and the second P-type doped amorphous silicon layer is greater than that of the lightly doped region, and the doping concentration of the heavily doped region and the second P-type doped amorphous silicon layer is 10 nm. 17 ~10 21 cm -3 The doping concentration of the lightly doped region is 10. 15 ~10 17 cm -3 .

[0015] In some embodiments, the N-type silicon substrate is an N-type single-crystal silicon wafer with a thickness of 100um-150um, which has undergone cleaning and texturing treatment before preparation.

[0016] In this embodiment, the tunneling layer is an ultrathin silicon oxide layer, which can be prepared by at least one of thermal oxidation, wet chemical oxidation, ultraviolet ozone oxidation or atomic layer deposition methods, with a thickness of 1-2 nm.

[0017] In this embodiment, the first and second N-type doped polysilicon layers are formed by chemical vapor deposition. A silicon source gas, a dopant gas, and a carrier gas are introduced to form the first N-type doped polysilicon layer on the tunneling layer. The flow rate of the dopant gas is controlled to form the second N-type doped polysilicon layer on the first N-type doped polysilicon layer. The thicknesses are 10-30 nm and 2-10 nm, respectively.

[0018] In some embodiments, the doping concentration of the second N-type doped polysilicon layer is higher than that of the first N-type doped polysilicon layer, wherein the doping concentration of the first N-type doped polysilicon layer is 10. 15 ~10 17 cm -3 The doping concentration of the second N-type doped polysilicon layer is 10. 16 ~10 21 cm -3 .

[0019] In this embodiment, the intrinsic amorphous silicon layer is prepared by plasma-enhanced chemical vapor deposition (PECVD) or hot-wire CVD (HWCVD). Silane (SiH4) and hydrogen gas are introduced into a low-temperature vacuum chamber to deposit the intrinsic amorphous silicon layer on the back side of an N-type silicon substrate, achieving chemical passivation of the back surface. The thickness is 5-10 nm, the deposition temperature is 100-350 °C, and the vacuum level is 10. -4 ~10 -5 Pa.

[0020] In this embodiment, the method for fabricating the perovskite / crystalline silicon tandem solar cell further includes: sequentially depositing a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, and a metal electrode layer on the formed composite tunneling layer, and depositing a first transparent conductive layer and a first metal electrode layer on the bottom of the first P-type doped amorphous silicon layer.

[0021] Specifically, the hole transport layer is selected from poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), poly-3-hexylthiophene (P3HT), and nickel oxide (NiO). x It is composed of one or more of the following materials: molybdenum trioxide (MoO3), cuprous iodide (CuI), and cuprous thiocyanate (CuSCN). It can be prepared by spin coating, evaporation, magnetron sputtering, etc., with a thickness of 10-20 nm.

[0022] In some embodiments, a self-assembled monolayer (SAM) can be used to form a SAM layer on the hole transport layer. The SAM layer is prepared by spin coating and has a thickness of 1-2 nm.

[0023] The perovskite layer can have an ABX3 structure and can be prepared using processes such as evaporation or solution methods.

[0024] The A site is an organic cation, including CH3NH3. + (MA + ), NH2CH=NH2 + (FA + CH3CH2NH3 + or Cs + One or more of them;

[0025] The B site is a metal cation, including Pb. 2+ Sn 2+ One or more of them;

[0026] The X-position is a halide anion, including F. - Cl - ,Br - I - One or more of them.

[0027] The passivation layer includes, but is not limited to, at least one of propylenediamine bromide (PDADBr), butylamine chloride (BACl), butylamine bromide (BABr), butylamine iodide (BAI), N,N-dimethyl-1,3-propanediamine hydrochloride (DMePDADCl), and dodecylamine bromide (DDDADBr); it may also be at least one of magnesium fluoride, lithium fluoride, and sodium fluoride.

[0028] The electron transport layer is composed of zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2), and [6,6]-phenyl C. 61 Methyl butyrate (PCBM), C60 (C 60 It is composed of one or more of the following materials: ), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), and can be prepared by processes such as spin coating, atomic layer deposition, and evaporation.

[0029] The buffer layer can be composed of oxide materials such as SnO2, Yb2O3, TiO2, and Al2O3, and is prepared by processes such as sputtering and atomic layer deposition, with a thickness of 5~30nm.

[0030] The first transparent conductive layer is prepared by sputtering or reactive ion deposition.

[0031] The first transparent conductive layer is a TCO material, including one or more of ITO, IXO, ICO, IWO, SnO2, IZO, and AZO, with a thickness of 0-100nm.

[0032] The first metal electrode layer is prepared by screen printing. After curing and annealing, the first metal electrode layer and the first transparent conductive layer form a good ohmic contact.

[0033] The first metal electrode layer is a metal material, which can be one or more of materials such as Ag, Cu, and Al.

[0034] This application also provides a perovskite / crystalline silicon tandem solar cell obtained by the above-described preparation method, comprising a crystalline silicon bottom cell and a perovskite top cell thereon. The crystalline silicon bottom cell includes an N-type silicon substrate, and on the side of the N-type silicon substrate opposite to the perovskite top cell, a tunneling layer, a first N-type doped polycrystalline silicon layer, a second N-type doped polycrystalline silicon layer, and a second P-type doped amorphous silicon layer are sequentially disposed, wherein the second N-type doped polycrystalline silicon layer and the second P-type doped amorphous silicon layer form a composite tunneling structure. On the side of the N-type silicon substrate opposite to the perovskite top cell, an intrinsic amorphous silicon layer, a first P-type doped amorphous silicon layer, a first transparent conductive layer, and a first metal electrode layer are sequentially disposed.

[0035] In this embodiment, the perovskite top solar cell includes a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, and a metal electrode layer disposed on a composite tunneling layer.

[0036] This invention provides a method for fabricating a perovskite / crystalline silicon tandem solar cell, comprising the steps of: providing an N-type silicon substrate, sequentially depositing a tunneling layer and first and second N-type doped polycrystalline silicon layers on one side; fabricating an intrinsic amorphous silicon layer on the other side, and then forming a first P-type doped amorphous silicon layer and a second P-type doped amorphous silicon layer on the surfaces of the intrinsic amorphous silicon layer and the second N-type doped polycrystalline silicon layer, respectively; and forming a composite tunneling layer on the surface of the second N-type doped polycrystalline silicon layer and the second P-type doped amorphous silicon layer. By replacing the traditional TCO with a composite tunneling layer, damage to the crystalline silicon cell caused by traditional sputtering processes is avoided, and the interfacial contact and bandgap matching between sub-cells are improved, thereby enhancing the photoelectric conversion efficiency and stability of the device. Attached Figure Description

[0037] Figure 1 This is a diagram illustrating the fabrication steps of the perovskite / crystalline silicon tandem solar cell described in this invention.

[0038] Figure 2 This is a schematic diagram illustrating the fabrication of the perovskite / crystalline silicon tandem solar cell described in this invention.

[0039] Figure 3 This is a schematic diagram of the perovskite / crystalline silicon tandem solar cell structure described in this invention.

[0040] The labels in the diagram are named as follows:

[0041] 10. Crystalline silicon bottom cell; 20. Perovskite top cell;

[0042] 101. First metal electrode layer; 102. First transparent conductive layer; 103. First P-type doped amorphous silicon layer; 104. Intrinsic amorphous silicon layer; 105. N-type silicon substrate; 106. Tunneling layer; 107. First N-type doped polycrystalline silicon layer; 108. Second N-type doped polycrystalline silicon layer; 109. Second P-type doped amorphous silicon layer;

[0043] 201. Hole transport layer; 202. Perovskite layer; 203. Passivation layer; 204. Electron transport layer; 205. Buffer layer; 206. Transparent conductive layer; 207. Metal electrode layer. Detailed Implementation

[0044] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0045] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] Traditional perovskite / crystalline silicon tandem solar cells use crystalline silicon as the cell substrate and perovskite cells as the top cells. They typically employ transparent conductive oxide as the tunneling layer between the series cells. However, this interconnection scheme, relying on total cost of ownership (TCO), faces numerous insurmountable technical bottlenecks in actual mass production.

[0047] First, there is severe plasma bombardment damage. TCO thin films are usually prepared using magnetron sputtering, and the physical bombardment of high-energy ions can severely damage the passivation layer on the surface of the bottom cell, leading to a sharp increase in the interface defect state density and a significant decrease in the open-circuit voltage of the bottom cell.

[0048] Secondly, there is the issue of optical parasitic absorption loss. TCO materials exhibit a significant free carrier absorption effect in the near-infrared band, which consumes photons that should be transmitted to the bottom cell, resulting in a decrease in the short-circuit current of the bottom cell and severely limiting the upper limit of the current matching of the tandem cell.

[0049] Therefore, this invention mainly replaces the traditional TCO tunneling layer by setting a heavily doped N-type polycrystalline silicon layer and a P-type doped amorphous silicon layer at the connection between the crystalline silicon bottom cell and the perovskite top cell. This avoids the risk of sputtering damage to the crystalline silicon bottom cell, improves interface contact and stability, and the composite tunneling structure formed by the N-type doped polycrystalline silicon layer and the P-type doped amorphous silicon layer can further improve the band matching between sub-cells, improve carrier extraction efficiency, reduce carrier recombination at the interface and in the bulk phase, and improve the open-circuit voltage and fill factor of the device, thereby improving the photoelectric conversion efficiency and stability of the cell.

[0050] This application replaces the traditional TCO tunneling layer with a heavily doped N-type polycrystalline silicon layer and a P-type doped amorphous silicon layer, thereby reducing the amount of indium metal used and thus lowering production costs.

[0051] Please see Figures 1-3 This application provides a method for fabricating a perovskite / crystalline silicon tandem solar cell, comprising the steps of: providing an N-type silicon substrate 105, and sequentially fabricating a tunneling layer 106, a first N-type doped polycrystalline silicon layer 107, and a second N-type doped polycrystalline silicon layer 108 on one side; fabricating an intrinsic amorphous silicon layer 104 on the other side of the N-type silicon substrate 105; forming a first P-type doped amorphous silicon layer 103 and a second P-type doped amorphous silicon layer 109 on the surfaces of the intrinsic amorphous silicon layer 104 and the second N-type doped polycrystalline silicon layer 108, respectively; and forming a composite tunneling layer on the surface of the second N-type doped polycrystalline silicon layer 108 and the second P-type doped amorphous silicon layer 109.

[0052] In this embodiment, the first P-type doped amorphous silicon layer 103 and the second P-type doped amorphous silicon layer 109 can be prepared individually or simultaneously using plasma-enhanced chemical vapor deposition (PECVD). Silicon source gas, dopant gas, and carrier gas are introduced to form the first P-type doped amorphous silicon layer 103 and the second P-type doped amorphous silicon layer 109 on the intrinsic amorphous silicon layer 104 and the second N-type doped polycrystalline silicon layer 108, respectively. The thicknesses are 10nm-15nm and 2nm-5nm.

[0053] Specifically, the first P-type doped amorphous silicon layer 103 and the second P-type doped amorphous silicon layer 109 can be prepared separately. The first P-type doped amorphous silicon layer 103 and the second P-type doped amorphous silicon layer 109 are formed on the intrinsic amorphous silicon layer 104 and the second N-type doped polycrystalline silicon layer 108 respectively using PECVD, with doping concentrations of 10⁻⁶ and 10⁻⁶, respectively. 15 ~1017 cm -3 and 10 17 ~10 21 cm -3 .

[0054] Preferably, the first P-type doped amorphous silicon layer 103 and the second P-type doped amorphous silicon layer 109 can be prepared simultaneously. The first P-type doped amorphous silicon layer 103 may include a lightly doped region and a heavily doped region sequentially disposed on the intrinsic amorphous silicon layer 104. After the lightly doped region is prepared on the intrinsic amorphous silicon layer 104 by PECVD, the heavily doped region and the second P-type doped amorphous silicon layer 109 are formed on the lightly doped region and the second N-type doped polycrystalline silicon layer 108 by double-sided PECVD. The thickness of the heavily doped region and the second P-type doped amorphous silicon layer 109 is 2-5 nm, and the doping concentration is the same. The thickness of the lightly doped region is 10-13 nm. The doping concentration of the heavily doped region and the second P-type doped amorphous silicon layer 109 is greater than that of the lightly doped region.

[0055] Furthermore, after the first P-type doped amorphous silicon layer 103 and the second P-type doped amorphous silicon layer 109 are prepared, an annealing process is also included, with an annealing temperature of 100℃~300℃, to improve the interfacial contact between the amorphous silicon layer and the polycrystalline silicon layer.

[0056] In some embodiments, the N-type silicon substrate 105 is an N-type single-crystal silicon wafer with a thickness of 100um-150um, which has been cleaned and texturized before preparation.

[0057] In this embodiment, the tunneling layer 106 is an ultrathin silicon oxide layer, which can be prepared by at least one of thermal oxidation, wet chemical oxidation, ultraviolet ozone oxidation or atomic layer deposition methods, with a thickness of 1-2 nm.

[0058] In this embodiment, the first N-type doped polysilicon layer 107 and the second N-type doped polysilicon layer 108 are formed by chemical vapor deposition. A silicon source gas, a dopant gas, and a carrier gas are introduced to form the first N-type doped polysilicon layer on the tunneling layer 106. The flow rate of the dopant gas is controlled to form the second N-type doped polysilicon layer on the first N-type doped polysilicon layer. The thicknesses are 10-30 nm and 2-10 nm, respectively. The doping concentration of the second N-type doped polysilicon layer 108 is higher than that of the first N-type doped polysilicon layer 107.

[0059] Specifically, the doping concentration of the first N-type doped polysilicon layer 107 is 10. 15 ~10 17 cm -3 The doping concentration of the second N-type doped polysilicon layer 108 is 10. 16 ~10 21 cm -3 .

[0060] In this embodiment, the intrinsic amorphous silicon layer 104 is prepared by plasma-enhanced chemical vapor deposition (PECVD) or hot-wire CVD (HWCVD). Silane (SiH4) and hydrogen are introduced into a vacuum chamber at a temperature strictly below freezing to deposit the intrinsic amorphous silicon layer 104 on the back side of the N-type silicon substrate 105, achieving chemical passivation of the back surface. The thickness is 5-10 nm, the deposition temperature is 100-350 °C, and the vacuum level is 10. -4 ~10 -5 Pa.

[0061] In this embodiment, the method for fabricating the perovskite / crystalline silicon tandem solar cell further includes: sequentially depositing a hole transport layer 201, a perovskite layer 202, a passivation layer 203, an electron transport layer 204, a buffer layer 205, a transparent conductive layer 206, and a metal electrode layer 207 on the formed composite tunneling layer, and then depositing a first transparent conductive layer 102 and a first metal electrode layer 101 on the bottom of the first P-type doped amorphous silicon layer 103.

[0062] Specifically, the hole transport layer 201 is selected from poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), poly-3-hexylthiophene (P3HT), and nickel oxide (NiO). x It is composed of one or more of the following materials: molybdenum trioxide (MoO3), cuprous iodide (CuI), and cuprous thiocyanate (CuSCN). It can be prepared by spin coating, evaporation, magnetron sputtering, etc., with a thickness of 10-20 nm.

[0063] In some embodiments, a self-assembled monolayer (SAM) can be used to form a SAM layer on the hole transport layer 201. The SAM layer is prepared by spin coating and has a thickness of 1-2 nm.

[0064] The perovskite layer 202 can have an ABX3 structure and can be prepared using processes such as evaporation or solution methods. The A-site can be an organic cation, including CH3NH3. + (MA + ), NH2CH=NH2 + (FA + CH3CH2NH3 + or Cs + One or more of them;

[0065] The B site is a metal cation, including Pb. 2+ Sn 2+ One or more of them;

[0066] The X-position is a halide anion, including F. - Cl - ,Br- I - One or more of them.

[0067] The passivation layer 203 can be prepared by at least one of vapor deposition, spin coating, and spray coating. The passivation layer may contain at least one of the following: propylenediamine iodine, including but not limited to propylenediamine bromide (PDADBr), butylamine chloride (BACl), butylamine bromide (BABr), butylamine iodide (BAI), N,N-dimethyl-1,3-propanediamine hydrochloride (DMePDADCl), and dodecylamine bromide (DDDADBr); or it may be composed of at least one of magnesium fluoride, lithium fluoride, and sodium fluoride.

[0068] The electron transport layer 204 is composed of zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2), and [6,6]-phenyl C. 61 Methyl butyrate (PCBM), C60 (C 60 It is composed of one or more of the following materials: ), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), and can be prepared by processes such as spin coating, atomic layer deposition, and evaporation.

[0069] The buffer layer 205 can be composed of oxide materials such as SnO2, Yb2O3, TiO2, and Al2O3, and is prepared by processes such as sputtering and atomic layer deposition, with a thickness of 5~30nm.

[0070] The first transparent conductive layer 102 and the transparent conductive layer 206 are prepared by sputtering or reactive ion deposition.

[0071] The first transparent conductive layer 102 and transparent conductive layer 206 are TCO materials, including one or more of ITO, IXO, ICO, IWO, SnO2, IZO and AZO, with a thickness of 0-100nm.

[0072] The first metal electrode layer 101 and the metal electrode layer 207 are prepared by screen printing. After curing and annealing, the first metal electrode layer 101 and the first transparent conductive layer 102, and the metal electrode layer 207 and the transparent conductive layer 206 form good ohmic contact.

[0073] The first metal electrode layer 101 and the metal electrode layer 207 are made of metal materials, such as Ag, Cu, Al, etc.

[0074] Please see Figure 3This application also provides a perovskite / crystalline silicon tandem solar cell obtained by the above-described preparation method, comprising a crystalline silicon bottom cell 10 and a perovskite top cell 20 thereon. The crystalline silicon bottom cell 10 includes an N-type silicon substrate 105, and a tunneling layer 106, a first N-type doped polycrystalline silicon layer 107, a second N-type doped polycrystalline silicon layer 108, and a second P-type doped amorphous silicon layer 109 are sequentially disposed on the side of the N-type silicon substrate 105 opposite to the perovskite top cell 20. The second N-type doped polycrystalline silicon layer 108 and the second P-type doped amorphous silicon layer 109 form a composite tunneling structure. An intrinsic amorphous silicon layer 104, a first P-type doped amorphous silicon layer 103, a first transparent conductive layer 102, and a first metal electrode layer 101 are sequentially disposed on the side of the N-type silicon substrate 105 opposite to the perovskite top cell 20.

[0075] In this embodiment, the perovskite top solar cell includes a hole transport layer 201, a perovskite layer 202, a passivation layer 203, an electron transport layer 204, a buffer layer 205, a transparent conductive layer 206, and a metal electrode layer 207 disposed on a composite tunneling layer.

[0076] The following specific embodiments and comparative examples clearly and completely describe the technical solution of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0077] Example 1

[0078] This embodiment provides a perovskite / crystalline silicon tandem solar cell, comprising, from bottom to top, a first metal electrode layer 101, a first transparent conductive layer 102, a first P-type doped amorphous silicon layer 103, an intrinsic amorphous silicon layer 104, an N-type silicon substrate 105, a tunneling layer 106, a first N-type doped polycrystalline silicon layer 107, a second N-type doped polycrystalline silicon layer 108, a second P-type doped amorphous silicon layer 109, a hole transport layer 201, a SAM layer, a perovskite layer 202, a passivation layer 203, an electron transport layer 204, a buffer layer 205, a transparent conductive layer 206, and a metal electrode layer 207. The fabrication method of the tandem solar cell includes the following steps:

[0079] S(1) Provide a pretreated N-type silicon substrate 105, and deposit a thin layer of SiO2 with a thickness of 2nm as a tunneling layer 106 on the N-type silicon substrate 105 by thermal oxidation.

[0080] S(2) Using LPCVD, a first N-type doped polysilicon layer 107 with a thickness of 30 nm and a second N-type doped polysilicon layer 108 with a thickness of 3 nm are sequentially deposited on the tunneling layer 106. Silicon source gas, phosphorus source gas, and N2 are introduced, and the flow rate of phosphorus source gas is controlled to form first and second N-type doped polysilicon layers with different doping concentrations. The doping concentration of the first N-type doped polysilicon layer is 10 nm. 15 ~10 17 cm -3 The doping concentration of the second N-type doped polysilicon layer is 10. 16 ~10 21 cm -3 ;

[0081] S(3) Remove the PSG phosphorus silica glass on the surface of the second N-type doped polycrystalline silicon layer and the winding plating on the other side of the N-type silicon substrate. Then, deposit an intrinsic amorphous silicon layer 104 with a thickness of 5 nm and a first P-type doped amorphous silicon layer 103 with a thickness of 12 nm on the other side of the N-type silicon substrate 105 by PECVD.

[0082] S(4) A 3nm second P-type doped amorphous silicon layer 109 is formed on the second N-type doped polycrystalline silicon layer 108 by PECVD.

[0083] S(5) Deposit an ITO thin film with a thickness of 80 nm on the first P-type doped amorphous silicon layer 103;

[0084] S(6) A nickel oxide film with a thickness of 10 nm was sequentially deposited on the second P-type doped amorphous silicon layer 109 by PVD sputtering, and then a SAM layer with a thickness of 2 nm was prepared on the nickel oxide film by spin coating.

[0085] S(7) The perovskite layer 202 is prepared by flash evaporation, including the following steps: Dissolve perovskite powder with ABX3 structure in 1 ml of DMF and DMSO solvent, with a solvent ratio of 8:2. After stirring, a perovskite precursor solution is obtained. The substrate is placed on a spin coater, and the spin coating speed is set to 3500 rpm and the spin coating time is 30 s. The perovskite precursor solution volume is 120 μl and coated on the surface of the battery substrate. After spin coating, the substrate is transferred to a flash evaporation stage, and the flash evaporation time is set to 30 s and the flash evaporation temperature is 30 °C. After flash evaporation, annealing is performed, and the annealing temperature is set to 100 °C and the annealing time is 15 min to obtain the perovskite layer 202 with a thickness of about 800 nm.

[0086] S(8) Using the vapor deposition method, weigh 3 mg of propylenediamine iodine and place it in a crucible. Place the sample obtained in the above steps on a mask and put it into the vapor deposition chamber. Wait until the vapor deposition vacuum degree is 2×10 -4Evaporation was performed at Pa, the evaporation voltage was adjusted to the evaporation temperature, and the evaporation rate was controlled at 0.1 Å / s. Propylene diamine iodine was deposited onto the film to obtain a passivation layer 203 with a thickness of 4 nm. After the passivation was completed, the annealing station temperature was set to 100℃ and annealing was performed for 8 minutes.

[0087] S(9), C 60 The electron transport layer 204 is prepared by evaporation onto the surface of the passivation layer 203. The thickness of the electron transport layer 204 is 20 nm, and the vacuum degree of the evaporation is 1 × 10⁻⁶. -4 Pa, evaporation temperature at 400℃, evaporation rate at 0.1 Å / s.

[0088] S(10) SnO2 is deposited onto the surface of the electron transport layer 204 by atomic layer deposition using an atomic layer deposition device to prepare the buffer layer 205. The thickness of the buffer layer 205 is 20 nm. The vacuum degree of the deposition is 50~100 Pa and the temperature of the deposition chamber is 100 °C.

[0089] S(11) The transparent conductive layer 206 is prepared on the surface of the buffer layer 205 by magnetron sputtering. The thickness of the transparent conductive layer 206 is 40 nm. The target material of the magnetron sputtering method is indium zinc oxide (IZO), the power of the magnetron sputtering method is 50 W, and the running time of the magnetron sputtering method is 1 h.

[0090] S(12) A layer of low-temperature conductive silver paste is printed on both sides of the entire cell using screen printing, and the sintering temperature is 150°C; the Ag grid line thickness is 6um and the grid line width is 20um to obtain a perovskite / crystalline silicon tandem solar cell.

[0091] Comparative Example 1

[0092] This comparative example uses a traditional HJT cell as the crystalline silicon bottom cell and fabricates a perovskite top cell on top of the HJT bottom cell. The structure, from bottom to top, includes: a first metal electrode layer, a first transparent conductive layer, a P-type doped amorphous silicon layer, an intrinsic amorphous silicon layer, an N-type silicon substrate, an intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a connecting layer, a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, and a metal electrode layer. The fabrication steps include:

[0093] S(1) Provides a pretreated N-type silicon substrate;

[0094] S(2) An intrinsic amorphous silicon layer with a thickness of 5 nm and a P-type doped amorphous silicon layer with a thickness of 12 nm are sequentially deposited on the back side of an N-type silicon substrate using PECVD process. Borane (B2H6) is used as the doping source gas for the P-type doped amorphous silicon layer.

[0095] S(3) An intrinsic amorphous silicon layer with a thickness of 5 nm and an N-type doped amorphous silicon layer with a thickness of 12 nm are sequentially deposited on the front side of an N-type silicon substrate using PECVD process. Phosphine (PH3) is used as the doping source gas for the N-type doped amorphous silicon layer.

[0096] S(4) An ITO transparent conductive film with a thickness of 20 nm is deposited on the surface of an N-type doped amorphous silicon layer using magnetron sputtering.

[0097] S(5) An ITO thin film with a thickness of 80 nm was deposited on a P-type doped amorphous silicon layer using magnetron sputtering.

[0098] S(6) A nickel oxide film with a thickness of 10 nm was deposited sequentially on the bonding layer by PVD sputtering, and then a SAM layer with a thickness of 2 nm was prepared on the nickel oxide film by spin coating.

[0099] S(7) The perovskite layer is prepared by flash evaporation, including the following steps: Dissolve perovskite powder with ABX3 structure in 1 ml of DMF and DMSO solvent in a solvent ratio of 8:2. After stirring, a perovskite precursor solution is obtained. The substrate is placed on a spin coater, the spin coater speed is set to 3500 rpm, the spin coater time is 30 s, and the perovskite precursor solution volume is 120 μl. The solution is coated on the surface of the battery substrate. After spin coatering, the substrate is transferred to a flash evaporation stage, the flash evaporation time is set to 30 s, the flash evaporation temperature is 30 °C, and after flash evaporation, the substrate is annealed. The annealing temperature is set to 100 °C, the annealing time is 15 min, and a perovskite layer with a thickness of about 800 nm is obtained.

[0100] S(8) Using the vapor deposition method, weigh 3 mg of propylenediamine iodine and place it in a crucible. Place the sample obtained in the above steps on a mask and put it into the vapor deposition chamber. Wait until the vapor deposition vacuum degree is 2×10 -4 Evaporation was performed at Pa, the evaporation voltage was adjusted to the evaporation temperature, and the evaporation rate was controlled at 0.1 Å / s. Propylene diamine iodine was deposited onto the film to obtain a passivation layer 203 with a thickness of 4 nm. After the passivation was completed, the annealing station temperature was set to 100℃ and annealing was performed for 8 minutes.

[0101] S(9), C 60 The electron transport layer is prepared by evaporation onto the surface of the passivation layer. The thickness of the electron transport layer is 20 nm, and the vacuum degree of the evaporation is 1 × 10⁻⁶. -4 Pa, evaporation temperature at 400℃, evaporation rate at 0.1 Å / s.

[0102] S(10) SnO2 is deposited onto the surface of the electron transport layer by atomic layer deposition using an atomic layer deposition device to prepare the buffer layer 205. The thickness of the buffer layer 205 is 20 nm. The vacuum degree of the deposition is 50~100 PaPa and the temperature of the deposition chamber is 100 °C.

[0103] S(11) The transparent conductive layer is prepared on the surface of the buffer layer by magnetron sputtering. The thickness of the transparent conductive layer is 40 nm. The target material of the magnetron sputtering method is indium zinc oxide (IZO), the power of the magnetron sputtering method is 50 W, and the running time of the magnetron sputtering method is 1 h.

[0104] S(12) A layer of low-temperature conductive silver paste is printed on both sides of the entire cell using screen printing, and the sintering temperature is 150°C; the Ag grid line thickness is 6um and the grid line width is 20um to obtain a perovskite / crystalline silicon tandem solar cell.

[0105] Comparative Example 2

[0106] This comparative example uses a traditional TOPcon solar cell as the crystalline silicon substrate. A perovskite top cell is fabricated on the TOPcon substrate, comprising the following structures from bottom to top: a first metal electrode layer, an emitter passivation film, a P-type emitter, an N-type silicon substrate, a tunneling layer, an N-type doped polycrystalline silicon layer, a connecting layer, a hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, and a metal electrode layer. The fabrication steps include:

[0107] S(1) Provide a pretreated N-type silicon substrate, and deposit a thin layer of SiO2 with a thickness of 2nm as a tunneling layer on the N-type silicon substrate by thermal oxidation;

[0108] S(2) A phosphorus-doped first N-type doped polysilicon layer with a thickness of 30 nm is sequentially deposited on the tunneling layer using LPCVD. Silicon source gas, phosphorus doping source, and N2 are introduced. The doping concentration of the N-type doped polysilicon layer is 5 × 10¹. 9 ~2×10² 0 cm⁻³;

[0109] S(3) Remove the PSG phosphorus silica glass on the surface of the N-type doped polysilicon layer and the winding plating on the other side of the N-type silicon substrate, and form a P-type emitter on the other side of the N-type silicon substrate using a boron diffusion process;

[0110] S(4) An emitter passivation film is deposited on the surface of the P-type emitter using a PECVD process. The emitter passivation film comprises an Al2O3 layer and a SiN layer deposited sequentially. x Layer; A first metal electrode layer is sintered on it using a high-temperature metallization process;

[0111] S(5) A 40 nm thick ITO film is deposited on an N-type doped polycrystalline silicon layer as a bonding layer using magnetron sputtering.

[0112] S(6) A nickel oxide film with a thickness of 10 nm was deposited sequentially on the bonding layer by PVD sputtering, and then a SAM layer with a thickness of 2 nm was prepared on the nickel oxide film by spin coating.

[0113] S(7) The perovskite layer is prepared by flash evaporation, including the following steps: Dissolve perovskite powder with ABX3 structure in 1 ml of DMF and DMSO solvent in a solvent ratio of 8:2. After stirring, a perovskite precursor solution is obtained. The substrate is placed on a spin coater, the spin coater speed is set to 3500 rpm, the spin coater time is 30 s, and the perovskite precursor solution volume is 120 μl. The solution is coated on the surface of the battery substrate. After spin coatering, the substrate is transferred to a flash evaporation stage, the flash evaporation time is set to 30 s, the flash evaporation temperature is 30 °C, and after flash evaporation, the substrate is annealed. The annealing temperature is set to 100 °C, the annealing time is 15 min, and a perovskite layer with a thickness of about 800 nm is obtained.

[0114] S(8) Using the vapor deposition method, weigh 3 mg of propylenediamine iodine and place it in a crucible. Place the sample obtained in the above steps on a mask and put it into the vapor deposition chamber. Wait until the vapor deposition vacuum degree is 2×10 -4 Evaporation was performed at Pa, the evaporation voltage was adjusted to the evaporation temperature, and the evaporation rate was controlled at 0.1 Å / s. Propylene diamine iodine was deposited onto the film to obtain a passivation layer with a thickness of 4 nm. After the passivation was completed, the annealing station temperature was set to 100℃ and annealing was performed for 8 minutes.

[0115] S(9), C 60 The electron transport layer is prepared by evaporation onto the surface of the passivation layer. The thickness of the electron transport layer is 20 nm, and the vacuum degree of the evaporation is 1 × 10⁻⁶. -4 Pa, evaporation temperature at 400℃, evaporation rate at 0.1 Å / s.

[0116] S(10) SnO2 is deposited onto the surface of the electron transport layer by atomic layer deposition using an atomic layer deposition device to prepare the buffer layer. The thickness of the buffer layer is 20 nm. The vacuum degree of the deposition is 50~100 Pa and the temperature of the deposition chamber is 100 °C.

[0117] S(11) The transparent conductive layer is prepared on the surface of the buffer layer by magnetron sputtering. The thickness of the transparent conductive layer is 40 nm. The target material of the magnetron sputtering method is indium zinc oxide (IZO), the power of the magnetron sputtering method is 50 W, and the running time of the magnetron sputtering method is 1 h.

[0118] S(12) A layer of low-temperature conductive silver paste is printed on the entire front of the cell using screen printing, and the sintering temperature is 150°C; the Ag grid line thickness is 6um and the grid line width is 20um, thus obtaining a perovskite / crystalline silicon tandem solar cell.

[0119] The perovskite / crystalline silicon tandem solar cells obtained in Example 1 and Comparative Examples 1-2 were tested under the following conditions: a standard solar intensity calibration was performed using a solar simulator, and the solar cells with an area of ​​1.0 cm² were tested. 2 The device in this embodiment underwent a long-term IV test, with the starting voltage set to 2V, the cutoff voltage to 0V, and the range to 100mA. The results were rounded to one decimal place. The test results are shown in Table 1 below.

[0120] Table 1 shows the performance of the tandem solar cells described in Example 1 and Comparative Examples 1-2.

[0121] Sample <![CDATA[J SC (mA cm -2 )]]> <![CDATA[V OC (V)]]> FF (%) PCE (%) Example 1 18.59 1.82 78.16 26.52 Comparative Example 1 18.53 1.80 76.61 25.61 Comparative Example 2 17.77 1.79 78.30 24.93

[0122] Therefore, it can be seen that the use of a second N-type doped polysilicon layer and a second P-type doped polysilicon layer to form a polysilicon tunneling layer in this application, which functionalizes the surface, helps to form better band matching at the interface, facilitates carrier extraction, reduces carrier recombination between the interface and the bulk phase, and increases the open-circuit voltage (V). OC Improved interface contact increases the fill factor (FF).

[0123] The above embodiments are merely preferred embodiments of the present invention. It should be noted that, for those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle of the present invention. All technical solutions after making equivalent substitutions to the claims of the present invention fall within the protection scope of the present invention, which is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a perovskite / crystalline silicon tandem solar cell, characterized by, The steps include: providing an N-type silicon substrate, sequentially fabricating a tunneling layer, a first N-type doped polycrystalline silicon layer, and a second N-type doped polycrystalline silicon layer on one side; fabricating an intrinsic amorphous silicon layer on the other side of the N-type silicon substrate, forming a first P-type doped amorphous silicon layer and a second P-type doped amorphous silicon layer on the surfaces of the intrinsic amorphous silicon layer and the second N-type doped polycrystalline silicon layer, respectively; and forming a composite tunneling layer on the surface of the second N-type doped polycrystalline silicon layer and the second P-type doped amorphous silicon layer. A hole transport layer, a perovskite layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, and a metal electrode layer are sequentially deposited on the formed composite tunneling layer. Then, a first transparent conductive layer and a first metal electrode layer are deposited on the bottom of the first P-type doped amorphous silicon layer.

2. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer are prepared individually or simultaneously using plasma-enhanced chemical vapor deposition. A silicon source gas, a doping gas, and a carrier gas are introduced to form the first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer on the intrinsic amorphous silicon layer and the second N-type doped polycrystalline silicon layer, respectively, with thicknesses of 10nm-15nm and 2nm-5nm.

3. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 2, characterized in that, The first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer are prepared separately, and are formed on intrinsic amorphous silicon and second N-type doped polysilicon respectively by PECVD, and the doping concentrations are 10 15 cm -3 -10 17 cm -3 and 10 17 cm -3 -10 21 cm -3 .

4. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 2, characterized in that, The first P-type doped amorphous silicon layer and the second P-type doped amorphous silicon layer are prepared simultaneously. The first P-type doped amorphous silicon layer includes a lightly doped region and a heavily doped region disposed on the intrinsic amorphous silicon layer. After the lightly doped region is prepared on the intrinsic amorphous silicon layer by PECVD, the heavily doped region and the second P-type doped amorphous silicon layer are formed on the lightly doped region and the second N-type doped polycrystalline silicon layer by double-sided PECVD. The thickness of the heavily doped region and the second P-type doped amorphous silicon layer is 2-5 nm, and the thickness of the lightly doped region is 10-13 nm. The doping concentration of the heavily doped region and the second P-type doped amorphous silicon layer is greater than that of the lightly doped region.

5. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The N-type silicon substrate is an N-type single crystal silicon wafer with a thickness of 100um-150um, which is cleaned and texturized before preparation.

6. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The tunneling layer is an ultrathin silicon oxide layer, prepared by at least one of thermal oxidation, wet chemical oxidation, ultraviolet ozone oxidation or atomic layer deposition, with a thickness of 1-2 nm.

7. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The first and second N-type doped polysilicon layers are formed by chemical vapor deposition. A silicon source gas, a dopant gas, and a carrier gas are introduced to form the first N-type doped polysilicon layer on the tunneling layer. The flow rate of the dopant gas is controlled to form the second N-type doped polysilicon layer on the first N-type doped polysilicon layer. The thicknesses are 10-30 nm and 2-10 nm, respectively.

8. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 7, characterized in that, The doping concentration of the second N-type doped polysilicon layer is higher than that of the first N-type doped polysilicon layer.

9. The method for fabricating perovskite / crystalline silicon tandem solar cells according to claim 1, characterized in that, The intrinsic amorphous silicon layer is prepared by plasma-enhanced chemical vapor deposition or hot-wire CVD. Silane and hydrogen are introduced into a low-temperature vacuum chamber to deposit the intrinsic amorphous silicon layer on the back side of an N-type silicon substrate, achieving chemical passivation of the back surface. The thickness is 5-10 nm.

10. A perovskite / crystalline silicon tandem solar cell, characterized in that, It is obtained by the preparation method according to any one of claims 1-9.

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