Resistive random access memory (RRAM) device and method of fabricating the same

Abstract

This invention belongs to the field of micro / nanoelectronic device technology, specifically a resistive switching material nanopillar array and memristor device using a block copolymer self-assembly patterning process, and a method thereof. The invention first uses columnar block copolymers to self-assemble into a vertical structure, which, after selective etching, yields a close-packed hole array. Second, resistive switching material is filled into the close-packed hole pattern to form a nanopillar array. Finally, electrodes are deposited using micro / nano fabrication processes to form a sandwich-structured memristor device. The close-packed hole fabrication method of this invention eliminates the need for traditional photolithography, allows for the control of nanopore size down to the sub-10nm scale through material and etching parameters, and is compatible with various resistive switching materials, thereby enabling the fabrication and performance tuning of memristors based on nanopillar arrays.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronic device technology, specifically relating to a resistive switching material nanopillar array and memristor device and their fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and the Internet of Things, traditional computing systems based on the von Neumann architecture are gradually facing bottlenecks such as the "memory wall" and the "power wall," making it difficult to meet the demands of efficient data processing and neuromorphic computing. Against this backdrop, novel non-volatile memory devices have attracted widespread attention. Among them, memristors, due to their simple structure, scalable size, low power consumption, and ability to achieve in-memory computing, have become one of the most promising core devices in the post-Moore's Law era. Since the concept of memristors was proposed, the device has undergone rapid development from theoretical prediction to experimental verification. Especially after HP Labs achieved a titanium dioxide-based memristor prototype in 2008, related research entered a period of explosive growth. Currently, memristors not only show application prospects in high-density storage but also play a significant role in neuromorphic computing, neuromorphic synapse simulation, and reconfigurable logic. Resistive random access memory (RAM) has become a key device in neuromorphic computing, showing great potential in synapse simulation. Currently, the resistive switching behavior of most memristors originates from the formation and breakage process of nanoscale conductive channels, a process usually accompanied by multi-physics coupling phenomena such as defect migration, electric field concentration, and localized thermal effects. However, the formation of conductive filaments in traditional planar memristors exhibits strong randomness, manifesting as uncontrollable formation locations, uneven size distribution, and unstable fracture behavior. This leads to significant performance fluctuations, such as wide switching voltage distribution, poor cycle stability, and insufficient inter-device consistency. These problems severely restrict the application of memristors in large-scale integrated circuits. Therefore, achieving controllable formation and repeatable fracture of conductive filaments has become one of the core scientific problems in current memristor research.

[0003] To address the aforementioned issues, researchers have proposed various strategies for regulating the behavior of conductive filaments. First, by controlling defect distribution through materials engineering, such as introducing gradient oxygen vacancies or dopants into oxides, the preferential growth path of the conductive filaments can be guided to some extent, thereby reducing the uncertainty of the formation process. Second, interface engineering is also widely used; by optimizing the electrode / dielectric interface (e.g., by introducing a buffer layer or controlling the interface barrier), the local electric field distribution can be effectively adjusted, thus affecting the formation and fracture location of the filaments. Furthermore, applying an external series resistor or current-limiting mechanism can also suppress the excessive growth of conductive filaments, achieving more stable fracture behavior. However, most of these methods are "indirect regulation" and still cannot fundamentally solve the problem of the randomness in the growth and transport of conductive filaments.

[0004] In recent years, nanoconfinement strategies have been considered an effective approach to achieve precise control of conductive filaments. The basic idea is to construct nanoscale spatial confinement structures to restrict the formation region of conductive filaments within a predefined nanometer range, thereby achieving controllability of their position, size, and growth path. Among various nanoconfinement structures, nanopillar arrays have become a research hotspot due to their well-defined geometry, tunable size, and ease of integration. By constructing oxide nanopillars within nanopores or templates, conductive filaments can be confined within a single nanopillar, significantly improving device consistency and stability. Furthermore, since the lateral dimensions of nanopillars are typically in the range of several nanometers to tens of nanometers, they naturally match the scale of conductive filaments, resulting in more concentrated current channels, which helps reduce power consumption and improve the on / off ratio.

[0005] Several mature technologies have been developed for the fabrication of nanopillar arrays. Template-assisted methods are among the most commonly used. For example, porous alumina templates are widely used to construct regular nanopillar arrays due to their highly ordered nanopore structure, tunable pore size, and large-area fabrication capabilities. High-density nanopillar structures can be achieved by depositing oxide materials in AAO nanopores. These templates are prepared by electrochemical deposition under acidic conditions, a cumbersome process involving the use of hazardous chemical reagents. Furthermore, the thickness of alumina templates is typically in the micrometer range, resulting in a high aspect ratio, which may hinder the precise controllability of filament formation. These inherent problems fundamentally compromise the uniformity between devices. Another common method is to use micro / nano fabrication techniques (such as EBL) to prepare high-resolution close-packed hole patterns, followed by filling with a dielectric to fabricate nanopillar arrays. However, EBL uses a point-by-point scanning method for pattern writing, resulting in low exposure efficiency, which is difficult to meet the demands of large-area, high-throughput manufacturing. Secondly, its equipment and operating costs are high, and it has strict requirements for vacuum environment and electron beam stability, limiting its industrialization. In addition, the BEL technology suffers from proximity effect when preparing sub-10nm resolution patterns, resulting in poor pattern quality.

[0006] Polymer self-assembly patterning (PAB) is an advanced patterning process based on the microphase separation phenomenon of block copolymers to form ordered patterns. With the guidance of external templates, it can further guide self-assembly to form regular lines and close-packed hole patterns. This technology can achieve sub-5nm resolution, breaking the optical diffraction limit. High-density, high-resolution periodic nanopatterns can be fabricated relatively easily through PAB. Since the early 21st century, DSA technology has received widespread attention from semiconductor manufacturers, and the 2021 IRDS still lists DSA as a potential patterning solution for advanced logic process nodes below 3 nm. Polymer PAB features high throughput, high resolution, low cost, and self-alignment, laying a solid foundation for its application in microelectronic devices. Large-area close-packed hole patterns can be easily obtained using columnar block copolymers, which can then be used to fabricate resistive switching layer nanopillar arrays and further construct memristor devices. In summary, polymer PAB provides an scalable approach for fabricating sub-10nm resolution nanopillar arrays and high-density, high-uniformity nanopillar array memristors. Summary of the Invention

[0007] The purpose of this invention is to provide a resistive switching material nanopillar array and a memristor device based on self-assembly patterning technology, and a method for preparing the same. More specifically, it provides a nanopillar array and a method for preparing the same, as well as a memristor device and a method for preparing the same.

[0008] The memristor fabrication method provided by this invention firstly involves the self-assembly of columnar block copolymers to form a vertical structure, followed by selective etching to obtain a close-packed aperture array. Secondly, resistive switching materials are filled into the close-packed aperture pattern to form a nanopillar array. Finally, electrodes are deposited using micro / nano fabrication processes to form a sandwich-structured memristor device. This close-packed aperture fabrication method eliminates the need for traditional photolithography, allows for the control of nanopore size down to the sub-10nm scale through material and etching parameters, and is compatible with various resistive switching materials, thereby enabling the fabrication and performance tuning of memristors based on nanopillar arrays.

[0009] This invention first provides a method for preparing a resistive switching material nanopillar array based on self-assembly patterning technology, comprising the following steps:

[0010] S1. The substrate is subjected to hydrophilic treatment to obtain a pretreated substrate;

[0011] S2. The pretreated substrate is surface modified using the first random copolymer solution to obtain a neutral interface layer that is uniformly wettable to the blocks contained in the second block copolymer.

[0012] S3. Spin-coat the second block copolymer solution onto the modified substrate to obtain a polymer film of a certain thickness (e.g., 10-150 nm).

[0013] S4. Anneal the second block copolymer film to obtain a vertically oriented columnar phase morphology.

[0014] S5. Selective etching process is used to etch the vertically oriented columnar phase morphology to remove a certain self-assembled phase domain and form a close-packed hole array pattern.

[0015] S6. Spin-coat a solution of resistive switching material nanoparticles or their precursors onto a close-packed pore array pattern to allow the resistive switching material to enter the nanopores, and perform thermal annealing to obtain a resistive switching material nanopillar array.

[0016] Furthermore, in step S1:

[0017] The substrate is selected from: semiconductor materials, such as silicon, silicon oxide, silicon nitride, etc., conductive glass (ITO), metal materials, such as gold, silver, copper, etc., metal silicides, such as platinum silicon, iridium silicon, tungsten silicon, palladium silicon, etc.

[0018] The hydrophilic treatment includes at least one of plasma etching, hydrogen fluoride solution etching, or piranha solution etching. This hydrophilic treatment increases the grafting rate of the substrate modification material, which is beneficial for the more uniform formation of the neutral layer wettable block copolymer.

[0019] Furthermore, in step S2:

[0020] The first random copolymer (molecular brush or molecular felt material) modifies the interfacial properties of the array template, so that the modified layer obtained by grafting or crosslinking is conducive to guiding the second block copolymer to perform directed self-assembly.

[0021] The components of the first random copolymer include at least one of polystyrene (PS), polymethyl methacrylate (PMMA), polymethyl methacrylate-β-cinnamoyl oxyethyl methacrylate (PMPA), or polyglycidyl methacrylate (PGMA).

[0022] Preferably, the first random copolymer is PS-r-PMMA-r-PGMA, wherein the percentage molar content of the PS component is 50-80%, the percentage molar content of the PMMA component is 20-50%, and the percentage molar content of the PGMA component is 0.01-5%.

[0023] The solution containing the first random copolymer has a mass percentage content of 0.01-2% for the first random copolymer.

[0024] The solvent in the solution containing the first random copolymer includes propylene glycol methyl ether acetate (PGMEA).

[0025] The curing method includes thermal curing or photocuring. The thermal curing temperature is 200-280℃, and the thermal curing time is 1-60 min. The photocuring is curing under ultraviolet light for 1 second to 60 minutes. The corresponding crosslinking curing method is selected based on the crosslinking groups of the first random copolymer.

[0026] Furthermore, in step S3:

[0027] The copolymer type of the second block copolymer is at least one of AbB type and Ab-(BrC) type.

[0028] Because columnar block copolymers can form vertically oriented hexagonal nanopillar structures on a neutral substrate through annealing and microphase separation, and then selectively etch away a certain phase in the block copolymer to form a porous structure, the whole structure constitutes a porous pattern.

[0029] The volume fraction of the second block copolymer is controlled to maintain its columnar phase structure.

[0030] For the PS-b-PMMA system, the PS volume fraction is controlled between 60% and 80%.

[0031] The second block copolymer is at least one of polystyrene-b-polymethyl methacrylate, polystyrene-b-polymethyl acrylate, polystyrene-b-polyisoprene, polystyrene-b-polylactic acid, polystyrene-b-polydimethylsiloxane, polystyrene-b-polytrimethylene carbonate, polystyrene-b-polyvinyl acetate, polystyrene-b-polyvinylpyridine, and polystyrene-b-poly(methyl methacrylate-r-glycidyl methacrylate derivative).

[0032] Both the second block copolymer and the first random copolymer contain A and B parts, and their properties are similar, which makes it easier to control their directed self-assembly.

[0033] The self-assembly cycle of the second block copolymer is 5-100 nm, and the diameter of the resulting close-packed pores is 2-80 nm.

[0034] Preferably, the microstructure of the second block copolymer includes at least one of star-shaped or bottle brush-shaped.

[0035] The solvent in the solution containing the second block copolymer includes propylene glycol methyl ether acetate (PGMEA).

[0036] Preferably, the mass percentage of the second block copolymer solution in the solution containing the second block copolymer is 0.1-10%.

[0037] Furthermore, in step S4:

[0038] The self-assembly annealing process includes at least one of thermal annealing, solvent annealing, or laser annealing.

[0039] The heat annealing temperature is 200-300℃, and the heat annealing time is 1-60 minutes.

[0040] Furthermore, in step S5:

[0041] The selective etching process is at least one of dry etching or wet etching.

[0042] The dry etching process uses a mixture of oxygen and other types of gases.

[0043] Furthermore, in step S6:

[0044] The resistive switching material is nanoparticles or a precursor solution. After spin coating, it enters the nanopores and is then annealed to obtain a nanopillar array structure, eliminating the need for photolithography to prepare the nanopores.

[0045] The resistive switching material is a DEX3, D3E2X9, or D2EE'X6 type perovskite material, such as CsPbBr3, Cs2AgBiBr6, MA3Bi2Br9, etc.

[0046] Preferably, the resistive switching material is a metal oxide material, such as HfO. x ZnO x wait.

[0047] In the block copolymers involved in this invention, "A", "B" and "C" represent monomer A molecular chain segments (i.e., A block), monomer B molecular chain segments (i.e., B block) and monomer C molecular chain segments (C block), respectively. "r" means that the A block and B block are randomly arranged along the main chain of the block copolymer, and "b" means that the A block and B block are homopolymerized within their respective blocks and are connected only at the ends of the two blocks.

[0048] The present invention also includes a resistive switching material nanopillar array obtained by the above preparation method.

[0049] This invention also provides a method for fabricating a memristor device based on a nanopillar array, comprising the following steps:

[0050] (1) The resistive switching material nanopillar array was prepared by the above method, wherein the substrate was ITO and the resistive switching material was perovskite material, and the resistive switching material nanopillar array was obtained as a perovskite nanopillar array.

[0051] (2) A polymethyl methacrylate isolation layer is spin-coated on the surface of the perovskite nanopillar array, and then a conductive electrode is deposited by micro-nano fabrication process to obtain a memristor device with a sandwich structure.

[0052] Preferably, the conductive electrode is made of gold, silver, ITO, etc.

[0053] The present invention also includes memristor devices prepared by the above method.

[0054] The resistive switching material nanopillar array of this invention is fabricated using a self-assembly patterning technique. The diameter of the nanopillar array can be as low as 10 nm, which is difficult to achieve on a large scale at the wafer level using traditional photolithography. Furthermore, this nanopillar array exhibits nano-confinement effects, and the polymer matrix on the outer side of the nanopillars further enhances these effects, as well as surface passivation. Memristor devices fabricated based on this nanopillar array possess nano-confinement properties, enabling the control of the growth and breakage of conductive filaments, thereby improving the resistive switching performance and stability of the device. This technology can be applied to the field of large-scale integrated circuit manufacturing. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of the process route for preparing the resistive switching material nanopillar array of the present invention.

[0056] Figure 2 This is a SEM image of a close-packed pore pattern formed based on a block copolymer self-assembly process.

[0057] Figure 3 SEM image of a nanopillar array structure fabricated using self-assembly patterning technology.

[0058] Figure 4 This is a schematic diagram of a memristor device structure based on a nanopillar array. Detailed Implementation

[0059] The present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0060] Unless otherwise specified, all experimental methods used were conventional; all materials and reagents used were commercially available. The first random copolymer and the second block copolymer used were both commercially available products.

[0061] Example 1: A method for fabricating a memristor device based on a nanopillar array, the process of which is as follows: Figure 1 As shown, the specific steps are as follows:

[0062] (1) Cut a 2cm×2cm cube of ITO with a diamond knife as a substrate. Then, use acetone and isopropanol to perform ultrasonic cleaning to remove organic matter from the silicon wafer surface. Each ultrasonic cleaning time is 5min. Then, blow it dry with nitrogen and then perform hydrophilic treatment with a plasma cleaner for 10min at a power of 80W to obtain the pretreated substrate.

[0063] (2) Using PGMEA as a solvent, a solution containing PS-r-PMMA-OH (first random copolymer) was prepared, wherein the percentage molar contents of PS component and PMMA component in the PS-r-PMMA-OH solution were 75% and 25%, respectively, and the mass percentage content of PS-r-PMMA-OH in the PS-r-PMMA-OH solution was 1%;

[0064] (3) The PS-r-PMMA-OH solution was dropped onto ITO and spin-coated to form a film. The spin-coating conditions were 2000 rpm for 1 min, and then crosslinked and cured at 250℃ for 60 min to obtain a modified layer with a film thickness of 10 nm, which modified the surface properties of the substrate.

[0065] (4) Using PGMEA as a solvent, prepare a solution containing PS-b-PMMA (second block copolymer), wherein the percentage molar content of PS block and PMMA block in the PS-b-PMMA solution is 75% and 25%, respectively, and the mass percentage content of PS-b-PMMA in the PS-b-PMMA solution is 5%;

[0066] (5) Spin-coat the PS-b-PMMA solution onto the guide template to form a film. The spin-coating conditions are 2000 rpm for 1 min.

[0067] (6) Under vacuum and at 250°C, annealing for 60 min induces the PS-b-PMMA block copolymer to self-assemble into a second block copolymer film layer, in which the PS block and PMMA block exhibit microphase separation, forming the initial nanopattern;

[0068] (7) A product with a nanopore pattern (referred to as nanopore pattern) is formed by selectively etching away the PMMA phase using a mixture of O2 (90% by volume) and Ar (10% by volume) as the plasma etching gas. The nanopore pattern is tested using scanning electron microscopy. Figure 2 As shown, the method of this embodiment can prepare a uniform, large-scale densely packed porous pattern with a pore size of 15 nm and a spacing of 40 nm; Figure 2 As shown;

[0069] (8) Lead bromide (PbBr2) and cesium bromide (CsBr) were dissolved in HBr solution at a molar ratio of 1:1, with a solution concentration of 2wt%. The solution was then dropped onto a close-packed porous pattern and spin-coated to form a film. The spin-coating conditions were 2000 rpm for 1 min, followed by annealing at 150 °C to form a CsPbBr3 perovskite nanopillar array with a diameter of 15 nm. Figure 3 As shown;

[0070] (9) Using PGMEA as solvent, prepare a solution containing polymethyl methacrylate (1%), drop the solution onto the nanopillar array, spin-coat the film, and rotate at 2000 rpm for 1 min. The thickness of the PMMA film is 10 nm.

[0071] (10) Using a magnetron sputtering instrument at a speed of 0.1 nm / s -1 and pressure ~10 -6 Torr deposits silver electrodes with a thickness of 100 micrometers to ultimately obtain memristor devices; such as Figure 4 As shown.

[0072] Example 2: A method for fabricating a memristor device based on a nanopillar array, the specific steps of which are as follows:

[0073] (1) A gold electrode layer was deposited on a silicon substrate of size 2cm×2cm by magnetron sputtering (at a rate of 0.1 nms). -1 and pressure ~10 -6 Torr), and then ultrasonically cleaned with acetone and isopropanol in sequence to remove organic matter from the surface of the silicon wafer. Each ultrasonic cleaning lasts for 5 minutes. Then, the wafer is dried with nitrogen and then hydrophilic treated with a plasma cleaner for 10 minutes at a power of 80W to obtain the pretreated substrate.

[0074] (2) Using PGMEA as a solvent, a solution containing PS-r-PMMA-OH (first random copolymer) was prepared, wherein the percentage molar contents of PS component and PMMA component in the PS-r-PMMA-OH solution were 75% and 25%, respectively, and the mass percentage content of PS-r-PMMA-OH in the PS-r-PMMA-OH solution was 1%;

[0075] (3) The PS-r-PMMA-OH solution was dropped onto ITO and spin-coated to form a film. The spin-coating conditions were 2000 rpm for 1 min, and then crosslinked and cured at 250℃ for 60 min to obtain a modified layer with a film thickness of 10 nm, which modified the surface properties of the substrate.

[0076] (4) Using PGMEA as a solvent, prepare a solution containing PS-b-PMMA (second block copolymer), wherein the percentage molar content of PS block and PMMA block in the PS-b-PMMA solution is 75% and 25%, respectively, and the mass percentage content of PS-b-PMMA in the PS-b-PMMA solution is 5%;

[0077] (5) Spin-coat the PS-b-PMMA solution onto the guide template to form a film. The spin-coating conditions are 2000 rpm for 1 min.

[0078] (6) Under vacuum and at 250°C, annealing for 60 min induces the PS-b-PMMA block copolymer to self-assemble into a second block copolymer film layer, in which the PS block and PMMA block exhibit microphase separation, forming the initial nanopattern;

[0079] (7) Using a mixture of O2 (90% by volume) and Ar (10% by volume) as plasma etching gas, the PMMA phase is selectively etched away to form a product with a nanopore array pattern (hereinafter referred to as nanopore pattern).

[0080] (8) Lead bromide (PbBr2) and cesium bromide (CsBr) were dissolved in HBr solution at a molar ratio of 1:1 with a solution concentration of 2wt%. The solution was then dropped onto a close-packed pore pattern and spin-coated to form a film. The spin-coating conditions were 2000 rpm for 1 min. The film was then annealed at 150 °C to form a CsPbBr3 perovskite nanopillar array with a diameter of 15 nm.

[0081] (9) Using PGMEA as solvent, prepare a solution containing polymethyl methacrylate (1%), drop the solution onto the nanopillar array, spin-coat the film, and rotate at 2000 rpm for 1 min. The thickness of the PMMA film is 10 nm.

[0082] (10) Using a magnetron sputtering instrument at a speed of 0.1 nm / s -1 and pressure ~10 -6 Torr deposits silver electrodes with a thickness of 100 micrometers to ultimately obtain memristor devices;

[0083] Example 3: A method for fabricating a memristor device based on a nanopillar array

[0084] Compared with Example 1, the difference is that in step (2), the hydroxyl-terminated PS-r-PMMA-OH (first random copolymer) is replaced with PS-r-PMMA-r-PGMA, wherein the percentage molar contents of PS component, PMMA component and PGMA component in PS-r-PMMA-r-PGMA are 75%, 24% and 1%, respectively.

[0085] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0086] Example 4: A method for fabricating a memristor device based on a nanopillar array

[0087] Compared with Example 1, the difference is that in step (2), the first random copolymer is changed to PS-r-PMMA-r-PMPA, PMPA (polymethyl methacrylate-β-cinnamoyl oxyethyl ester) contains crosslinkable β-phenylpropene functional groups, the percentage molar contents of PS component, PMMA component and PMPA component are 75%, 22% and 3% respectively, and the mass percentage content is 0.3%; and the crosslinking and curing at 250°C for 30 min is changed to ultraviolet light (wavelength 200-400nm) curing and crosslinking.

[0088] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0089] Example 5: A method for fabricating a memristor device based on a nanopillar array

[0090] Compared with Example 1, the difference is that in step (4), the second block copolymer is changed to a star copolymer, whose side arm contains PS-b-PMMA blocks, the percentage molar content of PS blocks and PMMA blocks is 65% and 35% respectively, and the mass percentage content of the second block copolymer is 1.5% of PGMEA solution.

[0091] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0092] Example 6: A method for fabricating a memristor device based on a nanopillar array

[0093] Compared with Example 1, the difference is that in step (4), the second block copolymer is changed to a bottle brush copolymer, whose side arm contains PS-b-PMMA blocks, the percentage molar content of PS blocks and PMMA blocks is 65% and 35% respectively, and the mass percentage content of the second block copolymer is 1.5% of PGMEA solution.

[0094] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0095] Example 7: A method for fabricating a memristor device based on a nanopillar array

[0096] Compared with Example 1, the difference is that in step (6), the thermal annealing method is changed to solvent annealing, the solvent is tetrahydrofuran or acetone, and the annealing time is 60 min at 30°C.

[0097] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0098] Example 8: A method for fabricating a memristor device based on a nanopillar array

[0099] Compared with Example 1, the difference is that in step (6), the thermal annealing method is changed to laser annealing. A carbon dioxide laser is used to anneal the block copolymer film for 20 minutes in a continuous irradiation or pulse mode.

[0100] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0101] Example 9: A method for fabricating a memristor device based on a nanopillar array

[0102] Compared with Example 1, the difference is that in step (6), the thermal annealing method is changed to microwave annealing, and the block copolymer film is annealed using a commercial microwave oven for 1 minute.

[0103] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0104] Example 10: A method for fabricating a memristor device based on a nanopillar array

[0105] Compared with Example 1, the difference is that in step (7), the selective etching process is changed to wet etching. UV exposure is used for 10 min, followed by rinsing with a mixed solvent of acetic acid / isopropanol (volume ratio 7 / 3) for 15 min.

[0106] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0107] Example 11: A method for fabricating a memristor device based on a nanopillar array

[0108] Compared with Example 1, the difference is that in step (8), the filling medium is changed to the precursor material Hf(OC4H9)4, and then the annealing time is 60 min at 200°C.

[0109] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

[0110] Example 12: A method for fabricating a memristor device based on a nanopillar array

[0111] Compared with Example 1, the difference is that in step (10), the top electrode is changed to ITO, and physical vapor deposition (power 100W, pressure 10) is used. -6 Torr).

[0112] The method in this embodiment has the same effect as in Embodiment 1, and it can also prepare uniform large-scale dense nanopillar arrays and sandwich structure memristor devices. The diameter of the nanopillars is 15 nm.

Claims

1. A method for preparing a resistive switching material nanopillar array, characterized in that, The specific steps are as follows: S1. The substrate is subjected to hydrophilic treatment to obtain a pretreated substrate; S2. The surface of the pretreated substrate is modified using the first random copolymer solution to obtain a neutral interface that is uniformly wettable to the blocks contained in the second block copolymer. S3. Spin-coat the second block copolymer solution onto the modified substrate to obtain a polymer film with a thickness of 10-150 nm. S4. Anneal the second block copolymer film to obtain a vertically oriented columnar phase morphology. S5. Selective etching process is used to etch the vertically oriented columnar phase morphology to remove a certain self-assembled phase domain and form a close-packed nanopore array pattern. S6. Spin-coat a solution of resistive switching material nanoparticles or their precursors onto a close-packed pore array pattern to allow the resistive switching material to enter the nanopores, and perform thermal annealing to obtain a resistive switching material nanopillar array.

2. The preparation method according to claim 1, characterized in that, In step S1: The substrate is selected from silicon, silicon oxide, silicon nitride, conductive glass, gold, silver, copper, platinum silicon, iridium silicon, tungsten silicon, and palladium silicon; The hydrophilic treatment is at least one of plasma etching, hydrogen fluoride solution etching, and piranha solution etching.

3. The preparation method according to claim 1, characterized in that, In step S2: The components of the first random copolymer include at least one of polystyrene, polymethyl methacrylate, poly(β-cinnamoyl ethyl methacrylate), and polyglycidyl methacrylate. In the solution containing the first random copolymer, the solvent is propylene glycol methyl ether acetate; the mass percentage of the first random copolymer is 0.01-2%. The curing method includes thermal curing or photocuring; wherein, the temperature for thermal curing is 200-280℃ and the time is 1-60min; and the photocuring is curing under ultraviolet light for 1s-60min.

4. The preparation method according to claim 3, characterized in that, In step S2, the first random copolymer is PS-r-PMMA-r-PGMA, and by percentage molar content, the PS component is 50-80%, the PMMA component is 20-50%, and the PGMA component is 0.01-5%.

5. The preparation method according to claim 3, characterized in that, In step S3: The volume fraction of the second block copolymer is controlled to maintain its columnar phase structure; The second block copolymer is at least one of polystyrene-b-polymethyl methacrylate, polystyrene-b-polymethyl acrylate, polystyrene-b-polyisoprene, polystyrene-b-polylactic acid, polystyrene-b-polydimethylsiloxane, polystyrene-b-polytrimethylene carbonate, polystyrene-b-polyvinyl acetate, polystyrene-b-polyvinylpyridine, and polystyrene-b-poly(methyl methacrylate-r-glycidyl methacrylate derivative); For the PS-b-PMMA system, the PS volume fraction should be controlled between 60% and 80%. Both the second block copolymer and the first random copolymer contain A and B parts, and their properties are similar. The self-assembly cycle of the second block copolymer is 5-100 nm, and the diameter of the close-packed pores formed is 2-80 nm. The solvent in the solution containing the second block copolymer is propylene glycol methyl ether acetate. The mass percentage of the second block copolymer solution in the solution is 0.1-10%.

6. The preparation method according to claim 1, characterized in that: In step S4, the self-assembly annealing process includes at least one of thermal annealing, solvent annealing, or laser annealing; In step S5, the selective etching method is at least one of dry etching or wet etching.

7. The preparation method according to claim 1, characterized in that, In step S6, the resistive switching material is selected from DEX3, D3E2X9, and D2EE'X6 type perovskite materials, or from metal oxide materials.

8. A resistive switching material nanopillar array obtained by the preparation method described in any one of claims 1-7.

9. A method for fabricating a memristor device based on a nanopillar array, characterized in that, The specific steps are as follows: (1) A resistive switching material nanopillar array is prepared according to the preparation method described in any one of claims 1-1, wherein the substrate is ITO, the resistive switching material is perovskite material, and the resistive switching material nanopillar array is a perovskite nanopillar array. (2) A polymethyl methacrylate isolation layer is spin-coated on the surface of the perovskite nanopillar array, and then a conductive electrode is deposited by micro-nano fabrication process to obtain a memristor device with a sandwich structure.

10. A memristor device obtained by the preparation method of claim 10.

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