High peak current density tunnel junction and its epitaxial growth method

Abstract

This invention discloses a high peak current density tunnel junction and its epitaxial growth method. The epitaxial growth method includes the following steps: providing a substrate; and sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate, wherein the first conductivity type heavily doped layer and the second conductivity type heavily doped layer are epitaxially grown at the same growth temperature. This invention, by employing an isothermal continuous epitaxial growth method, fundamentally eliminates the problem of thermal desorption of dopants during temperature change pauses in traditional variable-temperature processes, thus breaking through the bottleneck of peak current density in tunnel junctions.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high peak current density tunnel junction and its epitaxial growth method. Background Technology

[0002] In devices such as multi-junction solar cells, tandem semiconductor lasers, and vertical-cavity surface-emitting lasers (VCSELs), the tunnel junction is the core unit that connects different active regions and achieves electrical series connection. The peak current density of the tunnel junction directly determines the upper limit of the device's high-current operation and gain efficiency, and is a core performance indicator.

[0003] To optimize tunnel junction performance, the development of tunnel junctions (taking GaAs-based tunnel junctions as an example) in existing technologies typically follows two principles: First, ultra-thin design. To reduce unnecessary absorption of incident or emitted light and device thickness, the thickness of both the p-type and n-type heavily doped layers constituting the tunnel junction is usually strictly limited to below 30 nm. Second, variable-temperature growth. Because p-type dopants (such as carbon C) and n-type dopants (such as silicon Si and tellurium Te) achieve high concentrations and high electrical activity in semiconductor materials (such as GaAs), their optimal epitaxial growth temperatures often differ. To optimize the doping quality of the two layers separately, existing processes often pause growth after the first heavily doped layer is grown, raise or lower the reaction chamber temperature to the optimal growth temperature of the other layer, and then proceed with the growth of the second layer.

[0004] However, the inventors discovered significant flaws in the existing technology: First, dopant atom desorption: During the pause in temperature change (heating or cooling), the grown surface dopant atoms will undergo significant thermal desorption, resulting in the actual effective doping concentration at the tunnel junction interface being far lower than the design value.

[0005] Second, band overlap narrowing: The decrease in doping concentration at the tunnel junction interface causes the depletion region width of the pn junction to widen unintended. According to quantum tunneling theory, the tunneling probability of charge carriers is extremely sensitive to the depletion region width, exhibiting an exponential decay relationship. Therefore, the widening of the depletion region drastically reduces the tunneling probability of charge carriers, ultimately resulting in the peak current density of the tunnel junction failing to break through the bottleneck and falling far below theoretical expectations. Please refer to... Figure 1 In traditional variable-temperature tunnel junctions, the current-voltage characteristic curve rises slowly and enters a plateau saturation region after reaching a relatively low current density, severely limiting the peak current density. This is a direct electrical manifestation of the low tunneling efficiency caused by interface doping desorption and depletion region widening.

[0006] Third, the limitations of excessively thin heavily doped layers: In the pursuit of extremely thin designs, heavily doped tunnel junction layers are prone to lattice distortion under high doping conditions, and have extremely low tolerance for interface diffusion, making it difficult to support stable transmission of ultra-high current densities, resulting in low peak current of existing tunnel junctions. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a high peak current density tunnel junction and its epitaxial growth method that can overcome the bottleneck of peak current density of tunnel junctions.

[0008] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide an epitaxial growth method for a high peak current density tunnel junction, comprising the following steps: Provide a substrate; A first conductivity type heavily doped layer and a second conductivity type heavily doped layer are epitaxially grown sequentially on the substrate, and the first conductivity type heavily doped layer and the second conductivity type heavily doped layer are epitaxially grown at the same growth temperature.

[0009] Furthermore, the step of sequentially epitaxially growing a heavily doped layer of a first conductivity type and a heavily doped layer of a second conductivity type on the substrate includes: At a preset growth temperature, a heavily doped layer of the first conductivity type is epitaxially grown on the substrate; The growth source is switched, and the second type of heavily doped layer is epitaxially grown on the first type of heavily doped layer. During the switching process, the preset growth temperature is kept constant and the growth is not interrupted.

[0010] Furthermore, the step of sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate includes the following sub-steps: At a preset growth temperature, a heavily doped layer of a first conductivity type is epitaxially grown on the substrate; At a preset growth temperature, the surface of the first conductivity type heavily doped layer is rinsed with rinsing gas; The growth source is switched, and a second heavily doped layer of conductivity type is grown on the first heavily doped layer, while the preset growth temperature remains unchanged during the switching process.

[0011] Furthermore, the preset growth temperature range is 500℃~560℃.

[0012] Furthermore, when the first conductivity type heavy doping layer is an n-type heavy doping layer, the second conductivity type heavy doping layer is a p-type heavy doping layer; when the first conductivity type heavy doping layer is a p-type heavy doping layer, the second conductivity type heavy doping layer is an n-type heavy doping layer. The thickness of the n-type heavily doped layer is 50 nm to 80 nm, and the thickness of the p-type heavily doped layer is 20 nm to 40 nm; the doping concentration of the n-type heavily doped layer is greater than or equal to 1e19 / cm. 3 The doping concentration of the p-type heavily doped layer is greater than or equal to 1e20 / cm. 3 .

[0013] Furthermore, prior to the step of sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate, the following step is also included: A buffer layer is epitaxially grown on the substrate, the buffer layer being between the substrate and the first conductivity type heavily doped layer.

[0014] Furthermore, after the step of sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate, the following step is also included: A contact layer is epitaxially grown on the heavily doped layer of the second conductivity type; the conductivity type of the contact layer is the same as that of the heavily doped layer of the second conductivity type.

[0015] Furthermore, epitaxial growth is performed using metal-organic chemical vapor deposition or molecular beam epitaxy.

[0016] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a high peak current density tunnel junction, comprising: a first conductivity type heavily doped layer and a second conductivity type heavily doped layer; both the first conductivity type heavily doped layer and the second conductivity type heavily doped layer are formed by isothermal epitaxial growth at a preset growth temperature.

[0017] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a semiconductor device including the high peak current density tunnel junction.

[0018] The high peak current density tunnel junction and its epitaxial growth method of the present invention have at least the following beneficial effects: (i) This invention successfully solves the technical problems of interface doping desorption, depletion region broadening and low peak current density caused by temperature variation in traditional tunnel junctions by designing the thickness and doping concentration of the heavily doped layer through isothermal continuous growth. In the GaAs homogeneous material system, the peak current density is increased to more than 35,000 A / cm², which is a significant improvement compared with the traditional temperature variation process.

[0019] (ii) The growth temperature and supporting process determined in this invention have been verified to be effective in homogeneous or heterogeneous material systems such as GaAs, GaInP, and AlGaAs, and can generally achieve peak current density far superior to that of traditional temperature-controlled processes for the corresponding materials.

[0020] (iii) By increasing the thickness of the n-type heavily doped layer and the p-type heavily doped layer, this invention provides sufficient accumulation thickness and structural integrity for carrier transport under ultra-high current density while avoiding significant optical absorption, thereby enhancing the reliability of the device.

[0021] (iv) This invention provides a core tunnel junction unit technology with excellent performance, stable process and wide applicability for high-power and high-efficiency optoelectronic devices such as multi-junction solar cells and VCSELs. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a current-voltage characteristic curve of a tunnel junction using a traditional variable-temperature process.

[0023] Figure 2 This is a flowchart of one embodiment of the epitaxial growth method for high peak current density tunnel junctions of the present invention.

[0024] Figure 3 for Figure 2 A flowchart of an implementation method for step S300.

[0025] Figure 4 This is a current-voltage characteristic curve of the tunnel junction formed according to Embodiment 1 of the present invention.

[0026] Figure 5 This is a current-voltage characteristic curve of the tunnel junction formed according to Embodiment 2 of the present invention.

[0027] Figure 6 This is a current-voltage characteristic curve of the tunnel junction formed in Embodiment 3 of the present invention.

[0028] Figure 7 This is a schematic diagram of a high peak current density tunnel junction according to an embodiment of the present invention. Detailed Implementation The following disclosure provides various embodiments or examples for implementing different features of the present invention. Specific examples will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention.

[0029] The following disclosure provides various embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where other components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations.

[0030] Furthermore, spatial relation terms such as "below," "under," "below," "above," and "above" may be used herein to readily describe the relationship between one element or component and another element (or components) or component (or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms will encompass various different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and will be interpreted accordingly using the spatial relation descriptors used herein.

[0031] Although the numerical ranges and parameter settings presented in this invention are approximations, the numerical settings in specific instances are reported as precisely as possible. Any numerical value inherently contains some necessary error arising from the standard deviation found in the respective test measurements. Similarly, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable average standard error that can be conceived by one of ordinary skill in the art. Except in instances of operation / work, or unless expressly stated otherwise, all numerical ranges, totals, values, and percentages, such as those for material quantities, durations, temperatures, operating conditions, amounts, and other similarities disclosed herein, should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise stated, the numerical parameter settings set forth in this invention and the appended claims are approximations that can be changed upon request. At a minimum, each numerical parameter should be interpreted based on the number of significant figures reported and the application of ordinary rounding techniques. A range herein may be expressed as from one endpoint to another or between two endpoints. All scopes disclosed herein include endpoints unless otherwise stated.

[0032] Furthermore, the technical parts described in this invention and the appended claims are primarily the improved technical parts of this invention, and do not limit the object protected by this invention to only having these technical parts. Other known essential components (structures and / or methods) and / or non-essential components of the object protected, besides the technical parts described in this invention and the appended claims, are not included in this invention and the appended claims because they do not fall within the scope of improvements of this invention; however, this does not mean that the object protected by this invention does not possess these known components.

[0033] Please see Figure 2 This is a flowchart of an embodiment of the epitaxial growth method for a high peak current density tunnel junction according to the present invention. This embodiment includes the following steps: S100, providing a substrate.

[0034] Specifically, the substrate is selected from semiconductor materials suitable for epitaxial growth. It can be a homogeneous substrate (i.e., the same material or with the same lattice matching as the subsequent epitaxial layer material) or a heterogeneous substrate. Exemplarily, the substrate includes, but is not limited to, a semi-insulating GaAs substrate, an n-type GaAs substrate, or a p-type GaAs substrate. In a preferred embodiment of the present invention, an n-type GaAs substrate is selected. This substrate has good lattice matching with the subsequent GaAs-based tunnel junction layers (such as GaAs, AlGaAs, GaInP, etc.) to be grown, and its fabrication and processing technology is mature, which is beneficial for obtaining high-quality epitaxial layers.

[0035] In specific operations, the epitaxial growth method of tunnel junctions includes, but is not limited to, metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). In a preferred embodiment of the present invention, MOCVD is used for epitaxial growth. In this step, the substrate is loaded into the MOCVD reaction chamber for subsequent epitaxial growth steps.

[0036] S200, Epitaxially grow a buffer layer on the substrate.

[0037] To obtain a high-quality epitaxial surface, as a preferred embodiment, a buffer layer is grown on the substrate before growing each layer of the tunnel junction. The buffer layer is typically grown at a higher temperature to achieve better crystal quality. For example, the reaction chamber temperature is stabilized at approximately 700°C, and the buffer layer is grown at this temperature. The growth of the buffer layer effectively masks surface defects and dislocations on the substrate, providing a smooth substrate for the subsequent isothermal growth of heavily doped layers.

[0038] S300. A first conductivity type heavily doped layer and a second conductivity type heavily doped layer are sequentially epitaxially grown on the substrate. The first conductivity type heavily doped layer and the second conductivity type heavily doped layer are epitaxially grown at the same growth temperature. When the first conductivity type heavily doped layer is an n-type heavily doped layer, the second conductivity type heavily doped layer is a p-type heavily doped layer; when the first conductivity type heavily doped layer is a p-type heavily doped layer, the second conductivity type heavily doped layer is an n-type heavily doped layer.

[0039] This step is the core of achieving high peak current density in this invention. Unlike the traditional approach of "segmented temperature optimization," the inventors, through extensive experimentation, determined a balance temperature window—500℃ to 560℃—that simultaneously accommodates heavy n-type doping (Te doping) and heavy p-type doping (C doping), and used this as the growth temperature for the heavily doped tunnel junction layer. Within this temperature range, tellurium (Te) exhibits high doping efficiency and surface adhesion coefficient, while carbon (C), as a p-type dopant, also achieves a high concentration of active carriers. More importantly, because the reaction chamber temperature remains constant throughout the growth process, there is no need for heating or cooling pauses, completely eliminating the thermal desorption of doped atoms at the grown interface during temperature changes. This ensures a step-like distribution of doping concentration at the pn interface, forming a steeply distributed PN tunnel junction.

[0040] Please see Figure 3 This step S300 includes the following sub-steps: S310. At a preset growth temperature, the first conductivity type heavily doped layer is epitaxially grown on the substrate. If the aforementioned step S200 was performed and a buffer layer was grown on the substrate, then the first conductivity type heavily doped layer is grown on the buffer layer.

[0041] Taking n-type as the first conductivity type and p-type as the second conductivity type as an example, at a preset growth temperature (e.g., approximately 530°C), a group III source (such as TMGa, TMAl, or TMIn) and a group V source (AsH3 or PH3) are introduced into the reaction chamber, while an n-type dopant source, diethyltellurium (DETe), is introduced simultaneously. The growth rate is controlled at 5 nm / min to 20 nm / min, preferably 10 nm / min. The growth time is adjusted according to the target thickness, so that the thickness of the heavily doped n-type layer reaches 50 nm to 80 nm, and the doping concentration is controlled at greater than or equal to 1e19 / cm. 3 This thickness range is significantly increased compared to traditional ultrathin designs (≤30nm), but its function is not to form a light absorption layer, but to provide sufficient carrier accumulation effect and structural stability to support smooth tunneling under ultra-high current density.

[0042] S320. Switch the growth source and epitaxially grow the second conductivity type heavily doped layer on the first conductivity type heavily doped layer, keeping the preset growth temperature constant and ensuring that the growth is not interrupted during the switching process.

[0043] Once the first conductivity type heavily doped layer has grown to the set thickness, its corresponding group III source and dopant source are turned off. Immediately, the group III source for growing the second conductivity type heavily doped layer and its corresponding p-type dopant source, carbon tetrachloride (CCl4), are introduced, and growth continues at the same growth temperature. The growth rate is controlled between 5 nm / min and 20 nm / min, preferably 10 nm / min. The growth time is adjusted according to the target thickness, ensuring that the p-type heavily doped layer reaches a thickness of 20 nm to 40 nm, and the doping concentration is controlled to be greater than or equal to 1e20 / cm². 3 During this process, the first conductivity type heavily doped layer and the second conductivity type heavily doped layer grow continuously without interruption, effectively preventing the desorption of dopants.

[0044] In order to achieve rapid purification of the reaction chamber and in-situ protection of the surface, as a preferred embodiment, after the first conductivity type heavily doped layer is grown in step S310 and before the second conductivity type heavily doped layer is grown in step S320, the step of rinsing the surface of the first conductivity type heavily doped layer with rinsing gas is further included at a preset growth temperature.

[0045] Specifically, after shutting off the growth source of the first conductivity type heavily doped layer, a mixture of group V source and carrier gas (such as AsH3 / H2) is introduced into the reaction chamber to briefly flush the growth interface. The duration is controlled between 1 and 20 seconds, preferably 5 seconds. This operation effectively removes residual precursors and dopants from the reaction chamber, avoids memory effects, and protects the grown surface. Crucially, this flushing process is completed rapidly under isothermal conditions, without interrupting the entire process flow. Compared to the long process interruptions required by temperature variations in existing technologies, this brief, isothermal flushing time is negligible and can be considered as continuous growth of the two doping types, preventing thermal desorption of dopant atoms and thus ensuring the steepness of the doping distribution at the interface.

[0046] The growth order of the first conductivity type and the second conductivity type can be interchanged. That is, a p-type heavily doped layer can be grown on the substrate first, followed by an n-type heavily doped layer. The isothermal continuous growth is essentially the same and can both obtain a high-quality tunnel junction interface.

[0047] S400, Epitaxially grow a contact layer on the heavily doped layer of the second conductivity type.

[0048] To facilitate subsequent device fabrication and electrical testing, after the main structure of the tunnel junction is grown, a contact layer of the same type as the second conductivity type is grown at the growth temperature. The growth of this contact layer is also carried out in an isothermal manner, without introducing an additional temperature variation step.

[0049] After epitaxial growth was completed, a current channel of approximately 50 μm × 50 μm was formed on the sample surface by photolithography. The current-voltage characteristic curve was obtained by using the four-probe method to test the change of current with voltage and record the peak current density of the sample.

[0050] The present invention will be further illustrated below by way of several specific embodiments, as exemplified by the examples.

[0051] Implementation Method 1 Substrate preparation: An n-type GaAs substrate is used and placed into the MOCVD reaction chamber; Growth buffer layer: to stabilize the reaction chamber temperature at 700℃; Set the growth temperature: lower the reaction chamber temperature to 530℃ and keep it constant. All subsequent tunneling layers will grow at this temperature. Growth of n-type heavily doped layer: TMGa and DETe (tellurium source) are introduced, and high flow rate AsH3 is introduced. The growth rate is about 10 nm / min and the growth time is about 7.5 min to obtain n-type heavily doped GaAs layer. Isothermal switching: Turn off TMGa and DETe, keep the growth temperature constant at 530℃, and introduce AsH3 / H2 to rinse the interface for 5 seconds; Growth of p-type heavily doped layer: Immediately introduce TMGa and CCl4 (carbon source), keep the growth temperature constant at 530℃, the growth rate at about 5nm / min, and the growth time at about 6min to obtain a heavily C-doped p-type heavily doped GaAs layer. Isothermal switching: Turn off TMGa and CCl4, maintain the growth temperature at 530℃, and introduce AsH3 / H2 to rinse the interface for 5 seconds; Growth of p-type contact layer: TMGa and a small amount of CCl4 are introduced while maintaining the growth process to obtain a C-doped p-type contact GaAs layer.

[0052] Test results: A current channel of approximately 50µm x 50µm was formed on the P-side using photolithography. The current versus voltage curve was measured using the four-probe method. Please refer to [link / reference]. Figure 4 The peak current density of this sample reaches approximately 35,000 A / cm², which is far superior to that in the background technology. Figure 1 The peak current density demonstrated by conventional variable-temperature processes is typically below 25,000 A / cm². In this embodiment, the tunnel junction mentioned in the background art, using the same GaAs material system, achieves a significant leap in peak current density through the isothermal growth method of this invention.

[0053] Implementation Method 2 Substrate preparation: Same as in Implementation Method 1; Growth buffer layer: Same as in implementation method one; Tunnel junction growth temperature: The reaction chamber temperature was lowered to 540℃ and kept constant. All subsequent tunnel junction layers were grown at this temperature. Growth of n-type heavily doped layer: TMGa, TMIn and DETe are introduced, and PH3 with a high flow rate is introduced. The growth rate is about 10 nm / min and the growth time is about 7.5 min to obtain n-type heavily doped GaInP layer. Isothermal switching: TMGa, TMIn, PH3 and DETe are attached to the wall, and the growth temperature is kept constant at 540℃. AsH3 / H2 is introduced to rinse the interface for 5 seconds. Growth of p-type heavily doped layer: Immediately introduce TMGa, TMAl and CCl4, keep the growth temperature constant at 540℃, the growth rate is about 5nm / min, the growth time is about 6min, and a heavily C-doped p-type AlGaAs layer is obtained. Isothermal switching: Turn off TMGa, TMAl and CCl4, maintain growth temperature at 540℃, and introduce AsH3 / H2 to rinse the interface for 5 seconds; Growth of p-type contact layer: Same as in Implementation Method 1.

[0054] Test Results: A 50µm*50µm current channel was formed on the P-side using photolithography. The current versus voltage curve was measured using the four-probe method. Please refer to [link / reference]. Figure 5 The sample exhibits a peak current density of approximately 20,000 A / cm², significantly superior to tunnel junctions of similar materials grown using conventional variable-temperature processes. This result demonstrates that the isothermal growth method described in this invention can effectively suppress dopant thermal desorption and achieve high peak current densities, even in GaInP / AlGaAs heteromaterial systems.

[0055] Implementation Method 3 Substrate preparation: Same as in Implementation Method 1; Growth buffer layer: Same as in implementation method one; Set the growth temperature: lower the reaction chamber temperature to 550℃ and keep it constant. All subsequent tunneling layers will grow at this temperature. Growth of n-type heavily doped layer: TMAl, TMGa and DETe are introduced, and high flow rate of AsH3 is introduced. The growth rate is 10 nm / min and the growth time is 7.5 min to obtain n-type heavily doped AlGaAs layer. Isothermal switching: Turn off TMAl, TMGa and DETe, keep the growth temperature constant at 550℃, and introduce AsH3 / H2 to rinse the interface for 5 seconds; Growth of p-type heavily doped layer: Immediately introduce TMAl, TMGa and CCl4, keep the growth temperature constant at 550℃, the growth rate at about 5nm / min, and the growth time at about 6min to obtain a p-type heavily doped AlGaAs layer with heavy C doping. Isothermal switching: Turn off TMAl, TMGa and CCl4, maintain the growth temperature at 550℃, and introduce AsH3 / H2 to rinse the interface for 5 seconds. Growth of p-type contact layer: Same as in Implementation Method 1.

[0056] Test Results: A 50µm*50µm current channel was formed on the P-side using photolithography. The current versus voltage curve was measured using the four-probe method. Please refer to [link / reference]. Figure 6 The sample exhibits a peak current density of approximately 15,000 A / cm², significantly superior to tunnel junctions of similar materials grown using conventional temperature-controlled processes. This result further demonstrates the broad applicability of the core process of this invention to various material systems. Although the absolute peak current density of AlGaAs differs from that of GaAs due to factors such as the doping efficiency of the AlGaAs material itself, the performance obtained using the method of this invention still offers significant advantages over traditional temperature-controlled growth processes in this material system.

[0057] All three embodiments described above employed isothermal continuous growth at 500℃ to 560℃, and used a combination of n-type Te doping and p-type C doping, while setting the thicknesses of the n-layer and p-layer to 50–80 nm and 20–40 nm, respectively. The results from all three embodiments collectively demonstrate that: Implementation method one, as the main embodiment, strongly demonstrates that the present invention is superior to the prior art ( Figure 1 The resulting performance improvement is significant. Embodiments two and three demonstrate that the process of this invention has excellent versatility and can be widely applied to various semiconductor materials such as GaAs, GaInP, and AlGaAs, effectively suppressing thermal desorption of dopants and achieving peak current densities far exceeding those of traditional variable-temperature processes.

[0058] From a physical mechanism perspective, the superior performance of this invention stems from two synergistic effects: First, isothermal growth completely avoids the thermal desorption of doped atoms during temperature-dependent pauses in traditional processes, ensuring that the doping concentration at the pn metallurgical junction is close to the theoretical design value. Second, the moderately thickened heavily doped layers (50–80 nm for the n-layer and 20–40 nm for the p-layer) are not for light absorption, but rather provide sufficient accumulation layer thickness and structural integrity for carrier transport under ultra-high current densities, avoiding performance degradation caused by lattice mismatch or interface diffusion in traditional ultra-thin designs at high currents. It is this combination of isothermal continuous growth and thickness synergy that enables this invention to achieve improved peak current densities in various material systems such as GaAs, GaInP, and AlGaAs.

[0059] Please see Figure 7 This is a schematic diagram of a high peak current density tunnel junction according to an embodiment of the present invention. The high peak current density tunnel junction is obtained based on the epitaxial growth method of the high peak current density tunnel junction described in the above embodiment, and from bottom to top includes a substrate 100, a buffer layer 200, a first conductivity type heavily doped layer 300, a second conductivity type heavily doped layer 400, and a contact layer 500. Both the first conductivity type heavily doped layer 300 and the second conductivity type heavily doped layer 400 are formed by isothermal epitaxial growth at a preset growth temperature. The growth order of the two conductivity types of heavily doped layers can be interchanged; when the first conductivity type heavily doped layer 300 is an n-type heavily doped layer, the second conductivity type heavily doped layer 400 is a p-type heavily doped layer; when the first conductivity type heavily doped layer 300 is a p-type heavily doped layer, the second conductivity type heavily doped layer 400 is an n-type heavily doped layer. The thickness of the n-type heavily doped layer is 50 nm to 80 nm, and the thickness of the p-type heavily doped layer is 20 nm to 40 nm. The doping concentration of the n-type heavily doped layer is greater than or equal to 1e19 / cm². 3 The doping concentration of the p-type doped layer is greater than or equal to 1e20 / cm. 3 .

[0060] The present invention also discloses a semiconductor device, including the aforementioned high peak current density tunnel junction. The semiconductor device may be a multi-junction solar cell, a tandem semiconductor laser, a vertical-cavity surface-emitting laser, or the like.

[0061] This invention successfully solves the technical challenges of interface dopant desorption, depletion region broadening, and low peak current density caused by temperature variations in traditional tunnel junctions through the design of optimized heavy doping layer thickness and doping concentration during isothermal continuous growth. In GaAs homogeneous material systems, the peak current density is increased to over 35,000 A / cm², a significant improvement compared to traditional temperature-varying processes. The growth temperature and supporting processes determined in this invention have been verified as effective in homogeneous or heterogeneous material systems such as GaAs, GaInP, and AlGaAs, generally achieving peak current densities far superior to those achieved by traditional temperature-varying processes for the corresponding materials. By increasing the thickness of the n-type and p-type heavy doped layers, this invention avoids significant optical absorption while providing sufficient accumulation thickness and structural integrity for carrier transport at ultra-high current densities, thus enhancing device reliability. This invention provides a high-performance, stable, and widely applicable core tunnel junction unit technology for high-power, high-efficiency optoelectronic devices such as multi-junction solar cells and VCSELs.

Claims

1. A method for epitaxial growth of a high peak current density tunnel junction, characterized in that, Includes the following steps: Provide a substrate; A first conductivity type heavily doped layer and a second conductivity type heavily doped layer are epitaxially grown sequentially on the substrate, and the first conductivity type heavily doped layer and the second conductivity type heavily doped layer are epitaxially grown at the same growth temperature.

2. The epitaxial growth method for high peak current density tunnel junctions as described in claim 1, characterized in that... The step of sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate includes: At a preset growth temperature, a heavily doped layer of the first conductivity type is epitaxially grown on the substrate; The growth source is switched, and the second type of heavily doped layer is epitaxially grown on the first type of heavily doped layer. During the switching process, the preset growth temperature is kept constant and the growth is not interrupted.

3. The epitaxial growth method for high peak current density tunnel junctions as described in claim 1, characterized in that, in The step of sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate includes the following sub-steps: At a preset growth temperature, a heavily doped layer of the first conductivity type is epitaxially grown on the substrate; At a preset growth temperature, the surface of the first conductivity type heavily doped layer is rinsed with rinsing gas; The growth source is switched, and a second heavily doped layer of conductivity type is grown on the first heavily doped layer, while the preset growth temperature remains unchanged during the switching process.

4. The epitaxial growth method for high peak current density tunnel junctions as described in claim 1, characterized in that: The preset growth temperature range is 500℃~560℃.

5. The epitaxial growth method for high peak current density tunnel junctions as described in claim 1, characterized in that: When the first conductivity type heavy doping layer is an n-type heavy doping layer, the second conductivity type heavy doping layer is a p-type heavy doping layer; when the first conductivity type heavy doping layer is a p-type heavy doping layer, the second conductivity type heavy doping layer is an n-type heavy doping layer. The thickness of the n-type heavily doped layer is 50 nm to 80 nm, and the thickness of the p-type heavily doped layer is 20 nm to 40 nm; the doping concentration of the n-type heavily doped layer is greater than or equal to 1e19 / cm. 3 The doping concentration of the p-type heavily doped layer is greater than or equal to 1e20 / cm. 3 .

6. The epitaxial growth method for high peak current density tunnel junctions as described in claim 1, characterized in that, Before the step of sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate, the following step is also included: A buffer layer is epitaxially grown on the substrate, the buffer layer being between the substrate and the first conductivity type heavily doped layer.

7. The epitaxial growth method for high peak current density tunnel junctions as described in claim 1, characterized in that, After the step of sequentially epitaxially growing a first conductivity type heavily doped layer and a second conductivity type heavily doped layer on the substrate, the following step is also included: A contact layer is epitaxially grown on the heavily doped layer of the second conductivity type; the conductivity type of the contact layer is the same as that of the heavily doped layer of the second conductivity type.

8. The epitaxial growth method for high peak current density tunnel junctions as described in claim 1, characterized in that: Epitaxial growth is performed using metal-organic chemical vapor deposition or molecular beam epitaxy.

9. A high peak current density tunnel junction, characterized in that, It includes: a first conductivity type heavily doped layer and a second conductivity type heavily doped layer; both the first conductivity type heavily doped layer and the second conductivity type heavily doped layer are formed by isothermal epitaxial growth at a preset growth temperature.

10. A semiconductor device, characterized in that, Including the high peak current density tunnel junction as described in claim 9.

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