A method for preparing a redundant pattern for improving metal cmp topography
By employing a redundant pattern fabrication method with overlapping tiling in the copper tiling process, the problem of overlapping restrictions between the front-layer pattern structure and the metal region is solved, achieving higher pattern density uniformity and stability, reducing the risk of damage to the waveguide structure, and improving the morphology of the copper metal.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 国科光芯金杏(北京)实验室科技有限公司
- Filing Date
- 2025-01-24
- Publication Date
- 2026-07-31
AI Technical Summary
In copper inlay technology, the limitation that the front layer pattern structure and the metal area cannot overlap makes it difficult to achieve the target pattern density and uniformity requirements when adding redundant patterns to the front layer. Especially when the metal pattern density is high, the flexibility of adding redundant patterns and metal wiring to the front layer is limited, and it is difficult to stop the metal CMP process effectively, which can easily damage the front layer material structure.
Redundant patterns are added between the front-end structure and the metal structure by overlapping and embedding. This includes fabricating waveguide structures and redundant patterns on a silicon dioxide thin film, depositing and connecting metal deposition trenches, covering with copper metal, and then thinning and planarizing the surface using a CMP process. The upper surface of the waveguide structure is used as a stop layer, and finally a passivation layer is fabricated.
It improves the controllability and stability of the copper inlay process, reduces the risk of damage to the waveguide structure, achieves more uniform thickness control, and improves the structural morphology of metallic copper.
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Figure CN122497294A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing redundant patterns to improve the morphology of metal CMP. Background Technology
[0002] In semiconductor chip manufacturing, patterning is one of the core processes. It includes photolithography and etching, which replicate and transfer patterns from a photomask to thin film materials on a wafer to form circuits, optical paths, or micromechanical structures. Filling with dummy patterns plays a crucial role in this process. It not only relieves thin film stress and enhances the physical structure's strength but also reduces the loading effect caused by uneven pattern density during processing, thereby effectively controlling process consistency and stability.
[0003] Furthermore, chemical mechanical polishing (CMP) is equally important in chip manufacturing processes, widely used in surface planarization, copper siding, and other processes. Adding redundant patterns allows for more precise and uniform control of thickness and morphology during the process, which is beneficial for achieving higher chip yields and performance. Therefore, developing a suitable redundant pattern filling scheme to meet pattern density requirements during layout design is crucial and requires careful consideration.
[0004] The conventional method for filling redundant patterns is to uniformly fill the blank areas between the main design patterns to achieve the target pattern density and uniform distribution. For copper damascene processes using CMP, the general process is as follows: first, trenches are patterned in the dielectric layer; then, metallic copper is deposited using PVD to completely fill the trenches; finally, CMP is performed on the metallic copper until the dielectric layer is reached. When the trenches are deep and overlap with the previous layer material structure in the vertical direction of the chip, to ensure good uniformity and structural morphology of the metal deposition trench etching, the etching material should be a single dielectric as much as possible. Therefore, when adding redundant patterns to the previous layer, the metal (deposition trench) area should usually be avoided.
[0005] It is evident that in copper tiling, the mutual restriction between the front-layer pattern structure and the metal (deposition tank) area, which prevents overlap, makes it difficult to achieve the desired pattern density and uniformity when adding redundant patterns to the front layer. This is especially true when the metal pattern density is high, significantly limiting the flexibility of adding redundant patterns and metal wiring in the front layer. Furthermore, in metal CMP processes, if the front-layer material structure is used as a stop layer, the aforementioned restrictions and issues such as uneven pattern density will make it difficult to effectively stop the CMP process, leading to over-polishing and damage to the front-layer material structure. Summary of the Invention
[0006] In view of this, embodiments of this application provide a method for preparing redundant patterns to improve the morphology of metal CMP, which at least partially solves the problem in the prior art that, in copper tiling processes, the mutual restriction between the front layer pattern structure and the metal region, which prevents overlap, makes it difficult to achieve the target pattern density and uniformity when adding redundant patterns to the front layer.
[0007] This application provides a method for preparing redundant patterns to improve the morphology of metal CMP, the method comprising:
[0008] The method includes:
[0009] A silicon substrate is provided, and a silicon dioxide thin film is prepared on the silicon substrate;
[0010] A waveguide structure and corresponding redundant patterns are fabricated on the silicon dioxide thin film;
[0011] The waveguide structure and the redundant pattern are clad with silicon dioxide.
[0012] Metal deposition trenches are prepared on one or both sides of the waveguide structure, and the metal deposition trenches are interconnected within the gaps of the redundant pattern;
[0013] Deposit metallic copper to cover the metal deposition tank and the silica cladding;
[0014] The copper metal is thinned and planarized using a CMP process, with the upper surface of the waveguide structure serving as a stop layer.
[0015] Prepare a passivation layer.
[0016] According to a specific implementation of an embodiment of this application, the fabrication of the waveguide structure and corresponding redundant patterns on the silicon dioxide thin film includes:
[0017] Multilayer waveguide structures and redundant patterns corresponding to each waveguide layer are fabricated on the silicon dioxide thin film using a patterning process.
[0018] According to a specific implementation of an embodiment of this application, the step of fabricating a metal deposition trench on one or both sides of the waveguide structure includes:
[0019] The metal deposition trench is fabricated on one or both sides of the waveguide structure using a patterning process, wherein the bottom of the metal deposition trench extends to at least one layer of the waveguide redundancy pattern located below the top waveguide redundancy pattern.
[0020] According to a specific implementation of an embodiment of this application, the distance between the outer wall of the metal deposition tank and the side wall of the waveguide structure is greater than or equal to 1 μm.
[0021] According to a specific implementation of an embodiment of this application, the distance between the inner wall of the metal deposition tank and the side wall of the redundant pattern is greater than or equal to 1 μm.
[0022] According to a specific implementation of an embodiment of this application, the depth of the metal deposition tank in the metal deposition tank region is 0.5μm to 1.5μm, and the width is 15 to 300μm.
[0023] According to a specific implementation of an embodiment of this application, the step of fabricating a silicon dioxide cladding layer on the waveguide structure and the redundant pattern includes:
[0024] Silicon dioxide was deposited on the waveguide structure and the redundant pattern using a CVD process.
[0025] The silicon dioxide is thinned and planarized using a CMP process, and the upper surface of the waveguide structure is used as a stop layer to complete the preparation of the silicon dioxide cladding.
[0026] According to a specific implementation of an embodiment of this application, the deposited metallic copper includes:
[0027] Metallic copper with a thickness of 1μm to 2μm was deposited using the PVD process.
[0028] According to a specific implementation of an embodiment of this application, the preparation of the passivation layer includes:
[0029] A silicon dioxide passivation layer with a thickness greater than 50 nm is deposited using a CVD process.
[0030] According to one specific implementation of the present application, the material of the redundant pattern is silicon or silicon nitride, and the optical waveguide is a silicon nitride waveguide or a composite waveguide.
[0031] Beneficial effects:
[0032] The redundant pattern fabrication method for improving the CMP morphology of metal in this application embodiment adds redundant patterns to the front layer structure and the metal structure through overlapping and inlaying. This reduces the limiting relationship between the copper inlay process and the front layer pattern structure, making the addition of redundant patterns more flexible and easier to meet the target pattern density requirements, thus making the patterning process more stable and controllable. At the same time, due to the addition of redundant patterns, the thickness control of the CMP process in the cladding fabrication and copper inlay process is more uniform, and the detection is stopped more effectively when in contact with the waveguide structure, which greatly reduces the risk of damage to the waveguide structure and can effectively improve the structural morphology of the copper. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram illustrating the preparation of a silicon dioxide thin film according to an embodiment of the present invention;
[0035] Figure 2 This is a schematic diagram of the waveguide structure and redundancy pattern fabrication according to an embodiment of the present invention;
[0036] Figure 3 This is a schematic diagram illustrating the preparation of a silica cladding layer according to an embodiment of the present invention;
[0037] Figure 4 This is a schematic diagram illustrating the fabrication of a metal deposition tank according to an embodiment of the present invention;
[0038] Figure 5 for Figure 4 Top view;
[0039] Figure 6 This is a schematic diagram of deposited metallic copper according to an embodiment of the present invention;
[0040] Figure 7 This is a schematic diagram of silicon dioxide thinning and planarization according to an embodiment of the present invention;
[0041] Figure 8 for Figure 7 Top view;
[0042] Figure 9 This is a schematic diagram illustrating the preparation of a passivation layer according to an embodiment of the present invention.
[0043] In the figure: 1. Silicon substrate; 2. Silicon dioxide; 3-1. Waveguide structure; 3-2. Redundant pattern; 4. Metal deposition trench; 5. Copper metal. Detailed Implementation
[0044] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0045] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0046] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0047] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0048] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0049] In existing copper tiling processes, the mutual restriction that prevents the overlap between the front-layer pattern structure and the metal (deposition tank) area makes it difficult to achieve the required pattern density and uniformity when adding redundant patterns to the front layer. This is especially true when the metal pattern density is high, significantly limiting the flexibility of adding redundant patterns and metal wiring in the front layer. Furthermore, in metal CMP processes, if the front-layer material structure is used as a stop layer, the aforementioned restrictions and problems such as uneven pattern density will make it difficult to effectively stop the CMP process, leading to over-polishing and damage to the front-layer material structure.
[0050] To address the aforementioned issues, this application provides a method for preparing redundant patterns to improve the morphology of metal CMP. The redundant patterns are added and prepared by overlapping and inlaying the front-layer structure and the metal structure, thereby reducing the limiting relationship between the copper inlay process and the front-layer pattern structure, and thus improving the controllability, stability, and uniformity of the copper inlay process. The following refers to... Figures 1 to 9 Provide a detailed description.
[0051] In one embodiment, a method for preparing redundant patterns to improve the morphology of metal CMP includes the following steps:
[0052] Step S101: Provide a silicon substrate 1, and prepare a silicon dioxide 2 thin film on the silicon substrate 1;
[0053] Step S102: Prepare waveguide structure 3-1 and corresponding redundant pattern 3-2 on the silicon dioxide 2 thin film;
[0054] Step S103: Prepare a silicon dioxide cladding for the waveguide structure 3-1 and the redundant pattern 3-2;
[0055] Step S104: Prepare metal deposition trenches 4 on one or both sides of the waveguide structure 3-1, wherein the metal deposition trenches 4 are interconnected within the gaps of the redundant pattern 3-2.
[0056] Step S105: Deposit metallic copper to cover the metal deposition tank 4 and the silicon dioxide cladding;
[0057] Step S106: Thin and planarize the copper metal using CMP process, with the upper surface of the waveguide structure 3-1 as the stop layer;
[0058] Step S107: Prepare a passivation layer.
[0059] In specific implementation, the setting of the metal deposition tank 4, taking a waveguide modulation device as an example, refers to... Figure 5 Metal deposition trenches 4 are prepared on the left and right sides of the front waveguide structure 3-1, and the redundant pattern 3-2 of the front layer is uniformly arranged around the front waveguide structure 3-1. Here, the front layer refers to the layer that is prepared first in the fabrication process.
[0060] In specific implementation, the metal deposition tank 4 is specifically set on one or both sides of the waveguide structure 3-1 in the horizontal projection direction.
[0061] In this embodiment, the front-layer device structure (waveguide structure 3-1) and the metal deposition trench 4 are avoided, without overlapping or interlocking. Only the redundant front-layer pattern 3-2 and the metal deposition trench 4 are interlocked, and the metal deposition trenches 4 within a region are interconnected to form a whole. After depositing copper 5, the interconnected metal regions can form a whole without being divided by the redundant pattern 3-2, thus the copper 5 can form lead electrodes. Therefore, because the front-layer structure and the metal structure overlap and interlock, the constraint relationship between the copper inlay process and the front-layer pattern structure is reduced, thereby improving the controllability, stability, and uniformity of the copper inlay process.
[0062] In one embodiment, the fabrication of the waveguide structure 3-1 and the corresponding redundant pattern 3-2 on the silicon dioxide 2 thin film includes:
[0063] A multilayer waveguide structure 3-1 and a redundant pattern 3-2 corresponding to each layer of the waveguide structure 3-1 are fabricated on the silicon dioxide 2 thin film using a patterning process.
[0064] In specific implementation, the waveguide structure 3-1 is provided with multiple layers, corresponding to multiple redundant patterns 3-2. The method for preparing the multi-layer waveguide structure 3-1 and the multi-layer redundant patterns 3-2 specifically includes the following steps:
[0065] Silicon dioxide 2 was deposited on a silicon substrate by low-pressure chemical vapor deposition (LPCVD);
[0066] Then, a first dielectric layer is deposited to achieve a low-loss optical transmission channel;
[0067] The first layer of optical waveguide and corresponding redundant pattern 3-2 are formed by etching the first dielectric layer. The filling of the redundant pattern 3-2 also needs to meet the setting requirements of the metal deposition tank 4.
[0068] Then silica 2 was deposited and chemical mechanical polishing (CMP) was performed.
[0069] After CMP, a second dielectric layer is deposited. The waveguide structure 3-1 and the corresponding redundant pattern 3-2 of the second layer are formed by etching the second dielectric layer. The position of the redundant pattern 3-2 of this layer corresponds one-to-one with the position of the redundant pattern 3-24 of the first layer. The requirements for setting the metal deposition tank 4 must also be met.
[0070] Then, silicon dioxide 2 is deposited and chemically mechanically polished; if more layers of waveguide structure 3-1 and redundant pattern 3-2 are required, the above steps are repeated.
[0071] In one embodiment, refer to Figure 4 and Figure 5The fabrication of metal deposition trenches 4 on one or both sides of the waveguide structure 3-1 includes:
[0072] The metal deposition trench 4 is prepared on one or both sides of the waveguide structure 3-1 by a patterning process, and the bottom of the metal deposition trench 4 extends to at least one layer of the waveguide redundancy pattern 3-2 located below the top waveguide redundancy pattern 3-2.
[0073] Furthermore, the depth of the metal deposition tank 4 is 0.5 μm to 1.5 μm, and the width is 15 to 300 μm.
[0074] In practice, the metal deposition trench 4 can be fabricated using photolithography etching. The metal deposition trench 4 is etched around the redundant pattern 3-2 and the waveguide structure 3-1. The sidewalls of the metal deposition trench 4 are at a certain distance from either the redundant pattern 3-2 or the waveguide structure 3-1; that is, both the redundant pattern 3-2 and the waveguide structure 3-1 are covered with silicon dioxide 2. The metal deposition trench 4 does not overlap or interlock with the waveguide structure 3-1; it only overlaps and interlocks with the redundant pattern 3-2. After metal is deposited in the metal deposition trench 4, the metal region is divided into multiple regions due to the position of the waveguide structure 3-1. Metal deposition trenches 4 within a single region are interconnected, while those in different regions are not interconnected. (See attached diagram for details.) Figure 5 It should be noted that, in this embodiment, the width of the metal deposition tank 4 is the overall width of the outer perimeter of the metal deposition tank 4 in one metal region.
[0075] In one embodiment, the distance between the outer wall of the metal deposition tank 4 and the side wall of the waveguide structure 3-1 is greater than or equal to 1 μm.
[0076] In one embodiment, the distance between the inner wall of the metal deposition tank 4 and the sidewall of the redundant pattern 3-2 is greater than or equal to 1 μm. This can be understood as the thickness of the silicon dioxide 2 surrounding the redundant pattern 3-2 being greater than or equal to 1 μm.
[0077] In specific implementation, when preparing the metal deposition tank 4, the preparation process requirements of the metal deposition tank 4 need to be considered. In order to avoid damage to the waveguide structure 3-1 or redundant pattern 3-2 when photolithographically etching the metal deposition tank 4, the edge of the metal deposition tank 4 needs to maintain a certain distance (more than 1 μm) from the waveguide structure 3-1 or redundant pattern 3-2 to prevent it from being etched and damaged during metal etching.
[0078] In one embodiment, refer to Figure 1 The preparation of a silicon dioxide 2 thin film on the silicon substrate 1 includes:
[0079] A silicon dioxide thin film with a thickness of 1–8 μm was prepared on a silicon substrate 1 by CVD or thermal oxidation growth.
[0080] In one embodiment, refer to Figure 2 The fabrication of waveguide structure 3-1 and corresponding redundant pattern 3-2 on the silicon dioxide 2 thin film includes:
[0081] A dielectric layer is deposited on the silicon dioxide 2 thin film;
[0082] The dielectric layer is patterned to prepare the waveguide structure 3-1 and the redundant pattern 3-2.
[0083] In specific implementations, silicon nitride (SiNx) thin films can be used as the dielectric layer. SiNx thin films with a thickness of 100–500 nm and a refractive index of 1.9–2.2 are deposited using CVD processes. Then, SiNx waveguide structures 3-1 and redundant patterns 3-2 are fabricated using patterning processes such as photolithography and etching. In this embodiment, the subsequent metal deposition trench 4 overlaps and is embedded with the redundant pattern 3-2. Therefore, the redundant pattern 3-2 does not need to avoid the subsequent metal (deposition trench) region, making the addition of the redundant pattern 3-2 more flexible and easier to meet the target pattern density requirements, resulting in a more stable and controllable patterning process.
[0084] In one embodiment, the dielectric layer is a silicon nitride layer, a silicon layer, or formed by stacking multiple waveguide materials, wherein the deposition thickness of the silicon nitride layer is 100–500 nm and the refractive index is 1.9–2.2.
[0085] In one embodiment, refer to Figure 3 The fabrication of the silicon dioxide cladding on the waveguide structure 3-1 and the redundant pattern 3-2 includes:
[0086] Silicon dioxide 2 is deposited on the waveguide structure 3-1 and the redundant pattern 3-2 using a CVD process;
[0087] The silicon dioxide 2 is thinned and planarized using the CMP process, and the upper surface of the waveguide structure 3-1 is used as a stop layer to complete the cladding preparation of the silicon dioxide 2.
[0088] In practice, a silicon dioxide (SiNx) layer with a thickness of 1–1.5 μm is deposited using CVD. Then, a ceramic polishing (CMP) process is used to thin and planarize the SiNx layer (the upper surface of waveguide structure 3-1) as a stop layer. During CMP, since the previous SiNx layer is used as the stop layer, the thickness of SiNx 2 on waveguide structure 3-1 and redundant pattern 3-2 is zero. At this point, the redundant pattern 3-2 overlaps with the subsequent metal region, making it easier to meet requirements when adding dummy patterns to the previous waveguide structure 3-1. Therefore, using the previous layer as the stop layer in CMP is easier to control, resulting in less damage to the previous waveguide structure 3-1 and more precise and uniform control of the CMP thickness and morphology. The basic principle of stopping the polishing is that the SiNx film is hard, and a significant difference in polishing rate occurs when the SiNx layer comes into contact with the silicon dioxide 2 during CMP; this is the point at which polishing stops. The same principle of stopping the polishing also applies to the CMP process of copper 5 using the previous SiNx layer as the stop layer.
[0089] In one embodiment, the thickness of the silicon dioxide 2 deposited by the CVD process is 1-1.5 μm.
[0090] In one embodiment, refer to Figure 6 The deposited metallic copper 5 comprises:
[0091] Metallic copper with a thickness of 1μm to 2μm was deposited using a PVD process.
[0092] In practical implementation, the PVD process for depositing metallic copper 5 mainly focuses on thickness design; other process parameters are not required in this embodiment. Depositing metallic copper 5 can be achieved through methods such as thermal evaporation (temperature reaching the melting point of Cu) or sputtering (high-energy particle bombardment).
[0093] In one embodiment, refer to Figure 7 and Figure 8 The copper 5 layer was thinned and planarized using CMP (Chemical Motion Process) until the preceding SiNx layer was reached, creating an intercalated structure of the metal-SiNx redundant pattern 3-2. As shown in the figure, the preceding redundant pattern 3-2 is intercalated with the metal region. The metal region, due to its interconnection, remains a unified whole and is not divided by the preceding redundant pattern 3-2. Therefore, the metal region can serve as a lead electrode. Simultaneously, the addition of the preceding redundant pattern 3-2 results in more uniform thickness control during the cladding fabrication and copper 5 embedding process via CMP. It also allows for more effective detection stopping upon contact with SiNx, significantly reducing the risk of damage to the SiNx waveguide and effectively improving the structural morphology of the copper 5 layer.
[0094] In one embodiment, refer to Figure 9 The preparation of the passivation layer includes:
[0095] A silicon dioxide passivation layer with a thickness greater than 50 nm was deposited using a CVD process.
[0096] In the above embodiments, the CVD processes for SiNx and silicon dioxide 2 are mainly divided into LPCVD (low-pressure chemical vapor deposition) and PECVD (plasma-enhanced chemical vapor deposition). The SiNx used to prepare the waveguide structure 3-1 is usually deposited by LPCVD, which results in lower optical loss, and its deposition temperature is 600-800℃. The deposition temperature of PECVD is usually 300-500℃. Other process parameters, such as gas source, cavity pressure, gas flow rate, radio frequency power, deposition temperature, etc., are not particularly limited in this application.
[0097] In one embodiment, the material of the redundant pattern 3-2 is silicon or silicon nitride, and the optical waveguide 3-1 is a silicon nitride waveguide or a composite waveguide.
[0098] The embodiments provided by this invention involve adding redundant patterns to the front-layer structure and the metal structure through an overlapping and inlaying method. This reduces the constraints between the copper inlay process and the front-layer pattern structure, making the addition of redundant patterns more flexible and easier to meet the target pattern density requirements, thus making the patterning process more stable and controllable. At the same time, due to the addition of redundant patterns, the thickness control of the CMP process in the cladding preparation and copper inlay process is more uniform, and the detection is stopped more effectively when in contact with the waveguide structure, greatly reducing the risk of damage to the waveguide structure and effectively improving the structural morphology of the copper.
[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for preparing redundant patterns to improve the morphology of metal CMP, characterized in that, The method includes: A silicon substrate is provided, and a silicon dioxide thin film is prepared on the silicon substrate; A waveguide structure and corresponding redundant patterns are fabricated on the silicon dioxide thin film; The waveguide structure and the redundant pattern are clad with silicon dioxide. Metal deposition trenches are prepared on one or both sides of the waveguide structure, and the metal deposition trenches are interconnected within the gaps of the redundant pattern; Deposit metallic copper to cover the metal deposition tank and the silica cladding; The copper metal is thinned and planarized using a CMP process, with the upper surface of the waveguide structure serving as a stop layer. Prepare a passivation layer.
2. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 1, characterized in that, The fabrication of the waveguide structure and corresponding redundant patterns on the silicon dioxide thin film includes: Multilayer waveguide structures and redundant patterns corresponding to each waveguide layer are fabricated on the silicon dioxide thin film using a patterning process.
3. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 2, characterized in that, The fabrication of metal deposition trenches on one or both sides of the waveguide structure includes: The metal deposition trench is fabricated on one or both sides of the waveguide structure using a patterning process, wherein the bottom of the metal deposition trench extends to at least one layer of the waveguide redundancy pattern located below the top waveguide redundancy pattern.
4. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 1, characterized in that, The distance between the outer wall of the metal deposition tank and the side wall of the waveguide structure is greater than or equal to 1 μm.
5. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 1, characterized in that, The distance between the inner wall of the metal deposition tank and the sidewall of the redundant pattern is greater than or equal to 1 μm.
6. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 1, characterized in that, The depth of the metal deposition tank in the metal deposition tank area is 0.5μm to 1.5μm, and the width is 15 to 300μm.
7. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 1, characterized in that, The fabrication of the silicon dioxide cladding on the waveguide structure and the redundant pattern includes: Silicon dioxide was deposited on the waveguide structure and the redundant pattern using a CVD process. The silicon dioxide is thinned and planarized using a CMP process, and the upper surface of the waveguide structure is used as a stop layer to complete the preparation of the silicon dioxide cladding.
8. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 1, characterized in that, The deposited metallic copper comprises: Metallic copper with a thickness of 1μm to 2μm was deposited using the PVD process.
9. The method for preparing redundant patterns to improve the morphology of metal CMP according to claim 1, characterized in that, The preparation of the passivation layer includes: A silicon dioxide passivation layer with a thickness greater than 50 nm is deposited using a CVD process.
10. The method for preparing redundant patterns to improve the morphology of metal CMP according to any one of claims 1 to 9, characterized in that, The redundant pattern is made of silicon or silicon nitride, and the optical waveguide is a silicon nitride waveguide or a composite waveguide.