A method for preparing a vertical ordered array of silicon carbide hollow cylinders

Abstract

This invention discloses a method for preparing a vertical hollow cylindrical ordered array of silicon carbide. First, the silicon carbide wafer is cleaned using ultrasonic and plasma methods. Simultaneously, a suspension of 1 µm polystyrene (PS) spheres is prepared and the silicon carbide wafer is cleaned and dried. The PS spheres are then transferred to the cleaned silicon carbide wafer surface to form a monolayer of closely packed PS colloid. The silicon carbide wafer coated with the monolayer PS colloid is then subjected to reactive ion etching using O2 gas. The resulting product is further subjected to reactive ion etching using SF6 gas. The etched sample is then subjected to dichloromethane-assisted ultrasonic cleaning and dried. The resulting silicon carbide substrate is observed under a scanning electron microscope to obtain images of the nanostructure. This preparation method allows for flexible adjustment of experimental parameters to control the size, period, and wall thickness of the structure. Silicon carbide wafers are used as the main material, and the substrate surface exhibits a vertical hollow cylindrical ordered array structure.

Description

Technical Field

[0001] This invention relates to silicon carbide wafer etching technology, and more particularly to a method for preparing a vertical hollow cylindrical ordered array of silicon carbide. Background Technology

[0002] Silicon carbide (SiC) is a core material for third-generation wide-bandgap semiconductors, possessing superior properties such as high voltage resistance, high temperature resistance, low loss, and high thermal conductivity, surpassing traditional silicon-based materials in all aspects. It is a crucial cornerstone supporting high-end manufacturing and energy transformation. It is widely used in new energy vehicle electric drives, photovoltaic inverters, smart grids, communications, and aerospace, significantly improving energy conversion efficiency, reducing equipment losses and size, and contributing to the quality and efficiency improvement of the new energy industry. SiC possesses irreplaceable advantages in ultra-high voltage power transmission and extreme environment devices. Strategically, SiC is an important carrier for achieving the "dual carbon" goal and a core track in global semiconductor technology competition. Breaking through its technological and industrial chain bottlenecks is of profound significance for ensuring my country's industrial security and promoting the construction of a science and technology powerhouse.

[0003] However, silicon carbide has strong covalent bonds, extremely high hardness, and high brittleness, making it extremely difficult to process. Machining easily produces subsurface damage, microcracks, and edge chipping, and causes severe wear on cutting tools. Therefore, achieving nanoscale precision structures requires strict control of process parameters, which ordinary equipment cannot meet, resulting in low processing efficiency and high costs, severely restricting the fabrication of high-precision devices.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a method for preparing ordered arrays of silicon carbide vertical hollow cylinders to solve the aforementioned technical problems in the prior art.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A method for fabricating ordered arrays of silicon carbide vertical hollow cylinders includes the following steps:

[0008] Step 1. First, perform ultrasonic and plasma cleaning on the silicon carbide wafer, and at the same time prepare a suspension of 1 µm polystyrene (PS) spheres. After the silicon carbide wafer is cleaned and dried, it is ready for use.

[0009] Step 2. Transfer the PS balls to the cleaned silicon carbide wafer surface to form a single layer of close-packed PS colloid, for later use;

[0010] Step 3. Perform reactive ion etching on the silicon carbide wafer coated with a single layer of PS colloid;

[0011] Step 4. Further reactive ion etching is performed on the product obtained in Step 3;

[0012] Step 5. Perform dichloromethane-assisted ultrasonic cleaning on the etched sample and then dry it;

[0013] Step 6. Observe the silicon carbide substrate after the experiment under a scanning electron microscope to obtain images of the nanostructure.

[0014] Compared with existing technologies, the method for preparing a vertical hollow cylindrical ordered array of silicon carbide provided by this invention involves depositing polystyrene (PS) spheres on a silicon carbide wafer and etching it in multiple steps using a reactive ion etching machine to form the final substrate. Experimental parameters can be flexibly changed to control the size, period, wall thickness, etc. of the structure. Silicon carbide wafers are used as the main material, and the substrate surface exhibits a vertical hollow cylindrical ordered array structure. Attached Figure Description

[0015] Figure 1 This is a field emission scanning electron microscope image of the silicon carbide vertical hollow cylindrical ordered array substrate prepared in the embodiment of the present invention;

[0016] Figure 2 This is a schematic flowchart illustrating a method for preparing a silicon carbide vertical hollow cylindrical ordered array, as provided in this embodiment of the invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0018] First, the following explanations are provided for the terms that may be used in this article:

[0019] The terms “including,” “contains,” “comprising,” “having,” or other similar semantic descriptions shall be interpreted as non-exclusive inclusion.

[0020] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0021] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0022] like Figure 1 As shown, a method for fabricating a silicon carbide vertical hollow cylindrical ordered array includes the following steps:

[0023] Step 1. First, perform ultrasonic and plasma cleaning on the silicon carbide wafer, and at the same time prepare a suspension of 1 µm polystyrene (PS) spheres. After the silicon carbide wafer is cleaned and dried, it is ready for use.

[0024] Step 2. Transfer the PS balls to the cleaned silicon carbide wafer surface to form a single layer of close-packed PS colloid, for later use;

[0025] Step 3. Perform reactive ion etching on the silicon carbide wafer coated with a single layer of PS colloid;

[0026] Step 4. Further reactive ion etching is performed on the product obtained in Step 3;

[0027] Step 5. Perform dichloromethane-assisted ultrasonic cleaning on the etched sample and then dry it;

[0028] Step 6. Observe the silicon carbide substrate after the experiment under a scanning electron microscope to obtain images of the nanostructure.

[0029] In step 1, the 1 µm PS spheres used are the initial mask, which are then used as the final mask after reactive ion etching.

[0030] In step 3, the gas used for reactive ion etching is O2 at 20 sccm, the etching time is 280 s, and the etching power is 200 W.

[0031] In step 4, the gas used for reactive ion etching is SF6 at 80 sccm, the etching time is 50 s, and the etching power is 300 W.

[0032] A substrate with an ordered array of vertical hollow cylindrical silicon carbide was obtained.

[0033] In summary, the present invention provides a method for preparing a vertical hollow cylindrical ordered array of silicon carbide: Step 1. First, the silicon carbide wafer is cleaned by ultrasonic and plasma treatment, while a suspension of 1 µm polystyrene (PS) spheres is prepared. After the silicon carbide wafer is cleaned and dried, it is ready for use. Step 2. The PS spheres are transferred to the surface of the cleaned silicon carbide wafer to form a monolayer of closely packed PS colloid. Step 3. The silicon carbide wafer coated with the monolayer PS colloid is subjected to reactive ion etching using O2 gas. Step 4. The product obtained in Step 3 is further subjected to reactive ion etching using SF6 gas. Step 5. The etched sample is cleaned by ultrasonic treatment with dichloromethane assistance and then dried. Step 6. The silicon carbide substrate after the experiment is observed under a scanning electron microscope to obtain an image of the nanostructure.

[0034] The preparation method of this invention can flexibly change experimental parameters to control the size, period, wall thickness, etc. of the structure. It uses silicon carbide wafers as the main material, and the substrate surface has a vertical hollow cylindrical ordered array structure.

[0035] In this invention, mask-assisted reactive ion etching is used to prepare nanostructures on the surface of silicon carbide. This preparation method is simple, inexpensive, flexible, and clean, and the size, period, wall thickness, etc. of the structure can be adjusted according to different needs.

[0036] This invention addresses the shortcomings of existing preparation technologies, such as cumbersome steps and high process requirements, and provides a method for manufacturing silicon carbide nanosubstrates. This method is simple, inexpensive, flexible, and clean, using silicon carbide wafers as the main material, and the substrate surface is a vertical hollow cylindrical ordered array.

[0037] To more clearly demonstrate the technical solution and its effects provided by the present invention, the following detailed description of the method for preparing a silicon carbide vertical hollow cylindrical ordered array provided by the present invention is based on specific embodiments.

[0038] This invention proposes a method for fabricating three-dimensional nano-substrates on silicon carbide substrates using a single-layer colloidal crystal template as a mask and employing reactive ion etching. Substrates prepared using this method allow for flexible control of structural dimensions, periods, and wall thicknesses by simply altering experimental conditions. This fabrication method is simple, inexpensive, flexible, and clean, and the substrates can be widely applied in core fields such as new energy vehicles and smart grids. It can optimize the interface and heat dissipation characteristics of power devices, reduce conduction losses, and improve the devices' high-temperature and high-voltage resistance, making it suitable for high-voltage, high-frequency scenarios such as vehicle electric drives, charging piles, grid converters, and energy storage inverters. It can also be used for grid current and temperature sensing, contributing to the efficient and stable operation of energy systems.

[0039] like Figure 2As shown in the example, the preparation steps of the ordered array of silicon carbide vertical hollow cylinders are described in detail. The experimental materials and equipment include: silicon carbide wafers, 1 µm polystyrene microspheres, reactive ion etching machine, ultrasonic cleaner, plasma cleaner, ultrapure water system, O2 gas, SF6 gas, and dichloromethane (AR).

[0040] The experimental steps are as follows:

[0041] (1) First, perform ultrasonic and plasma cleaning on the silicon carbide wafer to ensure that the substrate surface is clean. At the same time, prepare a suspension of 1 µm polystyrene (PS) spheres and set them aside after the silicon carbide wafer has been cleaned and dried.

[0042] (2) Use the gas / liquid interface self-assembly method to transfer PS balls to the cleaned silicon carbide wafer surface to form a single layer of close-packed PS colloid, and let it dry naturally for later use.

[0043] (3) The silicon carbide wafer covered with a single layer of PS colloid was subjected to reactive ion etching. The gas used was O2 at 20 sccm, the etching time was 280 s, and the etching power was 200 W.

[0044] (4) Further reactive ion etching was performed using SF6 at 80 sccm, with an etching time of 50 s and an etching power of 300 W.

[0045] (5) Perform ultrasonic cleaning with dichloromethane on the etched sample to ensure that the PS balls remaining on the substrate surface are completely removed. After drying, the sample is the prepared sample.

[0046] (6) The silicon carbide substrate after the experiment was observed under a scanning electron microscope to obtain images of the nanostructure, such as... Figure 1 As shown.

[0047] In summary, Figure 1 In the image, a vertical hollow cylindrical ordered array structure of silicon carbide with a period of 1 µm is shown. As can be seen from the image, the structure consists of cylinders that are enclosed by vertical hollow cylinders and are slightly higher than the base plane.

[0048] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for preparing a vertical hollow cylindrical ordered array of silicon carbide, characterized in that, Includes the following steps: Step 1. First, perform ultrasonic and plasma cleaning on the silicon carbide wafer, and at the same time prepare a suspension of 1 µm polystyrene (PS) spheres. After the silicon carbide wafer is cleaned and dried, it is ready for use. Step 2. Transfer the PS balls to the cleaned silicon carbide wafer surface to form a single layer of close-packed PS colloid, for later use; Step 3. Perform reactive ion etching on the silicon carbide wafer coated with a single layer of PS colloid; Step 4. Further reactive ion etching is performed on the product obtained in Step 3; Step 5. Perform dichloromethane-assisted ultrasonic cleaning on the etched sample and then dry it; Step 6. Observe the silicon carbide substrate after the experiment under a scanning electron microscope to obtain images of the nanostructure.

2. The method for preparing a silicon carbide vertical hollow cylindrical ordered array according to claim 1, characterized in that, In step 1, the 1 µm PS spheres used are the initial mask, which are then used as the final mask after reactive ion etching.

3. The method for preparing a silicon carbide vertical hollow cylindrical ordered array according to claim 1, characterized in that, In step 3, the gas used for reactive ion etching is O2 at 20 sccm, the etching time is 280 s, and the etching power is 200 W.

4. The method for preparing a silicon carbide vertical hollow cylindrical ordered array according to claim 1, characterized in that, In step 4, the gas used for reactive ion etching is SF6 at 80 sccm, the etching time is 50 s, and the etching power is 300 W.

5. The method for preparing a silicon carbide vertical hollow cylindrical ordered array according to any one of claims 1-4, characterized in that, A substrate with an ordered array of vertical hollow cylindrical silicon carbide was obtained.

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