Wafer test path planning method, device, probe station, equipment and medium

Abstract

The application relates to a wafer test path planning method, device, probe station, equipment and medium. The wafer test path planning method comprises the following steps: acquiring coordinate information of each to-be-tested point on a wafer; determining a first test point based on the coordinate information of each to-be-tested point; taking the first test point as a test starting point, determining a next test point one by one, and generating a test path of each to-be-tested point; wherein the next test point is determined by selecting the next test point based on the coordinate difference value of the current test point and each untested point in the cutting direction. The total length of the test path is shortened, the risk of particle pollution caused by long path and vibration accumulation is reduced during the test process, the risk of wafer rework cleaning due to particle pollution is reduced, and the wafer delivery efficiency and overall manufacturing yield are improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method, apparatus, probe station, device and medium for planning wafer test paths. Background Technology

[0002] Wafer Acceptance Test (WAT) is a crucial step in the semiconductor manufacturing process. It assesses the stability and yield of the manufacturing process by performing electrical measurements on test keys on the wafer. During the test, the probes on the probe card must physically contact the metal bonding pads on the wafer surface to establish an electrical connection.

[0003] However, during the probe's insertion and withdrawal processes, it inevitably scrapes the surface of the metal solder joints, generating tiny metal shavings. These shavings may adhere to and accumulate on the probe tip. As testing continues, these accumulated shavings may detach during probe movement or subsequent insertions, falling onto the wafer surface and forming particulate contamination. When particulate contamination exceeds a certain limit, it directly affects the wafer's yield. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, probe station, equipment, and medium for planning wafer test paths to address the problems in the existing technology.

[0005] In a first aspect, this application provides a method for planning wafer test paths, including:

[0006] Obtain the coordinate information of each test point on the wafer;

[0007] Based on the coordinate information of each of the test points, the first test point is determined;

[0008] Starting from the first test point, determine the next test point one by one and generate the test path for each of the test points.

[0009] The step of determining the next test point includes: selecting the next test point based on the coordinate difference between the current test point and each untested point along the cutting path.

[0010] In one embodiment, selecting the next test point based on the coordinate difference between the current test point and each untested point along the cutting path includes:

[0011] Calculate the first difference between the current test point and each of the untested points on the first coordinate axis, and the second difference between the current test point and each of the untested points on the second coordinate axis; wherein, the first difference and the second difference are absolute values;

[0012] Select the untested point with the smallest first difference as the first candidate point set;

[0013] Select the untested points with the smallest second difference as the second candidate point set;

[0014] The next test point is selected based on the first candidate point set and the second candidate point set.

[0015] In one embodiment, selecting the next test point based on the first candidate point set and the second candidate point set includes:

[0016] If the second difference corresponding to the second candidate point set is less than half of the first difference corresponding to the first candidate point set, then the point with the smallest difference on the first coordinate axis is selected from the second candidate point set as the next test point.

[0017] Otherwise, from the first set of candidate points, select the point with the smallest difference on the second coordinate axis as the next test point.

[0018] In one embodiment, obtaining the coordinate information of each test point on the wafer includes:

[0019] A coordinate system is established with the center of the wafer as the origin, the dicing direction of the wafer as the first coordinate axis, and the direction perpendicular to the dicing direction as the second coordinate axis.

[0020] Obtain the position coordinates of each test point in the coordinate system, and use them as the coordinate information of each test point.

[0021] In one embodiment, determining the first test point includes:

[0022] The test point is the point in the target quadrant of the coordinate system whose absolute value of coordinates on the first coordinate axis and / or the second coordinate axis is the largest or smallest; wherein the target quadrant is any one of the first quadrant, the second quadrant, the third quadrant, or the fourth quadrant.

[0023] In one embodiment, determining the first test point based on the coordinate information of each of the test points includes:

[0024] Compare the coordinate values ​​of each test point on the first coordinate axis, and determine the point with the smallest coordinate value on the first coordinate axis as the first test point;

[0025] If multiple test points have the same and minimum coordinate values ​​on the first coordinate axis, then the coordinate values ​​of the multiple test points on the second coordinate axis are compared, and the point with the minimum coordinate value on the second coordinate axis is determined as the first test point.

[0026] Secondly, this application provides a wafer test path planning apparatus, comprising:

[0027] The coordinate acquisition module is used to acquire the coordinate information of each test point on the wafer;

[0028] The starting point determination module is used to determine the first test point based on the coordinate information of each of the test points;

[0029] The path generation module is used to determine the next test point one by one, taking the first test point as the test starting point, and generate test paths for each of the test points.

[0030] The path generation module is used to select the next test point based on the coordinate difference between the current test point and each untested point along the cutting path direction.

[0031] Thirdly, this application provides a probe station, comprising:

[0032] A support stage, used to hold the wafer to be tested;

[0033] A probe card is used to perform electrical tests on the test points on the wafer;

[0034] The controller is configured to execute the wafer test path planning method as described in the first aspect to control the probe station to sequentially test each of the test points according to the test path generated by the wafer test path planning method.

[0035] Fourthly, this application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the wafer test path planning method described in the first aspect.

[0036] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the wafer test path planning method described in the first aspect.

[0037] The wafer test path planning method, apparatus, probe station, equipment, and medium of this application have the following unexpected effects: By establishing a coordinate system with the dicing kerf as a reference, and combining the selection rules of the first test point with the search for the next test point based on the dicing kerf direction, the total length of the test path is shortened. Since the test path length is positively correlated with the probability of aluminum chip fallout from the probe, the risk of particle contamination caused by the length of the path and the accumulation of vibration during the test process is reduced, thereby reducing the risk of wafers needing to be reworked and cleaned due to particle contamination, and improving wafer shipment efficiency and overall manufacturing yield. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart of a wafer test path planning method provided in an exemplary embodiment of this application;

[0040] Figure 2 This is a flowchart illustrating the process of obtaining the coordinate information of the test point in an exemplary embodiment of this application;

[0041] Figure 3 This is a flowchart for determining a first test point provided in an exemplary embodiment of this application;

[0042] Figure 4 This is a flowchart for determining the next test point provided in an exemplary embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the wafer test path generated in an exemplary embodiment of this application;

[0044] Figure 6 This is a schematic diagram of the wafer testing path provided in related technologies;

[0045] Figure 7 This is a block diagram of a wafer test path planning apparatus provided in an exemplary embodiment of this application;

[0046] Figure 8 This is a block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] In the relevant solutions, the main approach to addressing metal particle contamination during cell testing is to conduct post-processing inspections and then pull the contaminated wafers back to the front-end process for wet cleaning. While this method effectively removes detached metal particles, it suffers from high scheduling costs, increased process costs due to the water washing step, and delays wafer delivery caused by this post-processing remedial mechanism, thus impacting overall production efficiency.

[0050] The wafer test path planning method provided in this application embodiment can be applied to, for example, Figure 8 The application environment is shown below. The application environment may include a computer device, which may be a server, and its internal structure diagram may be as follows. Figure 8 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores data related to test path planning. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a wafer test path planning method. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0051] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0052] In one exemplary embodiment, such as Figure 1 As shown, a method for planning wafer test paths is provided, which can be applied to... Figure 8 The following steps are used as an example of computer equipment, including steps S101 to S103.

[0053] Step S101: Obtain the coordinate information of each test point on the wafer.

[0054] The computer equipment can establish a coordinate system with the center of the wafer as the origin and obtain the position coordinates of each test point in the coordinate system. In this embodiment, at least one coordinate axis is established with the center of the wafer as the origin and according to the extension direction of the dicing track. In this way, the coordinate difference of the test point along the dicing track direction can be obtained based on the coordinate information of the test point, which helps to reduce the computational complexity of planning the test path.

[0055] Step S102: Determine the first test point based on the coordinate information of each test point.

[0056] This involves determining the distribution of test points in each quadrant based on their coordinate information, and identifying the first test point in quadrants with sparse or dense distribution. For example, the test point with the largest or smallest absolute value on a certain coordinate axis within the target quadrant can be selected as the first test point. Starting testing from the edge of the wafer allows subsequent paths to proceed orderly along the dicing direction, avoiding unnecessary backtracking caused by starting testing from the middle of the wafer. This reduces the complexity of planning the test path and shortens its total length.

[0057] Step S103: Using the first test point as the starting point, determine the next test point one by one, and generate the test path for each test point. Determining the next test point includes: selecting the next test point based on the coordinate difference between the current test point and each untested point along the cutting path direction.

[0058] In this embodiment, the next test point is selected based on the coordinate difference between the current test point and each untested point along the cutting path direction. The next test point can be selected as a point closer along the extension direction of the cutting path to reduce the total length of the generated test path.

[0059] Alternatively, in other embodiments, the straight-line distance between the current test point and each untested point can be calculated, and the untested point with the smallest straight-line distance can be selected as the next test point.

[0060] In the above-mentioned wafer test path planning method, the coordinate information of each test point on the wafer is obtained; based on the coordinate information of each test point, the first test point is determined; using the first test point as the test starting point, the next test point is determined one by one, generating the test path for each test point. Specifically, determining the next test point includes: selecting the next test point based on the coordinate difference between the current test point and each untested point along the dicing direction; by establishing a coordinate system with the dicing as a reference, and combining the selection rules of the first test point with the search for the next test point based on the dicing direction, the total length of the test path is shortened. Since the test path length is positively correlated with the probability of probe aluminum chip shedding, the risk of particle contamination caused by lengthy paths and vibration accumulation during testing is reduced, thereby reducing the risk of wafer rework and cleaning due to particle contamination, and improving wafer shipment efficiency and overall manufacturing yield.

[0061] In some embodiments, refer to Figure 2 As shown, step S101 obtains the coordinate information of each test point on the wafer, including steps S1011-S1012.

[0062] Step S1011: Establish a coordinate system with the center of the wafer as the origin, the dicing direction of the wafer as the first coordinate axis (Y-axis), and the direction perpendicular to the dicing direction as the second coordinate axis (X-axis).

[0063] Step S1012: Obtain the position coordinates of each test point in the coordinate system, as the coordinate information of each test point.

[0064] In this embodiment, by directly defining the wafer's dicing direction as the X and Y axes, the coordinate information of all test points is based on the wafer's dicing direction. This coordinate system is independent of the actual placement angle of the wafer on the probe station, ensuring consistency in path planning and providing an accurate coordinate basis for subsequent path search based on dicing direction priority. In subsequent steps, the coordinate difference along the dicing direction is the difference along the Y-axis, and the coordinate difference perpendicular to the dicing direction is the difference along the X-axis, reducing the complexity of determining the next test point one by one.

[0065] It is understandable that wafer dicing channels are typically distributed in a regular grid pattern (including both vertical and horizontal sets). Therefore, one set can be defined as the X-axis direction and the other as the Y-axis direction, without any coordinate transformation. The origin of the coordinate system can be set at any reference point, and the coordinate system direction is fixed to the wafer's own structure, independent of the actual placement angle of the wafer on the probe station.

[0066] In some embodiments, step S102, determining the first test point, includes: taking the test point located in the target quadrant of the coordinate system, which has the largest or smallest absolute value of the coordinate values ​​on the first coordinate axis and / or the second coordinate axis, as the first test point; wherein the target quadrant is any one of the first quadrant, the second quadrant, the third quadrant, or the fourth quadrant.

[0067] For example, when the target quadrant is set to the third quadrant, the test points within the area enclosed by the negative half-axis of the X-axis and the negative half-axis of the Y-axis are selected as candidates. The point with the largest absolute value of the Y-axis coordinate within the target quadrant (i.e., the point with the smallest Y-value, as it is negative) can be selected as the first test point; or the point with the largest absolute value of the X-axis coordinate (i.e., the point with the smallest X-value) can be selected; or, by comprehensively considering the coordinate values ​​of the X-axis and Y-axis, the point closest to the corner of the edge within the target quadrant can be selected.

[0068] The selection of the target quadrant can be flexibly configured based on the actual distribution of the test points on the wafer or historical data.

[0069] In some embodiments, refer to Figure 3 As shown, step S102 determines the first test point based on the coordinate information of each test point, including steps S1021-S1022.

[0070] Step S1021: Compare the coordinate values ​​of each test point on the first coordinate axis, and determine the point with the smallest coordinate value on the first coordinate axis as the first test point.

[0071] Since the origin of the coordinate system is located at the center of the wafer, the test point with the smallest Y-axis coordinate value is located at the farthest point along the negative Y-axis in the wafer plane, i.e., the lower edge region of the wafer. Thus, the test point closest to the lower edge of the wafer is selected from all test points, and the first test point is determined from these. The dicing trace extends in the same direction as the Y-axis; selecting the test point with the smallest Y-axis coordinate value as the starting point maximizes the progress along the dicing trace's extension direction.

[0072] Step S1022: If multiple test points have the same and minimum coordinate values ​​on the first coordinate axis, compare the coordinate values ​​of the multiple test points on the second coordinate axis, and determine the point with the minimum coordinate value on the second coordinate axis as the first test point.

[0073] It is understandable that since there may be multiple test points arranged side by side along the X-axis on the wafer, and there are multiple test points with the smallest coordinate value on the first coordinate axis, then among the multiple test points with the smallest Y value on the first coordinate axis, the point with the smallest X value is further selected, and the test point near the lower left edge in the third quadrant is selected as the first test point.

[0074] For example, there are three test points A (-50, -100), B (-30, -100), and C (-50, -80) in the third quadrant of the wafer. In step S1021, the Y-axis coordinates are compared. The Y-values ​​of points A and B are both -100, which is the minimum among all test points. Points A and B are thus selected as candidates. The X-axis coordinates of points A and B are then compared. The X-value of point A is -50, and the X-value of point B is -30. Since -50 is less than -30, point A is determined as the first test point.

[0075] Verification has shown that selecting the first test point from the third quadrant minimizes the total test path generated by subsequent path planning. The path starts from the lower left edge of the wafer and proceeds along the dicing direction, reducing long-distance back-and-forth movement across quadrants and thus suppressing the risk of aluminum chip shedding due to excessively long test paths.

[0076] It should be noted that the above embodiments are merely illustrative. In practical applications, points at the corresponding corners of the first, second, or fourth quadrants can be selected as the first test points based on the actual distribution of the test points on the wafer. The selection logic is similar to that in the above embodiments, only requiring adjustment of the comparison object (maximum or minimum value).

[0077] In some embodiments, refer to Figure 4 As shown, step S103 selects the next test point based on the coordinate difference between the current test point and each untested point along the cutting path direction, including steps S1031-S1034.

[0078] Step S1031: Calculate the first difference between the current test point and each untested point on the first coordinate axis, and the second difference between the current test point and each untested point on the second coordinate axis; wherein, the first difference and the second difference are absolute values.

[0079] In this embodiment, the absolute value of the coordinate difference between the current test point and each untested point on the first coordinate axis (Y-axis, i.e., along the cutting path direction) is calculated as the first difference (denoted as △Y); at the same time, the absolute value of the coordinate difference between the current test point and each untested point on the second coordinate axis (X-axis, perpendicular to the cutting path direction) is calculated as the second difference (denoted as △X).

[0080] It is understood that this embodiment uses absolute values ​​for calculation because the path length depends only on the actual distance between two points and is independent of the positive or negative direction of the coordinates. Regardless of whether the untested point is located in the positive or negative direction of the current test point, its movement distance is determined by the absolute value of the difference. For example, if the current test point coordinates are (30, 50), and there is an untested point with coordinates (30, -20), the difference between the two on the Y-axis is |50-(-20)|=70, meaning the probe station needs to move 70 units along the Y-axis.

[0081] Step S1032: Select the untested points with the smallest first difference as the first candidate point set.

[0082] In this embodiment, all first differences (ΔY) between the current test point and each untested point are compared, and one or more untested points with the smallest difference are selected to form a first candidate point set (denoted as set Y). The points in the first candidate point set are the test points that are closest to the current test point along the cutting path (Y-axis) direction among all the current untested points.

[0083] For example, if the ΔY values ​​of the current test point P and the five untested points A, B, C, D, and E are 10, 10, 25, 40, and 40 respectively, then the minimum value of ΔY is 10. Since the ΔY values ​​of points A and B are both 10, the set Y = {A, B}.

[0084] Step S1033: Select the untested points with the smallest second difference as the second candidate point set.

[0085] In this embodiment, all second differences (ΔX) between the current test point and each untested point are compared, and one or more untested points with the smallest difference are selected to form a second candidate point set (denoted as set X). The points in the second candidate point set are the test points that are closest to the current test point along the second cutting path (X-axis) direction among all the current untested points.

[0086] Step S1034: Select the next test point based on the first candidate point set and the second candidate point set.

[0087] In this embodiment, when selecting the next test point, it is preferable to select the test point that is closest along the cutting path direction (Y-axis). The direction will only be switched to test the significantly closer test point if there is a significantly closer test point along the direction perpendicular to the cutting path (X-axis).

[0088] In some embodiments, step S1034 selects the next test point based on the first candidate point set and the second candidate point set, including: if the second difference corresponding to the second candidate point set is less than half of the first difference corresponding to the first candidate point set, then select the point with the smallest difference on the first coordinate axis from the second candidate point set as the next test point; otherwise, select the point with the smallest difference on the second coordinate axis from the first candidate point set as the next test point.

[0089] In this embodiment, it is determined whether the minimum second difference (denoted as △Xmin) corresponding to the second candidate point set (set X) is less than half of the minimum first difference (denoted as △Ymin) corresponding to the first candidate point set (set Y).

[0090] If △Xmin < 1 / 2△Ymin, it indicates that there is a significantly closer untested point in the direction perpendicular to the cutting path. In this case, switching the direction to test the significantly closer untested point can compensate for the increased path cost caused by deviating from the cutting path. Then, from the second candidate point set (set X), the point with the smallest difference on the first coordinate axis (Y-axis) is selected as the next test point.

[0091] Otherwise, if △Xmin ≥ 1 / 2△Ymin, it means that the nearest point in the vertical direction is not significantly closer to the nearest point in the cutting direction. In this case, maintaining the principle of prioritizing the cutting direction, the point with the smallest difference on the second coordinate axis (X-axis) is selected from the first candidate point set (set Y) as the next test point.

[0092] The second difference, which is less than half of the first difference, is the empirically optimal value determined after analyzing a large amount of measured data. This threshold balances the principles of advancing along the cutting path and flexibly switching to the nearest point. If the threshold is too large, it will cause premature deviation from the cutting path; if the threshold is too small, it will basically ignore the nearest point in the vertical direction, making the path too rigid, neither of which is conducive to minimizing the overall path.

[0093] Figure 5 A schematic diagram of the wafer test path generated in this embodiment is shown. Figure 6 A schematic diagram of the wafer test path generated by the relevant technology is shown. (Refer to...) Figure 5 , Figure 6 In this embodiment, when selecting the next test point, it does not simply choose the test point closest to the current point, but prioritizes moving along the dicing direction. It only switches directions when there is an untested point that is significantly closer in the direction perpendicular to the dicing direction. This ensures that the test path follows the dicing direction as a whole, reducing mechanical vibration and path redundancy caused by frequent and irregular turning of the probe station during testing. This suppresses the risk of aluminum chip shedding due to excessively long test paths, reduces the frequency of wafer rework and cleaning, directly reduces manufacturing costs, avoids delivery delays caused by rework, improves the stability of wafer shipment yield, and reduces the risks caused by particle problems.

[0094] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0095] Based on the same inventive concept, this application also provides a wafer test path planning apparatus for implementing the wafer electrical test path planning method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations of one or more wafer test path planning apparatus embodiments provided below can be found in the limitations of the wafer electrical test path planning method described above, and will not be repeated here.

[0096] According to an exemplary embodiment, this embodiment provides a wafer test path planning apparatus, referring to... Figure 7 As shown, the wafer test path planning device includes a coordinate acquisition module 201, a starting point determination module 202, and a path generation module 203.

[0097] The coordinate acquisition module 201 is used to acquire the coordinate information of each test point on the wafer.

[0098] The starting point determination module 202 is used to determine the first test point based on the coordinate information of each test point.

[0099] The path generation module 203 is used to determine the next test point one by one, taking the first test point as the test starting point, and generate the test path for each test point; wherein, the path generation module is used to select the next test point based on the coordinate difference between the current test point and each untested point along the cutting path direction.

[0100] In some embodiments, the path generation module 203 is used to calculate a first difference between the current test point and each untested point on the first coordinate axis, and a second difference between the current test point and each untested point on the second coordinate axis; wherein the first difference and the second difference are both absolute values; the untested point with the smallest first difference is selected as the first candidate point set; the untested point with the smallest second difference is selected as the second candidate point set; and the next test point is selected based on the first candidate point set and the second candidate point set.

[0101] In some embodiments, the path generation module 203 is configured to select the point with the smallest difference on the first coordinate axis from the second candidate point set as the next test point if the second difference corresponding to the second candidate point set is less than half of the first difference corresponding to the first candidate point set; otherwise, select the point with the smallest difference on the second coordinate axis from the first candidate point set as the next test point.

[0102] In some embodiments, the coordinate acquisition module 201 is used to establish a coordinate system with the center of the wafer as the origin, the dicing direction of the wafer as the first coordinate axis, and the direction perpendicular to the dicing direction as the second coordinate axis; and to acquire the position coordinates of each test point in the coordinate system as the coordinate information of each test point.

[0103] In some embodiments, the starting point determination module 202 is used to select the test point located in the target quadrant of the coordinate system, which has the largest or smallest absolute value of the coordinate values ​​on the first coordinate axis and / or the second coordinate axis, as the first test point; wherein the target quadrant is any one of the first quadrant, the second quadrant, the third quadrant, or the fourth quadrant.

[0104] In some embodiments, the starting point determination module 202 is used to compare the coordinate values ​​of each test point on the first coordinate axis and determine the point with the smallest coordinate value on the first coordinate axis as the first test point; if there are multiple test points with the same coordinate value on the first coordinate axis and all of them are the smallest, then the coordinate values ​​of the multiple test points on the second coordinate axis are compared and the point with the smallest coordinate value on the second coordinate axis is determined as the first test point.

[0105] Each module in the aforementioned wafer test path planning device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0106] In one exemplary embodiment, a probe station is provided, the probe station including a carrier stage, a probe card, and a controller; the carrier stage is used to carry a wafer to be tested; the probe card is used to perform electrical tests on the test points on the wafer; the controller is configured to execute a wafer test path planning method as described above, so as to control the probe station to sequentially test each test point according to the test path generated by the wafer test path planning method.

[0107] In one exemplary embodiment, a computer device is provided, referring to Figure 8 As shown, the computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above-described embodiments of the path planning method for wafer electrical testing.

[0108] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above embodiments of the path planning method for wafer electrical testing.

[0109] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the above embodiments of the path planning method for wafer electrical testing.

[0110] It should be noted that the information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data that have been authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0111] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0112] The wafer test path planning method, apparatus, probe station, equipment, and medium of this application have the following unexpected effects: By establishing a coordinate system with the dicing kerf as a reference, and combining the selection rules of the first test point with the search for the next test point based on the dicing kerf direction, the total length of the test path is shortened. Since the test path length is positively correlated with the probability of aluminum chip fallout from the probe, the risk of particle contamination caused by the length of the path and the accumulation of vibration during the test process is reduced, thereby reducing the risk of wafers needing to be reworked and cleaned due to particle contamination, and improving wafer shipment efficiency and overall manufacturing yield.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for planning wafer test paths, characterized in that, include: A coordinate system is established with the center of the wafer as the origin, the dicing direction of the wafer as the first coordinate axis, and the direction perpendicular to the dicing direction as the second coordinate axis. Obtain the position coordinates of each test point in the coordinate system, and use them as the coordinate information of each test point; Based on the coordinate information of each of the test points, the first test point is determined; Starting from the first test point, determine the next test point one by one and generate the test path for each of the test points. The determination of the next test point includes: calculating a first difference between the current test point and each untested point on a first coordinate axis, and a second difference between the current test point and each untested point on a second coordinate axis; wherein the first difference and the second difference are absolute values; selecting the untested point with the smallest first difference as a first candidate point set; selecting the untested point with the smallest second difference as a second candidate point set; and selecting the next test point based on the first candidate point set and the second candidate point set.

2. The wafer test path planning method as described in claim 1, characterized in that, Based on the first candidate point set and the second candidate point set, the next test point is selected, including: If the second difference corresponding to the second candidate point set is less than half of the first difference corresponding to the first candidate point set, then the point with the smallest difference on the first coordinate axis is selected from the second candidate point set as the next test point. Otherwise, from the first set of candidate points, select the point with the smallest difference on the second coordinate axis as the next test point.

3. The wafer test path planning method as described in claim 2, characterized in that, Determining the first test point includes: The test point is the point in the target quadrant of the coordinate system whose absolute value of coordinates on the first coordinate axis and / or the second coordinate axis is the largest or smallest; wherein the target quadrant is any one of the first quadrant, the second quadrant, the third quadrant, or the fourth quadrant.

4. The wafer test path planning method as described in claim 3, characterized in that, The step of determining the first test point based on the coordinate information of each of the test points includes: Compare the coordinate values ​​of each test point on the first coordinate axis, and determine the point with the smallest coordinate value on the first coordinate axis as the first test point; If multiple test points have the same and minimum coordinate values ​​on the first coordinate axis, then the coordinate values ​​of the multiple test points on the second coordinate axis are compared, and the point with the minimum coordinate value on the second coordinate axis is determined as the first test point.

5. A wafer test path planning device, characterized in that, include: The coordinate acquisition module is used to establish a coordinate system with the center of the wafer as the origin, the dicing direction of the wafer as the first coordinate axis, and the direction perpendicular to the dicing direction as the second coordinate axis. Obtain the position coordinates of each test point in the coordinate system, and use them as the coordinate information of each test point; The starting point determination module is used to determine the first test point based on the coordinate information of each of the test points; The path generation module is used to determine the next test point one by one, taking the first test point as the test starting point, and generate test paths for each of the test points. The path generation module is configured to: calculate a first difference between the current test point and each untested point on a first coordinate axis, and a second difference between the current test point and each untested point on a second coordinate axis; wherein the first difference and the second difference are absolute values; select the untested point with the smallest first difference as a first candidate point set; select the untested point with the smallest second difference as a second candidate point set; and select the next test point based on the first candidate point set and the second candidate point set.

6. A probe station, characterized in that, include: A support stage, used to hold the wafer to be tested; A probe card is used to perform electrical tests on the test points on the wafer; The controller is configured to execute the wafer test path planning method as described in any one of claims 1 to 4, to control the probe station to sequentially test each of the test points according to the test path generated by the wafer test path planning method.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the wafer test path planning method according to any one of claims 1 to 4.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the wafer test path planning method according to any one of claims 1 to 4.

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