Temporary bonding and debonding methods
By forming a specific layer structure on the wafer and performing edge trimming, combined with laser dissociation interface, the problem of wafer edge step chipping was solved, resulting in smaller peeling step chipping and defect-free subsequent processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-04-27
- Publication Date
- 2026-07-31
AI Technical Summary
During semiconductor manufacturing, when temporary carriers and wafers are debonded, step chips with large differences in step height are generated at the wafer edge, resulting in defects such as scratches, abrasions, over-etching, side etching, and surface particle contamination on the wafer surface in subsequent processes.
Specific layer structures are formed on the device wafer and the carrier wafer, respectively. After edge trimming, the interface between the energy release layer and the second bonding layer is debonded by laser dissociation, thereby reducing the stress and peeling steps at the wafer edges.
It significantly reduces the height and width of the spalling step chipping, avoids defects on the wafer surface in subsequent processes, and easily repairs the spalling step chipping through chemical mechanical polishing.
Smart Images
Figure CN122497328A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a temporary bonding and debonding method. Background Technology
[0002] In the process flow of heterogeneous integration of advanced packaged chips (2.5D chips) and three-dimensional integrated chips (3D chips), temporary bonding and debonding (TBDB) technology is usually used to connect the related processes on the front and back sides of the wafer. That is, a temporary carrier wafer is used to temporarily bond to the front side of the wafer to be processed. The temporary carrier wafer serves as a carrier for the back side processing of the wafer. After the back side process of the wafer to be processed is completed, the temporary carrier wafer and the wafer to be processed are separated by debonding technology to continue to complete the front side process of the wafer to be processed.
[0003] To obtain better TBDB results, refer to Figure 1 , Figure 1 This is a schematic diagram of the semiconductor structure after bonding a temporary carrier and a wafer to be processed in the prior art. Typically, the following five layers are formed sequentially on the temporary carrier 1: a first buffer layer 2, a laser release layer 3 (LRL), a second buffer layer 4, an absorber layer 5, and a first bonding layer 6; a second bonding layer 8 is formed on the wafer to be processed 7. The first buffer layer 2 and the second buffer layer 4 serve as stress buffers and transition layers; the laser release layer 3 serves as a debonding layer; the absorber layer 5 serves as a protective layer for the wafer to be processed 7 to absorb excess laser energy; and the first bonding layer 6 serves as a temporary bonding layer to complete a temporary bonding with the second bonding layer 8 on the wafer to be processed 7.
[0004] During the debonding process, the ideal dissociation interface is the interface between the laser release layer 3 and the second buffer layer 4. After the laser is perpendicularly irradiated to this interface from one side of the temporary carrier 1, the adhesion between the laser release layer 3 and the second buffer layer 4 gradually decreases until it disappears, causing the laser release layer 3 and the second buffer layer 4 to dissociate, thereby realizing the separation between the temporary carrier 1 and the wafer 7 to be processed.
[0005] However, in the actual bonding process, reference Figure 1The actual unbonding interface shown by the red dashed line is significantly weakened at the edges of the temporary carrier 1 and the wafer to be processed 7 due to the bonding wave being greatly weakened. Therefore, the bonding force between the edge regions of the first bonding layer 6 and the edge regions of the second bonding layer 8 is less than the bonding force between the middle regions of the first bonding layer 6 and the middle regions of the second bonding layer 8. Debonding typically occurs when the lower-energy interface is broken first. During debonding, the adhesion between the laser-emitting layer 3 and the second buffer layer 4 gradually decreases. When the adhesion between the laser-emitting layer 3 and the second buffer layer 4 is less than the adhesion between the middle region of the first bonding layer 6 and the middle region of the second bonding layer 8, the laser-emitting layer 3 near the middle region separates from the second buffer layer 4. However, since the adhesion between the laser-emitting layer 3 and the second buffer layer 4 is still much greater than the adhesion between the edge regions of the first bonding layer 6 and the second bonding layer 8 (i.e., the adhesion between the edge regions of the first bonding layer 6 and the second bonding layer 8 is much less than the adhesion between the laser-emitting layer 3 and the second buffer layer 4), the first bonding layer 6 and the second bonding layer 8 near the edge regions separate. This causes the three thin films—the second buffer layer 4, the absorption layer 5, and the first bonding layer 6—to peel off at the edge of the temporary carrier 1 and the wafer 7 to be processed. In other words, a step-like chipping occurs at the wafer edge, and this phenomenon will result in a large step height difference at the wafer edge. Step chipping with a large step height difference will become a potential source of defects in subsequent wet cleaning, chemical mechanical polishing and other processes. Potential defects include at least: scratches, abrasions, over-etching, side etching, and surface particle contamination of the wafer. Summary of the Invention
[0006] The purpose of this application is to provide a temporary bonding and debonding method to solve the problem that during the debonding process of temporary carriers and wafers to be processed, step chips with large step height differences are generated at the edge of the wafer. These step chips can easily cause defects such as scratches, abrasions, over-etching, side etching, and surface particle contamination on the wafer surface in subsequent wet cleaning, chemical mechanical polishing and other processes.
[0007] To address the aforementioned technical problems, this application provides a temporary bonding and debonding method, comprising:
[0008] A device wafer is provided, wherein a first buffer layer, an energy absorption layer and a first bonding layer are sequentially formed on the front side of the device wafer;
[0009] The first semiconductor structure after the formation of the first bonding layer is subjected to edge trimming.
[0010] A carrier wafer is provided, and a second buffer layer, an energy release layer and a second bonding layer are sequentially formed on the front side of the carrier wafer;
[0011] The second semiconductor structure, after the formation of the second bonding layer, is inverted on the first bonding layer, and the second bonding layer is bonded to the first bonding layer;
[0012] After the back-side process of the device wafer is completed, the first semiconductor structure and the second semiconductor structure are peeled off from the interface between the energy release layer and the second bonding layer and debonded.
[0013] Optionally, in the temporary bonding and debonding method, the first semiconductor structure after the formation of the first bonding layer is subjected to mechanical edge trimming.
[0014] Optionally, in the temporary bonding and debonding method, the first semiconductor structure after the formation of the first bonding layer is subjected to laser edge trimming.
[0015] Optionally, in the temporary bonding and debonding method, during the edge-cutting process of the first semiconductor structure after the formation of the first bonding layer, the edges of the first bonding layer, the energy absorption layer, the first buffer layer, and at least a portion of the thickness of the carrier wafer are circumferentially cut with the same preset width.
[0016] Optionally, in the temporary bonding and debonding method, the preset width is 1mm to 3mm.
[0017] Optionally, in the temporary bonding and debonding method, after the second bonding layer is bonded to the first bonding layer, the diameter of the first bonding layer is smaller than the diameter of the second bonding layer.
[0018] Optionally, in the temporary bonding and debonding method, after completing the back-side processing of the device wafer, the step of peeling the first semiconductor structure and the second semiconductor structure from the interface between the energy release layer and the second bonding layer and performing debonding processing includes:
[0019] After the back-side process of the device wafer is completed, a laser is used to vertically irradiate the interface between the energy release layer and the second bonding layer from the back side of the supporting wafer, so as to cause the interface between the energy release layer and the second bonding layer to fail until the energy release layer and the second bonding layer are dissociated.
[0020] Optionally, in the temporary bonding and debonding method, during the debonding process, the diameter of the focused spot is not greater than the diameter of the second bonding layer.
[0021] Optionally, in the temporary bonding and debonding method, the thickness of the first buffer layer and the thickness of the second buffer layer are both 500 angstroms to 1000 angstroms.
[0022] Optionally, in the temporary bonding and debonding method, the thickness of the energy absorption layer is 100 angstroms to 1000 angstroms.
[0023] Optionally, in the temporary bonding and debonding method, the materials of the first buffer layer, the second buffer layer, the first bonding layer, and the second bonding layer are all silicon dioxide.
[0024] In summary, this application provides a temporary bonding and debonding method. A second buffer layer, an energy release layer, and a second bonding layer are sequentially formed on the front side of a carrier wafer. The second bonding layer is then bonded to a first bonding layer on the device wafer after edge trimming. Finally, after completing the back-side processing of the device wafer, the second bonding layer and the energy release layer are dissociated, thereby debonding the device wafer and the carrier wafer. By setting the second bonding layer as an adjacent layer to the energy release layer, this application ensures that during debonding, step-like chipping at the wafer edge only occurs at the edge of the second bonding layer, significantly reducing the height of the peeling step-like chipping. Furthermore, before bonding the first and second bonding layers, the first semiconductor structure is trimmed, reducing the stress at the edge of the first semiconductor structure during debonding, thereby reducing the width of the peeling step-like chipping. Compared with the high and wide peeling step chipping caused by traditional debonding processes, the height and width of the peeling step chipping in this application are significantly reduced (the height of the peeling step chipping is reduced by at least the thickness of the energy absorption layer and one buffer layer). The peeling step chipping generated by debonding in this application is located at the edge of the second bonding layer at the top of the device wafer, so it can be easily repaired by CMP (chemical mechanical polishing) process, avoiding defects such as wafer surface scratches, abrasions, over-etching, side etching, and surface particle contamination in subsequent wet cleaning, chemical mechanical polishing and other processes. Attached Figure Description
[0025] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0026] Figure 1 This is a schematic diagram of the semiconductor structure after the temporary carrier and the wafer to be processed are bonded in the existing technology;
[0027] Figure 2 This is a flowchart of a temporary bonding and debonding method according to an embodiment of this application;
[0028] Figure 3 This is a schematic diagram of the first semiconductor structure after edge trimming according to an embodiment of this application.
[0029] Figure 4This is a schematic diagram of the second semiconductor structure according to an embodiment of this application;
[0030] Figure 5 This is a schematic diagram of the semiconductor structure after the first semiconductor structure and the second semiconductor structure are bonded together according to an embodiment of this application;
[0031] Figure 6 This is a schematic diagram of the semiconductor structure of the device wafer after debonding, according to an embodiment of this application.
[0032] The reference numerals in the attached figures are explained as follows:
[0033] 1-Temporary carrier, 2-First buffer layer, 3-Laser release layer, 4-Second buffer layer, 5-Absorption layer, 6-First bonding layer, 7-Wafer to be processed, 8-Second bonding layer;
[0034] 11-Device wafer, 12-First buffer layer, 13-Energy absorption layer, 14-First bonding layer;
[0035] 21-Carrier wafer, 22-Second buffer layer, 23-Energy release layer, 24-Second bonding layer. Detailed Implementation
[0036] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0037] This application provides a temporary bonding and unbonding method, referencing... Figure 2 , Figure 2 This is a flowchart of a temporary bonding and debonding method according to an embodiment of this application, the temporary bonding and debonding method comprising:
[0038] First, perform step S1: Refer to Figure 3 , Figure 3 This is a schematic diagram of the first semiconductor structure after edge trimming according to an embodiment of this application. A device wafer 11 is provided, and a first buffer layer 12, an energy absorption layer 13 and a first bonding layer 14 are sequentially formed on the front side of the device wafer 11.
[0039] In this embodiment, the thickness of the first buffer layer 12 is 500 angstroms to 2500 angstroms.
[0040] Preferably, the first buffer layer 12 is formed using a CVD process.
[0041] Furthermore, the thickness of the energy absorption layer 13 is 100 angstroms to 2000 angstroms.
[0042] In this embodiment, the energy absorption layer 13 is a metal film. The energy absorption layer 13 can be formed using a PVD process.
[0043] Preferably, the material of the first buffer layer 12 and the material of the first bonding layer 14 are both silicon dioxide.
[0044] In this embodiment, the first bonding layer 14 is formed using a CVD process.
[0045] Preferably, the thickness of the first bonding layer 14 is 1000 angstroms to 5000 angstroms.
[0046] Then, proceed to step S2: Continue to refer to Figure 3 The first semiconductor structure after the formation of the first bonding layer 14 is subjected to edge trimming.
[0047] In this embodiment, the first semiconductor structure after the formation of the first bonding layer 14 is subjected to mechanical edge trimming.
[0048] In other embodiments, the first semiconductor structure after the formation of the first bonding layer 14 is subjected to laser shaving.
[0049] Preferably, during the edge-cutting process of the first semiconductor structure after the formation of the first bonding layer 14, the edges of the first bonding layer 14, the energy absorption layer 13, the first buffer layer 12, and at least a portion of the thickness of the carrier wafer 11 are circumferentially cut with the same preset width.
[0050] Preferably, the preset width is 1mm to 3mm.
[0051] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the second semiconductor structure according to an embodiment of this application. A carrier wafer 21 is provided, and a second buffer layer 22, an energy release layer 23 and a second bonding layer 24 are sequentially formed on the front side of the carrier wafer 21.
[0052] Preferably, the thickness of the second buffer layer 22 is 500 angstroms to 2500 angstroms.
[0053] In this embodiment, the material of the second buffer layer 22 and the material of the second bonding layer 24 are both silicon dioxide.
[0054] Furthermore, the second buffer layer 22 and the second bonding layer 24 are formed using a CVD process.
[0055] Preferably, the thickness of the energy-releasing layer 23 is 100 angstroms to 2000 angstroms.
[0056] In this embodiment, the energy release layer 23 is a metal film layer. The energy release layer 23 can be formed using a PVD process.
[0057] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the first semiconductor structure and the second semiconductor structure are bonded together according to an embodiment of this application. The second semiconductor structure after the formation of the second bonding layer 24 is inverted on the first bonding layer 14, and the second bonding layer 24 is bonded to the first bonding layer 14.
[0058] Preferably, the second bonding layer 24 is bonded to the first bonding layer 14 using a van der Waals force bonding process.
[0059] Preferably, after the second bonding layer 24 is bonded to the first bonding layer 14, the diameter of the first bonding layer 14 is smaller than the diameter of the second bonding layer 24.
[0060] Finally, step S5 is performed: after completing the back-side process of the device wafer, the first semiconductor structure and the second semiconductor structure are peeled off from the interface between the energy release layer 23 and the second bonding layer 24 and debonded.
[0061] Specifically, after completing the back-side fabrication of the device wafer, the step of peeling the first semiconductor structure and the second semiconductor structure from the interface between the energy release layer 23 and the second bonding layer 24 and performing debonding processing includes:
[0062] After the back-side process of the device wafer is completed, a laser is used to vertically irradiate the interface between the energy release layer 23 and the second bonding layer 24 from the back side of the carrier wafer 21 (i.e., the laser focal plane is located at the interface between the energy release layer 23 and the second bonding layer 24) to cause the interface between the energy release layer 23 and the second bonding layer 24 to fail until the energy release layer 23 and the second bonding layer 24 are dissociated.
[0063] In this embodiment, during the debonding process, the diameter of the focused spot is no greater than the diameter of the second bonding layer 24.
[0064] The back-side process of the device wafer includes, but is not limited to, back-side thinning process.
[0065] It is worth noting that continued reference Figure 5 and reference Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure of the device wafer after debonding according to an embodiment of this application. During the actual debonding process, the laser directly acts on the interface between the energy release layer 23 and the second bonding layer 24. The adhesion between the energy release layer 23 and the second bonding layer 24 gradually weakens. Therefore, during the debonding process, reference... Figure 5 The red dashed line represents the actual unbonding interface. The adhesion force between the energy release layer 23 and the second bonding layer 24 gradually decreases compared to the bonding force between the middle region of the first bonding layer 14 and the middle region of the second bonding layer 24. Therefore, the region of the second bonding layer 24 away from the edge is separated from the interface between the energy release layer 23 and the second bonding layer 24. However, since the bonding force between the edge of the first bonding layer 14 and the edge of the second bonding layer 24 is still much smaller than the adhesion force between the energy release layer 23 and the second bonding layer 24, the film at the edge of the second bonding layer 24 is still bonded to the energy release layer 23, and the film at the edge of the second bonding layer 24 peels off and separates from the film at the non-edge position of the second bonding layer 24. The second bonding layer 24, having lost its edge, is still bonded to the first bonding layer 14. That is, the edge of the second bonding layer 24 produces a peeling step and a chipping.
[0066] Furthermore, after the debonding process, the temporary bonding and debonding method may also include: using CMP (chemical mechanical polishing) to remove the second bonding layer 24, the first bonding layer 14 and the energy absorption layer 13 on the surface of the device wafer 11. Since the peeling step caused by debonding is located at the edge of the second bonding layer at the top of the device wafer, it can be easily repaired by CMP process, avoiding defects such as wafer surface scratches, abrasions, over-etching, side etching and surface particle contamination in subsequent wet cleaning, chemical mechanical polishing and other processes.
[0067] In summary, by setting the second bonding layer as an adjacent layer to the energy release layer, this application ensures that during debonding, the step-like chipping at the wafer edge only occurs at the edge of the second bonding layer, reducing the height of the peeling step-like chipping. Furthermore, before bonding the first and second bonding layers, the first semiconductor structure is edge-trimmed, reducing the stress at the edge of the first semiconductor structure during debonding, thereby reducing the width of the peeling step-like chipping. Compared to the high and wide peeling step-like chipping caused by traditional debonding processes, the height and width of the peeling step-like chipping in this application are significantly reduced (the height of the peeling step-like chipping is reduced by at least the thickness of the energy absorption layer and one buffer layer). The peeling step-like chipping generated by debonding in this application is located at the edge of the second bonding layer at the top of the device wafer, so it can be easily repaired by CMP (chemical mechanical polishing) processes, avoiding defects such as wafer surface scratches, abrasions, over-etching, side etching, and surface particle contamination that may occur during subsequent wet cleaning and CMP processes.
[0068] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A temporary bonding and debonding method, characterized in that, include: A device wafer is provided, wherein a first buffer layer, an energy absorption layer and a first bonding layer are sequentially formed on the front side of the device wafer; The first semiconductor structure after the formation of the first bonding layer is subjected to edge trimming. A carrier wafer is provided, and a second buffer layer, an energy release layer and a second bonding layer are sequentially formed on the front side of the carrier wafer; The second semiconductor structure, after the formation of the second bonding layer, is inverted on the first bonding layer, and the second bonding layer is bonded to the first bonding layer; After the back-side process of the device wafer is completed, the first semiconductor structure and the second semiconductor structure are peeled off from the interface between the energy release layer and the second bonding layer and debonded.
2. The temporary bonding and debonding method according to claim 1, characterized in that, The first semiconductor structure after the formation of the first bonding layer is subjected to mechanical edge trimming.
3. The temporary bonding and debonding method according to claim 1, characterized in that, The first semiconductor structure after the formation of the first bonding layer is subjected to laser edge trimming.
4. The temporary bonding and debonding method according to claim 1, characterized in that, During the edge-cutting process of the first semiconductor structure after the formation of the first bonding layer, the edges of the first bonding layer, the energy absorption layer, the first buffer layer, and at least a portion of the thickness of the carrier wafer are circumferentially cut with the same preset width.
5. The temporary bonding and debonding method according to claim 4, characterized in that, The preset width is 1mm to 3mm.
6. The temporary bonding and debonding method according to claim 1, characterized in that, After the second bonding layer is bonded to the first bonding layer, the diameter of the first bonding layer is smaller than the diameter of the second bonding layer.
7. The temporary bonding and debonding method according to claim 1, characterized in that, After completing the back-side fabrication of the device wafer, the step of peeling the first semiconductor structure and the second semiconductor structure from the interface between the energy release layer and the second bonding layer and performing debonding processing includes: After the back-side process of the device wafer is completed, a laser is used to vertically irradiate the interface between the energy release layer and the second bonding layer from the back side of the supporting wafer, so as to cause the interface between the energy release layer and the second bonding layer to fail until the energy release layer and the second bonding layer are dissociated.
8. The temporary bonding and debonding method according to claim 7, characterized in that, During the debonding process, the diameter of the focused spot is no larger than the diameter of the second bonding layer.
9. The temporary bonding and debonding method according to claim 1, characterized in that, The thickness of both the first buffer layer and the second buffer layer is 500 angstroms to 1000 angstroms.
10. The temporary bonding and debonding method according to claim 1, characterized in that, The thickness of the energy-absorbing layer is 100 angstroms to 1000 angstroms.