Semiconductor device and method of manufacture, test method

Abstract

This application discloses a semiconductor device and its fabrication and testing methods, belonging to the field of semiconductor technology. The semiconductor device includes: a semiconductor layer comprising a first surface and a second surface disposed opposite each other along its thickness direction; a trench extending from the first surface into the semiconductor layer, the trench having a V-shaped cross-section along its thickness direction; an insulating layer covering the sidewalls of the trench; and a gate filling the trench; wherein the semiconductor layer, the insulating layer, and the gate constitute a capacitor structure, the capacitor structure being suitable for detecting the interface quality of the gate insulating layer on the sidewalls of the gate trench in the trench-gate semiconductor device by measuring the capacitance. This application can accurately detect the interface quality of the gate insulating layer on the sidewalls of the gate trench.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and its preparation and testing methods. Background Technology

[0002] In trench-gate semiconductor devices, related techniques characterize the interface quality of the insulating layer on the sidewalls of the gate trench by testing the capacitance of the capacitor structure (composed of a semiconductor layer, an insulating layer in the gate trench, and a gate). However, the capacitance measured by this capacitor structure is affected by the capacitance at the bottom of the gate trench, making it impossible to accurately detect the interface quality of the insulating layer on the sidewalls of the gate trench. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a semiconductor device and its fabrication and testing methods, which can accurately detect the interface quality of the gate insulating layer on the sidewall of the gate trench.

[0004] In a first aspect, this application provides a semiconductor device, comprising: A semiconductor layer includes a first surface and a second surface disposed opposite to each other along the thickness direction; the semiconductor layer has a trench extending from the first surface into the semiconductor layer, and the trench has a V-shaped cross-section along the thickness direction; An insulating layer covers the sidewalls of the trench; A gate electrode is filled in the trench; The semiconductor layer, the insulating layer, and the gate constitute a capacitor structure, which is suitable for detecting the interface quality of the insulating layer on the gate trench sidewall in a trench gate semiconductor device by measuring the capacitance.

[0005] According to the semiconductor device of this application, by forming a trench extending from a first surface into the semiconductor layer in the semiconductor layer, the trench has a V-shaped cross-section along the thickness direction, so that the trench only has sidewalls and no bottom wall, the insulating layer covers the sidewalls of the trench, and the gate fills the trench, when performing capacitance measurement on the capacitor structure composed of the semiconductor layer, the insulating layer and the gate, only the capacitance of the trench sidewalls is extracted, avoiding the test influence caused by the bottom capacitance of the trench, and improving the detection accuracy of the interface quality of the gate insulating layer on the sidewall of the gate trench.

[0006] According to one embodiment of this application, the semiconductor device further includes: The first electrode is located on the side of the gate opposite to the second surface and is in contact with the gate; The second electrode is located on the second surface of the semiconductor layer.

[0007] According to one embodiment of this application, the semiconductor device further includes: A dielectric layer is located on the first surface of the semiconductor layer.

[0008] According to one embodiment of this application, the semiconductor layer includes: Substrate; An epitaxial layer is located on one side of the substrate along the thickness direction, the first surface is the surface of the epitaxial layer facing away from the substrate, and the trench extends from the first surface into the epitaxial layer.

[0009] According to one embodiment of this application, the angle between the sidewall of the trench and the thickness direction is 15° to 35°; and / or, The depth of the groove along the thickness direction is 0.5 μm to 1 μm; and / or, The thickness of the insulating layer is 300nm~800nm.

[0010] According to one embodiment of this application, the trench gate semiconductor device includes a semiconductor body, the gate trench extends from one side surface of the semiconductor body along the thickness direction into the semiconductor body, and the gate insulating layer covers the sidewalls and bottom wall of the gate trench; The semiconductor layer has the same film structure and material as the semiconductor body.

[0011] Secondly, this application provides a method for fabricating a semiconductor device, comprising: A semiconductor layer is provided, the semiconductor layer including a first surface and a second surface disposed opposite to each other along the thickness direction; A trench is formed in the semiconductor layer, the trench extending from the first surface into the semiconductor layer, and the cross-section of the trench along the thickness direction is V-shaped; An insulating layer is formed, which covers the sidewalls of the trench; The gate electrode is filled in the trench; The semiconductor layer, the insulating layer, and the gate constitute a capacitor structure, which is used to detect the interface quality of the gate insulating layer on the gate trench sidewall in the trench gate semiconductor device by testing the capacitance of the capacitor structure.

[0012] According to one embodiment of this application, forming a trench in the semiconductor layer includes: A mask layer with mask openings is formed on the first surface of the semiconductor layer; The semiconductor layer is isotropically etched through the mask opening to form trenches in the semiconductor layer.

[0013] According to one embodiment of this application, the method further includes: A dielectric layer is formed on the first surface of the semiconductor layer; A via is formed that penetrates the dielectric layer, and the via exposes the gate electrode; A first electrode is filled into the through hole, and the first electrode is in contact with the gate. A second electrode is formed on the second surface of the semiconductor layer.

[0014] Thirdly, this application provides a testing method applied to a semiconductor device as described in the first aspect above, the testing method comprising: A voltage signal is applied to the capacitor structure; Measure the capacitance of the capacitor structure; The interface quality of the gate insulating layer on the sidewall of the gate trench in a trench gate semiconductor device is determined based on the measured capacitance.

[0015] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: By setting trenches extending from the first surface into the semiconductor layer in the semiconductor layer, with the trenches having a V-shaped cross-section along the thickness direction, the trenches only have sidewalls and no bottom wall. The insulating layer covers the sidewalls of the trenches, and the gate fills the trenches. When measuring the capacitance of the capacitor structure composed of the semiconductor layer, the insulating layer, and the gate, only the capacitance of the trench sidewalls is extracted, avoiding the test influence caused by the bottom capacitance of the trench, and improving the detection accuracy of the interface quality of the gate insulating layer on the sidewalls of the gate trench.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this application; Figure 2 This is a schematic diagram of the trench gate semiconductor device provided in the embodiments of this application; Figure 3 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application; Figure 4 This is a flowchart illustrating the testing method provided in the embodiments of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] The semiconductor devices, fabrication methods, and testing methods provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0021] like Figure 1 As shown, the semiconductor device provided in this application embodiment includes a semiconductor layer 1, an insulating layer 2, and a gate 3.

[0022] Semiconductor layer 1 may include a single semiconductor layer or a stacked structure formed by multiple semiconductor layers. The material of the semiconductor layer may include SiC, etc.

[0023] Semiconductor layer 1 may be doped with ions. Semiconductor layer 1 may be doped with N-type dopant ions to form an N-type semiconductor layer. N-type dopant ions may include P (phosphorus) or N (nitrogen) ions, etc. Semiconductor layer 1 may also be doped with P-type dopant ions to form a P-type semiconductor layer. P-type dopant ions may include Al (aluminum) ions or B (boron) ions, etc.

[0024] The semiconductor layer 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction X. Figure 1 The second surface S2 shown is the bottom surface of semiconductor layer 1, and the first surface S1 is the top surface of semiconductor layer 1.

[0025] A trench 11 is provided in the semiconductor layer 1, extending from the first surface S1 into the semiconductor layer 1. The trench 11 has a V-shaped cross-section along the thickness direction X. The trench 11 has no bottom wall, and the sidewalls of the trench 11 are inclined in a direction away from the center of the trench 11.

[0026] The insulating layer 2 covers the sidewalls of the trench 11, that is, the insulating layer 2 covers the surface of the trench 11. The material of the insulating layer 2 may include silicon oxide, etc.

[0027] The gate 3 is filled in the trench 11, and the surface of the gate 3 facing away from the second surface S2 is flush with the first surface S1. The insulating layer 2 is located between the semiconductor layer 1 and the gate 3 to isolate the semiconductor layer 1 from the gate 3. The material of the gate 3 may include polysilicon, etc.

[0028] Semiconductor layer 1, insulating layer 2, and gate 3 constitute capacitor structure 10. Capacitor structure 10 is suitable for detecting the interface quality of the gate insulating layer on the sidewall of the gate trench in a trench gate semiconductor device by measuring capacitance. Semiconductor layer 1 is one electrode of capacitor structure 10, gate 3 is the other electrode of capacitor structure 10, and insulating layer 2 is the insulating dielectric layer between the two electrodes of capacitor structure 10.

[0029] By applying a voltage signal (such as the input voltage signal to gate 3, with semiconductor layer 1 grounded) to capacitor structure 10, the capacitance of capacitor structure 10 is measured, and a capacitance-voltage curve (CV curve) is constructed. Based on the CV curve, the interface quality of the gate insulating layer on the sidewalls of the gate trench in the trench-gate semiconductor device is detected. For example, based on the CV curve, the interface state density and trap charge of the gate insulating layer on the sidewalls of the gate trench are detected, and then the interface quality of the gate insulating layer on the sidewalls of the gate trench is detected based on the interface state density and trap charge. The interface quality of the gate insulating layer on the sidewalls of the gate trench directly affects the reliability of the device. Detecting the interface quality of the gate insulating layer on the sidewalls of the gate trench helps to improve device performance, enhance device reliability, optimize process control, and reduce the risk of failure.

[0030] As an example, such as Figure 2 As shown, the trench gate semiconductor device includes a semiconductor body 101. The semiconductor body 101 includes a third surface S3 and a fourth surface S4 disposed opposite to each other along the thickness direction X. The semiconductor body 101 also includes a well region 102, a first region 103, and a second region 107. The first region 103 is located on the third surface S3, and the well region 102 is located on the side of the first region 103 opposite to the third surface S3. The second region 107 extends from the third surface S3 into the semiconductor layer 101. A gate trench 104 extending from the third surface S3 into the semiconductor layer 101 is provided in the semiconductor layer 101. The gate trench 104 has a rectangular cross-section along the thickness direction X. The trench gate semiconductor device also includes a gate insulating layer 105 and a gate 106. The gate insulating layer 105 covers the surface of the gate trench 104 (including the sidewalls and bottom of the gate trench 104), and the gate 106 fills the gate trench 104. The trench gate semiconductor device also includes a source 108 and a drain 109. The source electrode 108 is located on the third surface S3 of the semiconductor body 101 and is in contact with the first region 103 and the second region 107. The drain electrode 109 is located on the fourth surface S4 of the semiconductor layer 101.

[0031] When analyzing the interface quality of the gate insulating layer 105 on the sidewalls of the gate trench 104, the semiconductor device in the related art consists of a semiconductor body 101, a gate trench 104, a gate insulating layer 105, and a gate 106, which together form a capacitor structure. Since the gate insulating layer 105 covers both the sidewalls and the bottom of the gate trench 104, when extracting the capacitance of the sidewalls of the gate trench 104, the capacitance of the bottom of the gate trench 104 is also extracted simultaneously, making it difficult to accurately detect the interface quality of the gate insulating layer 105 on the sidewalls of the gate trench 104.

[0032] In this embodiment, the semiconductor device has a trench 11 extending from the first surface S1 into the semiconductor layer 1. The trench 11 has a V-shaped cross-section along the thickness direction X, so that the trench 11 has only sidewalls and no bottom wall. The insulating layer 2 covers the sidewalls of the trench 11, and the gate 3 fills the trench 11. When performing capacitance testing on the capacitor structure composed of the semiconductor layer 1, the insulating layer 2, and the gate 3, only the capacitance of the sidewalls of the trench 11 is extracted to avoid the test influence caused by the bottom capacitance of the trench 11. Through the capacitance of the sidewalls of the trench 11, the interface quality of the gate insulating layer 105 on the sidewall of the gate trench 104 can be accurately detected.

[0033] In some embodiments, such as Figure 1 As shown, the semiconductor device also includes a first electrode 4 and a second electrode 5. The first electrode 4 is located on the side of the gate 3 opposite to the second surface S2 and is in contact with the gate 3. The second electrode 5 is located on the second surface S2 of the semiconductor layer 1.

[0034] The first electrode 4 is in contact with the gate 3 and is used to bring out the gate 3, that is, to bring out one electrode of the capacitor structure 10, so as to connect to the test equipment during capacitance testing. The orthographic projection of the first electrode 4 on the first surface S1 can be located within the orthographic projection of the gate 3 on the first surface S1, or overlap with the orthographic projection of the gate 3 on the first surface S1. The first electrode 4 has no contact with the semiconductor layer 1 to avoid the risk of short circuit.

[0035] The second electrode 5 is in contact with the second surface S2 of the semiconductor layer 1, and is used to lead out the semiconductor layer 1, that is, to lead out the other electrode of the capacitor structure 10, so as to connect to the test equipment during capacitance testing. The orthogonal projection of the second electrode 5 on the second surface S2 can completely cover the second surface S2.

[0036] The first electrode 4 and the second electrode 5 can each be a metal electrode. For example, the materials of the first electrode 4 and the second electrode 5 can include metals such as aluminum, copper, and nickel. The materials of the first electrode 4 and the second electrode 5 can be the same or different, and no specific limitation is made here.

[0037] During testing, a voltage signal is applied to the gate 3 through the first electrode 4, and the second electrode 5 is grounded. The capacitance of the capacitor structure 10 is measured, and a capacitance-voltage curve (CV curve) is constructed. Based on the CV curve, the interface quality of the gate insulating layer on the sidewall of the gate trench in the trench gate semiconductor device is detected.

[0038] In some embodiments, such as Figure 1 As shown, the semiconductor device further includes a dielectric layer 6, which is located on the first surface S1 of the semiconductor layer 1. The dielectric layer 6 covers the first surface S1 of the semiconductor layer 1 to prevent short circuits between the semiconductor layer 1 and other conductive structures. The material of the dielectric layer 6 may include silicon oxide, silicon nitride, etc.

[0039] In some embodiments, the semiconductor layer 1 in the semiconductor device and the semiconductor body 101 in the trench gate semiconductor device have the same film structure and material. Specifically, the semiconductor layer 1 in the semiconductor device and the semiconductor body 101 in the trench gate semiconductor device have the same film composition, the same film arrangement order, the same film thickness, the same film shape, and the same film material.

[0040] The film structure and material of semiconductor layer 1 can affect test data. In this embodiment, the film structure and material of semiconductor layer 1 in the semiconductor device are consistent with those of semiconductor body 101 in the trench gate semiconductor device, which further improves the accuracy of interface quality detection of gate insulating layer 105 on the sidewall of gate trench 104.

[0041] In some embodiments, the semiconductor layer 1 includes a substrate 12 and an epitaxial layer 13. The epitaxial layer 13 is located on one side of the substrate 12 along the thickness direction X. A first surface S1 is the surface of the epitaxial layer 13 facing away from the substrate 12, and a trench 11 extends from the first surface S1 into the epitaxial layer 13. A second surface S2 is the surface of the substrate 12 facing away from the epitaxial layer 13.

[0042] Substrate 12 can be doped with N-type ions to form an N-type substrate, or it can be doped with P-type ions to form a P-type substrate. Epitaxial layer 13 can be doped with ions or not. When epitaxial layer 13 is doped with ions, the doping type of epitaxial layer 13 and substrate 12 is the same. As an example, substrate 12 is an N-type substrate, and epitaxial layer 13 is an N-type epitaxial layer.

[0043] The substrate 12 and the epitaxial layer 13 can be made of the same material, for example, both the substrate 12 and the epitaxial layer 13 can be made of SiC.

[0044] like Figure 2As shown, the semiconductor body 101 in the trench gate semiconductor device includes a substrate 112 and an epitaxial layer 111. A third surface S3 is the surface of the epitaxial layer 111 facing away from the substrate 112, and a fourth surface S4 is the surface of the substrate 112 facing away from the epitaxial layer 111. A well region 102 and a first region 103 are located in the epitaxial layer 111, a second region 107 extends from the third surface S3 into the epitaxial layer 111, and a gate trench 104 extends from the third surface S3 into the epitaxial layer 111.

[0045] The substrate 12 in the semiconductor device and the substrate 112 in the trench gate semiconductor device can have the same film structure and material, such as the same thickness, the same shape, the same material, etc.

[0046] The epitaxial layer 13 in the semiconductor device and the epitaxial layer 111 in the trench gate semiconductor device can have the same film structure and material, such as the same thickness, the same shape, the same material, etc.

[0047] The film structure and material of substrate 12 and epitaxial layer 13 can affect the test data. In this embodiment, the film structure and material of substrate 12 and epitaxial layer 13 in the semiconductor device are consistent with those of substrate 112 and epitaxial layer 111 in the trench gate semiconductor device, which further improves the accuracy of the interface quality detection of the gate insulating layer 105 on the sidewall of the gate trench 104.

[0048] In some embodiments, the angle between the sidewall of the trench 11 and the thickness direction X is 15° to 35°. The angle between the two sidewalls of the trench 11 is 30° to 70°.

[0049] The angle between the sidewall of trench 11 and the thickness direction X cannot be too large or too small. If the angle is too large, the SiC crystal orientation will be closer to the plane, affecting the accuracy of the test data; if the angle is too small, it will affect the filling effect of the gate 3, affecting the accuracy of the test data. In this embodiment, the angle between the sidewall of trench 11 and the thickness direction X is set within the above range, which can ensure the accuracy of the test data, thereby improving the detection accuracy of the interface quality of the insulating layer of the gate trench sidewall in trench gate semiconductor devices.

[0050] In some embodiments, the depth of the groove 11 along the thickness direction X is 0.5 μm to 1 μm.

[0051] The depth of trench 11 along the thickness direction X can be the same as or different from the depth of gate trench 104 along the thickness direction X in the trench gate semiconductor device, and no specific limitation is made here.

[0052] In some embodiments, the thickness of the insulating layer 2 is 300 nm to 800 nm.

[0053] The thickness of insulating layer 2 may be the same as or different from the thickness of gate insulating layer 105 in the trench gate semiconductor device; no specific limitation is made here. Insulating layer 2 and gate insulating layer 105 in the trench gate semiconductor device are made of the same material, such as silicon oxide for both insulating layer 2 and gate insulating layer 105.

[0054] According to the semiconductor device provided in the embodiments of this application, a trench 11 extending from the first surface S1 into the semiconductor layer 1 is provided in the semiconductor layer 1. The cross-section of the trench 11 along the thickness direction X is V-shaped, so that the trench 11 has only sidewalls and no bottom wall. The insulating layer 2 covers the sidewalls of the trench 11, and the gate 3 fills the trench 11. When performing capacitance testing on the capacitor structure 10 composed of the semiconductor layer 1, the insulating layer 2 and the gate 3, only the capacitance of the trench sidewalls is extracted, avoiding the test influence caused by the bottom capacitance of the trench, and improving the detection accuracy of the interface quality of the gate insulating layer on the sidewall of the gate trench.

[0055] Accordingly, this application also provides a method for fabricating a semiconductor device, which can form the semiconductor device described in the above embodiments.

[0056] Figure 3 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of this application.

[0057] like Figure 3 As shown, the method for fabricating a semiconductor device provided in this application includes steps S110 to S140.

[0058] Step S110: Provide a semiconductor layer, the semiconductor layer including a first surface and a second surface disposed opposite to each other along the thickness direction.

[0059] Combination Figure 1 As shown, semiconductor layer 1 may include a single semiconductor layer or a stacked structure formed by multiple semiconductor layers. The material of the semiconductor layer may include SiC, etc.

[0060] In some embodiments, the semiconductor layer 1 may include a substrate 12 and an epitaxial layer 13. The epitaxial layer 13 is located on one side of the substrate 12 along the thickness direction X, the first surface S1 is the surface of the epitaxial layer 13 facing away from the substrate 12, and the second surface S2 is the surface of the substrate 12 facing away from the epitaxial layer 13.

[0061] Substrate 12 can be doped with N-type ions to form an N-type substrate, or it can be doped with P-type ions to form a P-type substrate. Epitaxial layer 13 can be doped with ions or not. When epitaxial layer 13 is doped with ions, the doping type of epitaxial layer 13 and substrate 12 is the same. As an example, substrate 12 is an N-type substrate, and epitaxial layer 13 is an N-type epitaxial layer.

[0062] The substrate 12 and the epitaxial layer 13 can be made of the same material, for example, both the substrate 12 and the epitaxial layer 13 can be made of SiC.

[0063] Step S120: A trench is formed in the semiconductor layer. The trench extends from the first surface into the semiconductor layer, and the cross-section of the trench along the thickness direction is V-shaped.

[0064] Combination Figure 1 As shown, the semiconductor layer 1 is etched to form a trench 11 extending from the first surface S1 into the semiconductor layer 1. The trench 11 has a V-shaped cross-section along the thickness direction X. The trench 11 has no bottom wall, and the sidewalls of the trench 11 are inclined in a direction away from the center of the trench 11.

[0065] In the case where the semiconductor layer 1 includes a substrate 12 and an epitaxial layer 13, the epitaxial layer 13 is etched to form a trench 11 extending from the first surface S1 into the epitaxial layer 13.

[0066] In some embodiments, forming trenches in a semiconductor layer includes: A mask layer with mask openings is formed on the first surface of the semiconductor layer; Through the mask opening, isotropic etching is performed on the semiconductor layer to form trenches in the semiconductor layer.

[0067] An isotropic etching process is used to etch the epitaxial layer 13 downwards through the mask opening, while also etching to the sides. By optimizing the etching process, V-shaped trenches 11 are formed.

[0068] This ensures that the cross-section of the trench 11 formed by isotropic etching along the thickness direction X is V-shaped.

[0069] Step S130: Form an insulating layer that covers the sidewalls of the trench.

[0070] Combination Figure 1 As shown, an insulating layer 2 is formed on the sidewall of trench 11 using a thin-film deposition process. The insulating layer 2 covers the sidewall of trench 11, that is, the insulating layer 2 covers the surface of trench 11. The material of the insulating layer 2 may include silicon oxide, etc.

[0071] Step S140: Fill the trench with a gate; wherein the semiconductor layer, the insulating layer and the gate constitute a capacitor structure, and the capacitor structure is suitable for detecting the interface quality of the gate insulating layer on the sidewall of the gate trench in the trench gate semiconductor device by measuring the capacitance.

[0072] Combination Figure 1 As shown, a thin-film deposition process is used to fill the trench 11 with gate 3. An insulating layer 2 is located between the semiconductor layer 1 and the gate 3 to isolate the semiconductor layer 1 from the gate 3. The material of the gate 3 may include polysilicon or the like.

[0073] Semiconductor layer 1, insulating layer 2, and gate 3 constitute capacitor structure 10. By applying a voltage signal to capacitor structure 10 (e.g., input voltage signal to gate 3, semiconductor layer 1 grounded), the capacitance of capacitor structure 10 is measured, and a capacitance-voltage curve (CV curve) is constructed. Based on the CV curve, the interface quality of the gate insulating layer on the sidewall of the gate trench in the trench-gate semiconductor device is detected. For example, based on the CV curve, the interface state density, trap charge, etc., of the gate insulating layer on the sidewall of the gate trench are detected, and then the interface quality of the gate insulating layer on the sidewall of the gate trench is detected based on the interface state density, trap charge, etc. The interface quality of the gate insulating layer on the sidewall of the gate trench directly affects the reliability of the device. By detecting the interface quality of the gate insulating layer on the sidewall of the gate trench, it is helpful to improve device performance, enhance device reliability, optimize process control, and reduce failure risk.

[0074] In this embodiment, a trench 11 extending from the first surface S1 into the semiconductor layer 1 is provided. The cross-section of the trench 11 along the thickness direction X is V-shaped, so that the trench 11 only has sidewalls and no bottom wall. The insulating layer 2 covers the sidewalls of the trench 11, and the gate 3 fills the trench 11. When performing capacitance testing on the capacitor structure composed of the semiconductor layer 1, the insulating layer 2 and the gate 3, only the capacitance of the sidewalls of the trench 11 is extracted to avoid the test influence caused by the bottom capacitance of the trench 11. Through the capacitance of the sidewalls of the trench 11, the interface quality of the gate insulating layer on the sidewalls of the gate trench can be accurately detected.

[0075] In some embodiments, the method for fabricating the semiconductor device further includes: A dielectric layer is formed on the first surface of the semiconductor layer; A via is formed that penetrates the dielectric layer, and the via exposes the gate electrode; A first electrode is filled into the through-hole, and the first electrode is in contact with the gate. A second electrode is formed on the second surface of the semiconductor layer.

[0076] Combination Figure 1 As shown, a dielectric layer 6 is formed on the first surface S1 of semiconductor layer 1 using a thin-film deposition process. The dielectric layer 6 covers semiconductor layer 1 and gate 3. Then, an etching process is used to form a through-hole in dielectric layer 6, exposing gate 3. A first electrode 4 is filled into the through-hole using a thin-film deposition process. The first electrode 4 is in contact with gate 3 but not with semiconductor layer 1. A second electrode 5 is formed on the second surface S2 of semiconductor layer 1 using a thin-film deposition process, and the second electrode 5 is in contact with the second surface S2 of semiconductor layer 1.

[0077] The first electrode 4 and the second electrode 5 can each be a metal electrode. For example, the materials of the first electrode 4 and the second electrode 5 can include metals such as aluminum, copper, and nickel. The materials of the first electrode 4 and the second electrode 5 can be the same or different, and no specific limitation is made here.

[0078] During testing, a voltage signal is applied to the gate 3 through the first electrode 4, and the second electrode 5 is grounded. The capacitance of the capacitor structure 10 is measured, and a capacitance-voltage curve (CV curve) is constructed. Based on the CV curve, the interface quality of the gate insulating layer on the sidewall of the gate trench in the trench gate semiconductor device is detected.

[0079] In some embodiments, combined with Figure 2 As shown, the semiconductor layer 1 in the semiconductor device and the semiconductor body 101 in the trench gate semiconductor device have the same film structure and material. The epitaxial layer 13 in the semiconductor device and the epitaxial layer 111 in the trench gate semiconductor device can have the same film structure and material.

[0080] In some embodiments, the angle between the sidewall of the groove 11 and the thickness direction X is 15° to 35°.

[0081] In some embodiments, the depth of the groove 11 along the thickness direction X is 0.5 μm to 1 μm.

[0082] In some embodiments, the thickness of the insulating layer 2 is 300 nm to 800 nm.

[0083] According to the semiconductor device fabrication method provided in the embodiments of this application, a trench 11 extending from the first surface S1 into the semiconductor layer 1 is provided in the semiconductor layer 1. The cross-section of the trench 11 along the thickness direction X is V-shaped, so that the trench 11 has only sidewalls and no bottom wall. The insulating layer 2 covers the sidewalls of the trench 11, and the gate 3 fills the trench 11. When performing capacitance testing on the capacitor structure 10 composed of the semiconductor layer 1, the insulating layer 2 and the gate 3, only the capacitance of the trench sidewalls is extracted, avoiding the test influence caused by the bottom capacitance of the trench, and improving the detection accuracy of the interface quality of the gate insulating layer on the sidewall of the gate trench.

[0084] Accordingly, this application also provides a testing method that can be applied to the semiconductor devices described in the above embodiments.

[0085] like Figure 4 As shown, the testing method provided in this application embodiment includes: Step S210: Apply a voltage signal to the capacitor structure.

[0086] Combination Figure 1As shown, a voltage signal is applied to the capacitor structure 10. For example, a voltage signal is input to the gate 3 through the first electrode 4, and the semiconductor layer 1 is grounded through the second electrode 5.

[0087] Step S220: Measure the capacitance of the capacitor structure.

[0088] Combination Figure 1 As shown, the capacitance of capacitor structure 10 is measured, and a curve of capacitance versus voltage (CV curve) is constructed.

[0089] Step S230: Determine the interface quality of the gate insulating layer on the sidewall of the gate trench in the trench gate semiconductor device based on the measured capacitance.

[0090] Based on measured capacitance, the interface quality of the gate insulating layer on the sidewalls of the gate trench in a trench-gate semiconductor device is detected using methods such as high- and low-frequency methods. For example, based on the CV curve, the interface state density and trapped charge of the gate insulating layer on the sidewalls of the gate trench are detected, and then the interface quality of the gate insulating layer on the sidewalls of the gate trench is determined based on the interface state density and trapped charge. The interface quality of the gate insulating layer on the sidewalls of the gate trench directly affects the reliability of the device. Detecting the interface quality of the gate insulating layer on the sidewalls of the gate trench helps to improve device performance, enhance device reliability, optimize process control, and reduce the risk of failure.

[0091] In summary, according to the test method provided in the embodiments of this application, when performing capacitance testing on the capacitor structure composed of semiconductor layer 1, insulating layer 2 and gate 3, only the capacitance of the sidewall of trench 11 is extracted, avoiding the test influence caused by the bottom capacitance of trench 11. Through the capacitance of the sidewall of trench 11, the interface quality of the gate insulating layer on the sidewall of the gate trench can be accurately detected.

[0092] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0093] In the description of this application, "multiple" means two or more.

[0094] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0095] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer includes a first surface and a second surface disposed opposite to each other along the thickness direction; the semiconductor layer has a trench extending from the first surface into the semiconductor layer, and the trench has a V-shaped cross-section along the thickness direction; An insulating layer covers the sidewalls of the trench; A gate electrode is filled in the trench; The semiconductor layer, the insulating layer, and the gate constitute a capacitor structure, which is adapted to detect the interface quality of the gate insulating layer on the gate trench sidewall in a trench gate semiconductor device by measuring the capacitance.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The first electrode is located on the side of the gate opposite to the second surface and is in contact with the gate; The second electrode is located on the second surface of the semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: A dielectric layer is located on the first surface of the semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor layer includes: Substrate; An epitaxial layer is located on one side of the substrate along the thickness direction, the first surface is the surface of the epitaxial layer opposite to the substrate, and the trench extends from the first surface into the epitaxial layer.

5. The semiconductor device according to claim 1, characterized in that, The angle between the sidewall of the groove and the thickness direction is 15° to 35°; and / or, The depth of the groove along the thickness direction is 0.5 μm to 1 μm; and / or, The thickness of the insulating layer is 300nm~800nm.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The trench gate semiconductor device includes a semiconductor body, the gate trench extending from one side surface of the semiconductor body along the thickness direction into the semiconductor body, and the gate insulating layer covering the sidewalls and bottom wall of the gate trench; The semiconductor layer has the same film structure and material as the semiconductor body.

7. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor layer is provided, the semiconductor layer including a first surface and a second surface disposed opposite to each other along the thickness direction; A trench is formed in the semiconductor layer, the trench extending from the first surface into the semiconductor layer, and the cross-section of the trench along the thickness direction is V-shaped; An insulating layer is formed, which covers the sidewalls of the trench; A gate electrode is filled in the trench; The semiconductor layer, the insulating layer, and the gate constitute a capacitor structure, which is adapted to detect the interface quality of the gate insulating layer on the gate trench sidewall in a trench gate semiconductor device by measuring the capacitance.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The formation of trenches in the semiconductor layer includes: A mask layer with mask openings is formed on the first surface of the semiconductor layer; The semiconductor layer is isotropically etched through the mask opening to form trenches in the semiconductor layer.

9. The method for fabricating a semiconductor device according to claim 7 or 8, characterized in that, The method further includes: A dielectric layer is formed on the first surface of the semiconductor layer; A via is formed that penetrates the dielectric layer, and the via exposes the gate electrode; A first electrode is filled into the through hole, and the first electrode is in contact with the gate. A second electrode is formed on the second surface of the semiconductor layer.

10. A testing method, characterized in that, The test method, applied to the semiconductor device as described in any one of claims 1-6, comprises: A voltage signal is applied to the capacitor structure; Measure the capacitance of the capacitor structure; The interface quality of the gate insulating layer on the sidewall of the gate trench in a trench gate semiconductor device is determined based on the measured capacitance.

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