Semiconductor test structures and test methods
By introducing an interdigitated structure into the semiconductor test structure to monitor leakage current, the problem of short circuit between adjacent conductive plugs is solved, enabling timely detection and elimination in the wafer fabrication plant and improving product yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-05-28
- Publication Date
- 2026-07-31
AI Technical Summary
During wafer manufacturing, short circuits caused by voids in the interlayer dielectric layer between adjacent conductive plugs cannot be detected in time by the continuous online process and existing electrical acceptance testing in the wafer fabrication plant, resulting in low product yield.
Design a semiconductor test structure including a gate structure, an interlayer dielectric layer, conductive plugs, and an interdigitated structure. By detecting the leakage current of the interdigitated structure, monitor whether there are voids in the interlayer dielectric layer between adjacent conductive plugs and detect short circuit problems in a timely manner.
By promptly identifying and eliminating short circuits between adjacent conductive plugs before the wafers leave the factory, product yield was improved and large-scale product scrapping was avoided.
Smart Images
Figure CN122497338A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of wafer testing technology, and in particular to a semiconductor testing structure and testing method. Background Technology
[0002] As integrated circuit design dimensions shrink, the filling capability of the interlayer dielectric layer between polysilicon gates becomes crucial when the distance between polysilicon gates is relatively close. If the filling capability of the interlayer dielectric layer is insufficient, a void gap can easily form between the polysilicon gates (within the interlayer dielectric layer). In the subsequent contact hole etching process of the conductive plug, the void will be connected to the contact hole of the conductive plug. When a metal material (such as tungsten) fills the contact hole, the metal material will also fill the void in the interlayer dielectric layer, causing two adjacent conductive plugs to be connected by the metal material in the void to form a circuit, resulting in low product yield.
[0003] However, the above problems are usually not detected and verified in a timely manner in the continuous inline process of the wafer fabrication plant and the existing wafer electrical acceptance test (WAT). Often, the process problems are only discovered when the wafer is shipped from the wafer fabrication plant to the testing plant (CP end) and the functional verification (chip probing) of all chips on the wafer is performed before packaging, resulting in a large number of scrapped products. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor test structure and test method to solve the problem that adjacent conductive plugs are connected by metal material in the voids in the interlayer dielectric layer to form a circuit, resulting in low product yield and the inability to detect short circuits between adjacent conductive plugs in a timely manner in the continuous inline process and existing wafer electrical acceptance test (WAT) in the wafer fabrication plant.
[0005] To address the aforementioned technical problems, in one aspect, the present invention provides a semiconductor testing structure, comprising:
[0006] A substrate in which an active region is formed;
[0007] Multiple shallow trench isolation structures are provided, each of which is disposed in the active region along the X direction, and the multiple shallow trench isolation structures are distributed at intervals in the active region along the Y direction.
[0008] Multiple gate structures are disposed on the surface of the substrate along the Y direction, and the multiple gate structures are spaced apart on the surface of the substrate along the X direction;
[0009] An interlayer dielectric layer covering the gate structure, the active region, and the shallow trench isolation structure;
[0010] A plurality of conductive plugs are spaced apart along the Y direction in the interlayer dielectric layer between the gate structures, and each conductive plug is in contact with the surface of the active region between the shallow trench isolation structures; and,
[0011] The first interdigital structure and the second interdigital structure, wherein...
[0012] The first interdigitated structure includes: a first shank and a plurality of first comb teeth;
[0013] The second interdigitated structure includes: a second shank and a plurality of second comb teeth;
[0014] All the first comb teeth and all the second comb teeth are respectively disposed on the interlayer dielectric layer along the X direction and respectively cover all the conductive plugs in the corresponding row, and the first comb teeth and the second comb teeth are staggered along the Y direction; the first handle is disposed on the interlayer dielectric layer along the Y direction and is connected to the left end of all the first comb teeth; the second handle is disposed on the interlayer dielectric layer along the Y direction and is connected to the right end of all the second comb teeth.
[0015] Optionally, in the semiconductor test structure, the semiconductor test structure further includes:
[0016] The first test pad is located on the interlayer dielectric layer and is connected to the first handle.
[0017] The second test pad is located on the interlayer dielectric layer and is connected to the second handle.
[0018] Optionally, in the semiconductor test structure, each of the gate structures includes: a gate polysilicon and a sidewall structure, wherein the gate polysilicon is disposed on the substrate surface along the Y direction, and the sidewall structure is disposed on the substrate surface along the Y direction and covers the side surfaces on both sides of the gate polysilicon.
[0019] Optionally, in the semiconductor test structure, along the X direction, the minimum spacing between adjacent gate polysilicon cells covering the surface of the shallow trench isolation structure does not exceed 0.21 μm.
[0020] Optionally, in the semiconductor test structure, the minimum spacing between adjacent gate polysilicon cells covering the surface of the active region along the X direction does not exceed 0.28 μm.
[0021] Optionally, in the semiconductor test structure, the minimum spacing between the gate polysilicon and the conductive plug on the surface of the active region along the X direction does not exceed 0.08 μm.
[0022] Optionally, in the semiconductor test structure, the minimum spacing between the conductive plug and the shallow trench isolation structure on the surface of the active region along the Y direction does not exceed 0.02 μm.
[0023] Optionally, in the semiconductor test structure, the minimum dimension of each of the shallow trench isolation structures along the Y direction does not exceed 0.3 μm.
[0024] Optionally, in the semiconductor test structure, the semiconductor test structure further includes: a well region of a first conductivity type and a heavily doped region of a second conductivity type, wherein the well region is located in the active region and the heavily doped region is located in the well region near the upper surface of the well region.
[0025] On the other hand, the present invention also provides a test method based on the semiconductor test structure, wherein a first voltage is applied to a first shank of the semiconductor test structure, a second voltage lower than the first voltage is applied to a second shank of the semiconductor test structure, and leakage current between a first comb tooth and a second comb tooth of the semiconductor test structure is detected. If the leakage current between the first comb tooth and the second comb tooth is <1.0E-012A, it is determined that there are no voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction and that no short circuit occurs between adjacent conductive plugs; if the leakage current between the first comb tooth and the second comb tooth is >1.0E-09A, it is determined that there are voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction, causing a short circuit between adjacent conductive plugs.
[0026] In summary, the semiconductor test structure provided in this application includes at least: a gate structure, an interlayer dielectric layer, conductive plugs, and a first interdigitated structure and a second interdigitated structure. The gate structure extends along the Y direction on the substrate surface and is spaced apart along the X direction. Multiple conductive plugs are spaced apart along the Y direction in the interlayer dielectric layer between the gate structures and are all in contact with the active region surface between the shallow trench isolation structures. The first interdigitated structure includes a first shank and multiple first comb teeth, and the second interdigitated structure includes a second shank and multiple second comb teeth. All first comb teeth and all second comb teeth cover all conductive plugs in a corresponding row along the X direction, and the first and second comb teeth are staggered along the Y direction. This application connects the conductive plugs in each row (X direction) through a first interdigital structure and a second interdigital structure. This allows for timely and effective monitoring of the interlayer dielectric layer between adjacent conductive plugs in each row (X direction) during the wafer electrical acceptance test (WAT) before shipment from the wafer fabrication plant, based on given test conditions. This monitoring can detect defects as quickly as possible at the wafer fabrication plant, promptly identifying products with short circuits between adjacent conductive plugs. This avoids the situation where defects are discovered only at the testing plant, resulting in the scrapping of a large number of products. This improves the timeliness and reliability of monitoring, while also ensuring the yield of shipped products. Attached Figure Description
[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0028] Figure 1 This is a schematic diagram of a semiconductor test structure without the first interdigitated structure and the second interdigitated structure according to an embodiment of the present invention;
[0029] Figure 2 This is a schematic diagram of the semiconductor test structure after the first interdigitated structure and the second interdigitated structure are placed according to an embodiment of the present invention.
[0030] Figure 3 yes Figure 2 A cross-sectional view of the semiconductor test structure along the aa' tangent line;
[0031] Figure 4 yes Figure 2 A cross-sectional view of the semiconductor test structure along the bb' tangent line;
[0032] Figure 5 yes Figure 2 A cross-sectional view of the semiconductor test structure along the cc' tangent line;
[0033] The reference numerals in the attached figures are explained as follows:
[0034] 10-Active region, 11-Heavily doped region, 12-Shallow trench isolation structure, 13-Well region, 20-Gate structure, 21-Gate polysilicon, 22-Sidewall structure, 31-Conductive plug, 41-First comb tooth, 42-First shank, 51-Second comb tooth, 52-Second shank, 60-Interlayer dielectric layer, 71-First test pad, 72-Second test pad. Detailed Implementation
[0035] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0036] This invention provides a semiconductor test structure, with reference to Figures 1-5 , Figure 1 This is a schematic diagram of a semiconductor test structure without the first interdigitated structure and the second interdigitated structure according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the semiconductor testing structure after placing the first interdigital structure and the second interdigital structure according to an embodiment of the present invention. Figure 3 yes Figure 2 A cross-sectional view of the semiconductor test structure along the tangent line aa'. Figure 4 yes Figure 2 A cross-sectional view of the semiconductor test structure along the bb' tangent line. Figure 5 yes Figure 2 A cross-sectional view of a semiconductor test structure along the cc' tangent line, the semiconductor test structure comprising:
[0037] A substrate in which an active region 10 is formed;
[0038] Multiple shallow trench isolation structures 12 are provided in the active region 10 along the X direction, and the multiple shallow trench isolation structures 12 are distributed at intervals in the active region 10 along the Y direction.
[0039] A plurality of gate structures 20 are disposed on the surface of the substrate along the Y direction, and the plurality of gate structures 20 are spaced apart on the surface of the substrate along the X direction;
[0040] An interlayer dielectric layer 60 covers the gate structure 20, the active region 10, and the shallow trench isolation structure 12.
[0041] A plurality of conductive plugs 31 are spaced apart along the Y direction in the interlayer dielectric layer 60 between the gate structures 20, and each conductive plug 31 is in contact with the surface of the active region between the shallow trench isolation structures 12; and,
[0042] The first interdigital structure and the second interdigital structure, wherein...
[0043] The first interdigitated structure includes: a first handle portion 42 and a plurality of first comb teeth portions 41;
[0044] The second interdigitated structure includes: a second shank portion 52 and a plurality of second comb teeth portions 51;
[0045] All the first comb teeth 41 and all the second comb teeth 51 are respectively disposed on the interlayer dielectric layer 60 along the X direction and respectively cover all the conductive plugs 31 in the corresponding row, and the first comb teeth 41 and the second comb teeth 51 are staggered along the Y direction; the first handle 42 is disposed on the interlayer dielectric layer 60 along the Y direction and is connected to the left end of all the first comb teeth 41; the second handle 52 is disposed on the interlayer dielectric layer 60 along the Y direction and is connected to the right end of all the second comb teeth 51.
[0046] Preferably, the first handle portion 42, the first comb tooth portion 41, the second handle portion 52, and the second comb tooth portion 51 are all made of metal wire. In this embodiment, the first handle portion 42, the first comb tooth portion 41, the second handle portion 52, and the second comb tooth portion 51 are made of copper wire.
[0047] Preferably, the critical dimension of each of the first comb teeth 41 along the Y direction is larger than the critical dimension of the conductive plug 31 at its bottom along the Y direction. Similarly, the critical dimension of each of the second comb teeth 51 along the Y direction is larger than the critical dimension of the conductive plug 31 at its bottom along the Y direction.
[0048] It is worth noting that this application does not limit the number of the first comb teeth 41 or the number of the second comb teeth 51. In this embodiment, the number of the first comb teeth 41 is 3; the number of the second comb teeth 51 is 3.
[0049] Furthermore, the semiconductor test structure may also include:
[0050] First test pad 71, the first test pad 71 is located on the interlayer dielectric layer 60 and connected to the first handle 42;
[0051] The second test pad 72 is located on the interlayer dielectric layer 60 and is connected to the second handle 52.
[0052] Preferably, the semiconductor test structure may further include: a well region 13 of a first conductivity type and a heavily doped region 11 of a second conductivity type, wherein the well region 13 is located in the active region 10 and the heavily doped region 11 is located in the well region 13 near the upper surface of the well region 13.
[0053] In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type. The P-type well region 13 and the heavily doped N-type region 11 separate the substrate via PNP junctions.
[0054] Preferably, the conductive plug 31 is made of tungsten metal.
[0055] Preferably, each of the gate structures 20 includes a gate polysilicon 21 and a sidewall structure 22. Each of the gate polysilicon 21 is disposed on the substrate surface along the Y direction, and each of the sidewall structures 22 is disposed on the substrate surface along the Y direction and covers the side surfaces on both sides of the gate polysilicon 21.
[0056] refer to Figure 3 Along the X direction, the minimum spacing D1 between adjacent gate polysilicon 21 covering the surface of the shallow trench isolation structure 12 does not exceed 0.21 μm.
[0057] In this embodiment, along the X direction, the minimum spacing D1 between adjacent gate polysilicon 21 covering the surface of the shallow trench isolation structure 12 is 0.21 μm.
[0058] refer to Figure 4 Along the X direction, the minimum spacing D2 between adjacent gate polysilicon 21 covering the surface of the active region 10 (well region 13) does not exceed 0.28 μm.
[0059] In this embodiment, along the X direction, the minimum spacing D2 between adjacent gate polysilicon 21 covering the surface of the active region 10 (well region 13) is 0.28 μm.
[0060] Further reference Figure 4 Along the X direction, the minimum spacing D3 between the gate polysilicon 21 and the conductive plug 31 on the surface of the active region 10 does not exceed 0.08 μm.
[0061] In this embodiment, along the X direction, the minimum spacing D3 between the gate polysilicon 21 and the conductive plug 31 on the surface of the active region 10 is 0.08 μm.
[0062] Better, for reference Figure 5 Along the Y direction, the minimum distance D4 between the conductive plug 31 and the shallow trench isolation structure 12 on the surface of the active region 10 does not exceed 0.02 μm.
[0063] In this embodiment, along the Y direction, the minimum distance D4 between the conductive plug 31 and the shallow trench isolation structure 12 on the surface of the active region 10 is 0.02 μm.
[0064] Further reference Figure 5 The minimum dimension D5 of each of the shallow trench isolation structures 12 along the Y direction does not exceed 0.3 μm, that is, along the Y direction, the minimum dimension D5 between the two active regions 10 on both sides of any one of the shallow trench isolation structures 12 does not exceed 0.3 μm.
[0065] In this embodiment, the minimum dimension D5 of each of the shallow trench isolation structures 12 along the Y direction is 0.3 μm, that is, along the Y direction, the minimum dimension D5 between the two active regions 10 on both sides of any one of the shallow trench isolation structures 12 is 0.3 μm.
[0066] Preferably, D1, D2, D3, D4, and D5 all conform to the design rules.
[0067] Based on the same inventive concept, the present invention also provides a test method based on the semiconductor test structure, wherein a first voltage is applied to the first shank 42 of the semiconductor test structure, a second voltage lower than the first voltage is applied to the second shank 52 of the semiconductor test structure, and leakage current between the first comb tooth portion and the second comb tooth portion of the semiconductor test structure is detected. If the leakage current between the first comb tooth portion and the second comb tooth portion is <1.0E-012A, it is determined that there are no voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction and that no short circuit occurs between adjacent conductive plugs; when the leakage current between the first comb tooth portion and the second comb tooth portion is >1.0E-09A, it is determined that there are voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction, causing a short circuit between adjacent conductive plugs.
[0068] Preferably, a first voltage is applied to the first test pad 71 of the semiconductor test structure, and a second voltage lower than the first voltage is applied to the second test pad 72 of the semiconductor test structure.
[0069] In this embodiment, the first voltage is 1.1Vdd, and the second voltage is 0V. The value of Vdd is greater than 0V and less than or equal to 5.5V.
[0070] Subsequently, the leakage current between the first comb portion and the second comb portion of the semiconductor test structure is detected. If the leakage current between the first comb portion and the second comb portion is <1.0E-012 amperes (A), it is determined that there are no voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction and that no short circuit occurs between adjacent conductive plugs. If the leakage current between the first comb portion and the second comb portion is >1.0E-09 amperes (A), it is determined that there are voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction, causing a short circuit between adjacent conductive plugs.
[0071] In this application, each row / each row (X direction) of conductive plugs is connected by a first interdigitated structure and a second interdigitated structure. According to the actual given test conditions, a potential difference is formed between the first test pad and the second test pad. This allows for timely and effective monitoring of whether there are voids in the interlayer dielectric layer between adjacent conductive plugs in each row (X direction) during the wafer electrical acceptance test (WAT) before shipment from the wafer fabrication plant. This can lead to short circuits between adjacent conductive plugs and can promptly detect products with short circuits between adjacent conductive plugs, thereby improving the timeliness and reliability of monitoring and ensuring the yield of shipped products.
[0072] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A semiconductor test structure, characterized by, include: A substrate in which an active region is formed; Multiple shallow trench isolation structures are provided, each of which is disposed in the active region along the X direction, and the multiple shallow trench isolation structures are distributed at intervals in the active region along the Y direction. Multiple gate structures are disposed on the surface of the substrate along the Y direction, and the multiple gate structures are spaced apart on the surface of the substrate along the X direction; An interlayer dielectric layer covering the gate structure, the active region, and the shallow trench isolation structure; Multiple conductive plugs are spaced apart along the Y direction in the interlayer dielectric layer between the gate structures, and each conductive plug is in contact with the surface of the active region between the shallow trench isolation structures. as well as, The first interdigital structure and the second interdigital structure, wherein... The first interdigitated structure includes: a first shank and a plurality of first comb teeth; The second interdigitated structure includes: a second shank and a plurality of second comb teeth; All the first comb teeth and all the second comb teeth are respectively disposed on the interlayer dielectric layer along the X direction and respectively cover all the conductive plugs in the corresponding row, and the first comb teeth and the second comb teeth are staggered along the Y direction; the first handle is disposed on the interlayer dielectric layer along the Y direction and is connected to the left end of all the first comb teeth; the second handle is disposed on the interlayer dielectric layer along the Y direction and is connected to the right end of all the second comb teeth.
2. The semiconductor test structure of claim 1, wherein, The semiconductor testing structure also includes: The first test pad is located on the interlayer dielectric layer and is connected to the first handle. The second test pad is located on the interlayer dielectric layer and is connected to the second handle.
3. The semiconductor test structure of claim 1, wherein, Each of the gate structures includes: a gate polysilicon and a sidewall structure, wherein the gate polysilicon is disposed on the substrate surface along the Y direction, and the sidewall structure is disposed on the substrate surface along the Y direction and covers the side surfaces on both sides of the gate polysilicon.
4. The semiconductor test structure of claim 3, wherein, Along the X direction, the minimum spacing between adjacent gate polysilicon cells covering the surface of the shallow trench isolation structure does not exceed 0.21 μm.
5. The semiconductor test structure according to claim 3, characterized in that, Along the X direction, the minimum spacing between adjacent gate polysilicon cells covering the surface of the active region does not exceed 0.28 μm.
6. The semiconductor test structure according to claim 3, characterized in that, Along the X direction, the minimum spacing between the gate polysilicon and the conductive plug on the surface of the active region does not exceed 0.08 μm.
7. The semiconductor test structure according to claim 1, characterized in that, Along the Y direction, the minimum distance between the conductive plug and the shallow trench isolation structure on the surface of the active region does not exceed 0.02 μm.
8. The semiconductor test structure according to claim 1, characterized in that, The minimum dimension of each of the shallow trench isolation structures along the Y direction does not exceed 0.3 μm.
9. The semiconductor test structure according to claim 1, characterized in that, The semiconductor test structure further includes: a well region of a first conductivity type and a heavily doped region of a second conductivity type, wherein the well region is located in the active region and the heavily doped region is located in the well region near the upper surface of the well region.
10. A testing method based on the semiconductor test structure of claim 1, characterized in that, A first voltage is applied to the first shank of the semiconductor test structure, and a second voltage lower than the first voltage is applied to the second shank of the semiconductor test structure. The leakage current between the first comb tooth and the second comb tooth is detected. If the leakage current between the first comb tooth and the second comb tooth is <1.0E-012A, it is determined that there are no voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction and that the adjacent conductive plugs are not short-circuited. If the leakage current between the first comb tooth and the second comb tooth is >1.0E-09A, it is determined that there are voids in the interlayer dielectric layer between adjacent conductive plugs along the X direction, which causes the adjacent conductive plugs to short-circuit.