A method and system for locating an abnormal process

Abstract

This application discloses a method and system for locating abnormal processes in superconducting quantum chip manufacturing. The method for locating abnormal processes leading to superconducting quantum chip defects includes: providing a test structure with a coating; determining, through microscopic inspection, that the coating in the test structure does not have morphological defects that would cause an open circuit; performing electrical measurements to determine the quality of the coating based on its resistance in the test structure. The above detection method can be conveniently used to determine whether there are problems with the manufacturing process of the connection structure used to connect the bit capacitor and the ground plane in a superconducting quantum chip.

Description

Technical Field

[0001] This application belongs to the field of quantum information, especially the field of superconducting quantum chip manufacturing. In particular, this application relates to a method and system for locating anomalies in a process. Background Technology

[0002] Currently, the fabrication of superconducting quantum chips with multiple superconducting qubits requires the creation of bandage structures. These bandage structures are used to interconnect the Josephson junctions that make up the qubits with other structures that constitute the qubits.

[0003] During the aforementioned bandage fabrication process, an open circuit may occur when measuring the resistance of the interconnected Josephson junction. Since the entire interconnect fabrication process includes photolithography and deposition of the Josephson junction and photolithography and deposition of the bandage structure, it is impossible to immediately identify which step's malfunction caused the open circuit. Summary of the Invention

[0004] The examples in this application provide a method and system for locating abnormal processes, which can be used to detect certain process steps in the manufacturing process of superconducting quantum chips—determining which step is abnormal, thereby optimizing the manufacturing process of superconducting quantum chips.

[0005] The solution presented in this application is implemented through the following steps.

[0006] In a first aspect, the method for locating process defects causing anomalies in superconducting quantum chips, as exemplified in this application, includes:

[0007] Provides a test structure with a coating;

[0008] Microscopic inspection confirmed that the coating in the test structure did not contain any morphological defects that would cause an open circuit.

[0009] Electrical measurements are performed to pinpoint abnormal processes based on the resistance of the coating in the test structure.

[0010] Based on some examples from this application, the test structure also includes:

[0011] First superconducting thin film;

[0012] The second superconducting film is separated from the first superconducting film;

[0013] One end of the coating is electrically connected to the first superconducting thin film, and the other end of the coating is electrically connected to the second superconducting thin film.

[0014] According to some examples of this application, the coating is elongated and has a first end and a second end;

[0015] The coating is electrically connected to the first superconducting thin film through the first end, and the coating is electrically connected to the second superconducting thin film through the second end.

[0016] According to some examples of this application, the microscopic inspection method includes: identifying the presence of a first component and a second component that are not physically connected from an optical image of the coating;

[0017] The first end is located in the first component, and the second end is located in the second component.

[0018] According to some examples of this application, the first superconducting thin film and the second superconducting thin film are manufactured simultaneously in the same step.

[0019] According to some examples of this application, the first superconducting thin film and the coating are manufactured in different steps, and the second superconducting thin film and the coating are manufactured in different steps.

[0020] According to some examples of this application, the first superconducting thin film and the second superconducting thin film are manufactured before coating.

[0021] According to some examples of this application, a first region and a second region are defined in a superconducting quantum chip for arranging two adjacent and coupled superconducting qubits;

[0022] The first region contains superconducting qubits, and the test structure is located in the second region.

[0023] According to some examples of this application, the first superconducting thin film is a portion of the ground plane of the superconducting quantum chip, and the second superconducting thin film is the bit capacitance of the superconducting quantum bit in the superconducting quantum chip;

[0024] And / or, methods for electrical measurement include:

[0025] The measurement system is assembled by making electrical contact between the electrodes used to measure resistance using a two-electrode method or a four-electrode method and the first and second superconducting thin films, respectively.

[0026] The resistance value of the coating is determined by measuring the system.

[0027] In a second aspect, examples of this application disclose a system for implementing the aforementioned method for locating anomalies, and the system includes:

[0028] Coating apparatus for manufacturing test structures with coatings;

[0029] Microscopic inspection apparatus for performing microscopic inspection to determine whether the coating in the test structure contains morphological defects that could cause an open circuit; and

[0030] An electrical measuring device is used to perform electrical measurements and locate abnormal processes based on the resistance of the coating in the test structure.

[0031] Beneficial effects:

[0032] In the above implementation process of this application, a test structure with a coating is constructed. Based on this, by conducting microscopic and electrical tests, it is possible to more accurately determine whether there are any abnormalities in the device during the fabrication of superconducting qubits, and if so, the steps that cause the abnormality; that is, to locate the process that leads to the abnormality. Attached Figure Description

[0033] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.

[0034] Figure 1 This is a schematic diagram of the structure of the superconducting quantum bit in the example of this application;

[0035] Figure 2 A schematic diagram of the test structure in the example of this application is disclosed;

[0036] Figure 3 A flowchart illustrating the process for locating abnormalities in the example of this application is disclosed;

[0037] Figure 4 It shows the relationship with Figure 2 A schematic diagram of the coating structure showing the presence of microscopic breakage defects for comparison with the test structure. Detailed Implementation

[0038] Quantum computing is receiving increasing attention and research both domestically and internationally. Among them, superconducting qubit systems based on Josephson junctions are considered one of the most promising systems for realizing quantum computing.

[0039] As a key component of quantum chips, superconducting qubits are mainly composed of superconducting circuits containing one or more Josephson junctions. The Josephson junction is generally composed of two superconducting layers with an extremely thin insulating layer (barrier layer) sandwiched between them. When the thickness of the insulating layer is as thin as a few nanometers, a significant electron pair tunneling effect occurs, which is the Josephson effect.

[0040] In practical implementation, superconducting qubits (transfer qubits) of the Transmon form are shaped like a "+". They consist of a large cross-shaped capacitor and a relatively small superconducting circuit containing a Josephson junction connected to the capacitor; the superconducting qubit essentially forms a two-level system.

[0041] For frequency-tunable superconducting qubits, the superconducting circuit containing Josephson junctions has two Josephson junctions in a loop, and it is described as consisting of a superconducting quantum interference device (SQUID).

[0042] In the fabrication of chips based on or above, micro-nano fabrication techniques such as electron beam masking, low-temperature development, oblique evaporation deposition, and metal stripping are used to fabricate various electronic components.

[0043] In the actual manufacturing process, some solutions require the creation of a bandage structure (or described as a binding structure). This bandage is used to interconnect the Josephson junction with the larger structure.

[0044] Large structures refer to quantum circuits relative to the linewidth of a Josephson junction, such as various signal transmission lines, readout resonators, and various bit control lines and readout lines.

[0045] As in this application Figure 1 In the example shown, the large structure includes a bit capacitor 101 that constitutes a superconducting quantum bit, and a ground plane 102 that provides a reference potential in the superconducting quantum chip.

[0046] Furthermore, the superconducting qubit has a SQUID (superconducting quantum interference device) composed of two Josephson structures. The SQUID includes two horizontal electrodes 201 and one vertical electrode 202.

[0047] Patches 203 are connected to the ends of each electrode to connect the Josephson junction to portions of the external circuitry (such as the aforementioned ground plane 102 and bit capacitor 101). A bandage 204 is also provided between the patch 203 and the external circuitry.

[0048] During this process, an open circuit may occur when measuring the resistance of the interconnected Josephson junction. However, because the entire process of fabricating the interconnect structure includes photolithography, deposition, and etching operations for Josephson junctions and bandage structures, it is impossible to immediately identify which process step caused the open circuit defect. This defect could be due to a problem in the process design, or it could be that the process design is sound but an error occurred during actual operation.

[0049] In view of the above problems, this application discloses a test structure. This test structure can be used to conveniently confirm whether the aforementioned open circuit anomaly occurs at a specified node in the process, and more specifically, for example, it can be used to confirm and identify whether the open circuit anomaly occurs during the bandage coating process.

[0050] Based on the study of the process, the applicant believes that the bandage coating process mainly includes IBE (Ion Beam Etching) and the preparation of superconducting metal films.

[0051] The purpose of IBE is to remove the oxide layer at the junction of the large structure and the Josephson junction (JJ) region through an ion source etching process, so as to ensure that subsequent coatings can achieve conductivity (i.e., no circuit break).

[0052] The superconducting metal coating is formed after etching with an ion source to achieve interconnection between the large structure and the junction. The superconducting metal coating can have different thicknesses depending on the thickness of the large structure and the junction, and the thickness of the superconducting metal coating can be set differently in different superconducting quantum chips.

[0053] Therefore, based on the above analysis, the possible anomalies during bandage coating include the two aspects mentioned above. If there are gaps or other anomalies—such as a broken bandage—these can be directly observed using an electron microscope or optical microscope. However, anomalies in ion source etching are not easily confirmed using a microscope because other interfering processes are present.

[0054] Therefore, it can be concluded that if there are no abnormalities on the surface of the entire interconnect structure, it is not possible to directly confirm that the open circuit is caused by an abnormality in the ion source, because the entire structure contains many processes, and each process needs to be eliminated one by one.

[0055] Based on the above considerations, in this application, the applicant proposes a test structure to confirm whether the inability to measure resistance is due to defects or problems in the bandage coating process. More specifically, it can be used to locate whether the problem is caused by the etching operation, i.e., whether the etching process has failed to fully remove insulating oxide layers, resulting in an open circuit in the coating.

[0056] Specifically, in this example, this application discloses a test structure for locating abnormal processes.

[0057] This test structure can be configured into a superconducting quantum chip, and the test structure is adjacent to the superconducting qubit configuration in the superconducting quantum chip.

[0058] In instances where the test structure is built into a superconducting quantum chip, the superconducting quantum chip can be a test-oriented superconducting quantum chip; that is, a chip used to verify or develop manufacturing processes, rather than a commercially available chip intended for mass production. However, this is not a limiting requirement; in other examples, the test structure can also be constructed into a chip intended for commercial sale.

[0059] Furthermore, considering factors such as coating process, coating quality, and layout design, the test structure in the example can be configured close to the superconducting qubits in the superconducting quantum chip. This allows the test structure to be manufactured synchronously with the fabrication steps of the component of interest under test within the superconducting qubit (e.g., undergoing the same coating process), enabling the quality of the coating on the test structure to evaluate the quality of the fabrication process of the aforementioned "component of interest under test." For example, the coating can be manufactured simultaneously with the bandage fabrication. If the coating process is problem-free, the issue likely lies in the etching process preceding the coating.

[0060] In this context, "proximity" refers, for example, to the region between two adjacent superconducting qubits coupled to each other in a superconducting quantum chip (or a region without functional components). More specifically, in some examples, "proximity" can refer to the region between the bit capacitances (such as cross capacitors) of two adjacent superconducting qubits. In other examples, "proximity" can also refer to the vicinity of the Josephson junction of a superconducting qubit.

[0061] In some specific and alternative examples, the test structure can be constructed within the region of the test node—that is, the Josephson node used for testing. For example, Figure 1 A formal structural diagram of the Josephson knot has been published, demonstrating the presence of the Josephson knot. Figure 2 The test structure shown can be formed in the region of the Josephson node used for testing—although the Josephson node is not contained in this region.

[0062] See the example. Figure 2 The test structure 300 includes a first superconducting thin film 301, a second superconducting thin film 302, and an electrically conductive trace 303.

[0063] A first superconducting thin film and a second superconducting thin film are formed on the surface of a substrate and are spaced apart from each other. Advantageously, the first and second superconducting thin films are coplanar with respect to the substrate. In some examples, they may have the same thickness; wherein the thickness is obtained by measuring perpendicularly to the substrate surface.

[0064] The first and second superconducting thin films can be fabricated simultaneously in the manufacture of superconducting quantum chips.

[0065] For example, in the fabrication of a superconducting quantum chip, after depositing a superconducting thin film layer on a substrate, a first superconducting thin film and a second superconducting thin film are simultaneously formed by patterning the film (e.g., etching to remove some material). For an aluminum-based superconducting quantum chip, the superconducting layer can be an aluminum thin film. The patterning operation can involve using photoresist and a photomask to form a patterned mask, followed by etching to form the superconducting quantum circuits and components.

[0066] Since the first and second superconducting thin films are used for the test structure, it can be understood that when arranging other superconducting qubits and their corresponding readout and control circuits in the superconducting quantum chip, space can be reserved for this test structure. Furthermore, the first and second superconducting thin films can be fabricated within this reserved space. Alternatively, this reserved space can also be a region initially designed for qubit fabrication, thus being converted into a test structure.

[0067] In the example, the first superconducting thin film can be the ground plane of the superconducting quantum chip, and the second superconducting thin film can be the bit capacitance in the superconducting quantum circuit that constitutes the superconducting qubit. Therefore, in some examples, the second superconducting thin film in the test structure can also have the same structure as the bit capacitance of the superconducting qubit. For example, the second superconducting thin film can be constructed as a cross capacitor in some bits; it can also be a bit capacitance structure of other forms.

[0068] Accordingly, in some examples, the first and second superconducting thin films may not be specially manufactured, but are formed during the fabrication of superconducting qubits, in the step of forming coating windows by photolithography and etching to form thin films for fabricating the devices in the qubits.

[0069] In addition to discussing the structure and materials, the distance between the first and second superconducting thin films can also be chosen. Based on the example above where the first superconducting thin film is constructed as a ground plane and the second superconducting thin film is constructed as a bit capacitor, the distance between the first and second superconducting thin films can be defined as a first gap; and this first gap is limited by the distance between the bit capacitor in the superconducting quantum bit and the ground plane. This means that the length of the coating / conductive trace in the test structure is also limited by this first gap, that is, in the example, the length of the conductive trace is at least greater than the first gap. The length of the conductive trace can be a distance measured perpendicularly to the first and second superconducting thin films.

[0070] Based on the above discussion of the first and second superconducting thin films, the conductive traces in the test structure are configured accordingly.

[0071] Structurally, in some examples, conductive traces can be constructed to reduce the number of process steps caused by structural complexity, thereby avoiding the uncertainties introduced by too many process steps. In other words, simple conductive trace structures can reduce the influencing factors that need to be considered during testing, thus simplifying the judgment criteria and enabling more accurate identification / location of key indicators or process steps.

[0072] However, a simple structure is not a specific limitation on the construction method of the conductive trace. In other examples, the conductive trace can also be constructed to be relatively more complex. That is, the structural form of the conductive trace can be constructed according to actual needs without particular limitation. For example, the length, width, etc. of the conductive trace can be designed according to the region between the first superconducting film and the second superconducting film (e.g., the distance / spacing between them, shape, etc.).

[0073] In some examples, the conductive traces can be straight lines, such as rectangles or trapezoids. To avoid potential problems with a single conductive trace, multiple conductive traces can be manufactured to prevent issues arising from a single trace that could lead to inaccurate process determination due to other factors (potentially unrelated to the coating process of the component of interest under test).

[0074] Generally, conductive traces can be manufactured synchronously with the actual manufacturing process steps of interest in the testing method, thus avoiding negative impacts from other processes or device structures. Furthermore, the conductive traces can be manufactured after the first and second superconducting thin films have been fabricated.

[0075] In the example, the conductive traces can be made of the same material as the first and second superconducting thin films, for example, all three can be made of aluminum, a superconducting material. In other examples, the three materials can also be independently selected as tantalum, titanium nitride, niobium, etc. That is, the three materials can be the same, and of course, they can also be different.

[0076] like Figure 2 As shown, the two ends of the conductive trace are electrically connected to the first and second superconducting thin films, respectively. That is, the ends of the conductive trace rest on the surface of the superconducting thin film. For a generally elongated conductive trace, the trace has two ends along its length or the direction of its extension, and these two ends (which can be described as the first end and the second end for ease of discussion) rest on the superconducting thin film. For example, the conductive trace achieves electrical contact by having its first end rest on the first superconducting thin film; the conductive trace achieves electrical contact by having its second end rest on the second superconducting thin film.

[0077] In other examples, if necessary, the ends (which may be partial) of the conductive traces can be embedded in the superconducting thin film—this may mean that the superconducting film needs to be etched to some extent. However, this may require more precise control over the etching process.

[0078] To reduce uncontrollable factors, or in other words, to simplify the process of locating anomalies, the two ends of the conductive trace can be made to overlap with the superconducting thin film at the same size. For example, in an example where the projected shape of the conductive trace is rectangular in the direction perpendicular to the chip surface, the overlap portion is a rectangular structure. Therefore, the aforementioned same size can refer to the overlap length—in Figure 2 In the examples shown, the overlap lengths are D1 and D2, and D1 and D2 are different; however, in other examples, D1 and D2 can be the same. In other words, the conductive trace overlaps with the first superconducting film, the conductive trace overlaps with the second superconducting film, and the overlap length between the conductive trace and the first superconducting film is equal to the overlap length between the conductive trace and the second superconducting film.

[0079] The length of the conductive traces has been discussed above, for example, determined by the spacing between the first and second superconducting films. Furthermore, the width of the conductive traces can also be discussed. Generally, the width of the conductive traces can be any suitable value; in the examples of this application, there is no particular limitation on the width of the conductive traces.

[0080] In some examples, the width of the conductive trace can be the same as its length; for example, the length and width of the conductive trace are equal. Alternatively, the width of the conductive trace may be less than its length; or the width of the conductive trace may be greater than its length.

[0081] Furthermore, the width of the conductive trace can also be configured differently depending on its shape. For example, the width of the conductive trace remains constant within its length direction—corresponding to a rectangular conductive trace; or, the width of the conductive trace varies (e.g., gradually) within its length direction—corresponding to a trapezoidal conductive trace.

[0082] In summary, the scheme described in this application discloses a test structure for identifying processes (which can be described as anomalous processes) that cause anomalies in superconducting quantum chips (more specifically, superconducting qubits). For example, in some of the examples above, this scheme can be used to determine whether the anomalous process is an etching process prior to the deposition of the bandage film.

[0083] Based on the above test structure, a superconducting quantum chip with this test structure is also disclosed in the example.

[0084] Depending on the design, the test structure can be located at the edge of the superconducting quantum chip; for example, at the edges of the chip's substrate. Alternatively, the test structure can be located in the center of the chip; for example, in the region defined by the intersection of the diagonals of the substrate in a rectangular structure of the chip.

[0085] The superconducting quantum chip can be further configured with various other superconducting quantum circuits and components—such as coupling structures between qubits, or components for manipulating or reading qubits, etc. These components, circuits, and other structures can be manufactured and laid out using methods commonly used in the field of superconducting quantum chips, and this application does not impose specific limitations on them.

[0086] Building upon this, the examples in this application also disclose a method for locating anomalous processes in a superconducting quantum chip that cause chip anomalies using the above-described test structure. Specifically, the examples disclose a method for locating anomalous processes.

[0087] See Figure 3 The method for locating abnormal processes includes the following steps:

[0088] Step S101: Provide a test structure with a coating;

[0089] Step S102: Determine by microscopic inspection that there are no morphological defects in the coating of the test structure that would cause an open circuit;

[0090] Step S103: Perform electrical measurements and locate abnormal processes based on the resistance of the coating in the test structure.

[0091] As mentioned earlier, this method for locating abnormal processes can be used to determine the coating quality of the aforementioned bandage—such as the quality of the coating process itself, or the quality of the etching process preceding coating. In this way, it can be determined whether the bandage's coating / etching process needs optimization or improvement to achieve better manufacturing processes during the development of superconducting quantum chips. Therefore, the optimized bandage coating process identified based on this can be used to manufacture high-quality bandages with structures such as… Figure 1 The superconducting qubits described in the text are then used to construct superconducting quantum chips by configuring corresponding quantum circuits.

[0092] In an application example that identifies coating anomalies that cause bandage, the test structure includes a first superconducting thin film, a second superconducting thin film, and conductive traces.

[0093] The first and second superconducting thin films are separate from each other. A conductive trace is located between the first and second superconducting thin films, and the two ends of the conductive trace (such as the first end and the second end, as described later) are electrically connected to the first and second superconducting thin films, respectively.

[0094] In other words, one end of the coating is electrically connected to the first superconducting thin film, and the other end of the coating is electrically connected to the second superconducting thin film. Furthermore, since the coating is implemented as a conductive trace, it can be understood that it has a generally elongated structure, and therefore has a first end and a second end extending in the length direction. Based on this, the coating is electrically connected to the first superconducting thin film through the first end, and the coating is electrically connected to the second superconducting thin film through the second end.

[0095] In different examples, the first superconducting thin film, the second superconducting thin film, and the coating can have different manufacturing sequences. Furthermore, to reduce the difficulty of identifying abnormal processes due to excessive process steps leading to structural anomalies, the manufacturing steps of the coating are usually asynchronous with those of the first and second superconducting thin films.

[0096] Specifically, in some examples, the first and second superconducting thin films are fabricated simultaneously in the same step; in other examples, they may be fabricated separately in different steps. In some examples, the first superconducting thin film and the coating are fabricated in different steps, and the second superconducting thin film and the coating are fabricated in different steps. Considering the fabrication process steps of superconducting qubits, in the examples of this application, the first and second superconducting thin films are fabricated before the coating.

[0097] A desirable option is to simultaneously fabricate the first and second superconducting thin films in the test structure during the fabrication of the superconducting qubits when manufacturing the quantum chip, and then simultaneously fabricate the coating in the test structure when fabricating the bandage in the qubit.

[0098] Therefore, it can be understood that a first region and a second region can be predefined in a superconducting quantum chip for arranging two adjacent and coupled superconducting qubits. Based on this, superconducting qubits are fabricated in the first region, and thus, the first region is described as the formal bit region. Correspondingly, the test structure is configured in the second region, and thus, the second region is described as the test bit region (although no bits are configured in this region—at least not the Josephson junctions that constitute the bits).

[0099] Furthermore, in order to evaluate the coating quality and process of the target device (which could be the aforementioned bandage or the aforementioned patch 203; or other components), the coating can be fabricated in the test bit region while the target device is fabricated in the aforementioned formal bit region. In such an example, the first superconducting thin film can be a structure located in the aforementioned test bit region that serves as part of the ground plane of the superconducting quantum chip, while the second superconducting thin film can be a structure located in the aforementioned test bit region that serves as the bit capacitance of the superconducting quantum bit in the superconducting quantum chip.

[0100] In step S101 above, the fabrication of the test structure can be achieved through micro-nano processes in the art, and the process may involve operations such as deposition, photolithography, and etching.

[0101] Deposition is used to fabricate thin films, and can be described, for example, as coating. Photolithography is used to form a patterned mask so that the thin film can be formed by deposition. Etching can modify the surface morphology of the deposited thin film or circuit, and remove surface oxides, impurities, etc.

[0102] Briefly, depending on the material to be deposited, deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxial techniques, and other deposition processes can be used. Exemplary deposition processes include, but are not limited to, ion beam assisted deposition (IBAD), evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), chemical vapor deposition (CVD), sol-gel deposition, and magnetron sputtering.

[0103] Furthermore, and depending on the material to be removed, the removal process may include, but is not limited to, wet etching, dry etching, or lift-off processes. During this process, known lithographic techniques (e.g., ultraviolet light exposure or electron beam exposure) can be used to pattern the thin film of material forming the circuit elements described herein.

[0104] For the sake of brevity, the conventional technologies associated with the manufacture of semiconductors and / or superconducting devices and integrated circuits (ICs) may or may not be described in detail in the above description.

[0105] Furthermore, the various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes with additional steps or functionalities not described in detail herein. In particular, the various steps in the fabrication of semiconductor and / or superconducting devices and semiconductor / superconductor-based ICs are well-known, and therefore, for the sake of brevity, many routine steps will be mentioned only briefly or will be omitted entirely without providing well-known process details.

[0106] In step S102, microscopic inspection is used to determine that the coating in the test structure does not have morphological defects that would cause an open circuit. This step focuses on whether there are explicit structural defects in the coating in the test structure that are sufficient to cause an open circuit when electrical measurements are performed from both ends of the coating.

[0107] Therefore, the microscopic detection method in the example may include: identifying the presence of a first and second component that are not physically connected from an optical image of the coating. For ease of understanding, the scenarios of conductive traces having both physically connected and physically disconnected portions can be illustrated. Please refer to... Figure 2 and Figure 4 ;in Figure 2 A schematic diagram of the structure of conductive trace 303 without two unconnected parts is shown. Figure 4 A schematic diagram showing conductive traces of a first component 403 and a second component 404 that are not physically connected is illustrated. Furthermore, depending on the arrangement of the coating, in... Figure 4 In the scheme shown, the first end 401 is located in the first component 403, and the second end 402 is located in the second component 404.

[0108] Specific microscopic inspections can include, for example, taking pictures of the area of ​​interest using a microscope to obtain corresponding images; then, visually determining whether there are any breaks in the coating; or directly observing the microscopic image using the equipment without taking pictures. If there are no breaks, proceed to the next step S103.

[0109] In some examples, in step S102, the microscope may be an electron microscopy imaging scheme, and more specifically, alternatively, a scanning electron microscope (SEM), a scanning tunneling microscope (STM), or an atomic force microscope (AFM); in other examples, the microscope may be an optical microscope.

[0110] In step S103, the electrical measurement method includes: assembling a measurement system by having the electrodes for measuring resistance using a two-electrode method or a four-electrode method (Kelvin method) respectively make electrical contact with the first superconducting thin film and the second superconducting thin film; and then determining the resistance value of the coating by detecting the resistance value through the measurement system.

[0111] The two-electrode method involves two electrodes; one electrode contacts a first superconducting thin film, and the other electrode contacts a second superconducting thin film. The four-electrode method involves four electrodes; two electrodes (separate from each other) contact the first superconducting thin film, and the other two electrodes (separate from each other) contact the second superconducting thin film. The four-electrode method separates the current and voltage electrodes, eliminating the influence of wiring and probe contact resistance.

[0112] The resistance of the coating can be obtained through the above method, and the coating quality can be judged accordingly. Since it has been determined by microscopic inspection in step S102 that the coating has no visible structural defects, if the resistance of the coating cannot be measured (or is infinitely large) in step S103, it indicates that there is a problem with the contact between the coating and the first and second superconducting films (i.e., no good electrical contact); that is, the circuit is open. This may be because the etching operation on the surface of the superconducting film before coating failed to remove the dirt, oxides, and other substances that could cause insulation from its surface as intended. That is, the etching operation did not perform as expected, while the coating operation was performed smoothly as expected; therefore, it can be determined that the coating abnormality in the bandage example is due to the etching operation; that is, the abnormal process located is the etching operation (such as ion beam etching) before the bandage is deposited.

[0113] On the other hand, since microscopic inspection in step S102 has confirmed that the coating has no visible structural defects, the measurement of the coating's resistance in step S103 indicates good contact between the coating and the first and second superconducting thin films. In other words, both the coating quality and the superconducting etching operation before coating proceeded smoothly as expected.

[0114] Furthermore, to facilitate the implementation of the above-described method for locating abnormalities, a system for locating abnormalities is also disclosed in the example. This system includes a coating apparatus, a microscopic inspection apparatus, and an electrical measurement apparatus.

[0115] The coating apparatus is used to manufacture test structures with coatings. The coating apparatus can be various deposition coating equipment, such as physical vapor deposition equipment or chemical vapor deposition equipment.

[0116] Microscopic inspection equipment is used to perform microscopic inspection to determine whether the coating in the test structure has morphological defects that could cause an open circuit.

[0117] Electrical measuring devices are used to perform electrical measurements and determine the quality of the coating based on the continuity or open circuit of the coating in the test structure. For example, it can be a combination of measuring instruments such as ammeters and voltmeters.

[0118] The embodiments described above with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0119] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments have been described above with reference to the accompanying drawings. Throughout the description, similar reference numerals are used to denote similar components. In the foregoing description, numerous specific details have been set forth for illustrative purposes in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the embodiments may be combined with and referenced to each other without contradiction.

[0120] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0121] The above description of the structure, features and effects of this application is based on the embodiments shown in the drawings. The above are only preferred embodiments of this application. However, this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for locating abnormal processes, used to locate processes that cause abnormalities in superconducting quantum chips, characterized in that, The method for locating abnormal processes includes: Provides a test structure with a coating; Microscopic inspection confirmed that the coating in the test structure did not contain any morphological defects that would cause an open circuit. Electrical measurements are performed, and the abnormal process is located based on the resistance of the coating in the test structure.

2. The method of positioning an abnormal process of claim 1, wherein, The test structure also includes: First superconducting thin film; The second superconducting film is separated from the first superconducting film; One end of the coating is electrically connected to the first superconducting thin film, and the other end of the coating is electrically connected to the second superconducting thin film.

3. The method of positioning an abnormal process of claim 2, wherein, The coating is elongated and has a first end and a second end; The coating is electrically connected to the first superconducting thin film through the first end, and the coating is electrically connected to the second superconducting thin film through the second end.

4. The method of positioning an abnormal process of claim 3, wherein, The microscopic inspection method includes: identifying, from the optical image of the coating, whether there is a first component and a second component that are not physically connected; The first end is located in the first component, and the second end is located in the second component.

5. The method of positioning an abnormal process of claim 2, wherein, The first superconducting thin film and the second superconducting thin film are manufactured simultaneously in the same step.

6. The method of positioning an abnormal process of claim 5, wherein, The first superconducting thin film and the coating are manufactured in different steps, and the second superconducting thin film and the coating are manufactured in different steps.

7. The method of positioning an abnormal process of claim 2 or 5 or 6, wherein, The first superconducting thin film and the second superconducting thin film are manufactured before the coating.

8. The method of positioning an abnormal process of claim 7, wherein, The superconducting quantum chip has a first region and a second region defined for arranging two adjacent and coupled superconducting qubits. The first region is fabricated with superconducting qubits, and the test structure is configured in the second region.

9. The method of positioning an abnormal process of claim 2, wherein, The first superconducting thin film is part of the ground plane of the superconducting quantum chip, and the second superconducting thin film is the bit capacitance of the superconducting quantum bit in the superconducting quantum chip; And / or, methods for electrical measurement include: The measurement system is assembled by making electrical contact between the electrodes used to measure resistance using a two-electrode method or a four-electrode method and the first and second superconducting thin films, respectively. The resistance value of the coating is determined by the measurement system.

10. A system for locating anomalies, used to implement the method for locating anomalies according to any one of claims 1 to 9, characterized in that, The system includes: A coating apparatus for manufacturing the test structure having the coating; Microscopic inspection apparatus for performing microscopic inspection to determine whether the coating in the test structure contains morphological defects that would cause an open circuit; and An electrical measuring device is used to perform electrical measurements and locate abnormal processes based on the resistance of the coating in the test structure.

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