Test method for recycled wafer control tablets and recycled wafer control tablets

Abstract

The testing method and regenerated wafer control wafer provided in this invention relate to the field of regenerated wafer technology. It involves pre-diffusion oxidation to form a sacrificial oxide layer on the surface of the regenerated wafer control wafer. This sacrificial oxide layer can cover surface defects. Then, an etching process removes the sacrificial oxide layer, exposing the regenerated surface of the wafer control wafer. This regenerated surface closely resembles the surface quality of the virgin wafer, thus enabling more accurate testing in subsequent processes. Therefore, by optimizing the process, the surface conditions of the regenerated wafer control wafer in the testing process are made similar to those of a new wafer, improving testing results and truly realizing the application value and added value of recycled wafers.

Description

Technical Field

[0001] This invention relates to the field of regenerated wafer technology, and more specifically, to a test method and a regenerated wafer control chip. Background Technology

[0002] See Figure 1 Typically, the thermal oxidation process after a wafer arrives at the factory involves performing a thermal oxidation process on the surface of the bare wafer. During the testing phase, wafer control is needed to repeatedly perform thermal oxidation tests, which usually requires the use of reclaimed wafers.

[0003] Returned reclaimed wafers require regeneration processes; however, traditional regeneration processes often result in uneven distribution of subsurface lattice damage. Specifically, traditional lapping, polishing, or harsh wet etching processes can introduce a layer of lattice defects (dislocations, microcracks) near the wafer surface. Due to the characteristics of the process itself or equipment (such as the pressure distribution of the polishing head), the depth and density of this damaged layer often differ between the wafer edge and center. Therefore, currently, returned reclaimed wafers tend to form an oxide film that is thin in the center and thick at the edges during thermal oxidation diffusion in the furnace tube. In contrast, the film thickness uniformity of native wafers is 85% better than that of reclaimed wafers. Furthermore, long-term control charts show that the CPK (Capability Process K index) of native wafers is 52% better than that of reclaimed wafers.

[0004] Moreover, existing regeneration technologies mainly focus on macroscopic surface indicators (such as roughness Ra and particle number), lacking evaluation and repair methods for the key indicator of "subsurface lattice integrity". This leads to the long-term existence of this "hidden" problem, which is difficult for regenerated wafer manufacturers to solve. Summary of the Invention

[0005] The purpose of this invention is to provide a testing method and a regenerated wafer control wafer, which can optimize the usage process so that the surface conditions of the regenerated wafer control wafer in the testing process can be close to those of a new wafer, thereby improving the testing effect and truly realizing the application value and added value of recycled wafers.

[0006] In a first aspect, the present invention provides a testing method for regenerated wafer control wafers, comprising: Provide a recycled wafer control chip; The regenerated wafer control is preheated and oxidized under a preset atmosphere to form a sacrificial oxide layer on the growth surface of the regenerated wafer control, wherein the center thickness of the sacrificial oxide layer is less than the edge thickness and penetrates into the growth surface to a preset depth H. The sacrificial oxide layer is removed by an etching process to expose the regenerated surface of the regenerated wafer control. The regenerated wafer control wafer is subjected to a testing process to form a test sacrificial layer on the regenerated surface of the regenerated wafer control wafer; Remove the test sacrificial layer to obtain the regenerated wafer control.

[0007] In an optional embodiment, the step of preheating and oxidizing the regenerated wafer control chip under a preset atmosphere includes: The regenerated wafer control wafer is subjected to thermal oxidation at a preset temperature in an atmosphere of water vapor and oxygen, so that the water vapor and oxygen react with the growth surface of the regenerated wafer control wafer under thermal diffusion to generate a sacrificial oxide layer.

[0008] In an optional embodiment, the regenerated wafer control chip is a silicon wafer, and the sacrificial oxide layer is a silicon dioxide layer.

[0009] In an optional implementation, the preset temperature is 750℃-1100℃.

[0010] In an optional implementation, the preset depth H accounts for 45% of the thickness of the sacrificial oxide layer.

[0011] In an optional embodiment, the thickness of the sacrificial oxide layer is between 80 nm and 120 nm.

[0012] In an optional embodiment, the step of removing the sacrificial oxide layer by an etching process includes: The regenerated wafer is placed in a wet etching tank for more than 1 minute, wherein the wet etching tank is filled with an isotropic etching solution.

[0013] In an optional embodiment, the etching solution is a 49% hydrofluoric acid solution.

[0014] In an optional embodiment, prior to the step of testing the regenerated wafer control wafer, the method further includes: The regenerated wafer control chip is cleaned.

[0015] In a second aspect, the present invention provides a regenerated wafer control wafer having a regenerated surface obtained through pretreatment; the pretreatment is as follows: The growth surface of the regenerated wafer is preheated and oxidized under a preset atmosphere to form a sacrificial oxide layer with a center thickness smaller than the edge thickness and a preset depth H into the growth surface. After the sacrificial oxide layer is removed by an etching process, the regenerated surface is exposed. The beneficial effects of the embodiments of the present invention include: The present invention provides a testing method and a regenerated wafer control wafer, which first provides a regenerated wafer control wafer. Then, the regenerated wafer control wafer is preheated and oxidized under a preset atmosphere to form a sacrificial oxide layer on the growth surface of the regenerated wafer control wafer. The center thickness of the sacrificial oxide layer is less than the edge thickness, and it penetrates to a preset depth H on the growth surface. Then, the sacrificial oxide layer is removed by an etching process to expose the regenerated surface of the regenerated wafer control wafer, at which point a regenerated wafer control wafer is obtained. Next, a testing process is performed on the regenerated wafer control wafer to form a test sacrificial layer on the regenerated surface of the regenerated wafer control wafer. Finally, the test sacrificial layer is removed to obtain a new regenerated wafer control wafer for recycling.

[0016] Compared to existing technologies, the testing method and regenerated wafer control wafer provided in this invention form a sacrificial oxide layer on the surface of the regenerated wafer control wafer through pre-diffusion oxidation. This sacrificial oxide layer can cover surface defects, and then the sacrificial oxide layer is removed by etching, exposing the regenerated surface of the regenerated wafer control wafer. This regenerated surface can approach the surface quality of the virgin wafer, thus playing a more accurate role in subsequent testing processes. Therefore, by optimizing the usage process, the surface conditions of the regenerated wafer control wafer in the testing process are close to those of a new wafer, improving the testing effect and truly realizing the application value and added value of recycled wafers. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a process flow diagram of regenerated wafers in existing technology; Figure 2 A process step diagram of the testing method for regenerated wafer control provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure corresponding to steps S1 and S5 in the test method for regenerated wafer control provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S2 in the testing method for regenerated wafer control provided in this embodiment of the invention; Figure 5 This is a schematic diagram of the structure corresponding to step S3 in the testing method for regenerated wafer control provided in this embodiment of the invention; Figure 6This is a schematic diagram of the structure corresponding to step S4 in the testing method for regenerated wafer control provided in this embodiment of the invention.

[0019] Icons: 100 - Regenerated wafer control layer; 110 - Sacrificial oxide layer; 130 - Test sacrificial layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0024] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0025] As disclosed in the background section, in the prior art, reclaimed wafers are prone to forming oxide films that are thin in the middle and thick at the edges during thermal oxidation diffusion in the furnace tube. In contrast, the film thickness uniformity of native wafers is 85% better than that of reclaimed wafers. From the long-term control chart, the CPK (Capability Process Kindex) of native wafers is 52% better than that of reclaimed wafers.

[0026] To address this, current regeneration processes typically involve grinding, polishing, or vigorous wet etching to remove the surface layer with numerous defects. However, traditional regeneration processes such as lapping, polishing, or vigorous wet etching can easily introduce a layer of lattice defects (dislocations, microcracks) near the wafer surface. Due to the characteristics of the process itself or the equipment (such as the pressure distribution of the polishing head), the depth and density of this damaged layer often differ between the wafer edge and the center.

[0027] To address the aforementioned problems, embodiments of the present invention provide a novel testing method for regenerated wafer control wafers and a regenerated wafer control wafer. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0028] See Figure 2 The present invention provides a testing method for regenerated wafer control wafers and a regenerated wafer control wafer 100, which can optimize the usage process so that the surface conditions of the regenerated wafer control wafer 100 in the testing process can be close to those of new wafers, thereby improving the testing effect and truly realizing the application value and added value of recycled wafers.

[0029] This invention provides a testing method for regenerated wafer control, comprising the following steps: S1: Provide a recycled wafer control chip 100.

[0030] See also Figure 3 Specifically, a regenerated wafer control wafer 100 can first be obtained. This regenerated wafer control wafer 100 can be obtained after the previous round of testing methods, for example, it can be a regenerated wafer control wafer 100 after testing and removal processes. The surface of the regenerated wafer control wafer 100 has a defect layer, which contains defects such as dislocations.

[0031] S2: The regenerated wafer control wafer 100 is preheated and oxidized under a preset atmosphere so that a sacrificial oxide layer 110 is formed on the growth surface of the regenerated wafer control wafer 100.

[0032] See also Figure 4 The sacrificial oxide layer 110 has a center thickness smaller than its edge thickness and extends into the growth surface to a predetermined depth H. Specifically, the sacrificial oxide layer 110 is an oxide film that is thin in the middle and thick at the edges, formed during thermal oxidation diffusion.

[0033] Furthermore, the preset atmosphere can be water vapor and oxygen. In actual processing, the regenerated wafer control wafer 100 can be subjected to thermal oxidation at a preset temperature in an atmosphere of water vapor and oxygen, so that water vapor and oxygen react with the defect layer on the growth surface of the regenerated wafer control wafer 100 under the action of thermal diffusion to generate a sacrificial oxide layer 110.

[0034] It should be noted that the regenerated wafer control 100 here is a silicon wafer, and the sacrificial oxide layer 110 is a silicon dioxide layer. Therefore, in an atmosphere of water vapor and oxygen, under the thermal diffusion of H2O and O2, it reacts with the surface Si to generate a layer of SiO2 oxide, thin in the middle and thick at the edges. This SiO2 layer penetrates to a predetermined depth H in the silicon wafer. This predetermined depth H accounts for 45% of the thickness of the sacrificial oxide layer. Specifically, the thickness of the sacrificial oxide layer 110 is the sum of the predetermined depth H and the thickness increase at the growth surface. The predetermined depth H can be controlled by adjusting the atmosphere concentration and reaction time. Furthermore, this predetermined depth H can be determined by measuring the thickness of the initial regenerated wafer control 100; it is a constant value. By setting this proportional value, repeated testing of the regenerated wafer control 100 is ensured.

[0035] It is worth noting that the preset temperature here is 750℃-1100℃. The thickness of the sacrificial oxide layer 110 is between 80nm and 120nm, preferably 100nm. After the tested regenerated wafer control wafer 100 is taken off the production line, it is first subjected to thermal oxidation at atmospheric pressure 750℃-1100℃ to form a diffused silicon dioxide layer of about 100nm.

[0036] S3: Remove the sacrificial oxide layer 110 by etching process to expose the regenerated surface of the regenerated wafer control 100.

[0037] See also Figure 5 Specifically, the regenerated wafer control 100 is placed in a wet etching bath for at least 1 minute, wherein the wet etching bath contains an isotropic etching solution. In actual fabrication, the wafer is placed in an acid pickling device using a wet etching process, and the silicon dioxide layer can be completely removed in 1 minute. The etching solution can be a 49% hydrofluoric acid solution, i.e., a 49% hydrofluoric acid (HF) solution is used, and the regenerated wafer control 100 is placed in an isotropic wet etching bath.

[0038] After etching away the silicon dioxide layer, the regenerated wafer control chip 100 can be cleaned to remove the etching solution and impurities from the surface, thus completing the repair. At this point, the defect layer on the surface of the regenerated wafer control chip 100 is removed.

[0039] S4: Perform a testing process on the regenerated wafer control wafer 100 to form a test sacrificial layer 130 on the regenerated surface of the regenerated wafer control wafer 100.

[0040] See also Figure 6 Specifically, the repaired regenerated wafer control chip 100 can be tested using a thermal oxidation process (such as gate oxide oxidation, high-temperature deposition process including polysilicon layer).

[0041] S5: Remove the test sacrificial layer 130 to obtain a new regenerated wafer control 100.

[0042] Please continue reading Figure 3 Specifically, a wet etching process can be used to remove the oxide layer, silicon nitride layer, and polysilicon layer, resulting in a new regenerated wafer control chip 100, which can then be recycled. In actual use, it can be recycled approximately 20 times.

[0043] It should be noted that although this mainly addresses the issue of regenerated wafer control 100, it can also be applied to the use of new wafers, meaning that new wafers can also use the aforementioned process.

[0044] This invention provides a regenerated wafer control wafer 100 and a testing method for the aforementioned regenerated wafer control wafer 100. The regenerated wafer control wafer 100 can be prepared by steps S1-S3 and tested by steps S4 and S5.

[0045] This invention adds a pre-processing step, allowing the bare wafer to react with the Si on its surface under the thermal diffusion of H2O and O2, generating a layer of SiO2 oxide that is thin in the middle and thick at the edges. This SiO2 layer penetrates 45% of the wafer, meaning that the thickness of the SiO2 layer penetrates 45% of the wafer. This SiO2 layer can be removed by wet cleaning, allowing the regenerated wafer to approach the thickness of a new wafer.

[0046] Further monitoring of the testing process leads to the following conclusions:

[0047] The oxide thickness uniformity of the native wafer is 0.12%, and the long-term process capability index (CPK) for thermal oxidation is 3.1. The oxide thickness uniformity of the regenerated wafer control 100 processed using conventional processes is 0.8%, with the native wafer exhibiting 85% better uniformity. Furthermore, the CPK of the regenerated wafer control 100 processed using conventional processes is 1.47, with the native wafer showing a 52% better CPK than the regenerated wafer.

[0048] The oxide film thickness uniformity of the regenerated wafer control wafer 100 obtained using the testing method provided in this embodiment of the invention is 0.23%, making the CPK (film density) closer to that of a native wafer. This method can improve uniformity by 72.8% without affecting the thickness of the high-temperature oxidation process, essentially comparable to a native wafer. Compared to a normal native wafer, if only the regenerated wafer control wafer 100 in this embodiment of the invention is used, approximately 70% of the cost can be saved annually. Furthermore, the regenerated wafer control wafer 100 can also be used as an NPW (Non-Product Wafer, test wafer) in advanced processes and automotive-grade sensitive processes.

[0049] In summary, the testing method and the regenerated wafer control wafer 100 provided in this embodiment of the invention first provide a regenerated wafer control wafer 100. Then, the regenerated wafer control wafer 100 is preheated and oxidized under a preset atmosphere to form a sacrificial oxide layer 110 on the growth surface of the regenerated wafer control wafer 100. The center thickness of the sacrificial oxide layer 110 is less than the edge thickness, and it penetrates to a preset depth H on the growth surface. Then, the sacrificial oxide layer 110 is removed by an etching process to expose the regenerated surface of the regenerated wafer control wafer 100, at which point the regenerated wafer control wafer 100 is obtained. Next, a testing process is performed on the regenerated wafer control wafer 100 to form a test sacrificial layer 130 on the regenerated surface of the regenerated wafer control wafer 100. Finally, the test sacrificial layer 130 is removed to obtain a new regenerated wafer control wafer 100 for recycling. Compared to existing technologies, the testing method and the regenerated wafer control wafer 100 provided in this embodiment of the invention form a sacrificial oxide layer 110 on the surface of the regenerated wafer control wafer 100 through pre-diffusion oxidation. This sacrificial oxide layer 110 can cover surface defects. Then, the sacrificial oxide layer 110 is removed by etching, exposing the regenerated surface of the regenerated wafer control wafer 100. This regenerated surface is close to the surface quality of the original wafer, thus playing a more accurate role in subsequent testing processes. Therefore, by optimizing the process, the surface conditions of the regenerated wafer control wafer 100 in the testing process are close to those of a new wafer, improving testing results and truly realizing the application value and added value of recycled wafers.

[0050] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A test method for a wafer prover, characterized by, include: Provide a recycled wafer control chip; The regenerated wafer control is preheated and oxidized under a preset atmosphere to form a sacrificial oxide layer on the growth surface of the regenerated wafer control, wherein the center thickness of the sacrificial oxide layer is less than the edge thickness and penetrates into the growth surface to a preset depth H. The sacrificial oxide layer is removed by an etching process to expose the regenerated surface of the regenerated wafer control wafer; The regenerated wafer control wafer is subjected to a testing process to form a test sacrificial layer on the regenerated surface of the regenerated wafer control wafer; Remove the test sacrificial layer to obtain a new regenerated wafer control.

2. The testing method for regenerated wafer control according to claim 1, characterized in that, The step of preheating and oxidizing the regenerated wafer control chip under a preset atmosphere includes: The regenerated wafer control wafer is subjected to thermal oxidation at a preset temperature in an atmosphere of water vapor and oxygen, so that the water vapor and oxygen react with the growth surface of the regenerated wafer control wafer under thermal diffusion to generate a sacrificial oxide layer.

3. The testing method for regenerated wafer control according to claim 2, characterized in that, The regenerated wafer control chip is a silicon wafer, and the sacrificial oxide layer is a silicon dioxide layer.

4. The testing method for regenerated wafer control according to claim 2, characterized in that, The preset temperature is 750℃-1100℃.

5. The test method for regenerated wafer control according to any one of claims 1-4, characterized in that, The preset depth H accounts for 45% of the thickness of the sacrificial oxide layer.

6. The test method for regenerated wafer control according to any one of claims 1-4, characterized in that, The thickness of the sacrificial oxide layer is between 80 nm and 120 nm.

7. The test method for regenerated wafer control according to any one of claims 1-4, characterized in that, The step of removing the sacrificial oxide layer by an etching process includes: The regenerated wafer is placed in a wet etching tank for more than 1 minute, wherein the wet etching tank is filled with an isotropic etching solution.

8. The testing method for regenerated wafer control according to claim 7, characterized in that, The etching solution is a 49% hydrofluoric acid solution.

9. The testing method for regenerated wafer control according to claim 1, characterized in that, Before the step of testing the regenerated wafer control wafer, the method further includes: The regenerated wafer control chip is cleaned.

10. A regenerated wafer control chip, characterized in that, The regenerated wafer control chip has a regenerated surface obtained through pretreatment; the pretreatment is as follows: The growth surface of the regenerated wafer is preheated and oxidized under a preset atmosphere to form a sacrificial oxide layer with a center thickness smaller than the edge thickness and a preset depth H into the growth surface. After the sacrificial oxide layer is removed by an etching process, the regenerated surface is exposed.

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