Wafer testing method

Abstract

This disclosure provides a wafer testing method, relating to the field of semiconductor technology. The method includes: providing a wafer including test pads, with multiple chips formed in the device region of the wafer; the test pads including a first test pad located within a dicing area of ​​the wafer and a second test pad located within the device region of the wafer, the first test pad being used for wafer acceptance testing and the second test pad being used for chip testing; forming a photoresist layer covering the wafer surface; using a test probe to penetrate the photoresist layer, making the test probe contact the test pads to test the wafer; after wafer acceptance testing and before chip testing, coating the photoresist layer with a photoresist material identical to the photoresist layer, such that the photoresist material fills the probe holes formed by the test probes in the photoresist layer; and removing the photoresist layer to expose the tested wafer surface. This method can avoid short-circuit problems caused by impurities during testing and improve device yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a wafer testing method. Background Technology

[0002] Wafer testing is an electrical test performed after the wafer completes its front-end processing but before dicing and packaging. Its core purpose is to screen out functional and performance-compliant chips (dies), eliminate defective products, reduce packaging costs, and provide data feedback for process improvement. Wafer testing can employ contact-based testing methods using probe cards. Metal probes on the probe card directly contact the test pads on the wafer, applying electrical signals to obtain test data. However, during the contact between the metal probes and the test pads, impurities such as metal shavings are generated. These impurities can fall into the device area as the wafer rotates, posing a risk of short circuits.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a wafer testing method, which forms a full-coverage photoresist layer on the surface of the wafer before the test probe contacts the test pad, thereby isolating impurities generated during the testing process and reducing the risk of chip short circuits.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a wafer testing method is provided, the wafer testing method comprising: A wafer is provided, the wafer including test pads; the wafer includes a device region and a dicing region, the device region having a plurality of chips formed thereon, the test pads including a first test pad located in the dicing region and a second test pad located in the device region, wherein the first test pad is used for wafer acceptance testing and the second test pad is used for chip testing; A photoresist layer is formed, the photoresist layer covering the surface of the wafer; The wafer is tested by using a test probe to penetrate the photoresist layer and make the test probe contact the test pad; wherein, after wafer acceptance testing and before chip testing, the process includes: coating the photoresist layer with a photoresist material identical to the photoresist layer, so that the photoresist material fills the probe hole formed by the test probe on the photoresist layer; Remove the photoresist layer to expose the surface of the wafer after testing.

[0007] In one exemplary embodiment of this disclosure, after forming the photoresist layer, the process includes: The surface of the photoresist layer is inspected to obtain the distribution and size of particles on the surface of the photoresist layer; If the total projected area of ​​the particles on the surface of the photoresist layer accounts for more than or equal to 1% of the surface area of ​​the photoresist layer and / or the maximum size of the particles is greater than 0.1 μm, then the photoresist layer is cleaned to remove the particles.

[0008] In one exemplary embodiment of this disclosure, after forming the photoresist layer, the process includes: The thickness of the photoresist layer was measured; If the thickness of the photoresist layer is within a preset thickness range, the wafer is tested.

[0009] In one exemplary embodiment of this disclosure, it includes: During the test, if the thickness of the photoresist layer is less than the minimum preset thickness, the photoresist coating process is repeated to increase the thickness of the photoresist layer until the thickness of the photoresist layer is within the preset thickness range.

[0010] In one exemplary embodiment of this disclosure, the preset thickness range of the photoresist layer is 50 nm to 500 nm.

[0011] In one exemplary embodiment of this disclosure, the preset thickness of the photoresist layer is in the range of 100nm to 300nm.

[0012] In one exemplary embodiment of this disclosure, forming a photoresist layer includes: Photoresist material is spin-coated onto the surface of the wafer; The photoresist material is dried to make the hardness of the formed photoresist layer within the range of 150HV to 350HV, so that the test probe can penetrate the photoresist layer and contact the test pad.

[0013] In one exemplary embodiment of this disclosure, the drying temperature is 80°C to 120°C, and the drying time is 30s to 120s.

[0014] In one exemplary embodiment of this disclosure, the chip testing includes an aging test, wherein the photoresist layer is tightly adhered to the surface of the wafer at an aging test temperature.

[0015] In one exemplary embodiment of this disclosure, the aging test temperature is -50℃ to 120℃.

[0016] In one exemplary embodiment of this disclosure, removing the photoresist layer includes: The first portion of the photoresist layer is removed using a dry ashing process. The second part of the photoresist layer is then removed using a wet cleaning process, wherein the thickness of the first part is greater than the thickness of the second part.

[0017] In one exemplary embodiment of this disclosure, after removing the photoresist layer, the process includes: The exposed surface of the wafer is inspected to obtain the residual value of the photoresist layer. If the residual value is higher than a preset residual value, the wet cleaning process is repeated until the residual value is lower than the preset residual value.

[0018] In one exemplary embodiment of this disclosure, the photoresist layer has optical transparency to allow visible light to pass through, through which the test pads can be identified.

[0019] The wafer testing method disclosed herein involves forming a full-surface photoresist layer on the wafer surface before testing. During wafer testing, a test probe penetrates the photoresist layer and contacts the test pads to complete the test. Throughout the entire testing process, the photoresist layer covers the wafer surface. Except for the contact point between the test probe and the test pads, the rest of the wafer is protected by the photoresist layer, providing comprehensive protection for the wafer. The photoresist layer also effectively isolates the test pads. This avoids short circuits caused by impurities on the test pads, improving test reliability. Simultaneously, the photoresist layer reduces the risk of short circuits caused by impurities falling into the device area due to contact between the test probes and test pads, preventing chip failure and improving yield. Furthermore, since the photoresist layer is a continuous film, it can be removed in a single process after wafer testing, reducing process complexity. Moreover, this photoresist layer does not adversely affect subsequent wafer packaging processes, providing a reliable physical basis for subsequent packaging.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 This is a flowchart of a wafer testing method according to an exemplary embodiment of the present disclosure.

[0023] Figure 2 This is a schematic diagram of the structure of a wafer according to an exemplary embodiment of the present disclosure.

[0024] Figure 3 In exemplary embodiments of this disclosure Figure 2 A schematic diagram showing the positional relationship between the chip and the second test pad.

[0025] Figure 4 This is a schematic diagram of the structure of a wafer according to an exemplary embodiment of the present disclosure.

[0026] Figure 5 In exemplary embodiments of this disclosure Figure 4 A schematic diagram showing the positional relationship between the chip and the second test pad.

[0027] Figure 6 This is a schematic diagram of the structure of a photoresist material according to an exemplary embodiment of the present disclosure.

[0028] Figure 7 This is a schematic diagram of the structure of a photoresist material according to an exemplary embodiment of the present disclosure.

[0029] Figure 8 This is a schematic diagram of the structure of a photoresist layer in an exemplary embodiment of the present disclosure.

[0030] Figure 9 This is a schematic diagram of the structure of a photoresist layer in an exemplary embodiment of the present disclosure.

[0031] Figure 10 This is a schematic diagram of the distribution of particulate matter on a photoresist layer in an exemplary embodiment of the present disclosure.

[0032] Figure 11 This is a schematic diagram of a wafer acceptance test according to an exemplary embodiment of the present disclosure.

[0033] Figure 12 This is a schematic diagram of a wafer acceptance test according to an exemplary embodiment of the present disclosure.

[0034] Figure 13This is a schematic diagram of the structure of a probe hole in an exemplary embodiment of the present disclosure.

[0035] Figure 14 This is a schematic diagram of the structure of a probe hole in an exemplary embodiment of the present disclosure.

[0036] Figure 15 This is a schematic diagram of the structure after the probe hole is filled with photoresist material in an exemplary embodiment of this disclosure.

[0037] Figure 16 This is a schematic diagram of the structure after the probe hole is filled with photoresist material in an exemplary embodiment of this disclosure.

[0038] Figure 17 This is a schematic diagram of the structure after a photoresist layer is formed inside a probe hole, as shown in an exemplary embodiment of this disclosure.

[0039] Figure 18 This is a schematic diagram of the structure after a photoresist layer is formed inside a probe hole, as shown in an exemplary embodiment of this disclosure.

[0040] Figure 19 This is a schematic diagram of a chip test according to an exemplary embodiment of the present disclosure.

[0041] Figure 20 This is a schematic diagram of a chip test according to an exemplary embodiment of the present disclosure.

[0042] Figure 21 This is a schematic diagram of the structure of a photoresist layer in an exemplary embodiment of the present disclosure.

[0043] The reference numerals in the attached figures are explained as follows: 100, Wafer; 110, Drill Track Area; 120, Device Area; 121, Chip; 200, Test Pad; 210, First Test Pad; 220, Second Test Pad; 300, Photoresist Layer; H, Thickness of Photoresist Layer; 30, Photoresist Material; 310, First Part of Photoresist Layer; 320, Second Part of Photoresist Layer; 400, Test Probe; 410, Probe Hole; 500, Particle; A, Maximum Size of Particle. Detailed Implementation

[0044] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0045] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0046] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0047] In semiconductor manufacturing, wafer testing is the electrical testing of chips or process structures on a wafer before dicing and packaging. Wafer testing includes Wafer Acceptance Test (WAT) and Chip Probing (CP). WAT uses test pads located within the dicing lanes to assess the stability and consistency of the wafer's manufacturing process. CP tests chips within the device area to screen for qualified chips. Both WAT and CP can obtain test results using probe cards. However, during wafer testing, repeated contact or relative sliding between the metal probes and exposed test pads can damage the pads, generating metal shavings and other impurities. These impurities can fall into the dicing lanes or device area as the wafer rotates, causing short circuits or leakage between test pads and chips, negatively impacting test reliability and product yield.

[0048] Based on this, the present disclosure provides a wafer testing method, such as... Figure 1 As shown, the method includes steps S10 to S40.

[0049] In step S10: a wafer is provided, the wafer including test pads; the wafer includes a device area and a dicing area, the device area is formed with multiple chips, the test pads include a first test pad located in the dicing area and a second test pad located in the device area, wherein the first test pad is used for wafer acceptance testing and the second test pad is used for chip testing. Step S20: Form a photoresist layer, which covers the surface of the wafer; Step S30: Using a test probe to penetrate the photoresist layer, the test probe contacts the test pad to test the wafer; wherein, after wafer acceptance testing and before chip testing, the process includes: coating the photoresist layer with the same photoresist material as the photoresist layer, so that the photoresist material fills the probe hole formed on the photoresist layer by the test probe. Step S40: Remove the photoresist layer to expose the surface of the tested wafer.

[0050] The wafer testing method disclosed herein involves forming a full-surface photoresist layer on the wafer surface before testing. During wafer testing, a test probe penetrates the photoresist layer and contacts the test pads to complete the test. Throughout the entire testing process, the photoresist layer covers the wafer surface. Except for the contact point between the test probe and the test pads, the rest of the wafer is protected by the photoresist layer, providing comprehensive protection for the wafer. The photoresist layer also effectively isolates the test pads. This avoids short circuits caused by impurities on the test pads, improving test reliability. Simultaneously, the photoresist layer reduces the risk of short circuits caused by impurities falling into the device area due to contact between the test probes and test pads, preventing chip failure and improving yield. Furthermore, since the photoresist layer is a continuous film, it can be removed in a single process after wafer testing, reducing process complexity. Moreover, this photoresist layer does not adversely affect subsequent wafer packaging processes, providing a reliable physical basis for subsequent packaging.

[0051] The following will be combined with the appendix Figure 2 To be continued Figure 21 The wafer testing method provided in this disclosure will be described in detail for each step: In the embodiments provided in this disclosure, such as Figure 2 and Figure 4 As shown, in step S10, a wafer 100 is provided, which includes test pads 200.

[0052] The wafer 100 includes a device region 120 and a dicing region 110. Multiple chips 121 are formed in the device region 120. An electrical test structure is provided in the dicing region 110. The electrical parameters of each part of the wafer 100 can be obtained through the electrical test structure to determine the process reliability of the wafer 100. In addition, alignment and positioning auxiliary structures such as alignment marks are also provided in the dicing region 110 for the alignment of equipment in the process.

[0053] Among them, such as Figure 2 and Figure 4As shown, the test pad 200 includes a plurality of first test pads 210, which are disposed in the dicing area 110. The first test pads 210 are used for wafer acceptance testing (WAT), that is, the first test pads 210 contact the test probes 400 on the probe card to measure the electrical characteristics of each test structure in the dicing area 110. They can also monitor the process uniformity to provide favorable data support for process reliability.

[0054] In some specific embodiments, since the tip size of the test probe 400 can be 20μm~50μm, in order to make the size of the first test pad 210 match the tip size of the test probe 400, the size of the first test pad 210 can be 50μm×50μm~100μm×100μm, so as to ensure reliable contact between the test probe 400 and the first test pad 210 and ensure test reliability.

[0055] In some specific embodiments, based on the minimum spacing limit of the probe card, the distance between two adjacent first test pads 210 can be 100μm~200μm. Within the above distance range, short circuit of the test probe 400 can be avoided, ensuring test reliability.

[0056] Among them, such as Figures 2 to 5 As shown, the test pad 200 includes a plurality of second test pads 220, which are disposed in the device area 120. The second test pads 220 are used for chip testing (CP), that is, the second test pads 220 contact the test probes 400 on the probe card to test the function of the chip 121 and obtain a qualified chip 121.

[0057] In some specific embodiments, such as Figure 3 As shown, multiple second test pads 220 can also be distributed in the central array area of ​​chip 121. The positions of the second test pads 220 can be consistent with those of the subsequent packaging pads, so as to facilitate direct bonding during subsequent packaging; as Figure 5 As shown, multiple second test pads 220 can be arranged around or along the edge of chip 121 to form a pad ring. The chip 121 is tested through the pad ring to obtain a qualified chip 121.

[0058] In some specific embodiments, since the tip size of the test probe 400 can be 20μm~50μm, in order to make the size of the second test pad 220 match the tip size of the test probe 400, the size of the second test pad 220 can be 60μm×60μm~100μm×100μm, so as to ensure reliable contact between the test probe 400 and the second test pad 220 and ensure test reliability.

[0059] In some specific embodiments, based on the minimum spacing limit of the probe card and the area constraint of the chip 121, the distance between two adjacent second test pads 220 can be 80μm~200μm. Within the above distance range, short circuits of the test probes 400 can be avoided, ensuring test reliability.

[0060] During wafer 100 testing, the test probe 400 contacts the test pad 200. Due to the hardness of the test probe 400, it can damage the test pad 200, generating impurities such as metal shavings. These impurities fall into the dicing area 110 or device area 120 as the wafer 100 rotates, causing short circuits or leakage between exposed test pads 200 or between chips 121. This reduces the accuracy of the test results and may even damage the chip 121, adversely affecting the yield. Therefore, in the wafer 100 testing method provided in this disclosure, before testing the wafer 100, step S20 is performed to form a photoresist layer 300 covering the surface of the wafer 100. During wafer 100 testing, step S30 is performed, whereby the test probe 400 penetrates the photoresist layer 300 to contact the test pad 200 for testing the wafer 100.

[0061] In this process, after wafer fabrication and before testing, the photoresist layer 300 covers the entire surface of the wafer 100. Compared to covering only the non-test areas with the photoresist layer 300, covering the entire surface of the wafer 100 with the photoresist layer 300 provides all-round protection for the wafer 100 during testing, preventing short circuits caused by metal shavings or other impurities falling into any structure of the wafer 100, thereby improving test reliability.

[0062] In this method, during wafer 100 testing, a test probe 400 penetrates the photoresist layer 300 to make contact with the test pad 200. By using this method, the test probe 400 penetrates the photoresist layer 300, ensuring contact between the probe and the test pad 200. The remaining portion of the wafer 100 is protected by the photoresist layer 300, except for the contact point or area between the test probe 400 and the test pad 200. This prevents impurities from entering the wafer 100 through the exposed portion of the test pad 200 and causing short circuits, thus providing comprehensive protection for the wafer 100. Furthermore, this method offers advantages over methods that involve creating windows in the photoresist layer 300 at the testing location. This method can reduce the exposed area of ​​the test pads 200, which is more conducive to improving the isolation of impurities by the photoresist layer 300. In addition, since there are many test pads 200 and their positions are relatively scattered, after an opening is formed at the test pads 200, the remaining photoresist layer 300 will no longer be continuous. When removing the remaining photoresist layer 300, it is impossible to remove it all at once, which increases the removal process and makes the process more complicated. However, the method disclosed in this invention, which uses the test probe 400 to penetrate the photoresist layer 300, can ensure the structural continuity of the photoresist layer 300. When removing the photoresist layer 300, it can be removed all at once, which can reduce the removal process steps, reduce the complexity of the process, and improve efficiency.

[0063] In some embodiments, the photoresist layer 300 may be made of organic materials. For example, the photoresist layer 300 may be at least one of epoxy resin, polyimide, acrylate, cyclic olefin polymer, etc. The photoresist layer 300 can achieve the function of insulation and isolation, and will not have a negative impact on the test process and test results, thus ensuring the reliability of the entire test process.

[0064] In some embodiments, forming a photoresist layer 300 includes: such as Figure 6 and Figure 7 As shown, photoresist material 30 is spin-coated onto the surface of wafer 100; as Figure 8 and Figure 9As shown, the photoresist material 30 is dried to ensure that the hardness of the resulting photoresist layer 300 is within the range of 150 HV to 350 HV, allowing the test probe 400 to penetrate the photoresist layer 300 and contact the test pad 200. The hardness of the photoresist layer 300 cannot be too low or too high. If it is below 150 HV, the probe is prone to plastic deformation or residue, affecting the reliability of the test; while if it is above 350 HV, although the penetration resistance is enhanced, the solvent stripping efficiency will be reduced, increasing the difficulty of cleaning. The photoresist material 30 can be determined according to the different types of photoresist layer 300. For example, when the photoresist layer 300 is epoxy resin, the photoresist material 30 can be a resin matrix. Furthermore, in order to enable the photoresist material 30 to form the photoresist layer 300, the photoresist material 30 can also include additives, such as stabilizers and surfactants, to improve the performance of the subsequently formed photoresist layer 300 and enable the photoresist layer 300 to achieve better protection for the wafer 100.

[0065] In some specific embodiments, forming the photoresist layer 300 may include: when the wafer 100 is stationary, dropping 1 mL to 5 mL of photoresist material 30 onto the center of the wafer 100, or when the wafer 100 is rotating at a speed of 500 rpm to 1000 rpm, dropping the photoresist material 30 onto the surface of the wafer 100, using centrifugal force to initially spread the photoresist material 30 on the surface of the wafer 100 to reduce bubbles and edge accumulation; then increasing the rotation speed of the wafer 100 to 1500 rpm to 3000 rpm and continuing for 30 s to 50 s, so that the photoresist material 30 is evenly spread from the center to the edge on the surface of the wafer 100.

[0066] In some specific embodiments, after the photoresist material 30 is uniformly spread on the surface of the wafer 100, the process includes: drying the photoresist material 30 to cure it and form a photoresist layer 300.

[0067] The drying conditions for the photoresist material 30 may include a drying temperature of 80℃~120℃ and a drying time of 30s~120s. For example, the photoresist material 30 can be heated at 110℃ for 90s using a hot plate to solidify it into a photoresist layer 300. Under the aforementioned drying temperature and time, the photoresist material 30 can solidify but still retains a certain degree of toughness. That is, the photoresist layer 300 formed by the photoresist material 30 possesses a certain degree of toughness, allowing the test probe 400 to penetrate the photoresist layer 300 and contact the test pad 200. During the penetration process, the test probe 400 will not deform or be damaged, ensuring the structural integrity of the test probe 400 and thus guaranteeing the accuracy of the test results.

[0068] In some embodiments, the hardness of the photoresist layer 300 is in the range of 150HV to 350HV. For example, the hardness of the photoresist layer 300 can be 150HV, 170HV, 200HV, 230HV, 250HV, 270HV, 290HV, 300HV, 310HV, 320HV, 330HV, 340HV, or 350HV. During the process of the test probe 400 penetrating the photoresist layer 300, the test probe 400 will not be deformed or damaged, ensuring the structural integrity of the test probe 400. In addition, the hardness of the photoresist layer 300 being within the above range can also ensure that the photoresist layer 300 will not be severely deformed or detached due to external forces, ensuring the reliability of the photoresist layer 300 in protecting the underlying structure.

[0069] In some embodiments, the photoresist layer 300 has optical transparency to allow visible light to pass through, enabling the identification of test pads 200 and making them visible. When the test probe 400 needs to penetrate the photoresist layer 300, the position of the test pads 200 can be directly observed without the need for additional tools to detect their location. This simplifies the contact process between the test probe 400 and the test pads 200 and ensures the correctness of their contact position, thus improving test reliability. Furthermore, because the photoresist layer 300 has optical transparency, it can also be used to directly identify alignment marks and other structures. In other words, the photoresist layer 300 does not affect the identification of any structures and does not introduce additional identification processing steps into the testing process, ensuring the testing efficiency of the wafer 100.

[0070] Since the photoresist layer 300 can be made of photoresist material 30 such as epoxy resin, and the photoresist material 30 only needs to be coated and dried, it does not need to undergo subsequent processes such as exposure and development, and can remain transparent or semi-transparent. For example, the photoresist layer 300 can be transparent, light yellow, amber, etc., and the underlying structure can be directly observed through the photoresist layer 300, ensuring the contact accuracy of the test probe 400 and the test pad 200, thereby improving the reliability of the test.

[0071] In the embodiments provided in this disclosure, after forming the photoresist layer 300, the method further includes: detecting the thickness H of the photoresist layer; if the thickness H of the photoresist layer is within a preset thickness range, then testing the wafer 100; if the thickness H of the photoresist layer is not within the preset thickness range, then repeating the coating and drying process of the photoresist material 30 until the photoresist layer 300 is within the preset thickness range. In this disclosure, a one-step coating and drying process can be used to form the photoresist layer 300. However, if the thickness H of the formed photoresist layer is too small, it cannot provide sufficient protection for the underlying structure and is costly. If the thickness H of the photoresist layer is too large, the test probe 400 cannot penetrate and may be damaged. In order to ensure that the photoresist layer 300 can perform the above functions, a multi-step coating and drying process can be used to adjust the thickness H of the photoresist layer so that the thickness H of the photoresist layer is within a preset thickness range. This allows the photoresist layer 300 to both protect the underlying structure and ensure that the test probe 400 can pass through smoothly to complete the wafer 100 test.

[0072] In some specific embodiments, the preset thickness range of the photoresist layer 300 is 50nm~500nm, for example, it can be 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, etc. Within the above thickness range, the photoresist layer 300 can ensure that it can protect the structure below it, and also allow the test probe 400 to pass through smoothly to complete the wafer 100 test. In addition, the photoresist layer 300 within the above thickness range is conducive to its subsequent removal and reduces the residue of particulate matter 500.

[0073] In some specific embodiments, the preset thickness range of the photoresist layer 300 is 100nm~400nm, for example, it can be 100nm, 170nm, 230nm, 280nm, 300nm, 310nm, 320nm, 330nm, 340nm, 350nm, 360nm, 370nm, 380nm, 390nm, 400nm, etc. Within the above thickness range, the photoresist layer 300 can not only achieve the purpose of protection and testing, but also further reduce the manufacturing cost of the photoresist layer 300 and ensure economic efficiency. In addition, the photoresist layer 300 within this thickness range can be applied to a variety of machine tools and has high applicability.

[0074] In some embodiments, during the testing of wafer 100, the photoresist layer 300 may be worn away, resulting in a reduction in the thickness H of the photoresist layer. This reduces its effectiveness in protecting the underlying structure. For example, the wear of the photoresist layer 300 may expose part of the photoresist layer 300 to the structure below it. The exposed structure may experience short circuits due to the intrusion of impurities. Therefore, the method further includes: if the thickness H of the photoresist layer is less than a preset minimum thickness during the testing process, the photoresist material 30 coating process is repeated to increase the thickness H of the photoresist layer until the thickness H of the photoresist layer is within the preset thickness range. By real-time detection of the thickness H of the photoresist layer during the testing process, it can be ensured that the photoresist layer 300 remains within the preset thickness range, thereby ensuring that the photoresist layer 300 provides continuous protection during the testing process.

[0075] It should be noted that during the testing of wafer 100, the loss of the photoresist layer 300 is uneven. For example, some locations of the photoresist layer 300 may not experience loss, while the loss at other locations may cause the thickness H of the photoresist layer to be less than the minimum value of the preset thickness range. In other words, when the thickness H of the photoresist layer is detected to be less than the minimum value of the preset thickness, it means that the minimum thickness of the photoresist layer 300 is less than the minimum value of the preset thickness range. In this case, the photoresist material 30 coating process can be repeated to ensure that the thickness H of the photoresist layer is greater than the minimum value of the preset thickness range at any location. This ensures that the photoresist layer 300 has continuous isolation and insulation properties, thus providing continuous protection for the underlying structure.

[0076] In the embodiments provided in this disclosure, after forming the photoresist layer 300, the method further includes: as follows Figure 10 As shown, the surface of the photoresist layer 300 is inspected to obtain the distribution and size of the particles 500 on the surface of the photoresist layer 300; if the total projected area of ​​the particles 500 on the surface of the photoresist layer 300 accounts for more than or equal to 1% of the surface area of ​​the photoresist layer 300 and / or the maximum size A of the particles is greater than 0.1 μm, then the photoresist layer 300 is cleaned to remove the particles 500.

[0077] Before testing wafer 100, the surface of photoresist layer 300 needs to be inspected to prevent particles 500 on the surface of photoresist layer 300 from causing wear to the test probe 400 when it penetrates the photoresist layer 300, thus causing test failure. At the same time, it is also necessary to prevent the test probe 400 from carrying particles 500 into the interior of wafer 100 when it penetrates the photoresist layer 300, which could cause a short circuit.

[0078] In some embodiments, when the total projected area of ​​particles 500 on the surface of the photoresist layer 300 accounts for more than or equal to 1% of the surface area of ​​the photoresist layer 300 and / or the maximum size A of the particles is greater than 0.1 μm, the presence of particles 500 will have an adverse effect on subsequent wafer 100 testing. Under the above conditions, particles 500 need to be cleaned to remove particles 500 and ensure that the cleanliness of the photoresist layer 300 meets the testing requirements.

[0079] In some embodiments, the particulate matter 500 can be cleaned using a wet cleaning process. This involves reacting a chemical solution with the particulate matter 500 to dissolve it, followed by physical removal. For example, a mixed solution of hydrogen chloride (HCl) and hydrogen peroxide (H₂O₂) can be used to chemically react with the particulate matter 500. Under the oxidizing effect of H₂O₂, the particulate matter 500 decomposes into soluble chlorides, thus removing it. Alternatively, a hydrofluoric acid (HF) solution can be used to remove oxide or metal layers, thereby stripping away the particulate matter 500. It should be noted that when using a wet cleaning process to remove the particulate matter 500, the photoresist layer 300 will not be damaged. The thickness H of the photoresist layer will remain within a preset thickness range to ensure that its protective performance is not compromised. Of course, in the actual process, the removal of particulate matter 500 may cause some damage to the photoresist layer 300. If the damage causes the thickness H of the photoresist layer to be less than the minimum value of the preset thickness range, the coating process of the photoresist material 30 can be repeated until the thickness H of the photoresist layer is within the preset thickness range to ensure the performance of the photoresist layer 300.

[0080] In the embodiments provided in this disclosure, step S30 includes: using a test probe 400 to penetrate the photoresist layer 300, so that the test probe 400 contacts the test pad 200 to test the wafer 100.

[0081] Among them, such as Figure 11 and Figure 12As shown, wafer 100 testing may include WAT (Waste Air Testing). During WAT testing, a test probe 400 can penetrate the photoresist layer 300 above the first test pad 210 located within the dicing area 110, allowing the test probe 400 to contact the first test pad 210 to obtain test results. In WAT, except for the contact point between the test probe 400 and the first test pad 210, the first test pad 210 and other structures are all within the coverage area of ​​the photoresist layer 300. The photoresist layer 300 also provides a certain degree of protection for the test probe 400. The photoresist layer 300 provides a limiting effect, preventing the generation of metal shavings or other impurities between the test probe 400 and the first test pad 210 due to relative sliding friction. Even if impurities are present between the test probe 400 and the first test pad 210, the photoresist layer 300 surrounds the impurities, preventing them from moving outside the contact area between the test probe 400 and the first test pad 210. In other words, the photoresist layer 300 also provides a certain degree of fixation for the impurities, which can strictly control the displacement of the impurities, reduce the risk of short circuits caused by the presence of impurities, ensure test reliability, and improve yield.

[0082] Among them, such as Figure 19 and Figure 20 As shown, wafer 100 testing may include photoresist layer 300 (CP). During CP testing, a test probe 400 can penetrate the photoresist layer 300 above the second test pad 220 located within device region 120, allowing the test probe 400 to contact the second test pad 220 to obtain test results. In CP, except for the contact point between the test probe 400 and the second test pad 220, the second test pad 220 and other structures are all within the coverage area of ​​the photoresist layer 300. The photoresist layer 300 also provides a certain degree of limitation for the test probe 400. The function is to prevent the generation of metal shavings and other impurities between the test probe 400 and the second test pad 220 due to relative sliding friction. Even if there are impurities between the test probe 400 and the second test pad 220, the photoresist layer 300 surrounds the impurities, preventing them from moving outside the contact area between the test probe 400 and the second test pad 220. In other words, the photoresist layer 300 also provides a certain degree of fixation for the impurities, which can strictly control the displacement of the impurities, reduce the risk of short circuits caused by the presence of impurities, ensure test reliability, and improve yield.

[0083] In some specific embodiments, CP includes aging tests, which can screen for early failures and ensure the long-term reliability of the device. The aging test includes a temperature cycling aging test, which cycles between high and low temperatures to obtain the reliability of the device's thermomechanical stress. At the aging test temperature, due to temperature changes, the photoresist layer 300 undergoes thermal expansion and contraction. In the contact area between the edge of the photoresist layer 300 and the edge of the wafer 100 surface, the thermal expansion and contraction of the photoresist layer 300 causes partial detachment between the edge of the photoresist layer 300 and the surface of the wafer 100. Impurities can easily penetrate into the interior of the wafer 100 from the detached location, thereby reducing the protective performance of the photoresist layer 300. Therefore, in this disclosure, at the aging test temperature, the photoresist layer 300 is tightly attached to the surface of the wafer 100, meaning that the photoresist layer 300 will not separate or detach from the surface of the wafer 100 due to temperature changes, thus ensuring the protective performance of the photoresist layer 300.

[0084] The aging test temperature is -50℃ to 120℃. For example, the low temperature of the aging test can be -40℃ and the high temperature of the aging test can be 98℃. During the alternating cycle of high and low temperatures, the photoresist layer 300 is tightly attached to the surface of the wafer 100 to ensure the protective performance of the photoresist layer 300 on the wafer 100, thereby ensuring the reliability of the test.

[0085] It should be noted that although the CP of this disclosure is illustrated by aging test, CP may also include other test processes such as open and short circuit test, DC parameter test, functional test, AC parameter test, etc. The photoresist layer 300 covers the entire surface of the wafer 100 throughout the entire CP test in order to protect the wafer 100.

[0086] In some embodiments, such as Figure 13 and Figure 14 As shown, since WAT and CP acquire different parameters, WAT is performed before CP. After WAT, the photoresist layer 300 located in the dicing area 110 generates probe holes 410 due to the insertion of test probes 400. These probe holes 410 expose part of the surface of the dicing area 110. During subsequent CP, due to temperature changes, the photoresist layer 300 expands and contracts, causing it to peel off from the surface of the wafer 100 at the probe hole 410 locations. Impurities can enter through the peeled area and adhere to the surface of the wafer 100, causing a short circuit problem. Therefore, after WAT and before CP, the method includes: Figures 15 to 18As shown, a photoresist material 30 identical to that of the photoresist layer 300 is coated on the photoresist layer 300. This photoresist material 30 fills the probe holes 410 formed by the test probes 400 on the photoresist layer 300. During subsequent wafer 100 testing, this avoids the problem of the photoresist layer 300 peeling off from the wafer 100 surface at the probe holes 410, ensuring the integrity of the photoresist layer 300 and providing all-round protection for the wafer 100. Furthermore, since the number of test pads 200 is large and dense, to prevent the photoresist layer 300 from breaking at the dense probe holes 410, the photoresist material 30 fills the probe holes 410, ensuring the structural continuity of the photoresist layer 300. This simplifies the removal process and improves efficiency during subsequent removal of the photoresist layer 300.

[0087] The photoresist layer 300 provided in this disclosure is used throughout the entire wafer 100 testing process, which can ensure the reliability of wafer 100 testing and provide a reliable physical basis for subsequent wafer 100 packaging.

[0088] In the embodiments provided in this disclosure, in step S40, the photoresist layer 300 is removed to expose the surface of the tested wafer 100.

[0089] In removing the photoresist layer 300, dry removal alone can easily produce inorganic residues and cause ionic damage to the structure beneath the photoresist layer 300. Wet removal alone has the problem of low removal efficiency. In order to improve the removal efficiency of the photoresist layer 300 and reduce residues, a combination of dry ashing and wet cleaning processes can be used to remove the photoresist layer 300. This method can ensure that the removal of the photoresist layer 300 will not damage the structure beneath it, while also improving removal efficiency, reducing residues, and thus improving product yield.

[0090] In some embodiments, reference Figure 21The removal of the photoresist layer 300 includes: removing the first portion 310 of the photoresist layer using a dry ashing process; and then removing the second portion 320 of the photoresist layer using a wet cleaning process. The thickness of the first portion 310 of the photoresist layer is greater than the thickness of the second portion 320 of the photoresist layer. The dry ashing process first removes most of the photoresist layer 300 (the first portion 310 of the photoresist layer) to ensure removal efficiency, and the remaining small portion of the photoresist layer 300 (the second portion 320 of the photoresist layer) can be used to protect the underlying structure from ion damage. The wet cleaning process then removes the remaining small portion of the photoresist layer 300 (the second portion 320 of the photoresist layer). The wet cleaning process can also be used to remove ash generated during the dry ashing process to further improve the cleanliness of the wafer 100 surface.

[0091] The ratio of the thickness of the first part 310 of the photoresist layer to the thickness of the second part 320 of the photoresist layer can be 5:1 to 20:1. This ensures that the dry ashing process can remove most of the photoresist layer 300 (the first part 310 of the photoresist layer) and that the remaining photoresist layer 300 (the second part 320 of the photoresist layer) can protect the underlying structure from ion damage. This improves the removal efficiency while ensuring the cleanliness of the wafer 100.

[0092] In some specific embodiments, if the thickness H of the photoresist layer is 300nm, the thickness of the first part 310 of the photoresist layer can be 250nm~285nm, and the thickness of the second part 320 of the photoresist layer can be 15nm~50nm.

[0093] It should be noted that, in this disclosure, thickness may refer to one of the minimum thickness, maximum thickness, or average thickness. When measuring the thickness of different film layers or the size relationship between different parts of the same film layer, one of the minimum thickness, maximum thickness, or average thickness may be used for comparison so that there is a unified measurement standard between different film layers or between different parts of the same film layer.

[0094] In some embodiments, the dry ashing process includes: placing the tested wafer 100 into a plasma chamber, introducing oxygen at a flow rate of 500 sccm to 2000 sccm, maintaining a chamber pressure of 0.2 Torr to 1.0 Torr, and an RF power density of 0.5 W / cm². 2 ~2.0W / cm 2 Under conditions of 100℃~300℃, after plasma ignition, oxygen free radicals and oxygen ions react with the photoresist layer 300, decomposing the photoresist layer 300 into byproducts such as CO2 and H2O. The reaction byproducts are then removed by purging the chamber.

[0095] In some embodiments, the wet cleaning process includes immersing the dry-ashed wafer 100 in an SPM solution at a temperature maintained at 120°C to 150°C for 5 to 15 minutes. The strong oxidizing properties of the solution decompose residual organic ash and the second portion 320 of the photoresist layer, while also oxidizing and dissolving some metallic contaminants. Following the wet cleaning process, the process further includes rinsing the wafer 100 with deionized water and drying the wafer 100.

[0096] It should be noted that the SPM solution in the wet cleaning process refers to a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). To ensure the effectiveness and safety of the SPM solution, it can be mixed in a heat-resistant quartz tank at a volume ratio of H2SO4:H2O2 = 3:1 to 4:1. Before mixing, the sulfuric acid should be heated to 120℃ to 150℃, and then the hydrogen peroxide should be added slowly to prevent the solution from exothermically causing splashing and to ensure safety.

[0097] In some embodiments, before performing a dry ashing process on the photoresist layer 300, a wet pretreatment can be performed on the photoresist layer 300. For example, concentrated sulfuric acid or other solvents can be used to soak the photoresist layer 300 at a temperature of 100°C to 150°C for 5 to 15 minutes to soften the surface of the photoresist layer 300, so as to facilitate the subsequent removal of the photoresist layer 300 by the dry ashing process.

[0098] After removing the photoresist layer 300, the method further includes: inspecting the surface of the exposed wafer 100 to obtain the residual value of the photoresist layer 300; if the residual value is higher than the preset residual value, repeating the wet cleaning process until the residual value is lower than the preset residual value.

[0099] The residual value of the photoresist layer 300 can be detected by at least one of optical microscopy, scanning microscopy, contact angle detection, or particle counter detection. For example, optical microscopy can be used to observe whether there are residual particles on the surface of wafer 100. If so, a particle counter can be used to detect the specific number of particles on the surface of wafer 100 to determine the residual value of the photoresist layer 300 on the surface of wafer 100.

[0100] In some embodiments, the residual value of the photoresist layer 300 can be measured by the maximum size and total number of residual particles on the surface of wafer 100. For example, if the total number of residual particles on the surface of wafer 100 is less than 10 and / or the maximum size of the residual particles is less than 0.1 μm, the residual value of the photoresist layer 300 on the surface of wafer 100 is considered to be lower than a preset residual value, and the photoresist layer 300 is removed relatively thoroughly. If the total number of residual particles on the surface of wafer 100 is greater than or equal to 10 and / or the maximum size of the residual particles is greater than or equal to 0.1 μm, the residual value of the photoresist layer 300 on the surface of wafer 100 is considered to be higher than the preset residual value, and the photoresist layer 300 is not removed thoroughly. The wet cleaning process needs to be repeated until the residual value is lower than the preset residual value. Of course, the criteria for judging residues will differ for devices at different process nodes. The preset residual value can be adaptively adjusted according to the judgment requirements of different devices to make the preset residual value adaptable to the process requirements of devices at different process nodes.

[0101] In some embodiments, after removing the photoresist layer 300 to expose the surface of the tested wafer 100, the method may further include dicing and packaging the wafer 100 to form a semiconductor device. Because the photoresist layer 300 is used to protect the wafer 100 during testing, testing reliability is improved, defective chips 121 can be effectively rejected, packaging yield can be increased, and the quality and reliability of the device can be enhanced.

[0102] It should be noted that although the steps of the wafer testing method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0103] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A wafer testing method, characterized by, include: A wafer is provided, the wafer including test pads; the wafer includes a device region and a dicing region, the device region having a plurality of chips formed thereon, the test pads including a first test pad located in the dicing region and a second test pad located in the device region, wherein the first test pad is used for wafer acceptance testing and the second test pad is used for chip testing; A photoresist layer is formed, the photoresist layer covering the surface of the wafer; The wafer is tested by using a test probe to penetrate the photoresist layer and make the test probe contact the test pad; wherein, after wafer acceptance testing and before chip testing, the process includes: coating the photoresist layer with a photoresist material identical to the photoresist layer, so that the photoresist material fills the probe hole formed by the test probe on the photoresist layer; Remove the photoresist layer to expose the surface of the wafer after testing.

2. The wafer testing method of claim 1, wherein After forming the photoresist layer, the process includes: The surface of the photoresist layer is inspected to obtain the distribution and size of particles on the surface of the photoresist layer; If the total projected area of ​​the particles on the surface of the photoresist layer accounts for more than or equal to 1% of the surface area of ​​the photoresist layer and / or the maximum size of the particles is greater than 0.1 μm, then the photoresist layer is cleaned to remove the particles.

3. The wafer testing method of claim 1, wherein After forming the photoresist layer, the process includes: The thickness of the photoresist layer was measured; If the thickness of the photoresist layer is within a preset thickness range, the wafer is tested.

4. The wafer testing method of claim 1, wherein include: During the test, if the thickness of the photoresist layer is less than the minimum preset thickness, the photoresist coating process is repeated to increase the thickness of the photoresist layer until the thickness of the photoresist layer is within the preset thickness range.

5. The wafer testing method according to claim 3 or 4, wherein The preset thickness range of the photoresist layer is 50nm~500nm.

6. The wafer testing method of claim 5, wherein The preset thickness range of the photoresist layer is 100nm~300nm.

7. The wafer testing method of claim 1, wherein Forming a photoresist layer includes: Photoresist material is spin-coated onto the surface of the wafer; The photoresist material is dried to make the hardness of the formed photoresist layer within the range of 150HV to 350HV, so that the test probe can penetrate the photoresist layer and contact the test pad.

8. The wafer testing method of claim 7, wherein, The drying temperature is 80℃~120℃, and the drying time is 30s~120s.

9. The wafer testing method of claim 1, wherein The chip testing includes an aging test, during which the photoresist layer adheres tightly to the surface of the wafer at the aging test temperature.

10. The wafer testing method of claim 9, wherein, The aging test temperature is -50℃ to 120℃.

11. The wafer testing method of claim 1, wherein Removing the photoresist layer includes: The first portion of the photoresist layer is removed using a dry ashing process. The second part of the photoresist layer is then removed using a wet cleaning process, wherein the thickness of the first part is greater than the thickness of the second part.

12. The wafer testing method of claim 11, wherein, After removing the photoresist layer, the process includes: detecting the surface of the exposed wafer to obtain a residue value of the photoresist layer, and repeating the wet cleaning process step until the residue value is lower than a preset residue value if the residue value is higher than the preset residue value.

13. The wafer testing method of any one of claims 1-4, wherein, The photoresist layer has optical transparency to allow visible light to pass through, and the test pad can be identified by passing through the photoresist layer.

Images