A method, device and storage medium for improving resistance value uniformity within a wafer

Abstract

This invention relates to the field of integrated circuit manufacturing technology, and discloses a method, apparatus, and storage medium for improving the uniformity of resistance values ​​within a wafer. The method includes the following steps: acquiring the measured resistance values ​​and chip coordinate data of chips in a reference wafer fabricated using a single full-field exposure process; defining the central region of the reference wafer and calculating the target resistance value, and identifying edge-problem chips that deviate from the target resistance value; calculating the effective length compensation value of the polysilicon layer pattern based on the deviation between the measured resistance value and the target resistance value; adjusting the effective length of the corresponding design pattern in the original design data of the target mask according to the effective length compensation value and the chip coordinate data, generating optimized mask data; and performing a single full-field exposure on the wafer to be processed using the optimized mask. This invention effectively improves the uniformity of resistance values ​​within a wafer and increases product yield through local optimization of the mask design layer pattern size, and is particularly suitable for mass production under a single full-field exposure process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method, apparatus and storage medium for improving the uniformity of resistance values ​​within a wafer. Background Technology

[0002] In the manufacturing of power semiconductor devices (such as BDI devices), the uniformity of resistance within the wafer is a key parameter affecting device performance consistency and production yield. Resistance is primarily influenced by ion implantation concentration and the annealing process. For 5-inch and 6-inch wafers, due to cost and efficiency considerations, single-shot lithography is commonly used. However, existing ion implantation equipment and annealing furnaces have inherent limitations in their process capabilities. This typically manifests as differences in ion implantation dose or annealing temperature between the wafer edge region and the center region. This results in systematically higher or lower resistance values ​​at the wafer edge, exceeding product specifications and creating fixed edge failure areas, leading to significant yield losses.

[0003] Currently, there are two main methods in the industry for improving the uniformity of resistance values ​​within wafers: one is to optimize and adjust process equipment parameters, but this method is limited by the physical limitations of the equipment, resulting in limited improvement potential; the other is through monitoring and real-time compensation during the photolithography process. For example, existing technology discloses a method for improving feature linewidth uniformity, which involves measuring the feature linewidth offset after photolithography and etching of the test wafer, calculating the photolithography parameter compensation value, and then applying the compensated parameters to subsequent photolithography processes on the wafer. The core idea of ​​this approach is to correct dimensional deviations during the etching process through dynamic adjustment of photolithography parameters, thereby indirectly improving the uniformity of resistance values. However, this approach has significant limitations: firstly, it is applicable to multi-exposure processes, requiring separate compensation calculations for each SHOT (exposure unit), and cannot adapt to the global exposure characteristics of a single-exposure process; secondly, this approach relies on the linear relationship between photolithography parameters and feature linewidth, while in actual production, resistance values ​​are also affected by subsequent processes such as ion implantation and annealing, making it difficult to fundamentally solve the problem of R-value uniformity through photolithography parameter compensation alone. For example, existing technology also discloses a method to reduce critical dimension drift. This method involves designing multiple test masks, establishing an etching prediction model, and correcting the perimeter and linewidth of the test mask pattern based on the model prediction results, thereby improving the uniformity of critical dimensions after etching. The core of this approach is to offset the dimensional drift caused by the etching process through pre-correction of the mask pattern. However, this approach also has shortcomings: First, it requires designing multiple test masks and conducting numerous process experiments to establish the prediction model, resulting in high development costs and long development cycles. Second, this approach requires continuous monitoring of the etching critical dimensions during production and adjusting the mask pattern based on the monitoring results, relying on manual intervention and failing to achieve fully automated production. Third, the core application scenario of this approach is the critical dimension control of the etching process, lacking specificity for resistance deviations caused by processes such as ion implantation and annealing, and cannot effectively solve the problem of out-of-specification R-values ​​at the edge of wafers exposed in a single exposure.

[0004] Clearly, existing process parameter compensation schemes are only applicable to multi-exposure processes, which require individual parameter compensation for each exposure unit. However, single full-field exposure processes do not have the division of multiple exposure units, so such schemes cannot be applied. Mask pattern optimization schemes require continuous process monitoring and manual intervention, which contradicts the high efficiency and low cost goals pursued by single-exposure processes. Furthermore, they are designed for dimensional drift in the etching process and cannot solve the resistance deviation caused by ion implantation and annealing.

[0005] Therefore, there is an urgent need for a wafer R-value uniformity improvement solution that does not rely on equipment upgrades and is applicable to single full-field exposure mode. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, the present invention aims to provide a method, apparatus and storage medium for improving the uniformity of resistance values ​​within a wafer, in order to solve the problem that the resistance values ​​of the wafer edge chips fail due to insufficient ion implantation equipment capacity and uneven annealing temperature when using the existing single full-field exposure process.

[0007] The first aspect of this invention provides a method for improving the uniformity of resistance values ​​within a wafer, comprising the steps of: obtaining measured resistance values ​​and chip coordinate data of chips in a reference wafer fabricated using a single full-field exposure process; defining a central region of the reference wafer, taking the average of the measured resistance values ​​of several chips located in the central region as a target resistance value, and selecting edge-problem chips from the reference wafer whose measured resistance values ​​deviate from the target resistance value; calculating an effective length compensation value for the polysilicon layer pattern in the edge-problem chip based on the deviation between the measured resistance value and the target resistance value; adjusting the effective length of the polysilicon layer design pattern corresponding to the edge-problem chip in the original design data of the target mask based on the effective length compensation value and the corresponding chip coordinate data, thereby generating optimized mask data; and performing a single full-field exposure on the wafer to be processed using a mask fabricated according to the optimized mask data to improve the uniformity of resistance values ​​within the wafer.

[0008] Optionally, in a first implementation of the first aspect of the present invention, a central region of the reference wafer is defined, and the average value of the measured resistance values ​​of a plurality of chips located in the central region is taken as the target resistance value. Edge-problem chips whose measured resistance values ​​deviate from the target resistance value are then selected from the reference wafer. This includes the following steps: defining a circular region with the center of the reference wafer as the origin and a new radius of 1 / 4 to 3 / 4 of the reference wafer's radius as the new radius; selecting the measured resistance values ​​of a plurality of chips from the central region using a ring-shaped uniform sampling rule and calculating the average value, taking the average value as the target resistance value; comparing the measured resistance values ​​of chips located outside the central region of the reference wafer with the target resistance value, selecting chips whose deviation rate exceeds a preset threshold, and defining the selected chips as edge-problem chips.

[0009] Optionally, in a second implementation of the first aspect of the present invention, the measured resistance values ​​of several chips are selected from the central region using a ring-shaped uniform sampling rule, and the average value is calculated. The average value is then used as the target resistance value. The steps include: dividing the central region into at least three ring-shaped sub-regions with the center of the reference wafer as the origin; uniformly selecting the measured resistance values ​​of at least three chips within each ring-shaped sub-region with the same center angle; averaging the measured resistance values ​​of the chips selected within all ring-shaped sub-regions, and defining the average value as the target resistance value.

[0010] Optionally, in a third implementation of the first aspect of the present invention, the measured resistance value of a chip located outside the central region of the reference wafer is compared with the target resistance value to screen out chips with a deviation rate exceeding a preset threshold, and the screened chips are defined as edge problem chips. This includes the following steps: setting a preset threshold for the deviation rate based on the product parameter specifications and process capabilities of the reference wafer; traversing all chips outside the central region of the reference wafer, calculating the resistance value deviation rate for each chip, where the resistance value deviation rate = |measured resistance value - target resistance value| / target resistance value; comparing the chip's deviation rate with the preset threshold, and if the chip's deviation rate is greater than the preset threshold, then the chip is defined as an edge problem chip.

[0011] Optionally, in a fourth implementation of the first aspect of the present invention, calculating the effective length compensation value of the polysilicon layer pattern in the edge-problem chip based on the deviation between the measured resistance value and the target resistance value includes the following steps: for each edge-problem chip, if the measured resistance value is greater than the target resistance value, then formula L is used. i =L d -S*|R i -R0| / ρ0 calculates the compensated length of the polysilicon layer pattern in the edge-problem chip, where the effective length compensation value ΔL = L. d -L i , where L i L represents the compensated length of the polysilicon layer pattern corresponding to the i-th edge-problem chip. d ρ0 represents the reference length of the polysilicon layer pattern corresponding to the chip in the central region, S represents the cross-sectional area of ​​the polysilicon layer pattern corresponding to the chip in the central region, and R represents the resistivity of the polysilicon layer corresponding to the chip in the central region. i Let Ri be the measured resistance value of the i-th edge problem chip, and R0 be the target resistance value. For each edge problem chip, if the measured resistance value is less than the target resistance value, then formula L is used. i =L d +S*|R i -R0| / ρ0 calculates the compensated length of the polysilicon layer pattern in the edge-problem chip, where the effective length compensation value ΔL = L. d -L i .

[0012] Optionally, in a fifth implementation of the first aspect of the present invention, the effective length of the polysilicon layer design pattern corresponding to the edge-problem chip in the original design data of the target mask is adjusted according to the effective length compensation value and the corresponding chip coordinate data to generate optimized mask data. This includes the steps of: obtaining the original design data of the target mask; locating the corresponding polysilicon layer design pattern in the original design data of the target mask according to the chip coordinate data of the edge-problem chip; adjusting the effective length of the polysilicon layer design pattern according to the effective length compensation value to generate optimized mask data.

[0013] Optionally, in the sixth implementation of the first aspect of the present invention, obtaining the measured resistance value and chip coordinate data of the chip in the reference wafer fabricated using a single full-field exposure process includes the following steps: selecting a wafer with specifications completely consistent with the wafer to be processed and fabricated using a single full-field exposure process as the reference wafer; fixing the reference wafer on a probe test stage and calibrating the center and coordinate system of the reference wafer using a visual positioning system; and, following a preset path, contacting the test pads of each chip on the reference wafer point by point with the probe, and recording the coordinate data of each chip on the reference wafer and the corresponding measured resistance value.

[0014] A second aspect of the present invention provides an apparatus for improving the uniformity of resistance values ​​within a wafer, comprising: an acquisition module for acquiring measured resistance values ​​and chip coordinate data of chips in a reference wafer fabricated using a single full-field exposure process; a screening module for defining a central region of the reference wafer, taking the average of the measured resistance values ​​of several chips located in the central region as a target resistance value, and screening out edge-problem chips whose measured resistance values ​​deviate from the target resistance value from the reference wafer; a calculation module for calculating an effective length compensation value for the polysilicon layer pattern in the edge-problem chip based on the deviation between the measured resistance value and the target resistance value; an optimization module for adjusting the effective length of the polysilicon layer design pattern corresponding to the edge-problem chip in the original design data of the target mask based on the effective length compensation value and the corresponding chip coordinate data, thereby generating optimized mask data; and a processing module for performing a single full-field exposure on the wafer to be processed using a mask fabricated according to the optimized mask data, so as to improve the uniformity of resistance values ​​within the wafer.

[0015] A third aspect of the present invention provides an electronic device comprising: a memory and at least one processor, the memory storing computer-readable instructions, the memory and the at least one processor being interconnected via a circuit; the at least one processor invokes the computer-readable instructions in the memory to cause the electronic device to perform various steps of the method described above for improving the uniformity of resistance values ​​within a wafer.

[0016] A fourth aspect of the present invention provides a computer-readable storage medium storing computer-readable instructions that, when executed on a computer, cause the computer to perform the steps of the method described above for improving the uniformity of resistance values ​​within a wafer.

[0017] Beneficial effects: This invention abandons the passive control approach of relying on process compensation in traditional solutions and turns to an active optimization strategy of design and process collaboration. By analyzing the measured resistance distribution data of the reference wafer, edge-problem chips are identified. Based on the resistance formula, a quantitative relationship between resistance deviation and the effective length of the polysilicon layer pattern is established. This optimizes the polysilicon layer pattern design of edge-problem chips on the mask, fundamentally offsetting the resistance deviation caused by process environment differences, and improving the uniformity of resistance values ​​within the wafer during a single full-field exposure. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a method for improving the uniformity of resistance values ​​within a wafer, as provided in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram illustrating the division of a central region in a reference wafer according to the present invention.

[0022] Figure 3 This is a schematic diagram of a device structure for improving the uniformity of resistance values ​​within a wafer, provided by the present invention.

[0023] Figure 4 This is a schematic diagram of the electronic device structure provided by the present invention. Detailed Implementation

[0024] This invention provides a method, apparatus, and storage medium for improving the uniformity of resistance values ​​within a wafer. The terms "first," "second," "third," "fourth," etc. (if present)," in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" or "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Please see Figure 1 , Figure 1 A flowchart of a method for improving the uniformity of resistivity within a wafer, provided by the present invention, is shown in the figure, and includes the following steps: S10. Obtain the measured resistance value and chip coordinate data of the chip in the reference wafer fabricated based on the single full-field exposure process; Specifically, the core manufacturing process of power semiconductor devices includes key steps such as wafer fabrication, ion implantation, annealing, photolithography, etching, and metallization. Among these, ion implantation and annealing directly determine the resistance distribution of the wafer. For 5-inch or 6-inch wafers, the corresponding diameters are 125mm or 150mm, and the thickness is 500-700μm. The commonly used material is single-crystal silicon, while silicon carbide is used in some high-performance applications. Single-pass full-field exposure refers to performing a single photolithography exposure on the entire wafer using a single mask, eliminating the need for multiple step-by-step exposures. It has advantages such as short process cycle, low equipment cost, and high throughput, and is particularly suitable for manufacturing power devices with small chip sizes and relatively simple pattern structures, such as the boron diffusion implantation process for BDI wafers.

[0026] In a single full-field exposure process, the mask pattern design directly determines the physical structure of the chip on the wafer. The polysilicon layer, as a crucial component of power devices (such as gate and resistor layers), has dimensional parameters such as length, width, and thickness that satisfy the classic resistance formula R=ρL / S (where R is the resistance value, ρ is the resistivity, L is the effective length, and S is the cross-sectional area). Therefore, the dimensional accuracy of the polysilicon layer pattern is one of the core factors affecting the chip's R value.

[0027] The core objective of step S10 in this embodiment is to obtain the measured resistance values ​​and chip coordinates (spatial coordinate information) of all chips on the reference wafer, providing a data foundation for subsequent edge chip localization and mask pattern optimization design. Specifically, it includes the following steps: S11. Select a wafer that is consistent with the specifications and process parameters of the wafer to be processed and is produced by a single full-field exposure process as the reference wafer. Specifically, in this embodiment, a wafer that is completely identical to the wafer to be processed in terms of specifications and process parameters and has undergone a single full-field exposure process is selected as the reference wafer. The completely identical specifications include, but are not limited to: wafer diameter, thickness, material, doping type, chip layout (such as chip size, number of rows and columns, and spacing); the completely identical process parameters include, but are not limited to: ion type, dose, and energy of ion implantation, annealing temperature, time, and atmosphere, and exposure method photolithography exposure dose and focal length.

[0028] For example, the wafer to be processed is a 5-inch BDI wafer, 125mm in diameter and 625μm thick, made of P-type single-crystal silicon, with boron as the dopant ion and an ion implantation dose of 1×10⁻⁶. 15 / cm², implantation energy 50keV, annealing temperature 1100℃, holding time 30 minutes, photolithography using a single exposure process, chip size 2mm×2mm, a total of 360 chips distributed on the wafer (18 rows × 20 columns), chip spacing 0.5mm. Another wafer produced in the same batch and under the same process conditions was selected as a reference wafer to ensure that its specifications and process parameters were completely consistent with the wafer to be processed.

[0029] The purpose of selecting a reference wafer in this embodiment is to ensure that the resistance distribution characteristics of the reference wafer can truly reflect the differences in the process environment of the wafer to be processed, avoid data deviations caused by inconsistent specifications or process parameters, and thus ensure the effectiveness of subsequent optimization design.

[0030] S12. Fix the reference wafer on the probe test stage and calibrate the center and coordinate system of the reference wafer using a visual positioning system; Specifically, in this embodiment, the reference wafer is first placed on the vacuum chuck of the probe test stage, and the vacuum adsorption device is activated to ensure that the wafer is firmly fixed without displacement or warping. Then, the vision positioning system is activated to capture a panoramic image of the reference wafer. The outline of the reference wafer is identified by an image recognition algorithm (such as the Hough circle detection algorithm), and the center coordinates (X0, Y0) of the reference wafer are calculated. A two-dimensional rectangular coordinate system is established with the center as the origin.

[0031] S13. Following the preset path, the probe contacts the test pads of each chip on the reference wafer point by point, and records the coordinate data of each chip on the reference wafer and the corresponding measured resistance value.

[0032] Specifically, to improve testing efficiency and data integrity, a spiral path is adopted to test point by point from the wafer center to the edge, avoiding repeated testing or missing chips. The path planning algorithm is based on the chip layout of the wafer, traversing each chip sequentially in the order of center → inner layer → middle layer → outer layer. Each chip typically has two test pads (input pad and output pad), and the probes use a dual-probe synchronous contact method. The probes are made of tungsten, with a tip diameter of 5μm, and the contact pressure is controlled at 10-20mN to avoid damaging the pads or causing poor contact.

[0033] As an example, a Keithley 2450 source meter was used to measure the resistance value. The measurement mode was DC four-point probe method, the test current was 1mA, the voltage measurement accuracy was ±0.1μV, and the resistance value calculation accuracy was ±0.1Ω, which meets the high precision requirements for resistance value measurement of power devices.

[0034] As an example, data is recorded in CSV format, with each data entry containing fields such as chip ID, X coordinate (mm), Y coordinate (mm), measured resistance value (Ω), and measurement time.

[0035] The measured resistance values ​​obtained in this embodiment cover the center and edge regions of the entire reference wafer, providing a complete dataset for subsequent center region definition and edge problem chip screening.

[0036] S20. Define the central region of the reference wafer, take the average of the measured resistance values ​​of several chips located in the central region as the target resistance value, and screen out edge problem chips whose measured resistance values ​​deviate from the target resistance value from the reference wafer. In this embodiment, the core objective of step S20 is to determine the target resistance value based on the data collected in step S10, and to screen out edge problem chips that need optimization. Specifically, it includes the following sub-steps: S21. The circular region defined by taking the center of the reference wafer as the origin and using 1 / 4 to 3 / 4 of the radius of the reference wafer as the new radius is defined as the central region. Specifically, the division of the central region of the reference wafer is not absolute. For example, the new radius of the central region can also be one-quarter, one-third, one-half, two-thirds, three-quarters, etc., of the radius of the reference wafer. Figure 2 As shown, in this embodiment, two-thirds of the radius of the reference wafer is preferably used as the boundary of the central region. This is an optimization result based on a large amount of process test data: the chip in this region is least affected by ion implantation beam scattering and annealing temperature field deviation, and the resistance value distribution is the most uniform, so it can be used as the resistance value reference for the entire wafer.

[0037] As an example, the radius R of a 5-inch reference wafer total =62.5mm, the new radius R of the central regioncenter =62.5mm×2 / 3≈41.7mm, the area of ​​the central region S center =π×(41.7mm)²≈5470mm², the area of ​​the entire wafer S total =π×(62.5mm)²≈12272mm², the central area accounts for about 44.6% of the total area, and the number of chips in this area is about 360×44.6%≈161.

[0038] The definition of the central region in this embodiment is universal and is not affected by wafer size or chip layout, making it applicable to various 5-inch / 6-inch single-exposure wafers.

[0039] S22. Using a circular uniform sampling rule, select the measured resistance values ​​of several chips from the central region and calculate the average value, and use the average value as the target resistance value. This embodiment employs a circular uniform sampling rule to ensure that the sampling chips are evenly distributed at different radii in the central region, avoiding deviations in the target resistance value caused by sampling being concentrated in a localized area of ​​the central region. Specifically, the following steps are included: S221. Using the center of the reference wafer as the origin, the central region is divided into at least 3 annular sub-regions according to the radius. In this embodiment, the number of annular sub-regions can be adjusted according to the reference wafer size and chip density, usually 3-5, to ensure that there are enough chip samples in each sub-region; preferably, the central region is uniformly divided into at least 3 annular sub-regions with the same radius.

[0040] For example, the central region of a 5-inch reference wafer has a radius of 41.7 mm, which is evenly divided into three annular sub-regions: First annular sub-region (inner layer): radius 0-13.9mm; Second annular sub-region (middle layer): radius 13.9-27.8mm; Third annular sub-region (outer layer): radius 27.8-41.7mm.

[0041] For example, if the central region of a 6-inch reference wafer has a radius of 50mm, it can be evenly divided into 4 annular sub-regions: First annular sub-region: radius 0-12.5mm (50mm×1 / 4); Second annular sub-region: radius 12.5-25mm; Third annular sub-region: radius 25-37.5mm; Fourth annular sub-region: radius 37.5-50mm.

[0042] S222, Select the measured resistance values ​​of at least 3 chips in each annular sub-region; In this embodiment, it is preferable to uniformly select the measured resistance values ​​of at least 3 chips in each annular sub-region using the same center angle. The setting of the same center angle ensures that the sampling chips are evenly distributed in the annular sub-region. For example, when selecting 3 chips in each annular sub-region, the center angle is 360° / 3=120°; when selecting 4 chips, the center angle is 360° / 4=90°.

[0043] As an example, three chips are selected within the first annular sub-region (0-13.9mm) of a 5-inch reference wafer, with an angle of 120° between adjacent centers.

[0044] S223. Calculate the average value of the measured resistance values ​​of the chips screened in all annular sub-regions, and define the average value as the target resistance value; In this embodiment, the arithmetic mean method is used to calculate the target resistance value to ensure its stability. The target resistance value represents the standard resistance value of the wafer under ideal process conditions and is the core benchmark for subsequent screening of edge-prone chips and calculation of compensation values.

[0045] For example, a total of 9 chips are selected from 3 annular sub-regions of a 5-inch reference wafer, with R values ​​of 99.5Ω, 100.3Ω, and 99.8Ω (first annular sub-region); 100.2Ω, 100.5Ω, and 99.7Ω (second annular sub-region); and 100.1Ω, 99.9Ω, and 100.4Ω (third annular sub-region). The target resistance value R0 = (99.5 + 100.3 + 99.8 + 100.2 + 100.5 + 99.7 + 100.1 + 99.9 + 100.4) / 9 = 100.0Ω.

[0046] S23. Compare the measured resistance value of the chip located outside the center region of the reference wafer with the target resistance value, screen out the chips whose deviation rate exceeds a preset threshold, and define the screened chips as edge problem chips. This embodiment clarifies the location and R-value deviation of edge-problem chips requiring pattern optimization by comparing resistance values, providing a precise target for subsequent compensation value calculation and mask optimization. Specifically, it includes the following steps: S231. Based on the product parameter specifications and process capabilities of the reference wafer, set a preset threshold for the deviation rate; Specifically, the preset threshold is set based on the product's parameter specifications and manufacturing capabilities, typically at 5%, 10%, or 15%, with the specific value adjustable according to the actual application scenario. For example, automotive electronic power devices have high requirements for resistance consistency, so the preset threshold can be set to 5%; industrial control devices can be set to 10%; and mid-to-low-end consumer electronics devices can be set to 15%.

[0047] For example, the product parameter specification of a certain automotive electronics BDI wafer requires a resistance value of 100±5Ω, so the preset threshold is set to 5% (that is, the resistance value must be in the range of 95Ω-105Ω).

[0048] For example, the product parameter specification of a certain industrial control power MOSFET wafer requires a resistance value of 200±15Ω, so the preset threshold is set to 15% (that is, the resistance value must be in the range of 185Ω-215Ω).

[0049] S232. Traverse the chips outside the center region of the reference wafer and calculate the resistance deviation rate for each chip. Resistance deviation rate = |measured resistance value - target resistance value| / target resistance value. Specifically, the formula for calculating the resistance value deviation rate can be simplified to: Deviation rate = |R i R0| / R0×100%, where R i Ri is the measured resistance value of the i-th chip outside the central region, and R0 is the target resistance value.

[0050] As an example, the measured R value of an edge chip on a 5-inch reference wafer is R. i =150Ω, R0=100Ω, its deviation rate =|150 100 / 100×100%=50%; another edge chip R i =90Ω, deviation rate=|90 100 / 100×100%=10%.

[0051] S233. Compare the chip's deviation rate with a preset threshold. If the chip's deviation rate is greater than the preset threshold, then define the chip as an edge-problem chip. Specifically, if the deviation rate of a chip located outside the central region is greater than a preset threshold, it is defined as an edge problem chip, indicating that the original graphic design of the chip needs to be further optimized; if the deviation rate is less than or equal to the preset threshold, the chip does not need to be optimized and the original graphic design is maintained.

[0052] For example, if a 5-inch reference wafer contains 199 chips in the edge region outside the center area, and the preset threshold is 15%, then 12 of these chips have a deviation rate greater than 15% (R0). i >115Ω or Ri <85Ω), these 12 chips are defined as edge problem chips.

[0053] S30. Calculate the effective length compensation value of the polysilicon layer pattern in the edge problem chip based on the deviation between the measured resistance value and the target resistance value. In this embodiment, step S30 calculates the effective length compensation value of the polysilicon layer pattern corresponding to each edge-problem chip based on the deviation data between the resistance formula and the R value, providing a quantitative basis for mask pattern optimization. Specifically, the resistance value of the polysilicon layer satisfies the classical resistance formula: R = ρL / S, where R is the resistance value of the polysilicon layer (Ω); ρ is the resistivity of the polysilicon layer (Ω). The value of ρ is determined by process parameters such as ion implantation dose, annealing temperature, and doping type; L is the effective length (μm) of the polysilicon layer pattern, i.e., the path length of current through the polysilicon layer; S is the cross-sectional area (μm²) of the polysilicon layer pattern, S=W×T, where W is the width (μm) of the polysilicon layer pattern and T is the thickness (μm) of the polysilicon layer. For the chip in the center region of the reference wafer, its process environment is stable and the ρ value is uniform, denoted as ρ0. The corresponding effective length of the polysilicon layer pattern is L (reference length), and the cross-sectional area is S (the width W and thickness T of the polysilicon layer are the same for the chips in the center region and the edge region, so S is a constant value). Then the resistance value of the chip in the center region is R=ρ0L / S, i.e., ρ0=RS / L. For chips with edge problems, due to differences in the process environment (such as changes in ion implantation dose and annealing temperature), its ρ value becomes ρ i (ρ) i (≠ρ0), which causes its resistance value to deviate from the resistance value of the chip in the central area.

[0054] The core idea of ​​this embodiment is to adjust the effective length of the polysilicon layer pattern of the edge-problem chip to correct its resistance value to the target resistance value. Specifically, this includes the following: S31. For each edge-prone chip, if the measured resistance value is greater than the target resistance value, then use formula L. i =L d -S*|R i -R0| / ρ0 calculates the compensated length of the polysilicon layer pattern in the edge-problem chip, where the effective length compensation value ΔL = L. d -L i It is positive, where L i L represents the compensated length of the polysilicon layer pattern corresponding to the i-th edge-problem chip. d ρ0 represents the reference length of the polysilicon layer pattern corresponding to the chip in the central region, S represents the cross-sectional area of ​​the polysilicon layer pattern, and R represents the resistivity of the polysilicon layer corresponding to the chip in the central region. iRi is the measured resistance value of the i-th edge problem chip, and R0 is the target resistance value; Specifically, for edge-problem chips, when R i When R0 (the measured resistance value is greater than the target resistance value), then formula L is used. i =L d -S*|R i -R0| / ρ0 calculates the compensated length of the polysilicon layer pattern in the edge-problem chip, where the effective length compensation value ΔL = L. d -L i A positive value indicates that the effective length of the polysilicon layer pattern in the current edge-problem chip needs to be reduced to lower the resistance value in order to correct the resistance value of the edge-problem chip to the target resistance value.

[0055] As an example, the reference length L for polysilicon layer patterning design of the central region chip. d The thickness is 15 μm (obtained from the original design data of the mask); the cross-sectional area S: the width W of the polysilicon layer pattern is 3 μm, and the thickness T is 0.6 μm (measured by scanning electron microscopy SEM), therefore S = 3 μm × 0.6 μm = 1.8 μm²; the target resistance value R0 = 100 Ω; the resistivity ρ0: from the formula ρ0 = R0 × S / L d The calculation yields ρ0 = 100Ω × 1.8μm² / 15μm = 12Ω μm; Suppose that the measured R value of a certain edge-problem chip is R i =120Ω, at this point Ri>R0, the formula for reducing the effective length is used to calculate: |R i R0|=20Ω;S×|Ri R0| / ρ0=1.8μm²×20Ω / 12Ω μm = 3μm; at this time L i =L d 3μm=15μm 3μm = 12μm; that is, ΔL = L d -L i =3μm, indicating that the effective length of the polysilicon layer pattern of the chip with edge problems needs to be reduced by 3μm to 12μm. After adjustment, its resistance value will be corrected to 100Ω.

[0056] S32. For each edge-prone chip, if the measured resistance value is less than the target resistance value, then use formula L. i =L d +S*|R i -R0| / ρ0 calculates the compensated length of the polysilicon layer pattern in the edge-problem chip, where the effective length compensation value ΔL = L.d -L i is negative.

[0057] Specifically, for the edge problem chip, when R i < R0 (the measured resistance value is less than the target resistance value), the formula L i = L d + S * |R i - R0| / ρ0 is used to calculate the compensated length of the polysilicon layer pattern in the edge problem chip. At this time, the effective length compensation value △L = L d - L i is negative, indicating that the effective length of the polysilicon layer pattern in the current edge problem chip needs to be increased to increase the resistance value in order to correct the resistance value of the edge problem chip to the target resistance value.

[0058] As an example, for an edge problem chip with a measured resistance value R i = 85Ω and R0 = 100Ω, at this time R i < R0, the formula for increasing the effective length is used for calculation: |R i R0| = 15Ω; S × |R i R0| / ρ0 = 1.8μm² × 15Ω / 12Ω μm = 2.25μm; L i = L d + 2.25μm = 15μm + 2.25μm = 17.25μm; that is, △L = L d - L i = -2.25μm, indicating that the effective length of the polysilicon layer pattern of this edge problem chip needs to be increased by 2.25μm and adjusted to 17.25μm. After adjustment, its resistance value will be corrected to 100Ω.

[0059] S40. According to the effective length compensation value and the corresponding chip coordinate data, adjust the effective length of the polysilicon layer design pattern corresponding to the edge problem chip in the original design data of the target mask plate to generate optimized mask plate data; The main function of step S40 in this embodiment is to adjust the original design data of the target mask plate to generate optimized mask plate data, which specifically includes the following steps: S41. Obtain the original design data of the target mask plate; Specifically, the raw design data of the target mask is typically stored in GDSII (Graphic Data System II) format. This format is a common mask graphic data format in the semiconductor industry, containing information such as the graphic structure, dimensions, and coordinates of all chips on the wafer. The raw design data can be exported using mask design software (such as CadenceVirtuoso). Its core content includes the graphic data of the polysilicon layer, such as the coordinates of the top left and bottom right corners of the rectangular graphic, and the layer number.

[0060] Furthermore, after obtaining the original design data, the data needs to be preprocessed, including format conversion (such as converting GDSII format to ASCII format for editing), graphic layering (such as extracting the graphic data of the polysilicon layer and ignoring the data of other layers such as oxide and metal layers), and coordinate calibration (ensuring that the chip coordinates on the mask are consistent with the chip coordinates of the reference wafer), in preparation for subsequent graphic adjustments.

[0061] S42. Based on the chip coordinate data of the edge problem chip, locate the corresponding polysilicon layer design pattern in the original design data of the target mask. Specifically, since the chip coordinates in the mask design data and the chip coordinates of the reference wafer use the same coordinate system (with the wafer center as the origin), precise positioning can be achieved through coordinate matching. For example, extract the coordinate data (Xi, Yi) of the edge-prone chip, such as (110mm, 110mm), (105mm, 120mm), etc.; in the original mask design data, traverse all the polysilicon layer patterns of the chips, and find the pattern whose coordinates match (Xi, Yi) of its corresponding chip. Furthermore, if there are multiple polysilicon layer patterns within the chip, it is necessary to filter out the polysilicon layer pattern used to implement the resistor function based on the pattern's functional identifier (such as the annotation "Resistor Poly" in the design file). This pattern is the target pattern that needs to be adjusted.

[0062] S43. Adjust the effective length of the polysilicon layer design pattern according to the effective length compensation value to generate optimized mask data.

[0063] Specifically, the adjustment method in this embodiment depends on the effective length direction of the polysilicon layer pattern (such as the X-axis or Y-axis direction). Typically, the length is adjusted along the current path direction, while the width remains constant, because changes in width have a relatively small impact on the resistance value, and adjusting the width may lead to pattern structure conflicts. During wafer fabrication, the effective length direction of the polysilicon layer pattern is clearly indicated in the mask design data through the current path, or determined by the positional relationship of the pads at both ends of the polysilicon layer; for example, the path of current flowing from one pad to the other is the effective length direction.

[0064] For example, if the effective length direction is the X-axis (the left and right boundaries of the pattern are distributed along the X-axis), the length is changed by adjusting the X-coordinate of the right boundary of the pattern, while the X-coordinate of the left boundary remains unchanged, to avoid the pattern overlapping with other structures within the chip. If the effective length direction is the Y-axis (the upper and lower boundaries of the pattern are distributed along the Y-axis), the length is changed by adjusting the Y-coordinate of the upper boundary of the pattern, while the Y-coordinate of the lower boundary remains unchanged. The adjusted pattern size must meet the minimum linewidth requirements of the photolithography process to avoid the pattern size being smaller than the process limit due to length adjustment, which would affect the photolithography effect.

[0065] As an example, suppose the effective length direction of the polysilicon layer pattern in the edge-problem chip is the X-axis direction, the original design has a left boundary X-coordinate of 10μm, a right boundary X-coordinate of 25μm, and a length L. d =15μm; if based on the calculated compensated length value L i =12μm, therefore the right boundary X coordinate needs to be adjusted to 10μm+12μm=22μm. After adjustment, the left boundary X=10μm, the right boundary X=22μm, and the width remains unchanged.

[0066] As an example, suppose the effective length direction of the polysilicon layer pattern in the edge-prone chip is the Y-axis direction, the lower boundary Y-coordinate of the original design is 5μm, the upper boundary Y-coordinate is 25μm, and the length L d =20μm; the compensated length value L was obtained based on the calculation. i =23.2μm, therefore the upper boundary Y coordinate needs to be adjusted to 5μm+23.2μm=28.2μm. After adjustment, the lower boundary Y of the graphic is 5μm, the upper boundary Y is 28.2μm, the length is 23.2μm, and the width remains unchanged.

[0067] After the polysilicon layer pattern is adjusted, the adjusted polysilicon layer pattern data is merged with the original design data of other layers (such as oxide layers and metal layers) to generate optimized mask data. The format is still GDSII, which is used for subsequent mask manufacturing. Further consistency checks are performed on the optimized mask data to ensure that the adjusted pattern has no overlap or breaks, and that the spacing between it and other structures within the chip meets design rules, thus avoiding device malfunctions caused by pattern adjustments.

[0068] S50. A single full-field exposure is performed on the wafer to be processed using a mask manufactured according to the optimized mask data, in order to improve the uniformity of the resistance value within the wafer.

[0069] Specifically, in this embodiment, the mask can be manufactured using electron beam lithography or laser direct writing technology based on the optimized mask data. The mask is then applied to the lithography process of the wafer to be processed for a single full-field exposure. Subsequent processes such as ion implantation, annealing, and etching remain consistent with the reference wafer without the need for additional parameter adjustments, thereby improving the uniformity of the resistance value within the wafer.

[0070] In summary, the inventive concept of this invention can be broken down into the following three key steps: First, problem localization driven by reference wafer data: By collecting the resistance and coordinate data of the entire chip on a reference wafer that is completely consistent with the specifications of the wafer to be processed, the spatial distribution characteristics of the resistance values ​​are accurately obtained, the difference in resistance values ​​between the central region and the edge region is clarified, and edge problem chips with resistance value deviation rates exceeding a preset threshold are screened out. This step provides accurate target objects for subsequent design optimization. Second, compensation value calculation guided by resistance formula: Based on the classic resistance formula R=ρL / S, the quantitative relationship between resistance value deviation and effective length of polysilicon layer pattern is derived. Since the process environment in the central region is relatively stable, the resistance value of the chip therein can be used as the target resistance value. The R-value deviation of edge-problem chips is essentially due to the ρ change caused by differences in the process environment. Therefore, the R-value deviation caused by the ρ change can be offset by adjusting the effective length L of the polysilicon layer pattern. That is, when ρ increases and causes the R-value to be too high, L is decreased to reduce the R-value; when ρ decreases and causes the R-value to be too low, L is increased to increase the R-value. Thirdly, precise optimization and application of mask patterns: Based on the calculated effective length compensation value, the length of the polysilicon layer pattern corresponding to the edge-problem chips in the original mask design data is differentially adjusted to generate an optimized mask. Applying the optimized mask to a single full-field exposure process can achieve precise control of the resistance value of edge-problem chips without additional process parameter adjustments or monitoring steps, ultimately improving the resistance uniformity of the entire wafer.

[0071] This invention breaks through the limitations of traditional design and process separation. By combining data-driven and theoretical derivation, it realizes the transformation from passive process compensation to active design optimization, which not only meets the high-efficiency and low-cost requirements of single-exposure process, but also solves the problem of resistance uniformity from the root.

[0072] The above describes a method for improving the uniformity of resistance values ​​within a wafer according to an embodiment of the present invention. The following describes an apparatus for improving the uniformity of resistance values ​​within a wafer according to an embodiment of the present invention. Please refer to [link to relevant documentation]. Figure 3 An apparatus for improving the uniformity of resistivity within a wafer, according to an embodiment of the present invention, includes: The acquisition module 10 is used to acquire the measured resistance value and chip coordinate data of the chip in the reference wafer fabricated based on a single full-field exposure process. The screening module 20 is used to define the central region of the reference wafer, take the average of the measured resistance values ​​of a number of chips located in the central region as the target resistance value, and screen out edge problem chips whose measured resistance values ​​deviate from the target resistance value from the reference wafer. Calculation module 30 is used to calculate the effective length compensation value of the polysilicon layer pattern in the edge problem chip based on the deviation between the measured resistance value and the target resistance value. The optimization module 40 is used to adjust the effective length of the polysilicon layer design pattern corresponding to the edge problem chip in the original design data of the target mask according to the effective length compensation value and the corresponding chip coordinate data, so as to generate optimized mask data. The processing module 50 is used to perform a single full-field exposure of the wafer to be processed using a mask manufactured according to the optimized mask data, so as to improve the uniformity of the resistance value within the wafer.

[0073] Based on the same ideas as the methods in the above embodiments, the device provided by the present invention can implement the methods in the above embodiments. For ease of explanation, the structural schematic diagram of the device embodiment only shows the parts related to the embodiments of the present invention. Those skilled in the art can understand that the illustrated structure does not constitute a limitation on the device, and may include more or fewer modules than illustrated, or combine certain modules, or have different module arrangements.

[0074] Figure 3 The device for improving the uniformity of resistance values ​​within a wafer in the embodiments of the present invention will be described in detail from the perspective of modular functional entities. The electronic device in the embodiments of the present invention will be described in detail from the perspective of hardware processing.

[0075] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. The electronic device 100 can vary significantly due to differences in configuration or performance. It may include one or more central processing units (CPUs) 111 (e.g., one or more processors) and a memory 121, and one or more storage media 130 (e.g., one or more mass storage devices) for storing application programs 133 or data 132. The memory 121 and storage media 131 can be temporary or persistent storage. The program stored in the storage media 130 may include one or more modules (not shown in the diagram), each module including a series of instruction operations on the electronic device 100. Furthermore, the processor 111 may be configured to communicate with the storage media 130 and execute the series of instruction operations in the storage media 130 on the electronic device 100.

[0076] Electronic device 100 may also include one or more power supplies 141, one or more wired or wireless network interfaces 151, one or more input / output interfaces 161, and / or one or more operating systems 131, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will understand that... Figure 4 The device structure shown does not constitute a limitation on the electronic device 100, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0077] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the steps of a method for improving the uniformity of resistance values ​​within a wafer.

[0078] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system, device, or unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0079] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for improving the uniformity of resistivity within a wafer, characterized in that, Including the following steps: Obtain the measured resistance value and chip coordinate data of the chip in the reference wafer fabricated using a single full-field exposure process; Define the central region of the reference wafer, take the average of the measured resistance values ​​of several chips located in the central region as the target resistance value, and screen out edge-problem chips whose measured resistance values ​​deviate from the target resistance value from the reference wafer; The effective length compensation value of the polysilicon layer pattern in the edge problem chip is calculated based on the deviation between the measured resistance value and the target resistance value. Based on the effective length compensation value and the corresponding chip coordinate data, the effective length of the polysilicon layer design pattern corresponding to the edge problem chip in the original design data of the target mask is adjusted to generate optimized mask data. A single full-field exposure is performed on the wafer to be processed using a mask manufactured according to the optimized mask data, in order to improve the uniformity of the resistivity within the wafer.

2. The method for improving the uniformity of resistance values ​​within a wafer according to claim 1, characterized in that, The process of defining the central region of the reference wafer, taking the average of the measured resistance values ​​of several chips located in the central region as the target resistance value, and selecting edge-problem chips from the reference wafer whose measured resistance values ​​deviate from the target resistance value includes the following steps: The circular region defined by taking the center of the reference wafer as the origin and using 1 / 4 to 3 / 4 of the radius of the reference wafer as the new radius is defined as the central region. The measured resistance values ​​of several chips are selected from the central region using a circular uniform sampling rule, and the average value is calculated. The average value is then used as the target resistance value. The measured resistance value of the chip located outside the center region of the reference wafer is compared with the target resistance value. Chips with a deviation rate exceeding a preset threshold are screened out and defined as edge problem chips.

3. The method for improving the uniformity of resistance values ​​within a wafer according to claim 2, characterized in that, The step of using a ring-shaped uniform sampling rule to select measured resistance values ​​of several chips from the central region and calculating the average value, and then using the average value as the target resistance value, includes the following steps: Using the center of the reference wafer as the origin, the central region is divided into at least three annular sub-regions according to their radius. Measured resistance values ​​of at least 3 chips are selected within each annular sub-region; The average value of the measured resistance values ​​of the chips selected in all annular sub-regions is calculated, and the average value is defined as the target resistance value.

4. The method for improving the uniformity of resistance values ​​within a wafer according to claim 2, characterized in that, The step of comparing the measured resistance value of a chip located outside the center region of the reference wafer with the target resistance value, filtering out chips with a deviation rate exceeding a preset threshold, and defining the filtered chips as edge problem chips includes the following steps: Based on the product parameter specifications and process capabilities of the reference wafer, a preset threshold for the deviation rate is set. Traverse the chips outside the center region of the reference wafer, and calculate the resistance deviation rate for each chip. Resistance deviation rate = |measured resistance value - target resistance value| / target resistance value; The deviation rate of the chip is compared with a preset threshold. If the deviation rate of the chip is greater than the preset threshold, the chip is defined as an edge problem chip.

5. The method for improving the uniformity of resistance values ​​within a wafer according to claim 1, characterized in that, The step of calculating the effective length compensation value of the polysilicon layer pattern in the edge-problem chip based on the deviation between the measured resistance value and the target resistance value includes the following steps: For each edge-prone chip, if the measured resistance value is greater than the target resistance value, then formula L is used. i =L d -S*|R i -R0| / ρ0 calculates the compensated length of the polysilicon layer pattern in the edge-problem chip, with the effective length compensation value ΔL=L. d -L i , where L i L represents the compensated length of the polysilicon layer pattern corresponding to the i-th edge-problem chip. d ρ0 represents the reference length of the polysilicon layer pattern corresponding to the chip in the central region, S represents the cross-sectional area of ​​the polysilicon layer pattern corresponding to the chip in the central region, and R represents the resistivity of the polysilicon layer corresponding to the chip in the central region. i Ri is the measured resistance value of the i-th edge problem chip, and R0 is the target resistance value; For each edge-prone chip, if the measured resistance value is less than the target resistance value, then formula L is used. i =L d +S*|R i -R0| / ρ0 calculates the compensated length of the polysilicon layer pattern in the edge-problem chip, with the effective length compensation value ΔL=L. d -L i .

6. The method for improving the uniformity of resistance values ​​within a wafer according to claim 1, characterized in that, The step of adjusting the effective length of the polysilicon layer design pattern corresponding to the edge-problem chip in the original design data of the target mask according to the effective length compensation value and the corresponding chip coordinate data to generate optimized mask data includes the following steps: Obtain the original design data of the target mask; Based on the chip coordinate data of the edge problem chip, locate the corresponding polysilicon layer design pattern in the original design data of the target mask. The effective length of the polysilicon layer design pattern is adjusted according to the effective length compensation value to generate optimized mask data.

7. The method for improving the uniformity of resistance values ​​within a wafer according to claim 1, characterized in that, The process of obtaining the measured resistance value and chip coordinate data of a chip in a reference wafer fabricated using a single full-field exposure process includes the following steps: Select a reference wafer that is identical in specifications and process parameters to the wafer to be processed and is produced by a single full-field exposure process. The reference wafer is fixed on the probe test stage, and the center and coordinate system of the reference wafer are calibrated by a vision positioning system. Following a preset path, probes are used to contact the test pads of each chip on the reference wafer point by point, recording the coordinate data of each chip on the reference wafer and the corresponding measured resistance value.

8. An apparatus for improving the uniformity of resistivity within a wafer, characterized in that, include: The acquisition module is used to acquire the measured resistance value and chip coordinate data of the chip in the reference wafer fabricated based on a single full-field exposure process; The filtering module is used to define the central region of the reference wafer, take the average of the measured resistance values ​​of several chips located in the central region as the target resistance value, and filter out edge-problem chips whose measured resistance values ​​deviate from the target resistance value from the reference wafer. The calculation module is used to calculate the effective length compensation value of the polysilicon layer pattern in the edge problem chip based on the deviation between the measured resistance value and the target resistance value. The optimization module is used to adjust the effective length of the polysilicon layer design pattern corresponding to the edge problem chip in the original design data of the target mask according to the effective length compensation value and the corresponding chip coordinate data, so as to generate optimized mask data. The processing module is used to perform a single full-field exposure of the wafer to be processed using a mask manufactured according to the optimized mask data, so as to improve the uniformity of the resistance value within the wafer.

9. An electronic device, characterized in that, It includes a memory and at least one processor, wherein the memory stores computer-readable instructions; The at least one processor invokes the computer-readable instructions in the memory to perform the steps of the method for improving the uniformity of resistance values ​​within a wafer as described in any one of claims 1-7.

10. A computer-readable storage medium storing computer-readable instructions thereon, characterized in that, When the computer-readable instructions are executed by a processor, they implement the steps of the method for improving the uniformity of resistance values ​​within a wafer as described in any one of claims 1-7.

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