A method for fabricating a semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; forming a transistor structure and a first dielectric layer on the transistor structure on the substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer; forming a second dielectric layer covering the first dielectric layer, the second dielectric layer including at least a first sublayer; forming a first pattern on the second dielectric layer, the orthographic projection of the area exposed by the first pattern on the substrate covering the orthographic projection of the gate layer and the source / drain regions on the substrate; performing an etching process using the first pattern as a mask to at least remove the second dielectric layer exposed by the first pattern to form a first trench and a second trench, the sidewalls of the first trench exposing the second dielectric layer, and the second trench exposing the first dielectric layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for preparing a semiconductor structure. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and high integration, resulting in increasingly smaller device dimensions. The fabrication process of semiconductor devices often includes the formation of conductive structures. For example, a through-hole structure to accommodate the conductive structure can be created through an etching process, followed by filling the through-hole with conductive material. However, with the continuous improvement in device miniaturization and integration, many problems remain to be addressed in the fabrication of conductive structures. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure, including:

[0004] A substrate is provided; a transistor structure and a first dielectric layer are formed on the substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer;

[0005] A second dielectric layer is formed covering the first dielectric layer, the second dielectric layer including at least a first sublayer;

[0006] A first pattern is formed on the second dielectric layer, wherein the orthographic projection of the area exposed by the first pattern on the substrate covers the orthographic projection of the gate layer and the source / drain regions on the substrate.

[0007] An etching process is performed using the first pattern as a mask to remove at least the second dielectric layer exposed by the first pattern to form a first trench and a second trench. The sidewalls of the first trench expose the second dielectric layer, and the second trench exposes the first dielectric layer.

[0008] In some embodiments, forming a second dielectric layer covering the first dielectric layer includes:

[0009] A first sublayer is formed, and the first sublayer covers the surface of the first dielectric layer;

[0010] A second sublayer is formed, which covers the surface of the first sublayer, and the first and second sublayers have different etching rates.

[0011] In some embodiments, forming a first pattern includes:

[0012] A mask material layer is formed on the second dielectric layer, and the mask material layer covers the surface of the second dielectric layer;

[0013] A patterning process is performed on the mask material layer to form a mask layer containing multiple first openings, wherein the orthographic projection of the area exposed by the first openings on the substrate covers the orthographic projection of the gate layer and the source / drain regions on the substrate.

[0014] A first linear material layer is formed, which covers the sidewalls and bottom of the first opening and the surface of the mask layer located between the first openings.

[0015] In some embodiments, an etching process is performed using a first pattern as a mask to at least remove a second dielectric layer exposed by the first pattern to form a first trench and a second trench, wherein the sidewalls of the first trench expose the second dielectric layer and the second trench exposes the first dielectric layer, including:

[0016] The second sublayer is etched using the first pattern and the first linear material layer as a mask to form a plurality of second openings in the second sublayer, the second openings exposing the surface of the first sublayer;

[0017] A second linear material is formed, which covers the sidewalls and bottom of the second opening and the surface of the second sub-layer located around the second opening;

[0018] The portion of the second linear material located on the surface of the second sublayer and at the bottom of the second opening is removed, and the second opening, the remaining second linear material, and the second dielectric layer constitute the second pattern.

[0019] An etching process is performed using the second pattern as a mask to remove the first sub-layer and the first dielectric layer exposed by the second pattern to form a first trench and a second trench. The sidewalls of the first trench expose the first dielectric layer, the sidewalls of the second trench expose the second dielectric layer and the first dielectric layer, and the bottom of the second trench exposes the surface of the gate layer.

[0020] In some embodiments, an etching process is performed using a first pattern as a mask to at least remove a second dielectric layer exposed by the first pattern to form a first trench and a second trench, wherein the sidewalls of the first trench expose the second dielectric layer and the second trench exposes the first dielectric layer, including:

[0021] The second sublayer is etched using the first pattern and the first linear material layer as a mask to form a plurality of second openings in the second sublayer, the second openings exposing the surface of the first sublayer;

[0022] A second linear material is formed, which covers the sidewalls and bottom of the second opening and the surface of the second sub-layer located around the second opening;

[0023] The portion of the second linear material located on the surface of the second sublayer and at the bottom of the second opening is removed, and the second opening, the remaining second linear material, and the second dielectric layer constitute the second pattern.

[0024] Using the second pattern as a mask, an etching process is performed to remove the first sublayer exposed by the second pattern to form a first trench and a second trench. The sidewalls of the first trench expose the second dielectric layer, and the bottom of the second trench exposes the surface of the first dielectric layer.

[0025] In some embodiments, after forming the first trench and the second trench, the fabrication method further includes:

[0026] A first contact structure is formed in a first trench using a first deposition process. The first contact structure is connected to the source / drain region, and the top surface of the first contact structure is lower than the top surface of the first trench.

[0027] An etching process is performed to remove the first dielectric layer exposed at the bottom of the second trench to form a fourth trench, which exposes the surface of the gate layer.

[0028] A third linear material is formed on the sidewalls of the second and fourth trenches and on the sidewalls of the portion of the first trench not filled by the first contact structure.

[0029] In some embodiments, after forming the first trench and the second trench, the fabrication method further includes:

[0030] The second trench and at least part of the first trench are filled using a second deposition process.

[0031] In some embodiments, after performing the second deposition process, the preparation method further includes:

[0032] At least a planarization process is performed on the second dielectric layer and a portion of the material formed by the second deposition process.

[0033] In some embodiments, a substrate is provided; a transistor structure and a first dielectric layer are formed on the substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer, including:

[0034] A transistor structure is formed on a substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer;

[0035] A third sublayer is formed on the transistor structure, which covers the transistor structure and the surface of the substrate surrounding the transistor structure.

[0036] A fourth sublayer is formed, which covers the surface of the third sublayer. The fourth sublayer and the first sublayer have different etching rates.

[0037] A fifth sublayer is formed, which covers the surface of the fourth sublayer. The fifth and fourth sublayers have different etching rates.

[0038] In some embodiments, after forming the first dielectric layer and before forming the second dielectric layer, the method further includes:

[0039] An etching process is performed to remove the portion of the first dielectric layer located above the source / drain regions to form a third trench, which exposes the surface of the source / drain regions.

[0040] The third trench is filled to form a second contact structure.

[0041] The method for fabricating a semiconductor structure provided in this disclosure includes: providing a substrate; forming a transistor structure and a first dielectric layer on the transistor structure on the substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer; forming a second dielectric layer covering the first dielectric layer, the second dielectric layer including at least a first sublayer; forming a first pattern on the second dielectric layer, the orthographic projection of the area exposed by the first pattern on the substrate covering the orthographic projection of the gate layer and the source / drain regions on the substrate; performing an etching process using the first pattern as a mask to at least remove the second dielectric layer exposed by the first pattern to form a first trench and a second trench, the sidewalls of the first trench exposing the second dielectric layer, and the second trench exposing the first dielectric layer.

[0042] In this embodiment, after forming the first dielectric layer on the source / drain regions, a second dielectric layer and a first pattern on the second dielectric layer are formed. The first pattern exposes the area directly above the gate layer and the source / drain regions, providing favorable conditions for simultaneously opening the area above the gate layer and the source / drain regions to obtain the trench structure during subsequent etching processes, thus helping to save on the number of photomasks used. Since the formed second dielectric layer can have a different composition than the first dielectric layer, subsequent etching processes can be stopped at the desired location in a timely manner. Compared to cases where both dielectric layers have the same composition, the former significantly increases the number and selectivity of desired locations. This allows for flexible selection of the target desired location for the etching step to stop before the subsequent step of filling the trench structure to obtain the contact structure, based on the performance requirements of the desired contact structure. Different fabrication methods can then be used to obtain the required contact structure, thereby improving the performance of the final semiconductor structure. Furthermore, the fabrication method provided in this embodiment does not have strict requirements on the photolithography resolution of the photolithography equipment; conventional photolithography equipment can be used, which helps reduce production costs. The process steps are relatively mature, effectively improving the reliability and stability of the fabrication process.

[0043] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0046] Figures 2 to 7 This is a schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure;

[0047] Figures 8 to 10 A process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0048] Figures 11 to 14 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0049] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0050] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0051] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] In semiconductor structures, transistors are a crucial component, typically consisting of a gate layer and source / drain regions located on either side of the gate layer. With the continuous miniaturization and increasing integration of semiconductor structures, the size of transistor structures is constantly shrinking, and the size of the connected structures is also decreasing accordingly. This adds many challenges to the fabrication process. To cope with these size variations, high-resolution lithography machines are often used to fabricate the required small-sized structures, resulting in higher costs.

[0056] Therefore, there are still many problems to be improved in the process of forming transistor structures and the structures connected to them.

[0057] Based on this, the technical solution of the present disclosure embodiment is proposed as follows:

[0058] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the preparation method includes the following steps:

[0059] Step S101: Provide a substrate; a transistor structure and a first dielectric layer are formed on the substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer;

[0060] Step S102: Form a second dielectric layer covering the first dielectric layer, wherein the second dielectric layer includes at least the first sublayer;

[0061] Step S103: Form a first pattern on the first dielectric layer, wherein the orthographic projection of the area exposed by the first pattern on the substrate covers the orthographic projection of the gate layer and the source / drain region on the substrate.

[0062] Step S104: Perform an etching process using the first pattern as a mask to remove at least the second dielectric layer exposed by the first pattern to form a first trench and a second trench. The sidewalls of the first trench expose the second dielectric layer, and the second trench exposes the first dielectric layer.

[0063] In this embodiment, after forming the first dielectric layer on the source / drain regions, a second dielectric layer and a first pattern on the second dielectric layer are formed. The first pattern exposes the area directly above the gate layer and the source / drain regions, providing favorable conditions for simultaneously opening the area above the gate layer and the source / drain regions to obtain the trench structure during subsequent etching processes, thus helping to save on the number of photomasks used. Since the formed second dielectric layer can have a different composition than the first dielectric layer, subsequent etching processes can be stopped at the desired location in a timely manner. Compared to cases where both dielectric layers have the same composition, the former significantly increases the number and selectivity of desired locations. This allows for flexible selection of the target desired location for the etching step to stop before the subsequent step of filling the trench structure to obtain the contact structure, based on the performance requirements of the desired contact structure. Different fabrication methods can then be used to obtain the required contact structure, thereby improving the performance of the final semiconductor structure. Furthermore, the fabrication method provided in this embodiment does not have strict requirements on the photolithography resolution of the photolithography equipment; conventional photolithography equipment can be used, which helps reduce production costs. The process steps are relatively mature, effectively improving the reliability and stability of the fabrication process.

[0064] It should be understood that, although Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0065] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0066] Figures 2 to 7 This is a schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure; Figures 8 to 10 A process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 11 to 14 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure.

[0067] The preparation method provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0068] First, execute step S101, as follows: Figure 2 As shown, a substrate 10 is provided; a transistor structure A and a first dielectric layer L1 located on the transistor structure A are formed on the substrate 10. The transistor structure A includes a gate layer 11 and source / drain regions 12 located on both sides of the gate layer 11.

[0069] Here, substrate 10 can be a semiconductor substrate. The materials of the semiconductor substrate specifically include elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In one specific embodiment, substrate 10 is a silicon substrate.

[0070] Continue to refer to Figure 2 In some embodiments, a substrate 10 is provided; a transistor structure A and a first dielectric layer L1 are formed on the substrate 10, the transistor structure A including a gate layer 11 and source / drain regions 12 located on both sides of the gate layer 11, including:

[0071] A transistor structure A is formed on the substrate 10. The transistor structure A includes a gate layer 11 and source / drain regions 12 located on both sides of the gate layer 11.

[0072] A third sublayer 111 is formed on transistor structure A, and the third sublayer 111 covers transistor structure A and the surface of substrate 10 located around transistor structure A;

[0073] A fourth sublayer 112 is formed, which covers the surface of the third sublayer 111.

[0074] A fifth sublayer 113 is formed, which covers the surface of the fourth sublayer 112; the fifth sublayer 113 and the subsequently formed second dielectric layer L2 (see subsequent appendices) Figure 3 The material layer located at the bottom of the middle layer (please refer to the following appendix) Figure 3 The first sublayer 121 in the middle has a different etching rate.

[0075] In some embodiments, the material of the gate layer 11 includes, but is not limited to, polysilicon, a barrier layer, and a conductive metal, and the source / drain region 12 may include, but is not limited to, a doped silicon-germanium layer or other conductive materials.

[0076] In some embodiments, an isolation structure (not shown) may also be provided between adjacent transistor structures A on the substrate 10, such as a shallow trench isolation structure (not shown).

[0077] It should be noted that the positional relationship and number of the gate layer 11 and the source / drain region 12 in the accompanying drawings of the embodiments of this disclosure are merely illustrative. Although the accompanying drawings show that only one source / drain region 12 structure is included between two adjacent gate layers 11, in reality, there can also be two source / drain region structures 12 at this position. No specific limitation is made here, and the choice can be made flexibly according to the actual situation.

[0078] In some embodiments, the first dielectric layer L1 comprises three sublayers: the material of the third sublayer 111 may include an oxide material, the material of the fourth sublayer 112 may include, but is not limited to, a nitride layer, and the material of the fifth sublayer 113 may include, but is not limited to, an oxide material.

[0079] Understandably, since the fifth sublayer 113 of the first dielectric layer L1 and the first sublayer 121 of the second dielectric layer L2 have different etching rates, the etching process can be carried out by controlling the etching selectivity ratio between the materials. This helps to identify the desired location where etching needs to be stopped in a timely manner during the etching process to form the first trench T1 and the second trench T2, thus providing a good prerequisite for obtaining the desired structure at the desired location.

[0080] In some specific embodiments, the material of the third sublayer 111 can be silicon oxide, the material of the fourth sublayer 112 can be silicon nitride, and the material of the fifth sublayer 113 can be silicon oxide.

[0081] Next, proceed with step S102, as follows: Figure 3 As shown, a second dielectric layer L2 is formed covering the first dielectric layer L1, and the second dielectric layer L2 includes at least the first sublayer 121.

[0082] In some embodiments, after forming the first dielectric layer L1 and before forming the second dielectric layer L2, the method further includes:

[0083] An etching process is performed to remove the portion of the first dielectric layer L1 located above the source / drain region 11 to form a third trench T3, which exposes the surface of the source / drain region 11.

[0084] The third trench T3 is filled to form the second contact structure 132.

[0085] In some embodiments, after the third trench T3 is formed and before the filling process is performed, the method further includes:

[0086] An insulating material C is formed on the sidewall of the third trench T3. The insulating material C can be made of silicon nitride. Using silicon nitride can improve the reliability of the final semiconductor, such as improving the breakdown performance.

[0087] In some embodiments, the material of the second contact structure 132 may include, but is not limited to, cobalt (Co).

[0088] In some embodiments, forming a second dielectric layer L2 covering the first dielectric layer L1 includes:

[0089] A first sublayer 121 is formed, which covers the surface of the first dielectric layer L1;

[0090] A second sublayer 122 is formed, which covers the surface of the first sublayer 121, and the first sublayer 121 and the second sublayer 122 have different etching rates.

[0091] Understandably, the second dielectric layer L2 formed here also covers the surface of the second contact structure 132 located in the first dielectric layer L1.

[0092] Here, the material of the first sublayer 121 in the second dielectric layer L2 may include, but is not limited to, nitrides, such as silicon nitride. The material of the second sublayer 122 may include, but is not limited to, oxides, such as silicon oxide.

[0093] Understandably, since the first sublayer 121 and the second sublayer 122 have different etching rates, and the first sublayer 121 and the fifth sublayer 113 of the first dielectric layer L1 also have different etching rates, this embodiment of the present disclosure allows for flexible selection of the technical route through different selective etching processes during the subsequent etching step S105. This allows for flexible selection of the target desired location where the trench to be formed needs to be stopped, thereby significantly increasing the number and selectivity of desired locations. This enables the subsequent step of filling the trench structure to obtain the contact structure to be performed before flexibly selecting the target desired location where the etching step should stop, based on the performance requirements of the desired contact structure. Consequently, different fabrication methods can be used to obtain the required contact structure, thereby improving the performance of the final semiconductor structure.

[0094] Then, proceed to step S103, as follows: Figure 4 and Figure 5 As shown, a first pattern P1 is formed on the second dielectric layer L2. The orthogonal projection of the area exposed by the first pattern P1 on the substrate 10 covers the orthogonal projection of the gate layer 11 and the source / drain region 12 on the substrate 10.

[0095] In some embodiments, forming the first pattern P1 includes:

[0096] A mask material layer 15a is formed on the second dielectric layer L2, and the mask material layer 15a covers the surface of the second dielectric layer L2;

[0097] A patterning process is performed on the mask material layer 15a to form a mask layer 15 containing a plurality of first openings H1. The orthogonal projection of the area exposed by the first openings H1 on the substrate 10 covers the orthogonal projection of the gate layer 11 and the source / drain region 12 on the substrate 10.

[0098] A first linear material layer 171 is formed, which covers the sidewalls and bottom of the first opening H1 and the surface of the mask layer 15 located between the first openings H1.

[0099] Here, the first opening H1 and the mask layer 15 constitute the first pattern P1.

[0100] In some embodiments, a patterning process is performed on the mask material layer 15a, including:

[0101] A photoresist pattern 16 is formed on the mask material layer 15a;

[0102] The mask material layer 15a is etched using the photoresist pattern 16 as a mask to obtain the mask layer 15.

[0103] In some embodiments, the mask material layer 15a may include a first mask material layer 151a and a second mask material layer 152a from bottom to top. Correspondingly, the mask layer 15 may also include a first mask layer 151 and a second mask layer 152 from bottom to top.

[0104] In some embodiments, the material of the second mask material layer 152a includes, but is not limited to, a Si-based anti-reflective layer (or Si-ARC), and the material of the first mask material layer 151a includes, but is not limited to, a spin-coated carbon (SOC) coating.

[0105] In some embodiments, the material of the first linear material layer 171 includes, but is not limited to, linear nitrides, such as linear silicon nitride, linear oxides, such as silicon oxide and low-temperature silicon oxide (LTO).

[0106] Understandably, due to the continuous miniaturization and integration of devices, the dimensions of various structures within semiconductor structures are becoming increasingly smaller, posing a severe challenge to the photolithography process in fabrication. One possible approach is to use a high-resolution photolithography machine, such as an extreme ultraviolet (EUV) lithography machine, to perform a series of operations including exposure and development to obtain the target structure with the required smaller critical dimensions. However, this method increases production costs and makes it difficult to control overlay accuracy. Furthermore, even when using a high-resolution photolithography machine, to maintain good production stability, operators typically continue with conventional process fabrication methods and steps. For example, in the first photolithography process, a pre-prepared photomask is aligned with the structure to be etched, and then a series of operations are performed to etch the trench structure corresponding to the source / drain regions. After this, another photolithography process is performed, using another pre-prepared photomask aligned with the structure to be etched, and then a series of operations are performed to etch the trench structure corresponding to the gate layer.

[0107] In other words, conventional techniques require two photolithography processes, a series of subsequent processes, and two photomasks to obtain the corresponding trench structures on the gate layer and source / drain regions, resulting in high production costs. Furthermore, the photomasks involve significant limitations due to the need to separate the portions for etching the source / drain regions from those for etching the gate layer, increasing operational complexity.

[0108] Furthermore, in conventional techniques, during the process step of forming the second contact structure corresponding to this application before forming the trench structure, in order to accurately identify whether the region to be etched is the source / drain region or the gate layer region, a first material with a first etching rate needs to be formed above the location of the corresponding source / drain region on the transistor, and a second material with a second etching rate needs to be formed above the location of the corresponding gate layer. The first material and the second material have a large etching selectivity ratio, that is, a self-alignment (SAC) operation needs to be performed, which increases the complexity of the process.

[0109] In this embodiment, the first pattern P1 directly exposes the regions corresponding to the gate layer 11 and the source / drain region 12 at once. This allows for the simultaneous opening of the regions corresponding to both structures (gate layer 11 and source / drain region 12) using a single photomask, saving on the number of photomasks and reducing the complexity of the photolithography process. Furthermore, since a single photomask is used in this step, it is not necessary to split the photomask for the corresponding source / drain region 12 and gate layer 11. This provides the photomask in this embodiment with greater design flexibility for splitting operations due to other reasons, effectively reducing costs. Additionally, the exposed region of the first pattern P1 does not need to strictly correspond to the dimensions of the regions containing the source / drain region 11 and gate layer 12. It only requires that the orthographic projection of the exposed region of the first pattern P1 on the substrate 10 covers the orthographic projections of the gate layer 11 and the source / drain region 12 on the substrate 10. This provides a larger process margin and allows for a larger photolithography process window during the corresponding photolithography process.

[0110] Furthermore, although in this embodiment, the area exposed by the first pattern P1 does not need to directly correspond to the areas where the source / drain region 11 and the gate layer 12 are located, but only need to cover the area between the orthographic projections (it can also be understood that the area exposed by the first pattern P1 can be larger than the areas where the source / drain region 11 and the gate layer 12 are located respectively), due to the subsequent process of the first linear material 171 and the second linear material layer 172 (please refer to the appendix)... Figure 7 ) and the third linear material layer 173 (please refer to the appendix) Figure 9 and attached Figure 13 The formation process of the key dimension (CD) allows for further control of the key dimension (CD) during these operations, continuously reducing it to the required size range.

[0111] Meanwhile, in this embodiment, since the first pattern P1 simultaneously exposes the upper regions corresponding to the two structures (gate layer 11 and source / drain region 12), the subsequent formation of the first groove T1 (see details) is facilitated. Figure 8 and Figure 11 ) and the second groove T2 (please refer to the details) Figure 8 and Figure 11 The operations can be conditionally obtained together, thus eliminating the need for the step of forming a different material layer around the gate layer 11 for self-alignment purposes, which is different from the material around the second contact structure 132, when forming the first dielectric layer L1 around the second contact structure 132. This helps to save process flow, simplify production steps, and improve production efficiency.

[0112] Finally, proceed with step S104, as follows: Figures 6 to 10 and Figures 11 to 14 As shown, an etching process is performed using the first pattern P1 as a mask to remove at least the second dielectric layer L1 exposed by the first pattern P1 to form a first trench T1 and a second trench T2. The sidewalls of the first trench T1 expose the second dielectric layer L2, and the second trench T1 exposes the first dielectric layer L1.

[0113] In some embodiments, such as Figures 6 to 8 As shown, an etching process is performed using a first pattern P1 as a mask to remove at least the second dielectric layer L2 exposed by the first pattern P1 to form a first trench T1 and a second trench T2. The sidewalls of the first trench T1 expose the second dielectric layer L2, and the second trench T1 exposes the first dielectric layer L1. This includes:

[0114] Using the first pattern P1 and the first linear material 171 as a mask, the second sublayer 122 is etched to form a plurality of second openings H2 in the second sublayer 122, the second openings H2 exposing the surface of the first sublayer 121 (see details). Figure 6 );

[0115] A second linear material 172 is formed, which covers the sidewalls and bottom of the second opening H2 and the surface of the second sublayer 122 located around the second opening H2 (see details). Figure 6 );

[0116] After removing the portion of the second linear material 172 located on the surface of the second sublayer 122 and at the bottom of the second opening H2, the second opening H2, the remaining second linear material 172, and the second dielectric layer L2 constitute the second pattern P2 (see details). Figure 7 );

[0117] Using the second pattern P2 as a mask, an etching process is performed to remove the first sublayer 121 and the first dielectric layer L1 exposed by the second pattern P2 to form a first trench T1 and a second trench T2. The sidewalls of the first trench T1 expose the second dielectric layer L2, the sidewalls of the second trench T2 expose the second dielectric layer L2 and the first dielectric layer L1, and the bottom of the second trench T2 exposes the surface of the gate layer 11 (see details). Figure 8 ).

[0118] Understandably, in this embodiment, the bottom of the first trench T1 will expose the surface of the second contact structure 132, thereby allowing the first contact structure 131 (see details) subsequently filled in the first trench T1 to be exposed. Figure 10 The connection with the source / drain region 12 can be ultimately achieved through the connection with the second contact structure 131.

[0119] In some embodiments, the material of the second linear material layer 172 includes, but is not limited to, a nitride layer, such as a silicon nitride layer. It is understood that the formation of the second linear material layer 172 can further make the dimensions of the formed first trench T1 and second trench T2 in the direction parallel to the plane of the substrate 10 smaller than the size of the first opening H1 in the first pattern P1. Additionally, it can improve the reliability of the ultimately obtained semiconductor, for example, by improving breakdown performance.

[0120] In some embodiments, such as Figure 9 As shown, after forming the first trench T1 and the second trench T2, the fabrication method further includes:

[0121] A third linear material layer 173 is formed on the sidewalls of the first trench T1 and the second trench T2.

[0122] In some embodiments, the material of the third linear material layer 173 may be the same as the material of the second linear material layer 172, which will not be described in detail here.

[0123] Understandably, the formation of the third linear material layer 173 further reduces the size of the structure obtained based on the first pattern P1 in the direction parallel to the plane of the substrate 10, making the size of the contact structures subsequently formed in the first trench T1 and the second trench T2 in the direction parallel to the plane of the substrate 10 smaller than the size of the first opening H1 in the first pattern P1. Additionally, it can improve the reliability of the finally obtained semiconductor, for example, by improving its breakdown performance.

[0124] In this embodiment, using the first pattern P1 as a mask and supplemented by the formation and interaction of the first linear material 171 and the second linear material 172, the second trench T2 exposing the gate layer 11 and the first trench T1 exposing the second contact structure 132 are obtained simultaneously. This achieves the realization that a trench structure with a further reduced size (compared to the size of the first opening H1 in the first pattern P1 before the formation of linear material) can be obtained with one photomask, one photolithography process, and one etching operation. This ensures that the size of the contact structure located in the trench structure in the final semiconductor structure meets the design requirements and also helps to control the overlay accuracy (OVL).

[0125] In addition, in this embodiment, since the first groove T1 and the second groove T2 are obtained simultaneously, the subsequent process steps of filling the two groove structures can be executed simultaneously, which helps to simplify the production process, reduce the difficulty and cost of the process, and improve production efficiency.

[0126] In other embodiments, such as Figure 6 , Figure 7 and Figure 11As shown, an etching process is performed using a first pattern P1 as a mask to remove at least the second dielectric layer L2 exposed by the first pattern P1 to form a first trench T1 and a second trench T2. The sidewalls of the first trench T1 expose the second dielectric layer L2, and the second trench T1 exposes the first dielectric layer L1. This includes:

[0127] Using the first pattern P1 and the first linear material layer 171 as a mask, the second sublayer 122 is etched to form a plurality of second openings H2 in the second sublayer 122, the second openings H2 exposing the surface of the first sublayer 121 (see details). Figure 6 );

[0128] A second linear material 172 is formed, which covers the sidewalls and bottom of the second opening H2 and the surface of the second sublayer 122 located around the second opening H2 (see details). Figure 6 );

[0129] After removing the portion of the second linear material 172 located on the surface of the second sublayer 122 and at the bottom of the second opening H2, the second opening H2, the remaining second linear material 172, and the second dielectric layer L2 constitute the second pattern P2 (see details). Figure 7 );

[0130] Using the second pattern P2 as a mask, an etching process is performed to remove the first sublayer 121 exposed by the second pattern P2 to form the first trench T1 and the second trench T2. The sidewalls of the first trench T2 expose the second dielectric layer L2, and the bottom of the second trench T2 exposes the surface of the first dielectric layer L1 (see details). Figure 11 ).

[0131] Understandably, in this embodiment, the bottom of the first trench T1 will expose the surface of the second contact structure 132, thereby allowing the first contact structure 131 (see details) subsequently filled in the first trench T1 to be exposed. Figure 10 The connection with the source / drain region 12 can be ultimately achieved through the connection with the second contact structure 132.

[0132] In this embodiment, the difference in etching rate between the first sublayer 121 and the fifth sublayer 113 of the second dielectric layer L1 is fully utilized during the etching process, so that the etching process to form the second trench T2 can be accurately stopped on the surface of the first dielectric layer L1.

[0133] In this embodiment, the material of the second linear material layer 172 can be the same as in the previous embodiment. It is understood that the formation of the second linear material layer 172 can further make the dimensions of the formed first trench T1 and second trench T2 in the direction parallel to the plane of the substrate 10 smaller than the opening size in the first pattern P1. Furthermore, it can improve the reliability of the finally obtained semiconductor, such as improving breakdown performance.

[0134] In this embodiment, using the first pattern P1 as a mask and supplemented by the formation and interaction of the first linear material 171 and the second linear material 172, a first trench T1 exposing the surface of the second contact structure 132 and a second trench T2 exposing the surface of the first dielectric layer L1 are obtained, respectively. This achieves a two-trench structure with a further reduced size (compared to the size of the first opening H1 in the first pattern P1 before the linear material is formed) by using a single photomask, a single photolithography process, and an etching operation. This is beneficial for ensuring that the size of the contact structure located in the trench structure in the final semiconductor structure meets the design requirements and also helps to control the overlay precision (OVL). In addition, in this embodiment, the method of temporarily not opening the area above the gate layer 11 helps to perform a different process on the second contact structure 132 connecting the source / drain region 12 than the process used to form the corresponding contact structure above the gate layer 11. This allows the contact structure at this location to have special properties different from the contact structure subsequently formed on the gate layer 11, meeting the performance requirements of the structure required at this location. For example, a first contact structure 131 with low contact resistance can be obtained (see Appendix for details). Figure 13 This increases the product's competitive advantage.

[0135] In some embodiments, such as Figure 7 As shown, in the process of removing the portion of the second linear material 172 located on the surface of the second sublayer 122 and at the bottom of the second opening H2, in order to remove the material cleanly, a certain thickness of the portion of the first sublayer 121 below the second opening H2 may also be removed.

[0136] In some embodiments, such as Figure 12 and Figure 13 As shown, in the formation Figure 11 Following the first trench T1 and the second trench T2 shown, the fabrication method further includes:

[0137] A first contact structure 131 is formed in the first trench T1 using a first deposition process. The first contact structure 131 is connected to the source / drain region 11, and the top surface of the first contact structure 131 is lower than the top surface of the first trench T1 (see details). Figure 12 );

[0138] An etching process is performed to remove the first dielectric layer L1 exposed at the bottom of the second trench T2 to form the fourth trench T4, which exposes the surface of the gate layer 11 (see details). Figure 13 );

[0139] A third linear material 173 is formed on the sidewalls of the second trench T2 and the fourth trench T4, and on the sidewalls of the portion of the first trench T1 not filled by the first contact structure 131 (see details). Figure 13 ).

[0140] Here, the connection between the first contact structure 131 and the source / drain region 11 can be understood as the first contact structure 131 achieving the connection with the source / drain region 11 through the connection between the first contact structure 131 and the second contact structure 132 located above the source / drain region 11.

[0141] In some embodiments, the first deposition process can be a selective deposition process. Since the structure of the first contact structure 131 formed by the selective deposition process is relatively dense, a contact structure with low resistance can be obtained.

[0142] In some embodiments, during deposition, parameters such as deposition time and deposition rate can be controlled to achieve the effect that the top surface of the first contact structure 131 is lower than the top surface of the first trench T1.

[0143] In some embodiments, the material of the first contact structure 131 may include, but is not limited to, conductive metal materials, such as tungsten (W).

[0144] In this embodiment, the material composition and effect of the third linear material 173 can be compared with... Figure 9 The material composition and effects of the third linear material 173 in the illustrated embodiment are the same, and will not be described in detail here.

[0145] In some embodiments, in forming such Figure 9 After the first trench T1, the second trench T2, and the third linear material layer 173, or forming as... Figure 13 Following the third linear material 173 shown, the preparation method further includes:

[0146] The first trench T1 and the second trench T2 are filled using a second deposition process to obtain the first contact structure 131 and the gate contact structure 18 (see details). Figure 10 ).

[0147] or,

[0148] The second deposition process is used to fill the unfilled portions of the second trench T2, the fourth trench T4, and the first trench T1 that were not filled by the first contact structure 131, so as to obtain the gate contact structure 18 and the deposited material above the first contact structure 131 in the second trench T2 (see details). Figure 14 ).

[0149] In some embodiments, the second deposition process can be chemical vapor deposition (CVD), which is a method of generating a thin film by chemically reacting one or more gaseous compounds or elements containing thin film elements on the substrate surface. It is a low-cost material formation method that helps reduce production costs.

[0150] In some embodiments, when a second deposition process is used to perform the filling process, the obtained result is as follows: Figure 10 The materials of the first contact structure 131 and the gate contact structure 18 shown can include, but are not limited to, conductive metal materials, such as tungsten (W). Similarly, when the filling process is performed using the second deposition process, the obtained... Figure 14 The materials shown on the first contact structure 131 and the gate contact structure 18 may include, but are not limited to, conductive metal materials, such as tungsten (W).

[0151] In some embodiments, during the deposition of some contact structures, a barrier layer 14 may be deposited first to reduce the diffusion of the material contained in the contact structure into the surrounding material.

[0152] In some specific embodiments, the material of the barrier layer 14 includes, but is not limited to, titanium nitride.

[0153] Understandable, Figures 7 to 10 In the illustrated embodiment, after performing a photolithography step, based on the first pattern P1 and two linear material deposition operations, an etching process can simultaneously obtain the first trench T1 and the second trench T2 corresponding to the source / drain region 11 and the gate layer 12. Simultaneously, after obtaining the trenches, a second linear material deposition process is performed to obtain a fillable structure with small critical dimensions and good overlay precision control. Then, a single material deposition process simultaneously obtains the corresponding contact structure above the areas corresponding to the source / drain region 11 and the gate layer 12. This embodiment features simple operation, a small number of photomasks (and can increase the design space for photomask splitting), low requirements for photolithography equipment (no high photolithography resolution is required; conventional etching equipment is sufficient), and a relatively simple yet mature process, thereby enabling low-cost and stable production operations.

[0154] In addition to the above-mentioned solutions, while maintaining the advantages of low requirements for lithography equipment (no need for high lithography resolution), saving on photomasks, and good control over critical dimensions and overlay accuracy, the embodiments of this disclosure also provide, for example... Figures 10 to 14The illustrated embodiments of methods for preparing contact structures with better performance provide operators with more options for preparation methods when they need to impose higher performance requirements on the obtained structure (e.g., reduce resistance).

[0155] In some embodiments, such as Figure 10 and Figure 14 As shown, after performing the second deposition process, the preparation method further includes:

[0156] At least the second dielectric layer L2 and a portion of the material formed by the second deposition process are planarized.

[0157] exist Figure 14 In the illustrated embodiment, during the planarization process, in the height direction perpendicular to the plane of the substrate 10, the following can be... Figure 13 As shown, the material layer above the first contact structure 131 is removed to obtain a flush upper surface.

[0158] It should be noted that the method for fabricating the semiconductor structure provided in this disclosure can be applied to any semiconductor device including such a structure, and is not limited thereto. The technical features described in the embodiments of this disclosure can be arbitrarily combined without conflict.

[0159] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A transistor structure and a first dielectric layer are formed on the substrate. The transistor structure includes a gate layer and source / drain regions located on both sides of the gate layer. A second dielectric layer is formed covering the first dielectric layer, the second dielectric layer including at least a first sublayer; A first pattern is formed on the second dielectric layer, wherein the orthographic projection of the area exposed by the first pattern on the substrate covers the orthographic projection of the gate layer and the source / drain regions on the substrate. An etching process is performed using the first pattern as a mask to remove at least the second dielectric layer exposed by the first pattern to form a first trench and a second trench. The sidewalls of the first trench expose the second dielectric layer, and the second trench exposes the first dielectric layer.

2. The preparation method according to claim 1, characterized in that, The second dielectric layer forming the first dielectric layer includes: A first sublayer is formed, which covers the surface of the first dielectric layer; A second sublayer is formed, which covers the surface of the first sublayer, and the first and second sublayers have different etching rates.

3. The preparation method according to claim 2, characterized in that, Forming the first pattern includes: A mask material layer is formed on the second dielectric layer, the mask material layer covering the surface of the second dielectric layer; A patterning process is performed on the mask material layer to form a mask layer containing a plurality of first openings, wherein the orthographic projection of the area exposed by the first openings on the substrate covers the orthographic projection of the gate layer and the source / drain regions on the substrate. A first linear material layer is formed, which covers the sidewalls and bottom of the first opening and the surface of the mask layer located between the first openings.

4. The preparation method according to claim 3, characterized in that, The etching process performed using the first pattern as a mask removes at least the second dielectric layer exposed by the first pattern to form a first trench and a second trench, wherein the sidewalls of the first trench expose the second dielectric layer and the second trench exposes the first dielectric layer, including: The second sublayer is etched using the first pattern and the first linear material layer as a mask to form a plurality of second openings in the second sublayer, the second openings exposing the surface of the first sublayer; A second linear material is formed, which covers the sidewalls and bottom of the second opening and the surface of the second sub-layer located around the second opening; The portion of the second linear material located on the surface of the second sublayer and at the bottom of the second opening is removed, and the second opening, the remaining second linear material, and the second dielectric layer constitute the second pattern; An etching process is performed using the second pattern as a mask to remove the first sub-layer and the first dielectric layer exposed by the second pattern to form the first trench and the second trench. The sidewalls of the first trench expose the first dielectric layer, the sidewalls of the second trench expose the second dielectric layer and the first dielectric layer, and the bottom of the second trench exposes the surface of the gate layer.

5. The preparation method according to claim 3, characterized in that, The etching process performed using the first pattern as a mask removes at least the second dielectric layer exposed by the first pattern to form a first trench and a second trench, wherein the sidewalls of the first trench expose the second dielectric layer and the second trench exposes the first dielectric layer, including: The second sublayer is etched using the first pattern and the first linear material layer as a mask to form a plurality of second openings in the second sublayer, the second openings exposing the surface of the first sublayer; A second linear material is formed, which covers the sidewalls and bottom of the second opening and the surface of the second sub-layer located around the second opening; The portion of the second linear material located on the surface of the second sublayer and at the bottom of the second opening is removed, and the second opening, the remaining second linear material, and the second dielectric layer constitute the second pattern; An etching process is performed using the second pattern as a mask to remove the first sublayer exposed by the second pattern to form the first trench and the second trench. The sidewalls of the first trench expose the second dielectric layer, and the bottom of the second trench exposes the surface of the first dielectric layer.

6. The preparation method according to claim 5, characterized in that, After forming the first trench and the second trench, the preparation method further includes: A first contact structure is formed in the first trench using a first deposition process. The first contact structure is connected to the source / drain region, and the top surface of the first contact structure is lower than the top surface of the first trench. An etching process is performed to remove the first dielectric layer exposed at the bottom of the second trench to form a fourth trench, the fourth trench exposing the surface of the gate layer; A third linear material is formed on the sidewalls of the second and fourth trenches and on the sidewalls of the portion of the first trench not filled by the first contact structure.

7. The preparation method according to claim 4 or 6, characterized in that, After forming the first trench and the second trench, the preparation method further includes: The second trench and at least a portion of the first trench are filled using a second deposition process.

8. The preparation method according to claim 7, characterized in that, After performing the second deposition process, the preparation method further includes: At least a planarization process is performed on the second dielectric layer and a portion of the material formed by the second deposition process.

9. The preparation method according to claim 1, characterized in that, The substrate is provided; a transistor structure and a first dielectric layer are formed on the substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer, including: A transistor structure is formed on the substrate, the transistor structure including a gate layer and source / drain regions located on both sides of the gate layer; A third sublayer is formed on the transistor structure, the third sublayer covering the transistor structure and the surface of the substrate surrounding the transistor structure; A fourth sublayer is formed, which covers the surface of the third sublayer, and the fourth sublayer and the first sublayer have different etching rates; A fifth sublayer is formed, which covers the surface of the fourth sublayer, and the fifth sublayer and the fourth sublayer have different etching rates.

10. The preparation method according to claim 1 or 9, characterized in that, After forming the first dielectric layer and before forming the second dielectric layer, the method further includes: An etching process is performed to remove the portion of the first dielectric layer located above the source / drain region to form a third trench that exposes the surface of the source / drain region. The third trench is filled to form a second contact structure.

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