Method of manufacturing a semiconductor structure

Abstract

This invention provides a method for manufacturing a semiconductor structure, comprising the following steps: forming a gate structure on a silicon substrate; forming doped regions in the silicon substrate on both sides of the gate structure; forming a dielectric layer on the silicon substrate to cover the gate structure and the doped regions; forming an opening in the dielectric layer to expose the doped regions, wherein the lower region of the opening is located within the doped regions; forming an undoped silicon layer in the lower region of the opening, wherein the silicon grain size of the undoped silicon layer is smaller than the silicon grain size of the silicon substrate; forming a metal layer on the undoped silicon layer; and performing a heat treatment to transform the metal layer and the undoped silicon layer into a metal silicide layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure in which metal silicide layers are formed on both sides of a gate structure. Background Technology

[0002] In semiconductor manufacturing, after forming a transistor, a dielectric layer covering the transistor is formed on a silicon substrate, and an etching process is performed to form contact holes in the dielectric layer that expose the source and drain regions of the transistor. Then, a conductive layer is filled into the contact holes to form contacts. Furthermore, to reduce the resistance at the source and drain regions, a metal silicide layer is formed at the exposed source and drain regions of the contact holes before filling in the conductive layer.

[0003] To ensure that the contact openings reliably expose the source and drain regions, the source and drain regions are typically over-etched during the etching process. As a result, when the metal silicide layer is formed, the metal silicide may diffuse into the silicon substrate surrounding the source and drain regions, affecting the electrical properties of the device. Summary of the Invention

[0004] The present invention relates to a method for manufacturing a semiconductor structure that can prevent the diffusion of metal silicide into the silicon substrate surrounding the source and drain regions during the formation of the metal silicide layer.

[0005] According to an embodiment of the present invention, a method for manufacturing a semiconductor structure includes the following steps: forming a gate structure on a silicon substrate; forming doped regions in the silicon substrate on both sides of the gate structure; forming a dielectric layer on the silicon substrate to cover the gate structure and the doped regions; forming an opening in the dielectric layer to expose the doped regions, wherein the lower region of the opening is located within the doped regions; forming an undoped silicon layer in the lower region of the opening, wherein the size of the silicon grains in the undoped silicon layer is smaller than the size of the silicon grains in the silicon substrate; forming a metal layer on the undoped silicon layer; and performing a heat treatment to transform the metal layer and the undoped silicon layer into a metal silicide layer.

[0006] Based on the above, in the semiconductor structure manufacturing method of the present invention, before performing the metal silicide process, an undoped silicon material layer with a silicon grain size smaller than the silicon grain size of the silicon substrate is formed on the doped region. Therefore, during the metal silicide process, the diffusion of metal silicide into the silicon substrate surrounding the doped region can be avoided. Attached Figure Description

[0007] Figures 1A to 1H This is a schematic cross-sectional view of the process for manufacturing a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0008] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0009] Figures 1A to 1H This is a schematic cross-sectional view of the process for manufacturing a semiconductor structure according to an embodiment of the present invention. The manufacturing method of this embodiment avoids the diffusion of metal silicide into the silicon substrate surrounding the source and drain regions during the formation of the metal silicide layer, thereby preventing leakage current problems. The manufacturing method of this embodiment will be described in detail below.

[0010] Reference Figure 1A A silicon substrate 100 is provided. The material of the silicon substrate 100 is, for example, single-crystal silicon. The silicon substrate 100 is, for example, a silicon wafer. Next, a gate structure GS is formed on the silicon substrate 100. The gate structure GS includes a gate dielectric layer 102, a gate 104, and a capping layer 106 sequentially formed on the silicon substrate 100, and spacers 108 formed on the sidewalls of the gate 104, but the invention is not limited thereto. The material of the gate dielectric layer 102 is, for example, silicon oxide. The material of the gate is, for example, polycrystalline silicon. The materials of the capping layer 106 and the spacers 108 are, for example, silicon nitride. The method of forming the gate structure GS is well known to those skilled in the art and will not be described separately here.

[0011] After forming the gate structure GS, doped regions 110 are formed in the silicon substrates 100 on both sides of the gate structure GS. The doped regions 110 can be formed, for example, by using the gate structure GS as a mask for an ion implantation process. The gate structure GS and the doped regions 110 can constitute a transistor, wherein the doped regions 110 can serve as the source and drain regions of the transistor.

[0012] Referring to 1B, a dielectric layer 112 is formed on a silicon substrate 100 to cover the gate structure GS and the doped region 110. The material of the dielectric layer 112 is, for example, silicon oxide. The dielectric layer 112 can serve as an inter-layer dielectric (ILD) layer. Next, an etching process is performed to form an opening H in the dielectric layer 112. The opening H exposes the doped region 110. The opening H is used to form contacts that connect to the source and drain regions of the transistor. Therefore, the opening H can be referred to as a contact opening.

[0013] In detail, the etching process can be performed using a patterned photoresist layer (not shown) and spacer 108 as an etching mask. Furthermore, to ensure that the opening H reliably exposes the doped region 110, the doped region 110 is over-etched to prevent dielectric layer 112 from remaining on the doped region 110. As a result, the lower region R of the opening H will be located within the doped region 110. That is, the bottom surface of the contact opening (opening H) is lower than the top surface of the silicon substrate 100.

[0014] Reference Figure 1C An undoped silicon material layer 114 is formed on the dielectric layer 112, and the undoped silicon material layer 114 fills the opening H. The size of the silicon grains in the undoped silicon material layer 114 must be smaller than the size of the silicon grains in the silicon substrate 100. Therefore, the doped silicon material layer 114 is, for example, amorphous silicon or polycrystalline silicon. The undoped silicon material layer 114 is formed, for example, by performing a physical vapor deposition (PVD) process.

[0015] In this step, the undoped silicon material layer 114 fills the lower region R of the opening H, and the top surface of the undoped silicon material layer 114 in the opening H is higher than the top surface of the silicon substrate 100. The top surface of the undoped silicon material layer 114 in the opening H is not higher than the top surface of the gate 104.

[0016] Reference Figure 1D An anisotropic etching process is performed to remove the undoped silicon material layer 114 on the top surface of the dielectric layer 112. During the removal of the undoped silicon material layer 114 on the top surface of the dielectric layer 112, the undoped silicon material layer 114 located in the opening H is also partially removed simultaneously, but the undoped silicon material layer 114 remains in the lower region R of the opening H. Furthermore, the undoped silicon material layer 114 remains on the sidewall of the opening H, and the thickness of the undoped silicon material layer 114 remaining on the sidewall of the opening H is less than the thickness of the undoped silicon material layer 114 remaining in the lower part of the opening H.

[0017] After removing the undoped silicon material layer 114 from the top surface of the dielectric layer 112, the top surface of the undoped silicon material layer 114 located below the opening H is still higher than the top surface of the silicon substrate 100, but the present invention is not limited thereto. After removing the undoped silicon material layer 114 from the top surface of the dielectric layer 112, the top surface of the undoped silicon material layer 114 located below the opening H may be coplanar with the top surface of the silicon substrate 100, or lower than the top surface of the silicon substrate 100.

[0018] Reference Figure 1EThe undoped silicon material layer 114 on the sidewall of the opening H is removed to form an undoped silicon layer 114a on the doped region 110. The method for removing the undoped silicon material layer 114 on the sidewall of the opening H is, for example, a wet etching process. In the wet etching process, the etchant used is, for example, diluted hydrofluoric acid (DHF).

[0019] In this step, during the removal of the undoped silicon material layer 114 on the sidewall of the aperture H, the undoped silicon material layer 114 located at the bottom of the aperture H is also partially removed simultaneously, but the undoped silicon material layer 114 is still retained in the lower region R of the aperture H. Since the thickness of the undoped silicon material layer 114 on the sidewall of the aperture H is less than the thickness of the undoped silicon material layer 114 at the bottom of the aperture H, the undoped silicon material layer 114 (undoped silicon layer 114a) can be retained in the lower region R of the aperture H after the removal of the undoped silicon material layer 114 on the sidewall of the aperture H.

[0020] The top surface of the undoped silicon layer 114a retained at the bottom of the opening H is higher than the top surface of the silicon substrate 100, but the present invention is not limited thereto. The top surface of the undoped silicon layer 114a retained at the bottom of the opening H may be coplanar with the top surface of the silicon substrate 100, or lower than the top surface of the silicon substrate 100.

[0021] Reference Figure 1F A metal layer 116 is conformally formed on a silicon substrate 100. The metal layer 116 covers the top surface of the dielectric layer 112, the sidewalls of the opening H, and the top surface of the undoped silicon layer 114a. The metal layer 116 is used to react with the undoped silicon layer 114a in a subsequent process to form a metal silicide layer. The material of the metal layer 116 is, for example, cobalt (Co), but the invention is not limited thereto.

[0022] Reference Figure 1G Heat treatment is performed to allow the metal material layer 116 on the undoped silicon layer 114a to react with the undoped silicon layer 114a. During the reaction, metal diffuses from the metal material layer 116 into the undoped silicon layer 114a to react with silicon and form metal silicide. Therefore, after heat treatment, the metal material layer 116 and the undoped silicon layer 114a can be completely transformed into a metal silicide layer 118. The metal silicide layer 118 formed at the doped region 110 can be used to reduce the resistance at the source and drain regions of the transistor.

[0023] Since the top surface of the undoped silicon layer 114a is higher than the top surface of the silicon substrate 100, the top surface of the formed metal silicide layer 118 will also be higher than the top surface of the silicon substrate 100. When the top surface of the undoped silicon layer 114a is not higher than the top surface of the silicon substrate 100, the formed metal silicide layer 118 is only located in the lower region R of the opening H.

[0024] Furthermore, the size of the silicon grains in the undoped silicon layer 114a is smaller than that in the silicon substrate 100, so the metal material layer 116 reacts rapidly with the undoped silicon layer 114a during heat treatment. Moreover, even if the top surface of the undoped silicon layer 114a is lower than the top surface of the silicon substrate 100 before heat treatment, exposing the lower region R of the opening H to the silicon substrate 100, the metal material layer 118 will preferentially react with the undoped silicon layer 114a during heat treatment, rather than reacting with the silicon substrate 100. On the other hand, the heat treatment temperature can therefore be lower, reducing energy consumption. This avoids the problem of metal silicide diffusion into the silicon substrate 100.

[0025] Reference Figure 1H The unreacted metal material layer 116 on the top surface of the dielectric layer 112 and on the sidewalls of the opening H is removed. This forms the semiconductor structure 10 of this embodiment. The method for removing the unreacted metal material layer 116 is, for example, a wet etching process. In the wet etching process, the etchant used is, for example, sulfuric acid.

[0026] In the manufacturing method of semiconductor structure 10, since an undoped silicon layer 114a with a silicon grain size smaller than that of silicon substrate 100 is formed on doped region 110, during the metal silicide process to form metal silicide layer 118, metal silicide diffusion into silicon substrate 100 around doped region 110 can be avoided, thereby preventing leakage current from generated in the formed component during operation.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A gate structure is formed on a silicon substrate; Doped regions are formed in the silicon substrate on both sides of the gate structure; A dielectric layer is formed on the silicon substrate to cover the gate structure and the doped region; An opening is formed in the dielectric layer to expose the doped region, wherein the lower region of the opening is located in the doped region; An undoped silicon layer is formed in the lower region of the opening, wherein the size of the silicon grains in the undoped silicon layer is smaller than the size of the silicon grains in the silicon substrate; A metal layer is formed on the undoped silicon layer; and Heat treatment is performed to transform the metal layer and the undoped silicon layer into a metal silicide layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The undoped silicon layer is made of amorphous silicon or polycrystalline silicon, and the silicon substrate is made of monocrystalline silicon.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The top surface of the undoped silicon layer is not lower than the top surface of the silicon substrate.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method for forming the undoped silicon layer includes: An undoped silicon material layer is formed on the dielectric layer, wherein the undoped silicon material layer at least fills the lower region of the opening; An anisotropic etching process is performed to remove the undoped silicon material layer on the top surface of the dielectric layer; and Remove the undoped silicon material layer from the sidewall of the opening.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The method for removing the undoped silicon material layer on the sidewall of the opening includes performing a wet etching process.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The etchant used in the wet etching process includes diluted hydrofluoric acid.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method for forming the metal layer includes: A metal material layer is conformally formed on the silicon substrate, wherein the metal material layer covers the top surface of the dielectric layer, the sidewalls of the opening, and the top surface of the undoped silicon layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, After forming the metal silicide layer, the process also includes removing the metal material layer from the top surface of the dielectric layer and the sidewall of the opening.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The method of removing the metal material layer on the top surface of the dielectric layer and on the sidewall of the opening includes performing a wet etching process.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The etchant used in the wet etching process includes sulfuric acid.

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