Fabrication method of solder resist structure of heterogeneous sandwich steps and semiconductor device

Abstract

This invention discloses a method for fabricating a heterogeneous sandwich-layered solder resist structure and a semiconductor device. An insulating dielectric layer is added above the passivation layer of the semiconductor device, effectively preventing moisture from penetrating from the device surface into the device interior, significantly enhancing the device's resistance to moisture intrusion. The insulating dielectric layer and the first solder resist layer form a composite sandwich structure, providing multiple barriers against moisture and solder intrusion. Compared to a single organic solder resist layer solution, the solder resist effect is significantly improved. The first and second solder resist layers extend the path length for moisture and solder intrusion, increasing the difficulty of intrusion and effectively preventing solder and moisture intrusion. Based on this, the occurrence of PI peeling is effectively prevented, improving the packaging reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for fabricating a solder resist structure of a heterogeneous sandwich step and a semiconductor device thereof. Background Technology

[0002] Silicon carbide (SiC) MOSFETs, as representatives of wide-bandgap semiconductor devices, are increasingly widely used in high-power applications such as new energy vehicles, photovoltaic inverters, and rail transportation due to their excellent high-voltage, high-temperature, and high-frequency characteristics. In the packaging process of SiC power devices, to meet the solderability requirements of module packaging, a NiPdAu (nickel-palladium-gold) solderable metal layer is typically fabricated on the surface of the device's source pad using a chemical plating process. The chemical plating process for NiPdAu offers advantages such as uniform plating, no need for external current, and suitability for complex-shaped workpieces, and has become one of the mainstream technologies for UBM (Underlying Machine) layer fabrication in wafer-level packaging.

[0003] However, existing technologies for fabricating NiPdAu solderable metal layers on the source pad of silicon carbide MOSFET devices via electroless plating and subsequent semi-clip packaging present the following technical problems: First, polyimide (PI) solder mask layers are prone to peeling. Although polyimide possesses good heat resistance and mechanical properties, the high-temperature chemical solution environment of the electroless plating process and the thermal stress during subsequent encapsulation can easily cause delamination at the interface between the PI layer and the underlying metal or dielectric layer, leading to solder mask failure. Studies have shown that moisture mainly migrates along the interface between adjacent polyimide layers.

[0004] Secondly, solder wetting is prone to occur at the interface between the Source PAD and the PI solder mask layer. During the half-Clip packaging process, the solder has good fluidity during high-temperature reflow soldering. If there is a tiny gap, the solder will seep in along the gap, which may cause short circuits between adjacent pads or solder seeping into the device interior, causing abnormal electrical performance.

[0005] Third, moisture ingress is a significant problem. Moisture can gradually penetrate into the device along the interface between the PI layer and the underlying dielectric layer. Under high temperature and high humidity bias test (HVH3TRB) and PC test conditions, the presence of moisture accelerates metal migration and corrosion, leading to reliability failure.

[0006] To address the aforementioned issues, the industry currently primarily employs a single-layer PI2 solder resist solution, which involves forming a PI solder resist layer after NiPdAu electroplating. While this solution provides some solder resist and protection, the interface between the PI layer and the underlying metal is relatively flat, allowing moisture and solder to easily penetrate along this interface, thus limiting the solder resist effectiveness. Summary of the Invention

[0007] The purpose of this invention is to provide a method for fabricating a solder resist structure of a heterogeneous sandwich step and a semiconductor device, so as to solve the problems existing in the prior art.

[0008] To achieve the above objectives, the present invention provides the following technical solution: This application provides a solder resist structure for a heterogeneous sandwich step, applied to the source pad region of a semiconductor device. The semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, and a passivation layer above the interlayer dielectric layer, comprising: An insulating dielectric layer is disposed above the passivation layer; wherein the insulating dielectric layer has a first opening, the first opening exposing a portion of the source pad; A first solder resist layer is disposed above the insulating dielectric layer; wherein, the first solder resist layer has a second opening; wherein, the second opening corresponds to the first opening; A metal plating layer is disposed within the first opening, and the metal plating layer is at least partially embedded in the first opening. The metal plating layer is used to form the solderable contact surface of the source pad. A second solder resist layer is disposed above the electroplated metal layer and the first solder resist layer; wherein, the second solder resist layer has a third opening, the third opening exposing a portion of the upper surface of the electroplated metal layer.

[0009] The aforementioned heterogeneous sandwich-step solder resist structure adds an insulating dielectric layer above the passivation layer, effectively preventing moisture from penetrating from the device surface into the device interior, significantly enhancing the device's resistance to moisture intrusion. The insulating dielectric layer and the first solder resist layer form a composite sandwich structure, providing multiple barriers against moisture and solder intrusion, resulting in a significantly improved solder resist performance compared to a single organic solder resist layer solution. The first and second solder resist layers extend the path length for moisture and solder intrusion, increasing the difficulty of intrusion and effectively preventing solder and moisture intrusion. Based on this, the occurrence of piping is effectively prevented, improving the device's packaging reliability.

[0010] In one preferred embodiment, the insulating dielectric layer comprises one or more inorganic dielectric layers; The inorganic media layers are stacked or combined.

[0011] In one preferred embodiment, the inorganic dielectric layer is an OX layer or a SIN layer.

[0012] In one preferred embodiment, the electroplated metal layer is a NiPdAu stacked structure.

[0013] In one preferred embodiment, the first solder resist layer and the second solder resist layer are semiconductor packaging material layers.

[0014] In one preferred embodiment, an adhesion enhancement layer is provided between the insulating dielectric layer and the first solder resist layer; The adhesion enhancement layer is used to improve the bonding strength between the insulating dielectric layer and the first solder resist layer.

[0015] In one preferred embodiment, a stepped structure is formed between the sidewall of the first opening and the upper surface of the insulating dielectric layer; The electroplated metal layer is disposed above the stepped structure.

[0016] In one preferred embodiment, the size of the second opening of the first solder mask layer is larger than the size of the third opening of the second solder mask layer, so that a stepped structure is formed between the first solder mask layer and the second solder mask layer.

[0017] In one preferred embodiment, the second solder resist layer covers the edge portion of the first solder resist layer and the electroplated metal layer, so as to form an interlayer step between the first solder resist layer and the second solder resist layer.

[0018] This application also provides a semiconductor device, including a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a solder resist structure of heterojunction steps.

[0019] The aforementioned semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a solder resist structure with heterojunction steps. Based on this, the solder resist structure with heterojunction steps effectively prevents PI peeling and improves the packaging reliability of the device. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings. Figure 1This is a schematic cross-sectional view of the weld resistance structure of a heterogeneous sandwich step according to an embodiment of the application; Figure 2 This is a three-dimensional schematic diagram of the weld resistance structure of a heterogeneous sandwich step according to an embodiment of the application; Figure 3 A flowchart illustrating the fabrication method of a weld resistance structure for a heterogeneous sandwich step according to an embodiment of the application; Figure 4 This is a schematic diagram of the fabrication process of a weld resistance structure for a heterogeneous sandwich step according to an embodiment of the application. Figure 5 This is a schematic diagram of the product process for a weld resistance structure of a heterogeneous sandwich step according to an embodiment of the application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] To facilitate understanding of the embodiments of this application, further explanation and description will be provided below with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application. In the drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0023] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “(the)” are also intended to include the plural forms. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0024] This application provides a weld resistance structure for a heterogeneous sandwich step.

[0025] Figure 1 This is a schematic cross-sectional view of the weld resistance structure of a heterogeneous sandwich step according to an embodiment of the application, as shown below. Figure 1 As shown, the semiconductor device is applied to the source pad region of a semiconductor device, which includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, and a passivation layer (PAS) above the interlayer dielectric layer, comprising: An insulating dielectric layer 100 is disposed above the passivation layer; wherein the insulating dielectric layer 100 has a first opening, the first opening exposing a portion of the source pad; A first solder resist layer 101 is disposed above the insulating dielectric layer 100; wherein, the first solder resist layer 101 has a second opening; wherein, the second opening corresponds to the first opening; A metallized plating layer 102 is disposed in the first opening. The metallized plating layer 102 is at least partially embedded in the first opening. The metallized plating layer 102 is used to form the solderable contact surface of the source pad. A second solder resist layer 103 is disposed above the electroplated metal layer 102 and the first solder resist layer 101; wherein, the second solder resist layer 103 has a third opening, the third opening exposing a portion of the upper surface of the electroplated metal layer 102.

[0026] like Figure 1 As shown, the semiconductor substrate is a silicon carbide substrate. An interlayer dielectric layer is formed on top of the semiconductor substrate. The interlayer dielectric layer is composed of silicon oxide or a low dielectric constant material and is used to achieve electrical isolation within the device. A passivation layer (PAS) is formed above the interlayer dielectric layer. The passivation layer is typically composed of silicon nitride and has a thickness of about 1 μm. It is used to protect the device surface from damage caused by the external environment.

[0027] like Figure 1 As shown, the insulating dielectric layer 100 is disposed above the passivation layer. Preferably, the insulating dielectric layer 100 comprises one or more inorganic dielectric layers; The inorganic media layers are stacked or combined.

[0028] The inorganic dielectric layer is either an OX (oxide semiconductor) layer or a SIN (silicon nitride) layer. When the insulating dielectric layer 100 includes one inorganic dielectric layer, either an OX layer or a SIN layer can be selected. When the insulating dielectric layer 100 includes multiple inorganic dielectric layers, the insulating dielectric layer 100 is a composite structure, which can be formed by stacking or combining multiple inorganic dielectric layers.

[0029] Preferably, the composite configuration includes material composite and structural composite.

[0030] Preferably, the insulating dielectric layer 100 comprises a silicon oxide layer and a silicon nitride layer stacked together. The thickness of the silicon oxide layer is 2500-3500 Å, and the thickness of the silicon nitride layer is 2500-3500 Å. The silicon oxide layer has good insulation properties and interfacial characteristics, while the silicon nitride layer has excellent moisture barrier properties and high density. The insulating dielectric layer 100 formed by the composite of these two layers can effectively block the penetration of moisture.

[0031] The insulating dielectric layer 100 has a first opening, which exposes a portion of the source pad.

[0032] like Figure 1 As shown, the first solder resist layer 101 is disposed above the insulating dielectric layer 100.

[0033] Preferably, the first solder resist layer 101 and the second solder resist layer 103 are semiconductor packaging material layers, typically made of polyimide. Preferably, the thickness of the first solder resist layer 101 is 10-14 μm. A second opening is formed in the first solder resist layer 101, corresponding to the first opening to form a through structure.

[0034] The insulating dielectric layer 100 is an inorganic dielectric layer with a dense microstructure. The diffusion coefficient of water molecules in this type of inorganic dielectric layer is much lower than that in the organic polyimide layer. The first solder resist layer 101 is an organic polyimide layer, which has good flexibility and process compatibility. The composite structure of the inorganic dielectric layer and the organic polyimide layer forms an interlayer interface with very different properties. Moisture needs to overcome a large energy barrier when crossing this interface, thus achieving effective moisture blocking.

[0035] Figure 2 This is a three-dimensional schematic diagram of the weld resistance structure of a heterogeneous sandwich step according to an embodiment of the application, as shown below. Figure 2 As shown, from a three-dimensional perspective, the planar shape of the second opening is rectangular or rounded, and its size matches the target size of the source pad.

[0036] like Figure 1 As shown, the electroless metal plating layer 102 is disposed within the first opening, at least partially embedded in the first opening. Preferably, the electroless metal plating layer 102 is a NiPdAu (nickel-palladium-gold) stacked structure. The electroless metal plating layer 102 is used to form the solderable contact surface of the source pad, meeting the soldering requirements in the subsequent module packaging process.

[0037] like Figure 1As shown, the second solder resist layer 103 is disposed above the electroless metal plating layer 102 and the first solder resist layer 101, and is a semiconductor packaging material layer, typically composed of polyimide. Preferably, the thickness of the second solder resist layer 103 is 10-14 μm. A third opening is provided in the second solder resist layer 103, exposing a portion of the upper surface of the electroless metal plating layer 102, allowing the upper surface of the electroless metal plating layer 102 to contact external solder to achieve electrical connection.

[0038] like Figure 1 As shown, the insulating dielectric layer 100, the first solder resist layer 101, the electroplated metal layer 102, and the second solder resist layer 103 form a sandwich stepped structure. According to preferred materials, an inorganic / organic composite interface is formed between the insulating dielectric layer 100 and the first solder resist layer 101. Due to the significant difference in properties between the two materials, this composite interface provides good protection against moisture and solder intrusion. The second solder resist layer 103 covers the edges of the first solder resist layer 101 and the electroplated metal layer 102, forming an interlayer step between the first solder resist layer 101 and the second solder resist layer 103. This stepped structure extends the path length for moisture and solder intrusion, increasing the difficulty of intrusion and effectively preventing solder and moisture intrusion.

[0039] Preferably, by adjusting the thickness parameters of the insulating dielectric layer 100, the first solder resist layer 101, the electroplated metal layer 102, and the second solder resist layer 103, the solder resist requirements of different devices can be adapted.

[0040] Preferably, the size of the second opening of the first solder resist layer 101 is larger than the size of the third opening of the second solder resist layer 103, forming a stepped structure between the first solder resist layer 101 and the second solder resist layer 103. The second solder resist layer 103 covers the edge portions of the first solder resist layer 101 and the electroplated metal layer 102, forming an interlayer step between the first solder resist layer 101 and the second solder resist layer 103. Simultaneously, the interlayer step between the first solder resist layer 101 and the second solder resist layer 103 disperses and buffers thermal stress at the step, reducing the stress concentration at the interface between the PI layer and the underlying structure, thereby effectively preventing PI peeling.

[0041] Preferably, the size of the second opening is larger than the size of the first opening, so that the first solder resist layer 101 and the insulating dielectric layer 100 also form a stepped structure. By setting multiple steps, the path length of moisture and solder intrusion is further extended and the intrusion difficulty is increased, forming multiple barriers to the intrusion of moisture and solder. Compared with a single step, the solder resist effect is significantly improved.

[0042] Preferably, an adhesion enhancement layer is further provided between the insulating dielectric layer 100 and the first solder resist layer 101. Preferably, the adhesion enhancement layer is a hexamethyldisilazane (HMDS) layer, which is used to improve the bonding strength between the insulating dielectric layer 100 and the first solder resist layer 101, and further prevent PI peeling.

[0043] The solder resist structure of the heterogeneous sandwich step in any of the above embodiments adds an insulating dielectric layer 100 above the passivation layer, which can effectively prevent moisture from penetrating from the device surface into the device interior, significantly enhancing the device's resistance to moisture intrusion. The insulating dielectric layer 100 and the first solder resist layer 101 form a composite sandwich structure, which can provide multiple barriers against the intrusion of moisture and solder, significantly improving the solder resist effect compared to a single organic solder resist layer solution. The first solder resist layer 101 and the second solder resist layer 103 extend the path length of moisture and solder intrusion, increasing the difficulty of intrusion, thereby effectively preventing solder intrusion and moisture intrusion. Based on this, the occurrence of PI peeling phenomenon is effectively prevented, improving the packaging reliability of the device.

[0044] This application also provides a semiconductor device, including a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a solder resist structure of heterojunction steps.

[0045] The aforementioned semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a solder resist structure with heterojunction steps. Based on this, the solder resist structure with heterojunction steps effectively prevents PI peeling and improves the packaging reliability of the device.

[0046] Based on this, the present application also provides a method for manufacturing a weld resistance structure of a heterogeneous sandwich step.

[0047] Figure 3 This is a flowchart illustrating a method for fabricating a weld resistance structure for a heterogeneous sandwich step according to an embodiment of the application. Figure 3 As shown, a method for fabricating a weld resist structure of a heterogeneous sandwich step according to an embodiment of the application includes steps S100 to S102: S100, deposit an insulating dielectric layer 100 above the passivation layer, and pattern the insulating dielectric layer 100 to form a first opening; S101, a first solder resist layer 101 and a second solder resist layer 103 are sequentially formed on the insulating dielectric layer 100, and a second opening is formed; S102, forming a through first opening and a second opening, and forming a chemically plated metal layer 102 based on the first opening.

[0048] Preferably, an insulating dielectric layer 100 is deposited above the passivation layer using a chemical vapor deposition (CVD) process. When the insulating dielectric layer 100 is a silicon oxide layer, the silicon oxide deposition temperature is 300℃~450℃, and a TEOS source or a silane source is used; when the insulating dielectric layer 100 is a silicon nitride layer, the deposition temperature is 300℃~500℃, and SiH4 and NH3 are used as reaction gases.

[0049] Preferably, Figure 4 This is a schematic diagram of the fabrication process of a weld resistance structure for a heterogeneous sandwich step according to an embodiment of the application, as shown below. Figure 4 As shown, the insulating dielectric layer 100 is patterned using photolithography and etching processes. Photoresist is coated on the surface of the insulating dielectric layer 100, and a photoresist pattern is formed through exposure and development. Using the photoresist pattern as a mask, the insulating dielectric layer 100 is sequentially etched using a dry etching process to form the first opening. Then, the photoresist is removed. like Figure 4 As shown, a first solder resist layer 101 is formed above the insulating dielectric layer 100. Specifically, a polyimide precursor solution is coated, and after pre-baking, exposure, development, and post-baking curing processes, a first solder resist layer 101 with a second opening is formed, as shown. Figure 4 As shown. The position of the second opening corresponds to the position of the first opening in the insulating dielectric layer 100.

[0050] like Figure 4 As shown, a second solder resist layer 103 is formed above the first solder resist layer 101. Specifically, a polyimide precursor solution is coated, and after pre-baking, exposure, development, and post-baking curing processes, a second solder resist layer 103 with a third opening is formed, the second opening exposing part of the upper surface of the chemically plated metal layer 102.

[0051] like Figure 4 As shown, a metallized layer 102 is formed within the first opening. Specifically, an electroless plating process is used to form a NiPdAu structure.

[0052] Figure 5 This is a product flow diagram of a weld resist structure for a heterogeneous sandwich step according to an embodiment of the application, as shown below. Figure 5 As shown, after forming an insulating dielectric layer 100 on the basis of a passivation layer (PAS), an insulating dielectric layer 100 with a first opening is formed by photolithography etching. On the basis of the insulating dielectric layer 100, a first solder resist layer 101 and a second solder resist layer 103 (PID) are formed, and finally, electroless plating is performed to form one of the packaging processes of a semiconductor device.

[0053] The method for fabricating the solder resist structure of the heterogeneous sandwich step according to the embodiments of this application involves depositing an insulating dielectric layer 100 above a passivation layer and patterning the insulating dielectric layer 100 to form a first opening; sequentially forming a first solder resist layer 101 and a second solder resist layer 103 on the insulating dielectric layer 100, and forming a second opening; forming a through-hole first opening and a through-hole, and forming a chemically plated metal layer 102 based on the first opening. The addition of the insulating dielectric layer 100 above the passivation layer effectively prevents moisture from penetrating from the device surface into the device interior, significantly enhancing the device's resistance to moisture intrusion. The insulating dielectric layer 100 and the first solder resist layer 101 form a composite sandwich structure, providing multiple barriers against moisture and solder intrusion, significantly improving the solder resist effect compared to a single organic solder resist layer solution. The first solder resist layer 101 and the second solder resist layer 103 extend the path length for moisture and solder intrusion, increasing the difficulty of intrusion, thereby effectively preventing solder and moisture intrusion. This effectively prevents PI peeling and improves the packaging reliability of the device.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art can make various improvements and modifications without departing from the spirit and principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0055] The following points should be noted regarding this application: (1) The accompanying drawings of the embodiments of this application only involve the structures involved in the embodiments of this application. Other structures can be referred to the general design.

[0056] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0057] (3) Where there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other to obtain new embodiments. The above are only specific implementations of this application, but the protection scope of this application is not limited thereto, and the protection scope of this application shall be determined by the protection scope of the claims.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

[0060] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a weld resistance structure for a heterogeneous sandwich step, characterized in that, Including the following steps: An insulating dielectric layer is deposited above the passivation layer, and the insulating dielectric layer is patterned to form a first opening; A first solder resist layer and a second solder resist layer are sequentially formed on the insulating dielectric layer, and a second opening is formed thereon; A first opening and a second opening are formed, and a chemically plated metal layer is formed based on the first opening.

2. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 1, characterized in that, The insulating dielectric layer includes one or more inorganic dielectric layers; The inorganic media layers are stacked or combined.

3. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 2, characterized in that, The inorganic dielectric layer is an OX layer or a SIN layer.

4. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 1, characterized in that, The electroplated metal layer has a NiPdAu stacked structure.

5. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 1, characterized in that, The first solder resist layer and the second solder resist layer are semiconductor packaging material layers.

6. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 1, characterized in that, An adhesion enhancement layer is provided between the insulating dielectric layer and the first solder resist layer; The adhesion enhancement layer is used to improve the bonding strength between the insulating dielectric layer and the first solder resist layer.

7. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 1, characterized in that, A stepped structure is formed between the sidewall of the first opening and the upper surface of the insulating dielectric layer; The electroplated metal layer is disposed above the stepped structure.

8. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 1, characterized in that, The size of the second opening in the first solder mask layer is larger than the size of the third opening in the second solder mask layer, so that a stepped structure is formed between the first solder mask layer and the second solder mask layer.

9. The method for fabricating the weld resistance structure of the heterogeneous sandwich step according to claim 1, characterized in that, The second solder resist layer covers the edge portion of the first solder resist layer and the electroplated metal layer, so as to form an interlayer step between the first solder resist layer and the second solder resist layer.

10. A semiconductor device, characterized in that, The method for fabricating a heterogeneous sandwich step solder resist structure includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a method for fabricating a heterogeneous sandwich step solder resist structure as described in any one of claims 1 to 9.

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