Semiconductor element and semiconductor device

Abstract

The present invention provides a semiconductor element and semiconductor device capable of being mounted on a substrate having various pad patterns. The semiconductor element (A1) includes a plurality of terminals (2). The semiconductor element (A1) includes a line segment (L1) overlapping each of the plurality of terminals (2). The plurality of terminals (2) are arranged along a first direction (x) of the semiconductor element (A1). The plurality of terminals (2) are divided into: a first group (21) with its center of gravity (G1) offset toward a second direction (y), and a second group (22) with its center of gravity (G2) offset toward the opposite side of the first group (21) based on the line segment (L1). Each of the plurality of terminals (2) has a shape in which the dimension in the second direction (y) is larger than the dimension in the first direction (x).

Description

Technical Field

[0001] This invention relates to semiconductor elements and semiconductor devices. Background Technology

[0002] Semiconductor devices equipped with Hall elements are used in various electronic devices such as mobile phones. One example of a semiconductor device equipped with a Hall element is disclosed in Patent Document 1. The semiconductor device disclosed in this document includes: leads connected to the Hall element; and a resin encapsulation covering a portion of the Hall element and the leads. Semiconductor devices equipped with Hall elements are sometimes used in a variety of camera modules. To meet such diverse requirements, it is desirable for the semiconductor device to be able to be mounted on various pad patterns.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent document 1: Japanese Patent Application Publication No. 2022-048197. Summary of the Invention

[0006] One technical problem of the present invention is to provide a semiconductor element and semiconductor device that have been improved compared with the prior art. In particular, in view of the above, one of the technical problems of the present invention is to provide a semiconductor element that can be mounted on an external substrate having various pad patterns.

[0007] A first aspect of the present invention provides a semiconductor element comprising a plurality of terminals. The semiconductor element includes a line segment overlapping each of the plurality of terminals. The plurality of terminals are arranged along a first direction of the semiconductor element. The plurality of terminals are divided into: a first group whose center of gravity is offset toward a second direction orthogonal to the first direction; and a second group whose center of gravity is offset toward a side opposite to the first group, based on the line segment. Each of the plurality of terminals has a shape in which the dimension in the second direction is larger than the dimension in the first direction.

[0008] A semiconductor device provided by a second aspect of the present invention includes a semiconductor element provided by a first aspect and an external substrate electrically connected to the semiconductor element. The external substrate includes a plurality of pads electrically connected to the plurality of terminals respectively. Each of the plurality of pads has a different shape than each of the plurality of terminals.

[0009] Other features and advantages of the invention will become clearer from the following detailed description based on the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a top view showing a semiconductor element according to the first embodiment of the present invention.

[0011] Figure 2 It is along Figure 1 A cross-sectional view of line II-II.

[0012] Figure 3 This is a top view of a semiconductor device according to a second embodiment of the present invention, with imaginary lines representing semiconductor elements of the first embodiment.

[0013] Figure 4 It is along Figure 3 A cross-sectional view of line IV-IV.

[0014] Figure 5 It will be with Figure 3 The image shows an enlarged view of the region V.

[0015] Figure 6 This is a diagram showing a portion of a semiconductor element according to a modified example of the present invention, which is compared with... Figure 5 The corresponding area is shown in a magnified image.

[0016] Figure 7 This is a diagram showing a portion of a semiconductor element according to a modified example of the present invention, which is compared with... Figure 5 The corresponding area is shown in a magnified image.

[0017] Figure 8 This is a diagram showing a portion of a semiconductor element according to a modified example of the present invention, which is compared with... Figure 5 The corresponding area is shown in a magnified image.

[0018] Figure 9 This is a diagram showing a portion of a semiconductor device according to a modified example of the present invention, which is compared with... Figure 5 The corresponding area is shown in a magnified image.

[0019] Figure 10 This is a diagram showing a portion of a semiconductor device according to a modified example of the present invention, which is compared with... Figure 5 The corresponding area is shown in a magnified image.

[0020] Figure 11 This is a diagram showing a portion of a semiconductor device according to a modified example of the present invention, which is compared with... Figure 5 The corresponding area is shown in a magnified image.

[0021] Figure 12 This is a top view showing an outline of the camera module according to the third embodiment of the present invention.

[0022] Figure 13 This is an exploded perspective view showing an outline of the camera module according to the third embodiment of the present invention.

[0023] Figure 14This is a rear view showing an outline of a portable terminal equipped with a camera module according to the third embodiment of the present invention. Detailed Implementation

[0024] Hereinafter, the details of the present invention will be described with reference to the accompanying drawings. Hereinafter, the same or similar constituent elements will be labeled with the same reference numerals, and repeated descriptions will be omitted.

[0025] In the description of the semiconductor element and the semiconductor device described later in this invention, the vertical direction in the top view is referred to as "first direction x", and the horizontal direction in the top view is referred to as "second direction y". The direction orthogonal to the first direction x and the second direction y is referred to as "third direction z". In this invention, terms such as "up", "down", "right", and "left" indicate the relative positional relationship of the components in the drawings, and are not necessarily terms that specify the relationship with the direction of gravity.

[0026] First, refer to Figure 1 and Figure 2 The semiconductor element A1 of the first embodiment of the present invention will be described. Figure 1 This is a top view schematically illustrating an example of a semiconductor element A1 according to a first embodiment of the present invention. Figure 1 As shown, semiconductor element A1 is a wafer-level chip-scale package (WL-CSP) type. Alternatively, semiconductor element A1 can also be a fan-out wafer-level package (FO-WLP) type. Semiconductor element A1 can be a rectangular shape in which the width in the first direction x is longer than the width in the second direction y when viewed in the third direction z. In this invention, a "rectangular shape" can include a quadrilateral with four corners at angles other than 90°, a quadrilateral with four corners in the range of 90° ± 5°, or a rounded quadrilateral with four rounded corners. For example, semiconductor element A1 has a rectangular shape with an aspect ratio of about 2 or more and less than 4 when viewed in the third direction z, and the length of the short side is more than 0.35 mm and less than 0.8 mm. In this invention, "aspect ratio" refers to the ratio of the length of the long side to the length of the short side. Semiconductor element A1 includes a wafer portion 10 and a plurality of terminals 2.

[0027] The wafer portion 10 functions as a semiconductor chip with built-in semiconductor circuitry and wiring. The semiconductor chip may include, for example, a magnetic sensor, an amplifier, an A / D converter, a PID control unit, a D / A converter, and an output driver. The wafer portion 10 is made of semiconductor materials. In this invention, "semiconductor materials" include, for example, silicon carbide (SiC), silicon (Si), gallium nitride (GaN), or diamond (C). In this invention, "A is composed of material B" means that the main component of A is material B, and does not mean that it is made solely of material B.

[0028] Semiconductor element A1 includes line segment L1 that overlaps with multiple terminals 2. Figure 1 Line segment L1 is illustrated using a single-dotted line. When viewed along a third direction z, line segment L1 divides each terminal 2 into two regions. Line segment L1 can be located at the center in the second direction y of semiconductor element A1, extending along the first direction x of semiconductor element A1. Line segment L1 does not need to physically exist on semiconductor element A1, as long as the line segment L1 overlapping with multiple terminals 2 can be defined. That is, this means that semiconductor element A1 includes portions that meet specific conditions.

[0029] Multiple terminals 2 function as components for electrically connecting the wafer portion 10 to an external substrate (e.g., a wiring board). Each terminal 2 is made of, for example, copper (Cu) or nickel (Ni). The sum of the areas of the multiple terminals 2 in top view can be 11% or more of the area of ​​the semiconductor element A1 in top view. The number of terminals 2 is not particularly limited and can be more than 3 and less than 10. However, an even number is preferred to ensure the balance and stability of the semiconductor element A1 in the second direction y during mounting. Hereinafter, as... Figure 1 As shown, an example of multiple terminals 2 including six terminals 2a to 2f will be described. The six terminals 2a to 2f are referred to as "terminal 2" unless otherwise specified. Unless otherwise specified, the six terminals 2a to 2f may have the same characteristics as each other or different characteristics. A conductive connection member 50 may be provided on each terminal 2.

[0030] Each conductive connection component 50 functions as a component for bonding the wafer portion 10 to an external substrate (e.g., a wiring substrate). When viewed in the third direction z, the periphery of each conductive connection component 50 coincides with the periphery of the corresponding terminal 2. Alternatively, the periphery of each conductive connection component 50 may be smaller than the periphery of the corresponding terminal 2 when viewed in the third direction z. Each conductive connection component 50 is, for example, solder or silver paste containing tin as the main component.

[0031] When viewed from a third-party direction z, terminal 2 has two or more different radii of curvature. Terminal 2 has a shape in which the dimension in the second direction y is larger than the dimension in the first direction x. That is, terminal 2 can have an elliptical shape. In this invention, "elliptical shape" refers to a closed curve-like shape having a principal axis and a secondary axis, meaning that the principal axis (hereinafter referred to as the "major axis") is longer than the secondary axis (hereinafter referred to as the "minor axis"). The dimension of terminal 2 along the minor axis is, for example, 150 μm or more and 300 μm or less, and the dimension along the major axis is 180 μm or more and 330 μm or less. Furthermore, the ratio of the length of the major axis to the length of the minor axis of terminal 2 can be in the range of 1.05 or more and 1.67 or less. In the illustrated example, each terminal 2 is an elongated circle in which the major axis along the second direction y is longer than the minor axis along the first direction x. More specifically, each terminal 2 has an elongated shape formed by combining a rectangle that is longer in the second direction y and two semicircles that are connected to the two ends of the rectangle in the second direction y. Terminal 2 has a symmetrical shape based on its center of gravity (i.e., the intersection of the major and minor axes). In this invention, "center of gravity of A" refers to the center of gravity of A in three dimensions, and can also refer to the geometric center of gravity of the shape when a specific face of A (e.g., the surface of terminal 2) is viewed in one direction. Although optional, the major axes of two adjacent terminals 2 can be parallel to each other.

[0032] When viewed from a third-party perspective, each terminal 2 comprises: a first region R1 with the center of gravity located relative to line segment L1, and a second region R2 with the center of gravity not located there. The ratio of the first region R1 to the second region R2 is less than 98%.

[0033] Six terminals 2a to 2f are arranged along a first direction x. In this invention, "a plurality of A's arranged along direction C" means that each A can be arranged in direction C and offset in any direction other than direction C. The six terminals 2a to 2f are arranged in two columns in a second direction y. More specifically, three terminals 2a to 2c are offset relative to three terminals 2d to 2f in the second direction y. In the illustrated example, the six terminals 2a to 2f are point-symmetrically arranged with reference to the center of the wafer portion 10.

[0034] The six terminals 2a to 2f are divided into two groups: a first group 21 with the center of gravity G1 offset to one side of the second direction y, based on line segment L1, and a second group 22 with the center of gravity G2 offset to the other side of the second direction y. In other words, the second group 22 has its center of gravity offset to the opposite side of the first group 21, based on line segment L1. In this invention, "offset" refers to the deviation of the position of a specific element from the reference point. In the illustrated example, the centers of gravity G1 are aligned in the second direction y, and the centers of gravity G2 are aligned in the second direction y. In this invention, "A and B are aligned in direction C" means that A and B are in the same position in direction C, which includes an error that is generally accepted as a manufacturing tolerance.

[0035] In the illustrated example, the first group 21 includes three terminals 2a to 2c, and the second group 22 includes three terminals 2d to 2f. Terminal 2b is located between terminals 2a and 2c in the first direction x. Terminal 2e is located between terminals 2d and 2f in the first direction x. Furthermore, one of terminals 2d to 2f in the second group 22 is located between two adjacent terminals 2 in the first group 21. That is, the centroid G1 of each of terminals 2a to 2c in the first group 21 does not overlap with the centroid G2 of each of terminals 2d to 2f in the second group 22, not only in the first direction x but also in the second direction y. Alternatively, terminals 2d and 2e may not be located between terminals 2a to 2c respectively in the first direction x. For example, the three terminals 2a to 2c may be located in the upper left, and the three terminals 2d to 2f may be located in the lower right.

[0036] exist Figure 1 The diagram illustrates the distance D1 between terminals 2a and 2b in the first direction x. Distance D1 corresponds to the distance between one end (lower end) of terminal 2a and one end (upper end) of terminal 2b in the first direction x. In this invention, "the distance between A and B" refers to the dimension between the closest (or furthest) portions of B relative to a specific portion of A. The distance between terminals 2b and 2c in the first direction x can be the same as distance D1. That is, two adjacent terminals 2 in the first group 21 are separated by distance D1. Similarly, two adjacent terminals 2 in the second group 22 can also be separated by distance D1. Distance D1 is, for example, 200 μm or more and 800 μm or less. In this invention, "size A is the same (equal) to size B" sometimes includes differences generally considered to be manufacturing tolerances.

[0037] exist Figure 1 The diagram illustrates the spacing D2 between terminals 2a and 2d in the first direction x. Spacing D2 corresponds to the distance along the first direction x between one end (lower end) of terminal 2a and one end (upper end) of terminal 2d. The spacing between two adjacent terminals 2 in the first direction x can all be the same as spacing D2. Spacing D2 is, for example, 50 μm or more and 400 μm or less.

[0038] exist Figure 1 The diagram illustrates the spacing D3 between terminals 2a and 2d in the second direction y. Spacing D3 corresponds to the distance along the second direction y between one end (left end) of terminal 2a and one end (right end) of terminal 2d in the second direction y. The spacing between the first group 21 and the second group 22 in the second direction y can also be entirely the same as spacing D3. Spacing D3 is, for example, 250 μm or more and 650 μm or less. Spacing D3 can be more than 50% of the dimension of semiconductor element A1 in the second direction y.

[0039] exist Figure 1 The diagram illustrates the dimension S1 of terminal 2a in the first direction x. Dimension S1 corresponds to the maximum length of terminal 2a in the first direction x. The dimensions of all six terminals 2a to 2f in the first direction x can also be the same as dimension S1. Dimension S1 is, for example, 180 μm or more and 330 μm or less.

[0040] Figure 1 The diagram illustrates the dimension S2 of terminal 2a in the second direction y. Dimension S2 corresponds to the maximum length of terminal 2a in the second direction y. The dimensions of all six terminals 2a to 2f in the second direction y can also be the same as dimension S2. Dimension S2 is, for example, 150 μm or more and 300 μm or less.

[0041] exist Figure 1 The diagram illustrates angle θ. Angle θ corresponds to the angle formed by the line segment connecting the centroid G1 of terminal 2a to the centroid G2 of terminal 2d, and the line segment connecting the centroid G1 of terminal 2b to the centroid G2 of terminal 2d. The angle formed by any three terminals 2 arranged in the first direction x can be the same as angle θ. Angle θ is, for example, 60° or more. This means that when viewed from the third direction z, any three terminals 2 are located in mutually inclined positions.

[0042] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shows an example of the internal structure of the wafer portion 10. Hereinafter, an example of one of the plurality of terminals 2 and the wafer portion 10 below that terminal 2 will be described. In the illustrated example, the wafer portion 10 includes a body 11, an electrode 12, a first protective film 30, a second protective film 31, a third protective film 32, a redistribution 41, a plurality of contact layers 42, and a terminal 2. However, the internal structure of the wafer portion 10 is not limited to this example. The wafer portion 10 may have different internal structures below each of the plurality of terminals 2.

[0043] The main body 11 includes a semiconductor substrate 111 and a semiconductor layer 112 located on the third z-direction side of the semiconductor substrate 111. The main body 11 has a main surface 11A facing the third z-direction side. The semiconductor layer 112 includes the main surface 11A. The semiconductor substrate 111 is obtained from a wafer. The semiconductor layer 112 includes various semiconductor circuits such as transistors and diodes, for example, on and near the main surface 11A.

[0044] Electrode 12 is connected to a semiconductor circuit formed in semiconductor layer 112. Electrode 12 is located on the third z-direction side of body 11. Electrode 12 is in contact with main surface 11A of body 11. Electrode 12 may contain, for example, aluminum (Al).

[0045] Electrode 12 has a connection surface 121. The connection surface 121 faces the same side as the main surface 11A of the body 11 in the third direction z. A portion of the connection surface 121 is covered by a first protective film 30.

[0046] The first protective film 30 covers the main surface 11A of the body 11 and a portion of the electrode 12. The first protective film 30 is a thin film containing silicon dioxide (SiO2) or silicon nitride (Si3N4) or a stack of these thin films.

[0047] The first protective film 30 has a first opening 30a. The first opening 30a extends through the first protective film 30 in the third direction z. The connection surface 121 of the electrode 12 is exposed from the first opening 30a. When viewed in the third direction z, the first opening 30a is located inside the periphery of the connection surface 121.

[0048] A second protective film 31 covers a portion of the electrode 12 and the first protective film 30. The second protective film 31 is located between the body 11 and the third protective film 32 in a third direction z. Furthermore, the second protective film 31 includes a portion located between the first protective film 30 and the redistribution 41. The second protective film 31 is housed within a first opening 30a of the first protective film 30 and includes portions in contact with both the first protective film 30 and the redistribution 41. The second protective film 31 is an insulator containing an organic compound. More specifically, the second protective film 31 is, for example, made of a material containing polyimide.

[0049] The third protective film 32 covers the second protective film 31 and the rewiring 41. The third protective film 32 is in contact with the terminal 2. The third protective film 32 has a larger third-direction z-dimensional dimension than the second protective film 31. The third protective film 32 has a second opening 321. The second opening 321 extends through the third protective film 32 in the third-direction z-dimensional direction. The rewiring 41 is exposed from the second opening 321. The composition of the third protective film 32 can be the same as or different from that of the second protective film 31. Alternatively, the third protective film 32 may not be provided. In this case, a weight reduction equivalent to the amount of the third protective film 32 can be achieved.

[0050] The rewiring 41 is connected to the electrode 12 via the contact layer 42. The rewiring 41 is located between the contact layer 42 and the terminal 2 in the third direction z. The rewiring 41 extends in a direction orthogonal to the third direction z (first direction x and / or second direction y). The rewiring 41 includes: a barrier layer in contact with the second protective film 31, a seed layer stacked on the barrier layer, and a plating layer stacked on the seed layer. The barrier layer comprises titanium (Ti). The seed layer and the plating layer each comprise copper (Cu).

[0051] The rewiring 41 is sandwiched between the second protective film 31 and the third protective film 32. The rewiring 41 has a plurality of recesses 411. The plurality of recesses 411 are recessed in a third direction z from the side opposite to the third protective film 32. When viewed in the third direction z, the plurality of recesses 411 overlap with a plurality of contact layers 42 respectively. The plurality of recesses 411 accommodate a portion of the terminal 2.

[0052] Contact layer 42 is electrically connected to electrode 12 and redistribution 41. Thus, redistribution 41 and contact layer 42 are electrically connected to electrode 12. Contact layer 42 is located between electrode 12 and redistribution 41 in the third direction z. Contact layer 42 includes: a barrier layer in contact with electrode 12 and second protective film 31, a seed layer stacked on the barrier layer, and a plating layer stacked on the seed layer. The barrier layer comprises titanium. The seed layer and plating layer each comprise copper.

[0053] The contact layer 42 includes a first contact layer 421 and a second contact layer 422. The first contact layer 421 and the second contact layer 422 are spaced apart from each other in the second direction y. A portion of each of the first contact layer 421 and the second contact layer 422 is respectively housed in the first opening 30a of the first protective film 30.

[0054] Terminal 2 is conductive to redistribution 41. Thus, terminal 2 is conductive to contact layer 42. Terminal 2 is located on the opposite side of contact layer 42 in the third direction z, with reference to redistribution 41. A portion of terminal 2 is housed in the second opening 321 of the third protective film 32. When viewed in the third direction z, terminal 2 can protrude outward from the second opening 321. Terminal 2 is exposed from the third protective film 32. More specifically, a portion of terminal 2 protrudes from the third protective film 32 in the third direction z. Terminal 2 contains copper.

[0055] When viewed in the third direction z, terminal 2 overlaps with both the first contact layer 421 and the second contact layer 422. When viewed in the third direction z, the area of ​​each of the first contact layer 421 and the second contact layer 422 is smaller than the area of ​​terminal 2. Furthermore, when viewed in the third direction z, terminal 2 completely overlaps with each of the contact layers of the first contact layer 421 and the second contact layer 422. With this structure, the cross-sectional area in the direction orthogonal to the third direction z in the conductive path from electrode 12 to terminal 2 is further increased, thus reducing the resistance value of the conductive path from electrode 12 to terminal 2.

[0056] The conductive connection component 50 is electrically connected to terminal 2. The conductive connection component 50 is located on the side opposite to the rewiring 41 in the third direction z, with terminal 2 as a reference. The melting point of the conductive connection component 50 is preferably lower than that of terminal 2. When viewed in a direction orthogonal to the third direction z, the end of the conductive connection component 50 may also be bent.

[0057] The function and effect of semiconductor element A1 are as follows.

[0058] Semiconductor element A1 has the advantage of being able to be mounted on an external substrate with various pad patterns. Semiconductor element A1 includes a line segment L1 that overlaps with a plurality of terminals 2. The plurality of terminals 2 includes: a first group 21 with its center of gravity G1 offset in a second direction y; and a second group 22 with its center of gravity G2 offset in the opposite direction to the first group 21, based on line segment L1. Each of the plurality of terminals 2 has a shape in which its dimension in the second direction y is larger than its dimension in the first direction x. Compared to the case where the terminals 2 are circular when viewed in a third direction z, the bonding surface of semiconductor element A1 is formed to be longer in the second direction y. Therefore, semiconductor element A1 has a high degree of freedom in mounting.

[0059] The semiconductor element A1 includes a plurality of terminals 2 arranged in at least two columns in a first direction x. This structure is advantageous for more stable mounting of the semiconductor element A1 compared to arranging the plurality of terminals 2 in only one column.

[0060] Semiconductor element A1 has the advantage of being easily housed in narrow spaces. Alternatively, the centroids G1 of terminals 2a-2c in the first group 21 can be aligned in the second direction y, and the centroids G2 of terminals 2d-2f in the second group 22 can be arranged in the second direction y. With this structure, each terminal 2 can be formed wide in the second direction y without increasing the size of semiconductor element A1 in the second direction y. That is, semiconductor element A1 can have an elongated shape. An elongated shape of semiconductor element A1 is preferred in terms of placing semiconductor element A1 in narrow spaces (e.g., the hollow core portion of a coil).

[0061] Two adjacent terminals 2 of the plurality of terminals 2 may contain parallel long axes. This allows for the appropriate spacing between the terminals 2. Such a structure improves the reliability of the semiconductor element A1.

[0062] The terminals 2a-2c of the first group 21 are alternately arranged with the terminals 2d-2f of the second group 22. Compared to a configuration where all terminals 2 are arranged adjacently in the first direction x, this structure eliminates the need for sufficient spacing in the first direction x to prevent short circuits between terminals 2. This facilitates a reduction in the size of the semiconductor element A1 in the second direction y. Furthermore, wiring for electrical connections from the terminals 2 to the semiconductor chip within the wafer portion 10 can be extended to a longer length. This is because each terminal 2 has space in the regions facing the first direction x and the second direction y.

[0063] Each terminal 2 includes a first region R1 on the side where the centers of gravity G1 and G2 are located, with line segment L1 as a reference, and a second region R2 on the side where the centers of gravity G1 and G2 are not located. The ratio of the first region R1 to the second region R2 is 98% or less. With this structure, each terminal 2 can be positioned near the center in the second direction y of the semiconductor element A1, and a sufficient number of terminals 2 can be provided in the second direction y. This is beneficial for further improving stability during installation and for further miniaturizing the semiconductor element A1.

[0064] Hereinafter, other embodiments and modifications of the semiconductor element of the present invention will be described. The structures of each part in each embodiment and modification can be combined with each other without causing technical inconsistencies.

[0065] Next, refer to Figures 3-5 The semiconductor device B1 according to the second embodiment of the present invention will be described. Figure 3 This is a top view schematically representing an example of a semiconductor device B1. Figures 3-5 In the diagram, line segment L1 is also represented by a single-dot dashed line. Semiconductor device B1 includes semiconductor element A1 and external substrate 7. Figure 3 In the diagram, the wafer portion 10 of semiconductor element A1 and multiple terminals 2 are illustrated with dashed lines (double-dotted lines), and the outer substrate 7 is illustrated with solid lines. Semiconductor element A1 is mounted on the outer substrate 7. The number of semiconductor elements A1 mounted on the outer substrate 7 can be one or multiple.

[0066] The outer substrate 7 is, for example, a wiring substrate. More specifically, the outer substrate 7 is a wiring substrate having a so-called multilayer wiring layer consisting of multiple wiring layers and insulating layers. The outer substrate 7 may be a wiring substrate larger than the outer periphery of the semiconductor element A1. As an example, the outer substrate 7 may be 2 mm larger than the length of the semiconductor element A1 in the first direction x and the second direction y, respectively. Alternatively, the outer periphery of the outer substrate 7 may be located inside the outer periphery of the semiconductor element A1, or may be aligned with the outer periphery of the semiconductor element A1.

[0067] The external substrate 7 includes a substrate body 71 and a plurality of pads 72. Alternatively, the external substrate 7 may be a structure that only includes pads 72 as leads. Alternatively, the external substrate 7 may be configured to include external terminals on the side opposite to the pads 72 in a third direction z, with reference to the substrate body 71. The substrate body 71 includes an insulator. Each pad 72 contains metal (e.g., Cu).

[0068] Figure 4 It is along Figure 3The cross-sectional view along line IV-IV shows an example of the internal structure of the semiconductor device B1. In the illustrated example, the conductive connection component 50 is molten and bonded to the pad 72. The conductive connection component 50 covers the entire surface of the pad 72 facing the third direction z. Alternatively, unlike the illustrated example, the conductive connection component 50 covers only a portion of the surface of the pad 72 facing the third direction z, protruding to the outside of the pad 72. The conductive connection component 50 is located between the terminal 2 and the pad 72 in the third direction z. The semiconductor element A1 is separated from the external substrate 7 in the third direction z by a portion of the terminal 2 and the thickness of the molten conductive connection component 50. Alternatively, unlike the illustrated example, the semiconductor element A1 is covered by a sealing resin such as an underfill adhesive. The sealing resin can cover the periphery of multiple terminals 2 and fill the spaces between adjacent terminals 2. With this structure, the adhesion between the semiconductor element A1 and the external substrate 7 is strong, and the semiconductor device B1 is less susceptible to external influences.

[0069] like Figure 3 and Figure 4 As shown, multiple pads 72 are respectively bonded to multiple conductive connection parts 50 of the semiconductor element A1. That is, the substrate body 71 is electrically connected to the semiconductor element A1 via multiple terminals 2. The number of pads 72 is not particularly limited and can be the same as the number of terminals 2. Hereinafter, as Figure 3 As shown, an example of multiple pads 72, including 6 pads 72a to 72f, will be explained.

[0070] Six pads 72a-72f are positioned corresponding to six terminals 2a-2f respectively. In this invention, "corresponding position" refers to a position that overlaps with at least a portion of the terminal 2 when viewed in a third direction z. That is, in the illustrated example, the six pads 72a-72f are arranged in two rows along the second direction y and in the first direction x. Preferably, the centroid Gp of each pad 72a-72f is located near the centroids G1 and G2 of the terminals 2a-2f. In this embodiment, the centroid Gp of each pad 72a-72f overlaps with one corresponding centroid among the centroids G1 and G2 of the six terminals 2a-2f. In this invention, "overlap of A and B when viewed in a certain direction" includes "complete overlap of A and B" and "partial overlap of A and B". That is, the angle formed by any three pads 72 arranged in the second direction y is equal to the angle θ.

[0071] exist Figure 3The diagram illustrates the spacing D4 between pads 72a and 72b in the first direction x. Spacing D4 corresponds to the minimum distance between pads 72a and 72b in the first direction x. The spacing between pads 72b and 72c, pads 72d and 72e, and pads 72e and 72f can be the same as spacing D4. That is, two pads 72 opposite each other in the first direction x can be separated by spacing D4. Spacing D4 is, for example, 200 μm or more and 800 μm or less. Spacing D4 is smaller than spacing D1.

[0072] exist Figure 3 The diagram illustrates the spacing D5 along the first direction x between pads 72a and 72d. Spacing D5 corresponds to the minimum distance between pads 72a and 72d along the first direction x. The spacing of two adjacent pads 72 along the first direction x can also be entirely the same as spacing D5. Spacing D5 is, for example, greater than 50 μm and less than 400 μm. Spacing D5 is smaller than spacing D2.

[0073] exist Figure 3 The diagram illustrates the spacing D6 between pads 72a and 72d in the second direction y. Spacing D6 corresponds to the maximum distance between pads 72a and 72d along the second direction y. The spacing between two adjacent pads 72 in the first direction x in the second direction y can also be entirely the same as spacing D6. Spacing D6 is, for example, greater than 250 μm and less than 650 μm. Spacing D6 is smaller than spacing D3.

[0074] Figure 5 It is Figure 3 The enlarged view of region V illustrates one terminal 2 and one pad 72. Figure 5 In the diagram, semiconductor element A1 (terminal 2) is shown as a solid line, and the external substrate 7 (pad 72) is shown as a dashed line (double-dotted line). See below for reference. Figure 5 The structure of each pad 72 is described. The multiple terminals 2a to 2f and the multiple pads 72a to 72f may have the same features or different features.

[0075] When viewed in the third direction z, pad 72 is circular. In this embodiment, pad 72 is connected to line segment L1. Pad 72 may have a shape in which dimension S3 in the first direction x and dimension S4 in the second direction y are equal. Dimensions S3 and S4 are 150 μm or more and 350 μm or less. Dimension S3 of pad 72 is larger than dimension S1 of terminal 2. Dimension S4 of pad 72 is smaller than dimension S2 of terminal 2. Unlike the illustrated example, pad 72 may be square when viewed in the third direction z, and its shape is arbitrary.

[0076] The function and effect of semiconductor device B1 are as follows.

[0077] Semiconductor device B1 can be mounted in various ways. Semiconductor device B1 includes a semiconductor element A1 and an external substrate 7 electrically connected to the semiconductor element A1. The external substrate 7 includes a plurality of pads 72 electrically connected to a plurality of terminals 2 respectively. Each pad 72 has a different shape than each terminal 2. As described above, the terminal 2 has a shape in which the dimension in the second direction y is larger than the dimension in the first direction x. Therefore, semiconductor device B1 has the advantage that semiconductor element A1 can be reliably mounted on external substrate 7 even if the pads 72 are slightly offset from the terminal 2.

[0078] The reliability of semiconductor device B1 is improved. The distance D2 in the first direction x between two adjacent terminals 2 can be larger than the distance D5 in the first direction x between two adjacent pads 72. With this structure, when the semiconductor element A1 is bonded to the external substrate 7, bridging between molten conductive connection parts 50 can be reduced.

[0079] The dimension S1 of terminal 2 in the first direction x can be smaller than the dimension S3 of pad 72 in the first direction x. With this structure, when bonding semiconductor element A1 to external substrate 7, bridging between molten conductive connection parts 50 can also be reduced.

[0080] Terminal 2 can have a shape in which the dimension in the second direction y is larger than the dimension in the first direction x. On the other hand, pad 72 has a shape in which the dimension in the first direction x is equal to the dimension in the second direction y. More specifically, terminal 2 can be oblong, while pad 72 can be circular. Even with such different shapes joining together, since terminal 2 is positioned corresponding to pad 72, semiconductor element A1 can be stably mounted on the external substrate 7. That is, such a structure improves reliability.

[0081] Next, refer to Figures 6-8 The semiconductor elements A2 to A4 of the modified examples of the first embodiment will be described. For ease of understanding, Figures 6-8 Semiconductor elements A2 to A4 are shown in modified examples with semiconductor device B1 mounted on external substrate 7. The difference between semiconductor elements A2 to A4 and semiconductor element A1 lies in the shape of terminal 2 as observed along the third direction z.

[0082] Figure 6Semiconductor element A2 represents a variation of the first embodiment. Semiconductor element A2 includes a teardrop-shaped terminal 2. In this invention, "teardrop shape" refers to a shape where the arcuate portion smoothly connects to the tapered portion at the front end. The "teardrop shape" is not limited to a symmetrical shape. The terminal 2 of semiconductor element A2 can be a teardrop shape including a tapered portion towards the central side (i.e., line segment L1) in the second direction y. In this invention, "A includes a tapered C towards B" means that the cross-section of C is smaller closer to B. Furthermore, the centroid G2 of terminal 2 can also coincide with the centroid Gp of pad 72.

[0083] With this structure, a sufficient number of terminals 2 can be provided at positions corresponding to the pads 72, and the amount of conductive connection parts 50 overflowing from the pads 72 can be reduced. Therefore, the semiconductor element A2 can be firmly bonded to the external substrate 7 while reducing bridging between multiple conductive connection parts 50.

[0084] Figure 7 Semiconductor element A3 represents a variation of the first embodiment. Semiconductor element A3 includes an elliptical terminal 2. Terminal 2 has a major axis along a second direction y. Terminal 2 has a symmetrical shape along the major axis. Furthermore, the centroid G2 of terminal 2 may coincide with the centroid Gp of pad 72.

[0085] With this structure, terminal 2 can be formed into a generally symmetrical shape with rounded corners. This shape is advantageous in uniformly distributing stress. Therefore, semiconductor element A3 has the advantage of high durability against the thermal expansion of terminal 2. Furthermore, this shape helps to uniform the flow of current through terminal 2, reducing resistance.

[0086] Figure 8 Semiconductor element A4 represents a variation of the first embodiment. Semiconductor element A4 includes a hexagonal terminal 2. Terminal 2 has a major axis along a second direction y. Terminal 2 has a symmetrical shape along the major axis. Furthermore, the centroid G2 of terminal 2 may coincide with the centroid Gp of pad 72.

[0087] Based on this structure, terminal 2 can be formed into a shape with many edges. This shape makes it easier to concentrate force on specific areas, thus improving the stability of the connection between terminal 2 and pad 72. From this effect, it can be understood that terminal 2 can be a polygon other than a hexagon.

[0088] As understood from the above description, terminal 2 can take various shapes without contradicting the technology of this invention. Such shapes can be achieved, for example, by casting metal material into a mold or by machining fine polygonal patterns on the surface. The conductive connection component 50 corresponding to the shape of terminal 2 can be achieved, for example, by using pre-formed solder.

[0089] Next, refer to Figures 9-11 The semiconductor devices B2 to B4 of the modified examples of the second embodiment will be described. For ease of understanding, Figures 9-11 Each is shown with semiconductor element A1 mounted on it. Semiconductor devices B2 to B4 may also include terminals 2 of semiconductor elements A2 to A4. Semiconductor devices B2 and B3 differ from semiconductor device B1 in the relative positions of terminals 2 and pads 72. Semiconductor device B4 differs from semiconductor device B1 in the size of pads 72.

[0090] Figure 9 Semiconductor device B2, representing a variation of the second embodiment, is shown. In semiconductor device B2, when viewed in a third direction z, the centroid G2 of terminal 2 does not overlap with the centroid Gp of pad 72. More specifically, the centroid G2 of terminal 2 is closer to line segment L1 than the centroid Gp of pad 72. Figure 9 The terminal 2 in this embodiment is offset to the left. Therefore, compared with the terminal 2 of semiconductor element A1, the second region R2 occupies a larger proportion.

[0091] exist Figure 9 The diagram illustrates angles α and β. Angle α corresponds to the angle formed by the line segment connecting the centroids of any three terminals 2. Angle β corresponds to the angle formed by the line segment connecting the centroids of any three pads 72. The distance between any three terminals 2 is less than the distance between any three pads 72. Therefore, angle α is less than angle β.

[0092] With this structure, uniform stress is not applied to the entire mating surface of terminal 2, allowing stress to concentrate in a specific area. That is, semiconductor device B2 has the advantage of reducing the risk of damage to terminal 2 and pad 72 by dispersing stress in a specific direction. Furthermore, compared to semiconductor device B1, terminal 2 is more centrally located in semiconductor device B2. Therefore, semiconductor device B2 facilitates miniaturization of dimensions in the second direction y.

[0093] Figure 10 Semiconductor device B3, representing a variation of the second embodiment, is shown. In semiconductor device B3, when viewed in a third direction z, the centroid G2 of terminal 2 does not overlap with the centroid Gp of pad 72. More specifically, the centroid G2 of terminal 2 is further away from line segment L1 than the centroid Gp of pad 72. Figure 10(Offset to the right of the line segment L1). In this embodiment, pad 72 overlaps with line segment L1 and is divided into two regions by line segment L1.

[0094] exist Figure 10 The diagram illustrates angles α and β. Angle α corresponds to the angle formed by the line segment connecting the centroids of any three terminals 2. Angle β corresponds to the angle formed by the line segment connecting the centroids of any three pads 72. The distance between any three terminals 2 is greater than the distance between any three pads 72. Therefore, angle α is less than angle β.

[0095] Like semiconductor device B2, semiconductor device B3 has the advantage of reducing the risk of damage to terminal 2 and pad 72 by dispersing stress in a specific direction.

[0096] Figure 11 Semiconductor device B4 illustrates a variation of the second embodiment. In semiconductor device B4, when viewed in the third direction z, pad 72 surrounds the periphery of terminal 2. The dimension of pad 72 in the second direction y can be equal to or larger than the dimension of terminal 2 in the second direction y. In the illustrated example, when viewed in the third direction z, the centroid G2 of terminal 2 overlaps with the centroid Gp of pad 72. Alternatively, the centroid G2 of terminal 2 may be offset from the centroid Gp of pad 72.

[0097] With this structure, when the conductive connection component 50 melts, it is difficult for it to overflow from the periphery of the pad 72. Therefore, the semiconductor device B4 is beneficial for improving the stability of the bonding.

[0098] The semiconductor devices B1 to B4 (hereinafter referred to as semiconductor devices B) of the second embodiment of the present invention can be mounted on a camera module C, for example. Figure 12 and Figure 13 A camera module C equipped with a semiconductor device B is shown. Figure 13 This is an exploded perspective view of the camera module C according to this embodiment. The camera module C includes: a lens 3 on which the camera is mounted; a semiconductor device B, such as a sensor 4 for detecting the position of the lens 3; and coils, magnets, etc. (not shown) for adjusting the position of the lens 3. This enables lens position control, which adjusts the position of the lens 3. Lens position control includes an autofocus mechanism, an image stabilization mechanism, etc.

[0099] The components of camera module C can be arranged around lens 3. Specifically, semiconductor device B can be arranged around lens position control mechanisms such as autofocus and image stabilization mechanisms that control the position of lens 3. Position detection sensor 4 can be mounted on semiconductor device B. Semiconductor device B can be housed within the unit or positioned outside the component supporting lens 3. Semiconductor device B is not limited to having position detection sensor 4 mounted on it; it can also house other electronic components.

[0100] Figure 13 This is an exploded perspective view of the camera module C according to this embodiment. The camera module C includes a substrate 300, a base 400, a holding frame 500, and a lens unit 600. An image sensor 302 is disposed on the substrate 300. The image sensor 302 may be constructed of a CCD (Charge-Coupled Device) or a CMOS (Complementary Metal-Oxide-Semiconductor). The image sensor 302 outputs image data of an optical image formed via the lens unit 600.

[0101] The retaining frame 500 internally holds the lens unit 600. A magnet 502 is disposed on the outer surface of the retaining frame 500. The base 400, together with the lens unit 600, holds the retaining frame 500 in a manner capable of movement along the optical axis (Z-axis) and in directions intersecting the optical axis (X-axis and Y-axis). A coil 402 and a semiconductor device B are disposed on the side of the base 400. The coil 402 is positioned opposite the magnet 502. The coil 402 may be an air-core coil. The magnet 502 and the coil 402 function as a drive source, i.e., a VCM (voice coil motor), to move or rotate the retaining frame 500 relative to the base 400.

[0102] When current flows through coil 402 in the magnetic field of magnet 502, a force is generated in coil 402 in a direction perpendicular to the magnetic field. This exerts a thrust on retaining frame 500 along a first direction x or a second direction y. Alternatively, the configuration of coil 402 or the direction of the magnetic field of magnet 502 can be designed so that by passing current through coil 402, a thrust along the Z direction is applied to retaining frame 500.

[0103] A semiconductor device B is disposed in the hollow portion of coil 402. Semiconductor device B functions as a position sensor to detect the position or orientation of holding frame 500 relative to base 400. The position sensor can be a magnetic sensor including a Hall element. The position sensor can output a voltage corresponding to the magnitude of the magnetic field change. As holding frame 500 moves, the positional relationship between semiconductor device B and magnet 502 changes, and the magnitude of the magnetic field detected at that position changes. Thus, the position sensor detects the position of magnet 502 relative to semiconductor device B, i.e., the position of holding frame 500 relative to base 400. The magnetic sensor may also have an electromagnetic conversion element other than a Hall element. The magnetic sensor can be various sensors capable of detecting magnetic fields, such as spin valve-type magnetoresistive effect elements (GMR elements, TMR elements, etc.) whose resistance changes according to changes in the external magnetic field, or combinations of these various sensors. Alternatively, the magnetic sensor may be composed of a sensor element group including multiple magnetic sensor elements.

[0104] The semiconductor device B supplies current to the coil 402 according to the position or orientation of the holding frame 500 relative to the base 400, so as to make the position or orientation of the holding frame 500 the target position or orientation. The semiconductor device B may also be disposed outside the coil 402. Alternatively, the holding frame 500 may include the semiconductor device B and the coil 402, and the base 400 may include a magnet 502.

[0105] By employing the semiconductor device B of this application in the camera module C, the camera module C can be miniaturized. This is because the semiconductor device B (semiconductor elements A1 to A4) disposed around the lens 3 is miniaturized.

[0106] The camera module C of the present invention can be used in a portable terminal M with a built-in camera. Figure 14 The illustration shows a schematic rear view of a portable terminal M equipped with a camera module C. The portable terminal M, for example, uses the camera module C as a rear-mounted camera. The camera module C has an autofocus mechanism and image stabilization. Therefore, the portable terminal M can automatically focus on the subject while optically correcting for camera shake (vibration) during shooting, resulting in images with minimal blur.

[0107] The camera module C of the present invention is not limited to a camera in a portable terminal M, and can also be used for other purposes. For example, the camera module C can be used in a camera mounting device that mounts a vehicle camera module VC. The vehicle camera module VC can be mounted forward on the windshield or rearward on the tailgate. This vehicle camera module VC functions as a rearview monitor, a dashcam, a collision avoidance control system, or an autonomous driving control system.

[0108] The semiconductor elements and devices of the present invention are not limited to the embodiments described above. The technical concept of the present invention is not limited to the material, shape, structure, or arrangement of the constituent components. Various modifications can be made to the technical concept of the present invention within the technical scope defined by the technical solution.

[0109] The semiconductor device of the present invention includes embodiments described in the following notes.

[0110] Postscript 1.

[0111] A semiconductor element (A1) includes multiple terminals (2).

[0112] The semiconductor element (A1) includes a line segment (L1) that overlaps with each of the plurality of terminals (2).

[0113] Multiple terminals (2) are arranged along a first direction (x) of the semiconductor element (A1).

[0114] The plurality of terminals (2) are divided into: a first group (21) in which the center of gravity (G1) is offset toward a second direction (y) that is orthogonal to the first direction (x); and a second group (22) in which the center of gravity (G2) is offset toward the opposite side of the first group (21) based on the line segment (L1).

[0115] Each of the plurality of terminals (2) has a shape in which the dimension (S2) in the second direction (y) is larger than the dimension (S1) in the first direction (x).

[0116] Postscript 2.

[0117] According to the semiconductor element (A1) described in Appendix 1, wherein,

[0118] The terminals (2a-2c) included in the first group (21) have centroids (G1) respectively aligned in the second direction (y).

[0119] The terminals (2d to 2f) included in the second group (22) have centroids (G2) respectively aligned in the second direction (y).

[0120] Postscript 3.

[0121] According to Appendix 1 or 2, the semiconductor element (A1) wherein,

[0122] Two adjacent terminals (2) of the plurality of terminals (2) contain long axes that are parallel to each other.

[0123] Appendix 4.

[0124] The semiconductor element (A1) according to any one of Appendices 1 to 3, wherein,

[0125] The terminals (2a to 2c) included in the first group (21) are alternately arranged with the terminals (2d to 2f) included in the second group (22).

[0126] Postscript 5.

[0127] The semiconductor element (A2) according to any one of Appendices 1 to 4, wherein,

[0128] At least one of the plurality of terminals (2) is a teardrop shape comprising a conical portion toward the line segment (L1).

[0129] Postscript 6.

[0130] The semiconductor element (A1) according to any one of Appendices 1 to 5, wherein,

[0131] Each of the plurality of terminals (2) includes a first region (R1) on the side where the center of gravity (G1, G2) is located, with the line segment (L1) as a reference, and a second region (R2) on the side where the center of gravity (G1, G2) is not located.

[0132] The proportion of the first region (R1) to the second region (R2) is less than 98%.

[0133] Postscript 7.

[0134] The semiconductor device (A3) according to any one of Appendices 1 to 6, wherein,

[0135] At least one of the plurality of terminals (2) is elliptical in shape.

[0136] Postscript 8.

[0137] The semiconductor device (A4) according to any one of Appendices 1 to 6, wherein,

[0138] At least one of the plurality of terminals (2) is polygonal.

[0139] Postscript 9.

[0140] The semiconductor element (A1) according to any one of Appendices 1 to 8 is a wafer-level chip-scale package (WL-CSP).

[0141] Postscript A1.

[0142] The semiconductor element (A1) according to any one of Appendices 1 to 9 comprises:

[0143] Body (11) containing semiconductor layer (112);

[0144] An electrode (12) is located on the third direction (z) side of the body (11) and is in communication with the semiconductor layer (112);

[0145] The first contact layer (421) and the second contact layer (422) are in contact with the electrode (12); and

[0146] A conductive connection component (50) is located on the side opposite to the electrode (12) in the third direction (z), with the first contact layer (421) as a reference, and is conductive to both the first contact layer (421) and the second contact layer (422).

[0147] The first contact layer (421) and the second contact layer (422) are spaced apart from each other in a direction orthogonal to the third direction (z).

[0148] When viewed in the third direction (z), the conductive connection component (50) overlaps with the first contact layer (421) and the second contact layer (422), respectively.

[0149] Postscript A2.

[0150] According to the semiconductor device (A1) described in Appendix A1, wherein,

[0151] One of the plurality of terminals (2) is electrically connected to the conductive connection component (50).

[0152] The conductive connection component (50) is located on the opposite side of the rewiring (41) with reference to the terminal (2).

[0153] The melting point of the conductive connection component (50) is lower than that of the terminal (2).

[0154] Postscript A3.

[0155] According to the semiconductor element (A1) described in appendix A1 or A2, wherein,

[0156] When viewed in the third direction (z), the areas of the first contact layer (421) and the second contact layer (422) are each smaller than the area of ​​the conductive connection component (50).

[0157] Postscript A4.

[0158] According to the semiconductor element (A1) described in Appendix A3, wherein...

[0159] When viewed in the third direction (z), the terminal (2) overlaps entirely with the first contact layer (421) and the second contact layer (422).

[0160] Postscript A5.

[0161] The semiconductor element (A1) according to any one of appendices A1 to A4, wherein,

[0162] The first contact layer (421) and the second contact layer (422) are electrically connected to the electrode (12).

[0163] Note A6.

[0164] The semiconductor element (A1) according to any one of appendices A1 to A5, wherein,

[0165] It also includes a first protective film (30), which is located on the same side as the electrode (12) with the body (11) as a reference, and covers a portion of the electrode (12) and the body (11).

[0166] The first protective film (30) has a first opening (30a) that extends through the third direction (z) and exposes the electrode (12).

[0167] At least a portion of each of the first contact layer (421) and the second contact layer (422) is received in the first opening (30a).

[0168] Postscript A7.

[0169] According to the semiconductor element (A1) described in Appendix A6, wherein,

[0170] The first protective film (30) contains silicon dioxide or silicon nitride.

[0171] Postscript A8.

[0172] The semiconductor device (A1) described in Appendix A6 or A7 also includes:

[0173] A second protective film (31) covering the first protective film (30); and

[0174] A rewiring (41) is provided, which is located in the third direction (z) between the first contact layer (421) and the conductive connection component (50).

[0175] The rewiring (41) is electrically connected to the first contact layer (421), the second contact layer (422), and the conductive connection component (50).

[0176] The second protective film (31) includes a portion sandwiched between the first protective film (30) and the rewiring (41).

[0177] Postscript A9.

[0178] According to the semiconductor element (A1) described in Appendix A8, wherein,

[0179] It also includes a third protective film (32) covering the second protective film (31) and the rewiring (41).

[0180] The third protective film (32) is in contact with the plurality of terminals (2).

[0181] The conductive connection component (50) is exposed from the third protective film (32).

[0182] Postscript 10.

[0183] A semiconductor device (B1) includes: a semiconductor element (A1) as described in any one of Appendices 1 to 9 and Appendices A1 to A9, and an external substrate (7) electrically connected to said semiconductor element (A1).

[0184] The external substrate (7) includes a plurality of pads (72) that are electrically connected to the plurality of terminals (2) respectively.

[0185] Each of the plurality of pads (72) has a different shape than each of the plurality of terminals (2).

[0186] Postscript 11.

[0187] According to the semiconductor device (B1) described in Appendix 10, wherein,

[0188] The distance (D2) in the first direction (x) between two adjacent terminals (2) is greater than the distance (D5) in the first direction (x) between two adjacent pads (72).

[0189] Postscript 12.

[0190] According to Appendix 10 or 11, the semiconductor device (B1) wherein,

[0191] The dimension (S1) of each of the plurality of terminals (2) in the first direction (x) is smaller than the dimension (S3) of each of the plurality of pads (72) in the first direction (x).

[0192] Postscript 13.

[0193] The semiconductor device (B1) according to any one of Appendices 10-12, wherein,

[0194] Each of the plurality of pads (72) is circular.

[0195] Postscript 14.

[0196] The semiconductor device (B1) according to any one of Appendices 10 to 13, wherein,

[0197] The plurality of terminals (2) includes 6 terminals (2a to 2f).

[0198] The plurality of pads (72) includes 6 pads (72a to 72f).

[0199] Postscript 15.

[0200] The semiconductor device (B1) according to any one of Appendices 10 to 14, wherein,

[0201] The centroids (G1, G2) of each of the plurality of terminals (2) overlap with the centroids (Gp) of the plurality of pads (72).

[0202] Postscript 16.

[0203] The semiconductor device (B2, B3) according to any one of Appendices 10 to 14, wherein,

[0204] The centroids (G1, G2) of each of the plurality of terminals (2) do not overlap with the centroids (Gp) of each of the plurality of pads (72).

[0205] Postscript 17.

[0206] The semiconductor device (B4) according to any one of Appendices 10 to 15, wherein,

[0207] Each of the plurality of pads (72) surrounds the periphery of each of the plurality of terminals (2).

[0208] Postscript 18

[0209] The semiconductor device (B1 to B4) according to any one of Appendix 10 to 17.

[0210] It also includes multiple conductive connection components (50).

[0211] The plurality of conductive connection components (50) are located in the third direction z between the plurality of terminals (2) and the plurality of pads (72).

[0212] Postscript 19.

[0213] A camera module (C) is characterized by comprising a semiconductor device (B) as described in any one of Appendices 10 to 18.

[0214] Postscript 20.

[0215] A portable terminal (M) is characterized by comprising the camera module (C) described in Appendix 19.

[0216] Explanation of reference numerals in the attached figures

[0217] A1~A5: Semiconductor components; B: Semiconductor devices

[0218] C: Camera module D1~D6: Interval

[0219] G1, G2, Gp: Center of gravity; L1: Line segment

[0220] M: Portable terminal; R1, R2: Areas; S1~S4: Size

[0221] x: First direction; y: Second direction; z: Third direction

[0222] 10: Wafer section; 11: Main body; 11A: Main surface

[0223] 111: Semiconductor substrate; 112: Semiconductor layer; 12: Electrode

[0224] 121: Connecting surfaces 2, 2a~2f: Terminals

[0225] 21: Group 1 22: Group 2

[0226] 3: Lens 30: First protective film 30a: First opening

[0227] 31: Second protective film; 32: Third protective film; 321: Second opening

[0228] 4: Position detection sensor 41: Rewiring

[0229] 411: Recessed portion 42: Contact layer

[0230] 421: First contact layer; 422: Second contact layer

[0231] 50: Conductive connection component; 7: External substrate

[0232] 71: Substrate body; 72, 72a~72f: Solder pads

[0233] 300: Substrate; 302: Imaging element; 400: Base

[0234] 402: Coil; 500: Holding Frame; 502: Magnet

[0235] 600: Lens unit.

Claims

1. A semiconductor device comprising multiple terminals, characterized in that: The semiconductor element includes a line segment that overlaps with each of the plurality of terminals. The plurality of terminals are arranged along a first direction of the semiconductor element. The plurality of terminals are divided into: a first group whose center of gravity is offset toward a second direction orthogonal to the first direction; and a second group whose center of gravity is offset toward the opposite side of the first group, based on the line segment. Each of the plurality of terminals has a shape in which the dimension in the second direction is larger than the dimension in the first direction.

2. The semiconductor device according to claim 1, characterized in that: The terminals included in the first group have centers of gravity aligned respectively in the second direction. The terminals included in the second group have centers of gravity aligned respectively in the second direction.

3. The semiconductor device according to claim 1, characterized in that: Two adjacent terminals among the plurality of terminals contain long axes that are parallel to each other.

4. The semiconductor device according to claim 1, characterized in that: The terminals included in the first group are arranged alternately with the terminals included in the second group.

5. The semiconductor device according to claim 1, characterized in that: At least one of the plurality of terminals is a teardrop shape comprising a tapered portion facing the line segment.

6. The semiconductor device according to claim 1, characterized in that: Each of the plurality of terminals includes a first region on the side where the center of gravity is located, and a second region on the side where the center of gravity is not located, based on the line segment. The proportion of the first region relative to the second region is less than 98%.

7. A semiconductor device, characterized in that, include: The semiconductor element according to any one of claims 1 to 6; and An external substrate electrically connected to the semiconductor element. The external substrate includes multiple pads that are electrically connected to the plurality of terminals respectively. Each of the plurality of pads has a different shape than each of the plurality of terminals.

8. The semiconductor device according to claim 7, characterized in that: The spacing in the first direction between two adjacent terminals is larger than the spacing in the first direction between two adjacent pads.

9. The semiconductor device according to claim 7, characterized in that: The dimension of each of the plurality of terminals in the first direction is smaller than the dimension of each of the plurality of pads in the first direction.

10. The semiconductor device according to claim 7, characterized in that: Each of the plurality of pads is circular.

11. The semiconductor device according to claim 7, characterized in that: The center of gravity of each of the plurality of terminals overlaps with the center of gravity of the plurality of pads, respectively.

12. The semiconductor device according to claim 7, characterized in that: The center of gravity of each of the plurality of terminals does not overlap with the center of gravity of the plurality of pads.

13. The semiconductor device according to claim 7, characterized in that: Each of the plurality of pads surrounds the periphery of each of the plurality of terminals.

14. A camera module, characterized in that: Includes the semiconductor device as described in claim 8.

Images