A top-mounted heat dissipation gallium nitride device based on TSV interconnection and a preparation method thereof

Abstract

This invention discloses a top-mounted heat-dissipating gallium nitride (GaN) device based on TSV interconnects and its fabrication method, primarily addressing the problems of long heat dissipation paths, high thermal resistance, and severe parasitic effects at high frequencies in existing lateral GaN power devices. The device includes a substrate, a GaN epitaxial layer, a passivation layer, a bonding layer, an insulating layer, a heat dissipation layer, and metal electrodes. A TSV via structure is provided below the electrodes. This structure is obtained by determining the via location on the back side of a thinned substrate and vertically penetrating the substrate and epitaxial layer using a DRIE process. Insulating pads and conductive fillers for electrical isolation are provided on the inner walls of the vias. A UBM (Underground Bracket Microstructure) and a solder ball interconnect layer are sequentially connected to the lower end of the structure. A bottom filler is filled between the substrate and the packaging substrate to achieve low-resistance interconnection with the packaging substrate. This invention enables active heat extraction from the device's operating area and short-path extraction of electrical signals, significantly reducing the device junction temperature and improving power density and reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device packaging and thermal management technology, specifically relating to a top-mounted heat-dissipating gallium nitride device based on TSV interconnect and its fabrication method, mainly used for optimizing the heat dissipation performance of high power density GaN devices. Background Technology

[0002] Gallium nitride (GaN), as a representative of third-generation semiconductor materials, exhibits significant advantages in high-frequency, high-power-density power electronics due to its high critical breakdown electric field, high electron saturation drift velocity, and excellent thermal stability. Lateral GaN devices based on AlGaN / GaN heterojunctions, such as Schottky barrier diodes (SBDs) and high electron mobility transistors (HEMTs), have become key components in high-efficiency power conversion, RF power amplification, and high-density power integrated systems due to their low conduction losses, high switching speeds, and excellent high-temperature operating capabilities.

[0003] However, with the continuous increase in device power density, existing lateral GaN power devices face increasingly severe challenges in packaging and application:

[0004] First, heat dissipation bottlenecks limit the ultimate performance of devices. Currently, most GaN-on-Si power devices in the industry employ traditional bottom-heat dissipation solutions. In this structure, the heat generated by the two-dimensional electron gas (2DEG) channel must penetrate downwards through a heterojunction epitaxial buffer layer several micrometers thick and a silicon substrate hundreds of micrometers thick. Due to the numerous dislocations and lattice mismatches in the epitaxial layer, phonon scattering is severe, resulting in a buffer layer thermal conductivity far lower than that of the bulk material. Combined with the conductive thermal resistance generated by the thick substrate, the path from the heat source to the heat sink is extremely long and has enormous thermal resistance. This high junction-to-environment thermal resistance causes a sharp rise in the device junction temperature, which not only leads to a decrease in mobility and a sharp increase in on-resistance but also seriously threatens the long-term reliability of the device.

[0005] Secondly, parasitic effects from electrical interconnects limit high-frequency applications. Traditional packaging processes commonly use wire bonding to expose electrodes. These metal leads (such as gold wires or aluminum strips) generate significant parasitic inductance during MHz-level high-frequency switching. The presence of parasitic inductance leads to severe voltage overshoot, turn-off ringing, and additional switching losses, forcing the system to reduce its operating frequency to maintain stability, thus negating the high-frequency and high-efficiency advantages that GaN devices should possess.

[0006] Finally, existing packaging solutions struggle to balance electromagnetic shielding with structural compactness. While the industry has experimented with techniques such as flip-chip bonding to reduce inductance, these often create conflicts between thermal management and PCB routing space. Furthermore, exposed high-voltage electrodes generate strong electromagnetic radiation during high-speed switching, increasing the complexity and size of system-level filtering circuits.

[0007] Therefore, how to design a new device structure that can break the substrate thermal resistance limit and achieve efficient near-field heat dissipation, while eliminating lead parasitic inductance and improving high-frequency characteristics, has become a key technical problem to be solved in the current GaN power integration field. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of existing lateral GaN power devices, such as long heat dissipation paths, high thermal resistance, and severe parasitic effects at high frequencies, and to provide a top-mounted heat-dissipating gallium nitride device based on TSV interconnects and its fabrication method. By constructing a near-junction top-mounted heat dissipation structure on the front side of the device and combining it with back-side via vertical interconnect technology, efficient heat dissipation from the device's operating area and short-path extraction of electrical signals are achieved, thereby significantly reducing the device junction temperature, decreasing parasitic parameters, and improving the device's power density and operational reliability.

[0009] To achieve the above objectives, the technical solution of the present invention includes the following:

[0010] A top-mounted heat-dissipating gallium nitride device based on TSV interconnect includes, from bottom to top: a substrate, a GaN epitaxial layer, a passivation layer, a bonding layer, an insulating layer, and a heat dissipation layer. It also includes a front metal electrode that contacts the lower surface of the bonding layer, and a TSV via structure that extends vertically downward to penetrate the substrate layer below the electrode for vertically leading out the electrode.

[0011] The GaN epitaxial layer includes a nucleation layer, a buffer layer, a channel layer, a spacer layer, and a barrier layer;

[0012] The TSV via structure includes an insulating pad located at the via wall and a conductive filler located inside the insulating pad. The insulating pad is used to electrically isolate the conductive filler from the substrate and epitaxial layer at the via wall. The lower end of the TSV via structure is sequentially connected to a bump under metallization layer (UBM) and a solder ball interconnect layer to complete low-resistance interconnection with the packaging substrate. The solder ball interconnect layer adopts a bump structure of copper pillars and SnAg solder. The space between the packaging substrate and the substrate is filled with bottom filler adhesive.

[0013] Furthermore, this invention also proposes a method for fabricating a top-mounted heat-dissipating gallium nitride device based on TSV interconnects, the steps of which are as follows:

[0014] (1) Select a substrate material and grow a core layer, a buffer layer, an undoped GaN channel layer, a spacer layer and an AlGaN barrier layer on its surface in sequence to form a heterojunction structure, namely a GaN epitaxial layer;

[0015] (2) Define the pattern and process the active region of the GaN epitaxial layer, and prepare the front metal electrode of the device; wherein, when preparing the SBD device, form the cathode ohmic electrode and reserve the anode Schottky electrode formation area; when preparing the HEMT device, form the source, drain and gate.

[0016] (3) Deposit SiO2 or SiN by plasma-enhanced chemical vapor deposition (PECVD) x As the first passivation layer, after sputtering a Ti / Cu seed layer on its surface, a bonding layer is formed through a thickening process, which includes at least electroplating, sintering, and welding.

[0017] (4) The front side of the chip obtained in step (3) is fixed on the carrier plate with temporary bonding adhesive, and the back side of the substrate is mechanically ground and polished to complete the substrate thinning process.

[0018] (5) Coat the back of the thinned substrate with photoresist and develop it to define the via location; use deep reactive ion etching (DRIE) to vertically penetrate the substrate and epitaxial layer until the bottom of the front metal electrode is exposed to form a TSV via structure.

[0019] (6) After insulating the hole wall of the TSV via, electroplated copper pillars are used to fill it, and a bump under metallization layer UBM and solder balls are implanted on the back side to form a solder ball interconnect layer.

[0020] (7) After debonding, an insulating and thermally conductive layer is set above the bonding layer on the front side of the chip, and a heat dissipation layer is installed on the side of the insulating and thermally conductive layer away from the chip to form a top heat dissipation structure.

[0021] (8) Align the chip with solder balls with the PCB pads and solder them. Fill the space between the back of the chip and the PCB with bottom filler glue. After curing, complete the device packaging and integration.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] First, this invention abandons the conventional front-side wire bonding in the prior art and leads the electrical circuitry to the back side through TSV, thereby freeing up space on the front side of the chip; the heat dissipation path is directly led upward from the surface of the heterojunction with the largest heat generation through the Cu bonding layer and AlN insulating layer. This "near-field heat dissipation" greatly shortens the heat conduction path, thereby significantly reducing the thermal resistance from the junction to the environment.

[0024] Secondly, due to its extremely high heat dissipation efficiency, the device can operate at a low junction temperature for a long time, avoiding the self-heating effect that causes the junction temperature of the device to rise. This not only suppresses leakage current caused by high temperature, but also ensures current density under high power, effectively improving the breakdown voltage stability of the device.

[0025] Third, this invention introduces an AlN ceramic insulating layer, which has high thermal conductivity and high insulation properties. It not only acts as an efficient thermal bridge but also provides extremely strong vertical withstand voltage, which can protect the Cu heat sink from being charged and greatly improve the integrated safety of the system.

[0026] Fourth, since the TSV vertical interconnect used in this invention is currently the solution with the lowest parasitic inductance, the current passes through the chip vertically, and its path is the shortest; it not only completely eliminates the ringing phenomenon of the switching waveform, but also allows the device to operate at a higher frequency, effectively reducing the size of passive components such as inductors and capacitors in the power supply system, and significantly improving the power density. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the gallium nitride device structure with back-through holes for near-junction heat dissipation according to the present invention;

[0028] Figure 2 This is a schematic diagram of the process flow for fabricating gallium nitride devices with back-through holes for near-junction heat dissipation according to the present invention.

[0029] Figure 3 This is a schematic diagram of the process for manufacturing the bottom solder balls in this invention. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0031] Example 1: Refer to Appendix Figure 1 The present invention proposes a top-mounted heat-dissipating gallium nitride device based on TSV interconnect, which includes, from bottom to top: a substrate 8, a GaN epitaxial layer 6, a passivation layer 4, a bonding layer 3, an insulating layer 2 and a heat dissipation layer 1, and also includes a front metal electrode 5 in contact with the lower surface of the bonding layer, and a TSV via structure 7 is provided below the electrode, which extends vertically downward to penetrate the substrate layer, for vertically leading out the electrode.

[0032] The GaN epitaxial layer 6 includes a nucleation layer, a buffer layer, a channel layer, a spacer layer, and a barrier layer;

[0033] The TSV via structure 7 includes an insulating pad located at the via wall and a conductive filler located inside the insulating pad. The insulating pad is used to electrically isolate the conductive filler from the substrate and epitaxial layer at the via wall. The lower end of the TSV via structure is sequentially connected to a bump under metallization layer (UBM) and a solder ball interconnect layer 9 to complete low-resistance interconnection with the packaging substrate. The solder ball interconnect layer adopts a bump structure of copper pillars and SnAg solder. The space between the packaging substrate and the substrate is filled with bottom filler adhesive.

[0034] In this embodiment, the substrate is made of semi-insulating SiC or high-resistivity Si with a thickness of 50-200 μm; the nucleation layer is made of AlN with a thickness of 20-200 nm; the buffer layer is made of GaN, AlN, or AlGaN with a thickness of 0.1-5 μm; the channel layer is made of intrinsic GaN with a thickness of 50-1000 nm; the spacer layer is made of AlN with a thickness of 1-5 nm; the barrier layer is made of AlGaN with a thickness of 10-30 nm; and the passivation layer is made of SiO2. 2. The bonding layer is any one of Si3N4 or Al2O3, with a thickness of 50~200nm; the bonding layer is one or more combinations of Ti / Cu, Ti / Au, Cu, Au, Cu-Sn bonding layer, and sintered silver bonding layer, with a thickness of 1~50μm; the insulating layer is any one of AlN ceramic, Al2O3 ceramic, or Si3N4 ceramic, with a thickness of 0.2~1mm; the heat dissipation layer is any one of copper alloy, aluminum alloy, high thermal conductivity pure metal, or high thermal conductivity ceramic, with a thickness of 0.1~10mm.

[0035] Depending on the device type and design requirements, in this embodiment, the front metal electrode is formed into a two-terminal device structure or a three-terminal device structure; wherein, when the device is a Schottky barrier diode (SBD), the front metal electrode includes an anode Schottky electrode and a cathode Ohm electrode; when the device is a high electron mobility transistor (HEMT), the front metal electrode includes a source, a drain, and a gate.

[0036] When the device is a Schottky barrier diode (SBD), the cathode ohmic electrode forms an ohmic contact with the cathode contact region on the surface of the GaN epitaxial layer; the anode region has an anode groove structure, and the anode Schottky electrode is disposed at the anode groove structure and forms a Schottky contact with the exposed GaN epitaxial layer thereon; the cathode ohmic electrode adopts a Ti / Al / Ni / Au metal stack with a thickness of 50~100nm / 200~500nm / 50~100nm / 50~100nm, and the anode Schottky electrode adopts a Ni / Au or Pt / Au metal stack with a thickness of 30~50nm / 100~200nm.

[0037] When the device is a high electron mobility transistor (HEMT), the source and drain are disposed on the surface of the GaN epitaxial layer and form an ohmic contact. The gate is located between the source and drain and is disposed correspondingly to the barrier layer to control the channel turn-on and turn-off. The source and drain are made of Ti / Al / Ni / Au metal stack, and the gate is made of Ni / Au metal stack to form a gate Schottky contact.

[0038] The aforementioned packaging substrate layer is any one of a PCB substrate, a ceramic substrate, or a metal core substrate, and its thickness is 0.5~5mm; the ceramic substrate includes AlN and SiC substrates, and the metal core substrate includes copper core and aluminum core substrates.

[0039] The aforementioned TSV through-hole structure vertically penetrates the GaN epitaxial layer and the thinned substrate, with a hole size of 30~100μm; and a SiO2 insulating pad with a thickness of 1μm is deposited on the inner wall of the TSV.

[0040] The copper pillars in the above-mentioned solder ball interconnect layer have a diameter of 50~200μm and a height of 20~100μm, and the SnAg solder thickness is 10~50μm; the bottom filler is an epoxy resin-based bottom filler, and the filling thickness is consistent with the total height of the solder ball interconnect layer, which is 30~150μm.

[0041] Example 2: Refer to Figure 2 This invention proposes a method for fabricating a top-mounted heat-dissipating gallium nitride device based on TSV interconnect, specifically including the following steps:

[0042] Step 1) Select a substrate material and grow a core layer, a buffer layer, an undoped GaN channel layer, a spacer layer and an AlGaN barrier layer on its surface in sequence to form a heterojunction structure, namely a GaN epitaxial layer.

[0043] Step 2) Define the pattern and process the active region of the GaN epitaxial layer, and fabricate the front metal electrode of the device; wherein, when fabricating an SBD device, a cathode ohmic electrode is formed and a region for forming an anode Schottky electrode is reserved; when fabricating a HEMT device, the source, drain and gate are formed.

[0044] Step 3) Deposit SiO2 or SiN by plasma-enhanced chemical vapor deposition (PECVD) xAs the first passivation layer, after a Ti / Cu seed layer is sputtered on its surface, a bonding layer is formed through a thickening process, which includes at least electroplating, sintering, and welding. In this embodiment, the first passivation layer is a passivation dielectric layer formed on the surface of the GaN epitaxial layer and the front metal electrode; the layer adopts any one of SiO2, Si3N4 or Al2O3, and the thickness is 50nm~200nm; after depositing the first passivation layer, a contact window is formed above the predetermined connection area of ​​the front metal electrode by photolithography and dry etching; when the device is an SBD, the contact window is disposed above at least one of the cathode ohmic electrode and the reserved anode Schottky electrode formation area, and after opening the anode area, an anode groove structure is formed by ICP etching, and then a Ni / Au metal layer is deposited to form the anode Schottky electrode; when the device is a HEMT, the contact window is disposed above at least one of the source, drain and gate; the thickness of the Ti layer in the Ti / Cu seed layer is 20nm~50nm, the thickness of the Cu layer is 100nm~300nm; the thickness of the bonding layer is 1μm~50μm.

[0045] Step 4) Fix the front side of the chip obtained in Step 3) onto the carrier plate with temporary bonding adhesive, and mechanically grind and polish the back side of the substrate to complete the substrate thinning process;

[0046] Step 5) Coat the back of the thinned substrate with photoresist and develop it to define the via location; use deep reactive ion etching (DRIE) to vertically penetrate the substrate and epitaxial layer until the bottom of the front metal electrode is exposed to form a TSV via structure.

[0047] Step 6) After insulating the walls of the TSV vias, copper pillars are electroplated for filling, and a metallized under bump (UBM) layer and solder balls are implanted on the back side to form a solder ball interconnect layer. In this embodiment, the insulation treatment of the TSV via walls specifically involves depositing SiO2 or SiN on the inner wall of the TSV via using PECVD. x An insulating layer is formed, and the insulating layer at the bottom of the hole is removed by anisotropic etching, while the insulating layer on the hole wall is retained. Subsequently, a copper filler is formed in the TSV via by electroplating. A Ti / Ni / Au stacked UBM layer is prepared at the exit of the TSV via on the back side, wherein the thickness of the Ti layer is 50nm~100nm, the thickness of the Ni layer is 1μm~3μm, and the thickness of the Au layer is 50nm~200nm. The solder ball interconnect layer is a bump structure formed by copper pillars and SnAg solder, and the diameter of the bump is 100μm~500μm.

[0048] Step 7) After debonding, an insulating and thermally conductive layer is placed above the bonding layer on the front side of the chip, and a heat dissipation layer is installed on the side of the insulating and thermally conductive layer away from the chip to form a top-mounted heat dissipation structure. In this embodiment, the thermal interface material is one of thermally conductive silicone grease, graphene thermally conductive film, nano-silver paste, or Cu-Sn bonding material; the insulating and thermally conductive layer is a double-sided metallized AlN ceramic sheet with a thickness of 0.2mm to 1mm; the heat dissipation layer is a finned Cu heat sink or a water-cooled plate, and is fixed to the side of the insulating and thermally conductive layer away from the chip by welding, sintering, or pressing.

[0049] Step 8) Align the chip with solder balls with the PCB pads and solder them. Fill the space between the back of the chip and the PCB with underfill adhesive. After curing, the device packaging and integration are completed.

[0050] Example 3: Refer to Figure 1-3 The overall structure of the device proposed in this embodiment is the same as that in Embodiment 1, and its preparation method is the same as that in Embodiment 2. Now, given the relevant materials and specific parameters, the specific implementation process of preparing the device using the present invention will be described in further detail:

[0051] Reference Figure 1 The device provided in this embodiment includes a copper heat sink 1, an insulating layer 2, a bonding layer 3, a passivation layer 4, a front metal electrode 5, a GaN epitaxial layer 6, a TSV via structure 7, a substrate layer 8, and a solder ball interconnect layer 9. Wherein:

[0052] The bonding layer 3 is a Ti / Cu or Ti / Au metal stack layer formed by sputtering or electroplating processes, with a thickness of 1μm-10μm, and is located on the front metal electrode 5.

[0053] The front metal electrode 5 can be a two-terminal device structure or a three-terminal device structure depending on the device type; when the device is an SBD, the front metal electrode 5 includes an anode Schottky electrode and a cathode Ohm electrode; when the device is a HEMT, the front metal electrode 5 includes a source, a drain and a gate, which are located on the GaN epitaxial layer 6.

[0054] The GaN epitaxial layer 6 comprises, from bottom to top, a nucleation layer, a buffer layer, an undoped GaN channel layer, a spacer layer, and an AlGaN barrier layer, and is located above the substrate layer 8.

[0055] The TSV through-hole structure 7 has an inner wall covered with a hole wall insulating liner with a thickness of 1μm, and a center filled with an electroplated copper pillar that penetrates the Si substrate and GaN buffer layer and is electrically connected to the bottom of the corresponding front metal electrode.

[0056] The substrate layer 8 is made of high-resistivity silicon (Si) or silicon carbide (SiC), and its thickness is reduced to 100μm~200μm by mechanical grinding.

[0057] Reference Figure 2-3 This embodiment provides three specific implementation methods. Unless otherwise specified, the experimental methods described are conventional methods, and the reagents and materials described are commercially available unless otherwise specified.

[0058] Method 1: A high-efficiency GaN Schottky barrier diode (SBD) with vertical conductivity and top heat dissipation characteristics was fabricated on a Si(111) substrate by MOCVD epitaxial growth, DRIE deep silicon etching and 3D wafer-level packaging technology.

[0059] Step 1: Heterojunction epitaxial growth, constructing the core electrical structure on the substrate using MOCVD, such as... Figure 2 (a) in the middle.

[0060] 1.1) Substrate preparation:

[0061] A 6-inch Si(111) substrate with a thickness of approximately 625 μm and a resistivity ρ > 1000 Ω·cm was selected. First, standard RCA cleaning was performed, followed by in-situ baking at 1050°C in an H2 atmosphere for 10 minutes in the MOCVD reaction chamber to remove the surface oxide layer.

[0062] 1.2) AlN nucleation layer growth:

[0063] At 1000-1100℃, TMAl and NH3 are introduced to grow a 200nm AlN nucleation layer, which serves as a dislocation barrier layer for subsequent growth.

[0064] 1.3) Stepped buffer layer:

[0065] Three AlGaN buffer layers were grown sequentially, with Al compositions of 70%, 40%, and 15%, respectively, each layer approximately 1 μm thick. The compensation doping concentration was achieved to 1 × 10⁻⁶ C₃H₈. 18 cm -3 To improve the longitudinal breakdown field strength;

[0066] 1.4) Active layer growth:

[0067] A 150 nm intrinsic GaN channel layer (i-GaN) was grown; a 1 nm AlN spacer layer was grown to effectively reduce alloy scattering and improve the 2DEG mobility to 1800 cm⁻¹. 2 / V·s or more; growing 25nm Al 0.25 Ga 0.75 N-barrier layer.

[0068] Step 2: Mesa isolation and electrode formation. In this stage, device boundaries are defined and electrical connections are established through plasma etching, such as... Figure 2(b) in the middle.

[0069] 2.1) ICP mesa etching: Photoresist was used as a mask, and dry etching was performed using an ICP etching machine. The Cl2 / BCl3 flow ratio was 30 / 10 sccm, the bias power was 50W, and the etching depth was 350nm to ensure complete cut-off of the 2DEG in the isolation region;

[0070] 2.2) Cathode Ohmic Contact: Ti / Al / Ni / Au (20 / 120 / 40 / 50 nm) was continuously deposited using electron beam evaporation (E-beam). It was then placed in a rapid thermal annealing (RTA) furnace and annealed at 850 °C for 30 seconds in a N2 environment to form a low specific contact resistance (ρ). c <1×10 -5 Ω·cm 2 Ohmic contact;

[0071] 2.3) Reserved anode formation area: Define the shape of the anode area and reserve the area for the subsequent anode Schottky electrode formation, so as to provide a process basis for the subsequent passivation layer opening, anode groove structure formation and anode metal deposition.

[0072] Step 3: Passivation and front thermal coupling preparation. This stage prepares the physical interface for the top-mounted heatsink, such as... Figure 2 (c) in the middle.

[0073] 3.1) Passivation layer deposition: A 100 nm SiO2 protective layer was deposited using PECVD at 300 °C. This layer needs to have extremely high density to reduce the influence of surface states and provide a dielectric basis for subsequent front-side interconnects and heat dissipation layer integration;

[0074] 3.2) Contact window etching and anode formation: Dry etching is performed using CHF3 gas to form a contact window above the predetermined connection area of ​​the cathode ohmic electrode and the reserved anode Schottky electrode formation area; after opening the anode area, an anode groove structure is formed by ICP etching, and then a Ni / Au (50 / 150nm) metal layer is deposited to form the anode Schottky electrode. The Schottky barrier height is optimized by controlling the annealing temperature to balance the on-state voltage and reverse leakage current.

[0075] 3.3) Heat dissipation seed layer: A Ti (30nm) / Cu (200nm) layer is deposited over the entire wafer using magnetron sputtering. The Ti layer is used to enhance adhesion, and the Cu layer provides the substrate for electroplating.

[0076] Step 4: Temporary bonding support. This stage is to provide mechanical rigidity for subsequent backside thinning, such as... Figure 2 (d) in the middle.

[0077] 4.1) Temporary bonding adhesive coating: Temporary bonding adhesive (60μm thickness) from brands such as BrewerScience is spin-coated onto the front side of the chip, and the gas is vented through multi-step heating;

[0078] 4.2) Carrier bonding: A 1mm thick Si carrier wafer is pressed onto the front side of the chip in a vacuum bonding machine, applying a pressure of 1500N and holding at 200℃ for 20 minutes.

[0079] Step 5: Backside thinning and TSV core etching, this is key to achieving vertical electrode placement, such as... Figure 2 (e) in the middle.

[0080] 5.1) Backside mechanical thinning: The original 625μm Si substrate was coarsely ground to 180μm using a grinding wheel, followed by CMP fine grinding with a 0.1μm particle size polishing slurry to achieve a final substrate thickness of 150μm. 5μm;

[0081] 5.2) TSV Deep Silicon Etching: Bosch process (DRIE) is used. Straight holes with a diameter of 50 μm are etched on the back side of the substrate by continuously cycling SF6 etching pulses and C4F8 passivation pulses. When etching reaches the GaN interface, the process switches to Cl2-dominated mode until the front metal bottom surface is fully exposed.

[0082] Step 6: TSV metallization and ball-mounting, such as Figure 2 (f) and Figure 3 As shown.

[0083] 6.1) Lateral insulation of the via walls: A 1 μm layer of SiO2 was deposited using low-temperature PECVD. The insulating layer at the bottom of the via was removed by anisotropic reactive ion etching (RIE), while the insulation of the via walls was preserved to prevent leakage to the substrate;

[0084] 6.2) TSV Copper Filling: An acidic copper sulfate plating solution is used. A low-current pre-plating process is performed for 5 minutes to ensure coverage, followed by increasing the current density (e.g., 2 A / dm³). 2 Complete the filling of the solid copper pillar;

[0085] 6.3) Ball-mounting process: Deposit Ti / Ni / Au (50 / 300 / 50nm) as UBM layer on the back outlet of TSV; then form a bump structure composed of copper pillars and SnAg solder, wherein the copper pillars have a diameter of 150μm, and the solder is reflow soldered to form a stable back interconnect electrode.

[0086] Step 7: Debond and integrate with the top-mounted heat dissipation system, such as Figure 2 (g) in the middle.

[0087] 7.1) Laser debonding: Use ultraviolet laser to penetrate the substrate (if it is glass) or remove the front support by thermal sliding (if it is silicon substrate), and then use acetone to ultrasonically clean the residual adhesive.

[0088] 7.2) Thickening of the front Cu bonding layer: Local electroplating is performed on the seed layer in step 3 to make the front copper layer thickness reach 10μm, which serves as a high-efficiency thermal spreading layer;

[0089] 7.3) AlN thermal bridge installation: A 30 μm thick nano-silver paste is printed on the Cu bonding layer. A double-sided metallized AlN ceramic sheet (200 μm thick) is placed on top and sintered without pressure at 260 °C to form atomic-level thermal contact;

[0090] 7.4) Copper heat sink fixing: A copper heat sink with a finned structure is installed on the top layer of AlN by welding or threaded pressing;

[0091] Step 8: Populate and integrate with the system, such as Figure 2 (h) in the middle.

[0092] 8.1) Underfill: As shown in Figure (h), a high thermal conductivity epoxy resin filler is injected between the back of the chip and the PCB. This material is doped with 50% by volume micron-sized Al2O3 particles, and has a thermal conductivity >2.0 W / m·K;

[0093] 8.2) SMT Placement: Place the module with the top heat sink on the PCB pads and perform the final SMT reflow soldering.

[0094] Method 2: The heat dissipation structure adopts an integrated silicon-based micro-channel cold plate to meet the liquid cooling requirements of higher power density.

[0095] Step 1: Growth of high-performance heterojunction GaN epitaxial layer 6. To further improve thermal conductivity, a substrate material with higher thermal conductivity is selected, such as... Figure 2 (a) in the middle.

[0096] A 6-inch, 500μm thick 4H-SiC substrate was selected. After RCA standard cleaning, it was placed in an MOCVD reaction chamber and baked in situ at 1100℃ for 15 minutes in an H2 atmosphere to remove the surface oxide layer.

[0097] The temperature was set to 700℃, the pressure to 100mbar, NH3 and TMAl were introduced, the flow rate ratio was set to 2000, and an AlN nucleation layer with a thickness of 100nm was grown.

[0098] The temperature was increased to 1050℃, the pressure was 150mbar, NH3 and TMGa were introduced at a flow rate ratio of 2000, and a GaN buffer layer with a thickness of 2μm was grown.

[0099] Growth of a 200nm intrinsic GaN channel layer (i-GaN); growth of a 2nm AlN spacer layer; growth of a 25nm Al... 0.25 Ga 0.75 N-barrier layer, process conditions: temperature 1000℃, pressure 100mbar, NH3 / TMGa flow rate ratio 1500, TMGa / TMAl flow rate ratio 10.

[0100] Step Two: Mesa Isolation and Front Metal Electrode 5 Fabrication. After the GaN epitaxial layer 6 is grown, the active region, conductive path, and auxiliary isolation structure of the device are defined using high-precision subtractive and additive manufacturing processes, such as... Figure 2 (b) in the middle.

[0101] A 1.5 μm thick positive photoresist was spin-coated onto the surface of GaN epitaxial layer 6. After pre-baking at 110°C for 60 seconds, the pattern was transferred using a stepper exposure machine.

[0102] The reaction gases were set with Cl2 flow rate at 30 sccm and BCl3 flow rate at 10 sccm. The ICP source power was set to 500W to generate high-density ions, and the bias power was set to 60W to precisely control the etching rate and ion bombardment damage. The chamber pressure was maintained at 5 mTorr, and the etching rate was controlled at approximately 100 nm / min. The etching depth was set to 300 nm to ensure penetration through the 2DEG interface into the high-resistivity GaN buffer layer. After etching, the process was verified using a mesa staircase analyzer, and the mesa edge tilt angle was maintained between 45° and 60° to facilitate subsequent passivation layer coverage.

[0103] Based on this, the fabrication of the front metal electrode 5 began. First, the cathode region was immersed in a 1:10 HCl:H₂O solution for 30 seconds to remove surface oxides. Then, electron beam evaporation (E-beam) was performed under a vacuum better than 2 × 10⁻⁶. -4 A Ti / Al / Ni / Au (20nm / 120nm / 40nm / 50nm) metal stack layer was deposited under Pa. After deposition, the sample was placed in a rapid thermal annealing (RTA) furnace and subjected to a high-temperature treatment at 850℃ for 30 seconds in a pure N2 atmosphere to form an ohmic contact with low specific contact resistance. Subsequently, the anode region was patterned and a region for the formation of the anode Schottky electrode was reserved.

[0104] To further enhance the device's breakdown voltage characteristics and suppress edge leakage current, an ion implantation process was subsequently introduced. In this embodiment, N-ion implantation was employed. +(Nitrogen ions) were implanted using a dual-energy gradient. The first-stage implantation energy was set at 60 keV, followed by a second-stage implantation at 120 keV, with the total implanted dose controlled at 5 × 10⁻⁶. 13 cm -2 ~1×10 14 cm -2 To avoid lattice channel effects, the implantation beam is tilted at a 7° angle to the sample normal. After implantation, the sample is treated in an oxygen plasma ashing machine for 10 minutes to thoroughly remove the photoresist mask deformed by ion bombardment using high-energy oxygen free radicals. Finally, ultrasonic cleaning with acetone and isopropanol is performed to ensure the cleanliness of the front metal electrode 5 and the active area surface. This series of sequential subtractive and additive processes lays a solid physical foundation for the subsequent deposition of passivation layer 4 and the integration of heat dissipation layer 1.

[0105] Step 3: After completing the fabrication and ion implantation isolation process of the front metal electrode 5, the next crucial stage is the deposition of the passivation layer 4 and the construction of the front thermal coupling interface. This provides a highly thermally conductive and insulating physical interface for the subsequent integration of the heat dissipation layer 1. Figure 2 (c) in the middle.

[0106] A 100 nm thick Si3N4 passivation layer 4 was deposited on the sample surface using plasma-enhanced chemical vapor deposition (PECVD). In this step, the reaction chamber temperature was set to 300 °C, the pressure was maintained at 120 Pa, and deposition was performed by introducing a mixed gas of SiH4 at a flow rate of 20 sccm and NH3 at a flow rate of 10 sccm, while 300 W of radio frequency power was applied. Since Si3N4 has a higher thermal conductivity than traditional silicon dioxide, this effectively reduces the interfacial thermal resistance. Simultaneously, its high density provides chemical protection to the active region of the GaN epitaxial layer 6, preventing contamination from subsequent metal deposition.

[0107] Subsequently, the electrode lead-out window was defined by photolithography, and dry anisotropic etching was performed with CHF3 at 40 sccm to form a contact window above the predetermined connection area of ​​the front metal electrode 5. After opening the anode region, an anode groove structure was formed by ICP etching, and then Ni / Au metal layers with thicknesses of 50 nm and 150 nm were deposited to form the anode Schottky electrode. After annealing at 400°C for 5 minutes, the ideal factor of the Schottky barrier was optimized. After cleaning, a 1 μm thick AlN insulating layer was deposited over the passivation layer by magnetron sputtering, utilizing its excellent thermal conductivity as a thermal bridge between the active heat source and the cooling system.

[0108] A 50 nm Ti and a 300 nm Au seed layer were sequentially magnetron sputtered onto an AlN insulating layer, and then the Au layer was thickened to 3 μm by electroplating to form a highly dense bonding layer. This gold layer can be used for gold-gold thermo-pressed eutectic bonding with the heat dissipation layer, and can also spread heat laterally, ultimately completing the construction of a front thermal coupling interface with high thermal conductivity, strong insulation and high mechanical strength, providing a solid physical support for the device's electrothermal decoupling architecture.

[0109] Step 4: Temporary bonding support. Spin-coat a 60μm thick layer of heat-release temporary bonding adhesive onto the front side of the chip. Press it onto a 1.5mm thick sapphire substrate at 200℃, applying 1500N of pressure for 20 minutes. Figure 2 (d) in the middle.

[0110] Step 5: Substrate layer 8 thinning and TSV via structure 7 etching, as shown Figure 2 (e) in the middle.

[0111] The substrate layer 8 is subjected to back-side mechanical thinning and chemical mechanical polishing. A high-power inductively coupled plasma (ICP) dry etching process is used to etch TSV via structure 7 on the back side of the substrate layer 8, realizing a vertical conductive path from the front metal electrode 5 to the back side of the substrate, providing a structural basis for vertical electrostatic attraction.

[0112] The 4H-SiC substrate 8 was mechanically rough-ground on the back side using a diamond grinding wheel to reduce the thickness to 130 μm. Then, CMP chemical mechanical polishing was performed using a polishing slurry with a particle size of 0.1 μm to fix the final thickness of the substrate 8 at 120±5 μm, ensuring the uniformity of the substrate thickness.

[0113] A high-power inductively coupled plasma (ICP) dry etching process was used to etch TSV via structures 7 on the back side of substrate layer 8. SF6 (100-200 sccm) and O2 (10-30 sccm) were used as the main reactant gases. The ICP source power was set to 1500W-2500W to maintain high-density plasma, and the bias power was set to 200W-400W to provide sufficient ion bombardment energy. Straight holes with a diameter of 40μm were etched under a low-pressure environment of 5-15mTorr. When the etching signal was detected to be close to the GaN epitaxial interface, the reactant gases were switched to an etching process dominated by Cl2 (30-50 sccm) and BCl3 (10-20 sccm) until the via completely penetrated the substrate layer 8 and the GaN epitaxial layer 6, accurately exposing the metal bottom surface of the front metal electrode 5, thus completing the etching of the TSV via structure 7.

[0114] Step Six: Metallization of TSV Through-Hole Structure 7 and Implantation of Solder Balls 9, as shown Figure 2 (f) in the middle.

[0115] The TSV via structure 7 is insulated and filled with metal. A UBM layer is prepared on the back side of the substrate layer 8 and solder balls 9 are implanted to achieve low-resistance and low-parasitic-inductance interconnection between the device and the PCB substrate.

[0116] The TSV via structure 7 is insulated and filled with metal. A 1μm thick SiO2 layer is deposited on the inner wall of the TSV via structure 7 as an insulating pad using a low-temperature PECVD process. The insulating layer at the bottom of the via is removed by anisotropic RIE etching, while the insulation of the via wall is retained to prevent leakage. Subsequently, an acidic copper sulfate electroplating solution is used. A low current is first used for pre-plating for 5 minutes to ensure the copper layer coverage of the via wall, and then the current density is adjusted to 2A / dm. 2 Complete the filling of the solid copper pillar inside the TSV through-hole structure 7 to form a vertical conductive path;

[0117] On the back side of substrate layer 8, at the copper pillar exit of TSV via structure 7, a Ti / Ni / Au (50 / 300 / 50nm) metal stack is deposited by electron beam evaporation as a UBM (Under Bump Metallization) layer to improve solder ball adhesion and electrical conductivity. SAC305 solder balls 9 with a diameter of 150μm are placed on the UBM layer using a ball-mounting machine. The sample is then sent to a reflow oven, where the solder balls 9 are soldered at a peak temperature of 250℃ to form a stable back electrode.

[0118] Step 7: Integration and bonding of heat dissipation layer 1, such as... Figure 2 (g) in the middle.

[0119] After heating to the softening point of the adhesive, the chip is debonded by sliding to release the temporary bond between the chip and the substrate. Then, the front side of the chip is ultrasonically cleaned with acetone to remove the residual temporary bonding adhesive and ensure that the surface of the bonding layer 3 is clean.

[0120] A high thermal conductivity silicon wafer was selected as the substrate, and a microchannel array was etched on the surface of the silicon wafer using the DRIE etching process. The microchannel trenches were 50μm wide and 200μm deep. A Ti / Au metal stack was then magnetron sputtered on the chip mating surface of the heat dissipation layer 1 to complete the processing of the heat dissipation layer 1.

[0121] The processed microchannel heat dissipation layer 1 is precisely aligned with the bonding layer 3 on the front side of the chip and placed in a high-pressure bonding machine. It is kept at 300℃ and 12MPa pressure for 40 minutes to complete the gold-gold eutectic bonding between the heat dissipation layer 1 and the bonding layer 3, thereby achieving efficient thermal coupling between the heat source and the liquid cooling heat sink.

[0122] Step 8: Perform bottom filling protection on the device, complete the mounting to the PCB substrate, and build a liquid cooling circulation system for heat dissipation layer 1 to achieve full system-wide packaging integration of the device, such as... Figure 2 (h) in the middle.

[0123] Align the back of the chip with solder balls 9 with the pads on the PCB substrate for SMT mounting; then inject high thermal conductivity epoxy resin doped with 50% volume ratio of micron-sized Al2O3 particles as a bottom filler in the gap between the chip substrate layer 8 and the PCB substrate. Its thermal conductivity is >2.0W / m·K, which improves the mechanical reliability and moisture and dust resistance of the device.

[0124] A high-precision microfluidic metal interface is installed at the microchannel inlet and outlet of the heat dissipation layer 1. The heat dissipation layer 1 is connected to the micro liquid cooling pump and the heat dissipation radiator through pipelines to build a closed microchannel liquid cooling circulation system and realize active liquid cooling heat dissipation.

[0125] Method 3: A vertically led AlGaN / GaN HEMT device with an integrated array thermoelectric cooling module was fabricated on a semi-insulating 4H-SiC substrate to achieve electrothermal synergistic enhancement of active cooling and near-junction heat dissipation, which is suitable for the extreme heat dissipation and high-frequency application requirements of ultra-high power density RF and power HEMT devices.

[0126] Step A: Front-side epitaxy and electrode fabrication. An AlGaN / GaN HEMT heterojunction epitaxial layer is grown on the surface of a semi-insulating 4H-SiC substrate using MOCVD technology to construct the core electrical structure.

[0127] A 6-inch 4H-SiC substrate with a thickness of 500μm was selected;

[0128] A1) A 6-inch semi-insulating 4H-SiC substrate with an initial thickness of 500 μm and resistivity ρ > 1 × 10⁻⁶ is selected. 14 Ω·cm. After RCA standard cleaning to remove surface impurities and oxides, it is placed in the MOCVD reaction chamber and baked in situ at 1150℃ for 20 minutes in an H2 atmosphere to further remove residual oxide layer on the surface and improve the adhesion between the epitaxial layer and the substrate.

[0129] A2) The GaN epitaxial layers are grown sequentially using MOCVD: a 100 nm thick AlN nucleation layer; a 500 nm thick undoped GaN channel layer; and a 25 nm thick AlN nucleation layer. 0.25 Ga 0.75 The N-barrier layer forms a two-dimensional electron gas (2DEG) channel at the interface.

[0130] Temperature: 1050℃

[0131] Pressure: 100 mbar

[0132] NH3 to TMAl flow rate ratio: 2000:1

[0133] Growth time: 15 min;

[0134] A3) A Ti / Al / Ni / Au metal stack is deposited using electron beam evaporation and then rapidly thermally annealed to form source-drain ohmic contacts for constructing the conductive electrodes of the device.

[0135] Vacuum degree: better than 2×10 -4 Pa

[0136] Annealing atmosphere: pure N2

[0137] Annealing temperature: 850℃

[0138] Annealing time: 30s;

[0139] A4) Electron beam lithography is used to define a T-shaped gate region with a gate length of 0.15 μm. Ni / Au metal stacks are deposited by electron beam evaporation to form gate Schottky contacts, thus completing the fabrication of the front metal electrode of the HEMT device.

[0140] Step B: A 100nm thick high-density Si3N4 layer is deposited on the front side of the chip using PECVD process to suppress the current collapse effect on the device surface. This is combined with spin-coated laser-released temporary bonding adhesive and sapphire substrate to complete vacuum bonding, providing rigid mechanical support for subsequent high aspect ratio via etching and ultra-thin substrate processing on the back side.

[0141] B1) A 100nm thick, highly dense Si3N4 passivation layer was continuously deposited using PECVD. This layer not only serves as an electrical isolation substrate for subsequent thermoelectric modules but also effectively neutralizes GaN surface states, suppresses the current collapse effect unique to HEMT devices, and improves the RF power stability of the device. The process conditions are as follows:

[0142] Temperature: 300℃

[0143] Pressure: 120 mbar

[0144] The flow rate ratio of SiH4 to NH3 is 2:1.

[0145] RF power: 300W;

[0146] B2) A laser-release temporary bonding adhesive with high thermal stability is spin-coated onto the front side of the device. The device is then pressed onto a 1.5mm thick sapphire substrate using a precision alignment system. The high light transmittance of sapphire provides an optical pathway for subsequent laser debonding and also provides rigid mechanical support during the back-side thinning process.

[0147] Spin coating speed: 3000 rpm

[0148] Spin coating time: 30s

[0149] Heating and exhaust: 60℃ / 10min → 100℃ / 10min → 150℃ / 10min

[0150] Bonding temperature: 200℃

[0151] Bonding pressure: 0.2 MPa

[0152] Vacuum degree: 1×10 -3 Pa

[0153] Insulation and pressure holding time: 25 minutes;

[0154] Step C: The thickness of the 4H-SiC substrate is precisely reduced to 100μm using mechanical grinding and chemical mechanical polishing (CMP) to significantly reduce the bulk thermal resistance. Then, a high-power ICP plasma dry etching process is used to vertically penetrate the substrate from the back side and precisely stop at the bottom of the source metal on the front side to form a high aspect ratio TSV blind via for reducing parasitic inductance.

[0155] C1) The SiC substrate was mechanically ground on the back side, followed by CMP polishing with a polishing slurry containing diamond particles. The substrate was thinned to about 100 μm to balance the mechanical strength and thermal conductivity of the device, laying the foundation for building an ultra-short vertical electrical path.

[0156] C2) Using the source metal as an etching stop layer, a high-power ICP-RIE etching technique is employed to vertically penetrate the SiC substrate from the back side. A real-time endpoint detection system (EPD) monitors spectral changes to ensure precise etching stop at the bottom surface of the source metal, forming a high aspect ratio TSV blind via. The etching parameters are as follows:

[0157] Reaction gases: SF6 / O2

[0158] ICP source power: 2000W

[0159] Bias power: 300W

[0160] Cavity pressure: 5~15 mTorr;

[0161] Step D: A Ti / Cu seed layer is deposited on the inner wall of the TSV blind via and a solid copper pillar is filled using a high aspect ratio electroplating process to achieve vertical extraction of the source signal and significantly reduce parasitic inductance. Finally, the sapphire substrate is safely removed using 355nm ultraviolet laser debonding technology, and chemical cleaning is used to ensure that the surface of the insulating layer reaches molecular-level cleanliness.

[0162] D1) A Ti adhesion layer and a Cu seed layer are sequentially sputtered into the hole. A high aspect ratio electroplating process is used to fill the solid copper pillar, achieving direct vertical outgoing of the source signal from the front to the back. Compared to traditional gold wire bonding, this vertical path significantly reduces the source negative feedback inductance. The electroplating process conditions are as follows:

[0163] Pre-plating current density: 0.5A / dm 2

[0164] Pre-plating time: 8 min

[0165] Formal electroplating current density: 2.5 A / dm 2 ;

[0166] D2) A 355nm ultraviolet laser is used to scan the back of the sapphire substrate. The laser energy penetrates the sapphire, causing photochemical decomposition of the bonding adhesive interface. After the substrate is peeled off, acetone is used for ultrasonic cleaning to remove organic residues, ensuring that the surface of the insulating layer on the front of the device is clean at the molecular level.

[0167] Laser wavelength: 355nm

[0168] Cleaning solvent: acetone

[0169] Cleaning time: 10 minutes;

[0170] Step E: A high thermal conductivity AlN insulating layer is magnetron sputtered above the gate on the front side of the device to achieve electrothermal isolation. Bismuth telluride-based thermoelectric materials are grown in situ using MOCVD to construct an array-type TEC module with the cooling center offset 0.5~2μm towards the drain end, thereby achieving active heat extraction of local hot spots at the gate edge.

[0171] E1) A 1 μm thick AlN insulating layer is deposited directly above the gate by magnetron sputtering. AlN has extremely high insulation strength and excellent thermal conductivity (>180 W / m·K), which not only prevents the thermoelectric module from interfering with the gate electrical signal, but also ensures that heat can be conducted to the cooling end without loss.

[0172] E2) Bi2Te3-based array thermoelectric modules were grown in situ on top of AlN using MOCVD technology. Based on HEMT electric field distribution simulation, the center of the cooling array was shifted 1 μm towards the drain to accurately cover the local hot spots generated by high-energy electron scattering in the 2DEG channel.

[0173] Step F: The chip is seamlessly integrated onto the surface of a copper-tungsten alloy heat sink with microchannels using a low-temperature nano-silver sintering process, forming a heat dissipation interface with extremely low contact thermal resistance. Finally, the entire system's electrothermal pin interconnection is completed through bottom filling and SMT mounting, constructing a closed-loop electrothermal active cooling system with millisecond-level junction temperature dynamic adjustment capability.

[0174] F1) The chip is integrated onto a copper-tungsten (CuW) heat sink using a low-temperature nano-silver sintering process. After sintering, the nano-silver layer forms a metallic interface with high thermal conductivity (>200 W / m·K) and high-temperature resistance, ensuring that the large amount of heat generated by the TEC can be quickly dissipated by the heat sink. The sintering process parameters are as follows:

[0175] Sintering pressure: 5MPa

[0176] Sintering temperature: 260℃

[0177] Sintering time: 60 min;

[0178] F2) A high thermal conductivity underfill is applied to the back of the chip to complete the SMT mounting. An independent current source is provided for the thermoelectric module via reserved pins on the PCB. The system dynamically adjusts the TEC input current based on feedback from the temperature sensor integrated on the heat sink, achieving closed-loop precise control of the junction temperature of the HEMT device.

[0179] The above descriptions are merely a few specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and results of the present invention. For example, in addition to using Si(111) and 4H-SiC, the substrate layer 8 can also use semi-insulating 6H-SiC, high-resistivity silicon and other semiconductor substrate materials; in addition to using copper fin structures, silicon-based microchannel cold plates, copper-tungsten alloy fin heat sinks, the heat dissipation layer 1 can also use high thermal conductivity alloys such as copper-molybdenum alloy, aluminum-magnesium-silicon alloy, aluminum-silicon-carbon alloy and various heat dissipation structures made of high thermal conductivity ceramics such as SiC and AlN; in addition to using AlN ceramics, the insulating layer 2 can also use Al2O3 ceramics, Si3N4 ceramics, two-dimensional hexagonal boron nitride (h-BN) thin films and other materials that are compatible with AlN ceramics. Materials with high insulation and high thermal conductivity; the bonding layer 3 can use Cu, Au, or nano-sintered silver layers, or copper-based solder (Cu-Sn), various conductive and thermally conductive adhesives, and other conductive and thermally conductive bonding materials; the filling material for the TSV via structure 7 can use pure copper pillars, or copper-tungsten alloys, copper-molybdenum alloys, and other metals and alloys with high conductivity and low thermal expansion coefficients; the solder balls 9 can use SAC305 tin-silver-copper solder balls, SnAgCu solder balls, or SnCuNi high-temperature lead-free solder balls, and other solder bump structures adapted to package interconnection. However, these modifications and changes based on the concept of this invention are still within the scope of protection of the claims of this invention.

Claims

1. A top-mounted heat-dissipating gallium nitride device based on TSV interconnect, characterized in that, From bottom to top, it includes: a substrate, a GaN epitaxial layer, a passivation layer, a bonding layer, an insulating layer, and a heat dissipation layer. It also includes a front metal electrode that contacts the lower surface of the bonding layer, and a TSV via structure that extends vertically downward to penetrate the substrate layer below the electrode for vertically leading out the electrode. The GaN epitaxial layer includes a nucleation layer, a buffer layer, a channel layer, a spacer layer, and a barrier layer; The TSV via structure includes an insulating pad located at the via wall and a conductive filler located inside the insulating pad. The insulating pad is used to electrically isolate the conductive filler from the substrate and epitaxial layer at the via wall. The lower end of the TSV via structure is sequentially connected to a bump under metallization layer (UBM) and a solder ball interconnect layer to complete low-resistance interconnection with the packaging substrate. The solder ball interconnect layer adopts a bump structure of copper pillars and SnAg solder. The space between the packaging substrate and the substrate is filled with bottom filler adhesive.

2. The device according to claim 1, characterized in that: The substrate is made of semi-insulating SiC or high-resistivity Si, with a thickness of 50-200 μm; the nucleation layer is made of AlN, with a thickness of 20-200 nm; the buffer layer is made of GaN, AlN, or AlGaN, with a thickness of 0.1-5 μm; the channel layer is made of intrinsic GaN, with a thickness of 50-1000 nm; the spacer layer is made of AlN, with a thickness of 1-5 nm; the barrier layer is made of AlGaN, with a thickness of 10-30 nm; the passivation layer is made of SiO2, The thickness of the bonding layer is 50~200nm, which is any one of Si3N4 or Al2O3; the bonding layer is one or more combinations of Ti / Cu, Ti / Au, Cu, Au, Cu-Sn bonding layer, and sintered silver bonding layer; the thickness of the bonding layer is 1~50μm; the insulating layer is any one of AlN ceramic, Al2O3 ceramic or Si3N4 ceramic; the thickness of the insulating layer is 0.2~1mm; the heat dissipation layer is any one of copper alloy, aluminum alloy, high thermal conductivity pure metal or high thermal conductivity ceramic; the thickness of the heat dissipation layer is 0.1~10mm.

3. The device according to claim 1, characterized in that: Depending on the device type and design requirements, the front metal electrode can be formed into a two-terminal device structure or a three-terminal device structure; wherein, when the device is a Schottky barrier diode (SBD), the front metal electrode includes an anode Schottky electrode and a cathode Ohm electrode; when the device is a high electron mobility transistor (HEMT), the front metal electrode includes a source, a drain, and a gate. When the device is a Schottky barrier diode (SBD), the cathode ohmic electrode forms an ohmic contact with the cathode contact region on the surface of the GaN epitaxial layer; the anode region has an anode groove structure, and the anode Schottky electrode is disposed at the anode groove structure and forms a Schottky contact with the exposed GaN epitaxial layer thereon; the cathode ohmic electrode adopts a Ti / Al / Ni / Au metal stack with a thickness of 50~100nm / 200~500nm / 50~100nm / 50~100nm, and the anode Schottky electrode adopts a Ni / Au or Pt / Au metal stack with a thickness of 30~50nm / 100~200nm; When the device is a high electron mobility transistor (HEMT), the source and drain are disposed on the surface of the GaN epitaxial layer and form an ohmic contact. The gate is located between the source and drain and is disposed correspondingly to the barrier layer to control the channel turn-on and turn-off. The source and drain are made of Ti / Al / Ni / Au metal stack, and the gate is made of Ni / Au metal stack to form a gate Schottky contact.

4. The device according to claim 1, characterized in that: The packaging substrate layer is any one of PCB substrate, ceramic substrate or metal core substrate, and its thickness is 0.5~5mm; the ceramic substrate includes AlN and SiC substrates, and the metal core substrate includes copper core and aluminum core substrates.

5. The device according to claim 1, characterized in that: The TSV via structure penetrates vertically through the GaN epitaxial layer and the thinned substrate, with a pore size of 30~100μm; and a 1μm thick SiO2 insulating pad is deposited on the inner wall of the TSV via structure.

6. The device according to claim 1, characterized in that: The copper pillars in the solder ball interconnect layer have a diameter of 50~200μm and a height of 20~100μm, and the SnAg solder thickness is 10~50μm; the underfill adhesive is an epoxy resin-based underfill adhesive, and the filling thickness is consistent with the total height of the solder ball interconnect layer, which is 30~150μm.

7. A method for fabricating a top-mounted heat-dissipating gallium nitride device based on TSV interconnect, characterized in that, Includes the following steps: (1) Select a substrate material and grow a core layer, a buffer layer, an undoped GaN channel layer, a spacer layer and an AlGaN barrier layer on its surface in sequence to form a heterojunction structure, namely a GaN epitaxial layer; (2) Define the pattern and process the active region of the GaN epitaxial layer, and prepare the front metal electrode of the device; wherein, when preparing the SBD device, form the cathode ohmic electrode and reserve the anode Schottky electrode formation area; when preparing the HEMT device, form the source, drain and gate. (3) Deposit SiO2 or SiN by plasma-enhanced chemical vapor deposition (PECVD) x As the first passivation layer, after sputtering a Ti / Cu seed layer on its surface, a bonding layer is formed through a thickening process, which includes at least electroplating, sintering, and welding. (4) The front side of the chip obtained in step (3) is fixed on the carrier plate with temporary bonding adhesive, and the back side of the substrate is mechanically ground and polished to complete the substrate thinning process. (5) Coat the back of the thinned substrate with photoresist and develop it to define the via location; use deep reactive ion etching (DRIE) to vertically penetrate the substrate and epitaxial layer until the bottom of the front metal electrode is exposed to form a TSV via structure. (6) After insulating the hole wall of the TSV via, electroplating is used to fill the copper pillars, and a bump under metallization layer UBM and solder balls are prepared on the back side to form a solder ball interconnect layer. (7) After debonding, an insulating and thermally conductive layer is set above the bonding layer on the front side of the chip, and a heat dissipation layer is installed on the side of the insulating and thermally conductive layer away from the chip to form a top heat dissipation structure. (8) Align the chip with solder balls with the PCB pads and solder them. Fill the space between the back of the chip and the PCB with bottom filler glue. After curing, the device is packaged and integrated.

8. The method according to claim 7, characterized in that: In step (3), the first passivation layer is a passivation dielectric layer formed on the surface of the GaN epitaxial layer and the front metal electrode; the layer adopts any one of SiO2, Si3N4 or Al2O3, and the thickness is 50nm~200nm; after depositing the first passivation layer, a contact window is formed above the predetermined connection area of ​​the front metal electrode by photolithography and dry etching; when the device is SBD, after opening the anode region, an anode groove structure is formed by ICP etching, and then a Ni / Au metal layer is deposited to form an anode Schottky electrode; when the device is HEMT, the contact window is disposed above at least one of the source, drain and gate; the thickness of the Ti layer in the Ti / Cu seed layer is 20nm~50nm, and the thickness of the Cu layer is 100nm~300nm; the thickness of the bonding layer is 1μm~50μm.

9. The method according to claim 7, characterized in that: In step (6), the insulation treatment of the TSV via wall specifically involves depositing SiO2 or SiN on the inner wall of the TSV via by PECVD. X An insulating layer is formed, and the insulating layer at the bottom of the hole is removed by anisotropic etching, while the insulating layer on the hole wall is retained. Subsequently, a copper filler is formed in the TSV via by electroplating. A Ti / Ni / Au stacked UBM layer is prepared at the exit of the TSV via on the back side, wherein the thickness of the Ti layer is 50nm~100nm, the thickness of the Ni layer is 1μm~3μm, and the thickness of the Au layer is 50nm~200nm. The solder ball interconnect layer is a bump structure formed by copper pillars and SnAg solder, and the diameter of the bump is 100μm~500μm.

10. The method according to claim 7, characterized in that: The thermal interface material mentioned in step (7) is one of thermally conductive silicone grease, graphene thermally conductive film, nano silver paste or Cu-Sn bonding material; the insulating thermally conductive layer is a double-sided metallized AlN ceramic sheet with a thickness of 0.2mm~1mm; the heat dissipation layer is a finned Cu heat sink or water-cooled plate, and is fixed to the side of the insulating thermally conductive layer away from the chip by welding, sintering or pressing.

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