A 2.5D packaging structure and a preparation method of the 2.5D packaging structure

Abstract

This invention provides a 2.5D packaging structure and a method for fabricating the 2.5D packaging structure. The structure includes several chips and a wiring layer, with each chip connected to the wiring layer. It further includes: a polymer composite interface layer disposed between adjacent chips and connected to the side of the chip closest to the wiring layer; a metal matrix composite host layer connected to the polymer composite interface layer and spaced apart from the chips; and a molding compound layer covering the chips, the polymer composite interface layer, and the metal matrix composite host layer. This invention allows the polymer composite interface layer to directly contact the side of the chip closest to the wiring layer (i.e., the active surface), enabling efficient collection of heat generated by the chip and transfer to the metal matrix composite host layer. The metal matrix composite host layer has excellent thermal conductivity, allowing heat to diffuse laterally and conduct downwards, thereby significantly improving the heat dissipation efficiency of the package.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D packaging structure and a method for fabricating the 2.5D packaging structure. Background Technology

[0002] 2.5D packaging is an advanced semiconductor heterogeneous integration technology that enables the horizontal side-by-side integration of multiple chips (such as GPUs, CPUs, and HBM memory) by inserting a high-density interconnect interposer between the chip and the packaging substrate.

[0003] A typical 2.5D package is a "sandwich" multi-layer structure, including a chip layer: located on the top layer, it consists of chips with different functions placed side by side, such as GPU, CPU and HBM memory stack; an interconnect layer: the chips are connected to the underlying interposer layer through microbumps, which is the core of the entire package; and a substrate layer: the entire "interposer + chip" assembly is mounted on the bottom organic packaging substrate through C4 bumps, and finally connected to the circuit board.

[0004] However, existing 2.5D packaging has the following defects. (1) Severe thermal crosstalk: Joule heat generated by high-power chips (such as GPUs) is conducted laterally through the silicon interposer, causing the temperature of adjacent chips (such as HBMs) to rise. The heat dissipation path is singular and inefficient. (2) Thermomechanical stress concentration: The coefficients of thermal expansion (CTE) of materials such as chips, silicon interposers, organic substrates, and molding compounds are seriously mismatched, resulting in complex internal stresses when the temperature changes. (3) Chip displacement risk: In the molding process, the flow of high-viscosity molten resin generates huge scouring force, which pushes the chip that is not completely fixed to shift. Summary of the Invention

[0005] The core of this invention lies in proposing a 2.5D packaging structure and a method for fabricating the 2.5D packaging structure. It transforms the "passive gap" between chips in traditional 2.5D packaging into an "active functional integration area"—by setting a composite island structure composed of a "polymer composite interface layer + metal matrix composite main body layer," it simultaneously achieves three major functions: heat collection and conduction, mechanical anchoring to prevent displacement, and thermal stress buffering. In conjunction with the thermally conductive / stress-buffering vias in the wiring layer, it constructs a three-dimensional heat dissipation network that penetrates the packaging thickness and a multi-layer stress release system.

[0006] A 2.5D package structure includes a plurality of chips and a wiring layer, wherein each chip is connected to the wiring layer, and further includes: A polymer composite interface layer is disposed between adjacent chips and connected to the side of the chip closest to the wiring layer; A metal-based composite host layer is connected and disposed on the polymer composite interface layer, and is spaced apart from the chip; A molding layer is provided to cover the chip, the polymer composite interface layer, and the metal-based composite host layer.

[0007] Preferably, the polymer composite interface layer material is an aluminum nitride-polymer composite material or a boron nitride-epoxy resin composite material; the metal-based composite host layer material is a copper-molybdenum-copper material or an aluminum-silicon carbide material.

[0008] Preferably, it further includes a stress-reducing polymer layer covering the sidewall of the metal-based composite host layer.

[0009] Preferably, the material of the stress-reducing polymer layer is polyimide, benzocyclobutene, or polybenzoxazole.

[0010] Preferably, the molding layer has a plurality of through holes, the through holes being located above the metal-based composite body layer, and the through holes are filled with particle-reinforced resin thermally conductive columns.

[0011] Preferably, the wiring layer includes a first wiring layer, a silicon dielectric layer, and a second wiring layer stacked sequentially along the direction away from the chip. The first wiring layer has a plurality of vias located on one side of the polymer composite interface layer, and the vias are filled with stress-reducing material or thermally conductive material.

[0012] Preferably, a stress buffer layer is formed on the sidewall of the through hole, and a thermally conductive material layer is formed within the stress buffer layer.

[0013] A method for fabricating a 2.5D packaging structure includes the following steps: A temporary carrier plate is provided, and a temporary bonding adhesive layer is coated on the temporary carrier plate; Several chips are attached to the temporary bonding adhesive layer with their contact surfaces facing each other. A polymer composite interface layer connected to the chip near the wiring layer is provided between adjacent chips, and a metal-based composite body layer is connected to the polymer composite interface layer. A molding layer is formed covering the chip, the polymer composite interface layer, and the metal-based composite host layer; Remove the temporary carrier and the temporary bonding adhesive layer to form a wiring layer on the back side of the chip.

[0014] Preferably, the method further includes the following steps: forming a stress-reducing polymer layer covering the sidewalls of the metal-based composite host layer; and then forming a molding compound layer.

[0015] Preferably, the step of forming a wiring layer on the back side of the chip includes: sequentially stacking a first wiring layer, a silicon dielectric layer, and a second wiring layer in a direction away from the chip; forming a plurality of vias in the first wiring layer, the vias being located on one side of the polymer composite interface layer; and filling the vias with a stress-reducing material or a thermally conductive material.

[0016] The present invention has the following beneficial effects: This invention uses a polymer composite interface layer to directly contact the chip's side near the wiring layer (i.e., the active side), which can efficiently collect the heat generated by the chip and transfer it to the metal matrix composite host layer. The metal matrix composite host layer has good thermal conductivity, which can diffuse the heat laterally and conduct it downward, thereby significantly improving the heat dissipation efficiency of the package. A gap is maintained between the metal matrix composite host layer and the chip, and the molding layer fills the gap to form a physical locking structure, which plays a mechanical anchoring role for the chip and effectively prevents the chip from shifting position during the molding process. The polymer composite interface layer has a certain degree of flexibility, and the metal matrix composite host layer can be made of a material with a low coefficient of thermal expansion. The synergistic effect of the two can buffer the thermomechanical stress caused by the mismatch of the material's coefficient of thermal expansion, and avoid stress concentration that could lead to chip or interconnect structure failure.

[0017] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0018] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 The method for preparing a 2.5D packaging structure provided in the embodiments of the present invention includes a temporary carrier plate and a schematic diagram of the structure after a temporary bonding adhesive layer is coated on the temporary carrier plate; Figure 2 The following is a schematic diagram of the 2.5D packaging structure fabrication method provided in the embodiments of the present invention, wherein the edge surfaces of several chips are attached to the temporary bonding adhesive layer, and a polymer composite interface layer connected to the side of the chip near the wiring layer is provided between adjacent chips, and a metal-based composite body layer connected to the polymer composite interface layer is shown. Figure 3A schematic diagram of the structure after forming a stress-buffered polymer layer covering the sidewall of the metal-based composite host layer in the method for preparing the 2.5D packaging structure provided in the embodiments of the present invention; Figure 4 A schematic diagram of the structure after forming a molding compound layer covering the chip, polymer composite interface layer and metal matrix composite body layer in the fabrication method of the 2.5D packaging structure provided in the embodiments of the present invention; Figure 5 A schematic diagram of the structure after forming particle-reinforced resin thermally conductive pillars in the molding layer in the preparation method of the 2.5D packaging structure provided in the embodiments of the present invention; Figure 6 A schematic diagram of the structure after removing the temporary carrier and the temporary bonding adhesive layer in the method for fabricating the 2.5D packaging structure provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the structure after a wiring layer is formed on the back side of the chip in the method for fabricating a 2.5D package structure provided in an embodiment of the present invention. Detailed Implementation

[0020] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0021] like Figure 1-7 As shown, the 2.5D packaging structure prepared in this embodiment includes: Several chips 2, with their active surfaces facing the wiring layer 5; A polymer composite interface layer 31 and a metal-based composite host layer 32 are disposed between adjacent chips 2, with the metal-based composite host layer 32 being disposed at a distance from the chip 2. Stress-reducing polymer layer 33 (material can be PBO) covering the sidewalls of the metal matrix composite host layer 32. A molding layer 4 covering chip 2, polymer composite interface layer 31 and metal matrix composite host layer 32; A particle-reinforced resin thermally conductive column 7 (the material can be BN-epoxy resin) penetrates the plastic seal layer 4 and is located above the metal matrix composite body layer 32. The wiring layer 5 disposed on the active surface of chip 2 includes a first wiring layer 51, a silicon dielectric layer 52, and a second wiring layer 53.

[0022] This structure achieves the following beneficial effects.

[0023] High-efficiency heat dissipation: The chip's heat is discharged through two paths: polymer composite interface layer → metal matrix composite main body layer → heat conduction pillars → external heat sink, and through polymer composite interface layer → heat conduction vias in wiring layer → solder balls, forming a three-dimensional heat dissipation network.

[0024] To prevent chip misalignment: The gap between the metal-based composite substrate and the chip is filled with molding compound to form a mechanical latch, resisting fluid impact during the molding process.

[0025] Thermal stress buffering: The flexibility of the polymer composite interface layer, the stress-buffered polymer layer, and the stress-buffered layer in the wiring layer vias work together to absorb the stress caused by CTE mismatch, avoiding damage to the chip and interconnect structure.

[0026] The polymer composite interface layer 31 is made of aluminum nitride-polymer composite material or boron nitride-epoxy resin composite material; the metal matrix composite host layer 32 is made of copper-molybdenum-copper material or aluminum-silicon carbide material.

[0027] Aluminum nitride-polymer composites: These use epoxy resin, polyimide, etc., as the matrix, filled with aluminum nitride (AlN) ceramic particles. Boron nitride-epoxy resin composites: These use epoxy resin as the matrix, filled with hexagonal boron nitride (BN) particles. Copper-molybdenum-copper (Cu-Mo-Cu): A sandwich laminate composite material. By adjusting the thickness ratio of the copper layer to the molybdenum core, the coefficient of thermal expansion (CTE) can be adjusted within the range of 5.6-8.8 ppm / °C, and the thermal conductivity can reach 200-250 W / (m·K). Aluminum-silicon carbide (AlSiC): A silicon carbide particle-reinforced aluminum matrix composite material. The CTE can be adjusted to 6.5-9.5 ppm / °C, and the thermal conductivity is 150-200 W / (m·K). All of the above materials can utilize existing materials.

[0028] Technical effects: Preferably, the system further includes a stress-reducing polymer layer 33, which covers the sidewalls of the metal-based composite host layer (32). There is a CTE difference between the metal-based composite host layer and the molding compound layer, which generates shear stress when the temperature changes. The low-modulus polymer layer covering the sidewalls absorbs this stress through its own deformation, preventing stress concentration from being transmitted to the chip edges. The stress-reducing polymer layer uses polymers with low elastic modulus and high elongation at break, such as polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO). The thickness is typically 1-20 μm.

[0029] Preferably, the molding layer 4 has several through holes located above the metal-based composite main body layer 32, and the through holes are filled with particle-reinforced resin thermally conductive pillars 7. After molding, through holes (50-200 μm in diameter) are created on the molding layer at the corresponding positions of the metal-based composite main body layer by laser drilling or reactive ion etching. Then, the thermally conductive composite material is filled by vacuum dispensing or screen printing, and finally cured. Typical materials for the particle-reinforced resin thermally conductive pillars are boron nitride (BN) / epoxy resin composites or alumina (Al2O3) / epoxy resin composites, with a filler volume fraction typically of 70-80%. Metal pastes (such as silver paste) can also be used, but attention must be paid to conductivity.

[0030] The upper surface of the heat-conducting pillar contacts the heat sink, forming a continuous heat dissipation channel from the chip → interface layer → main body layer → heat-conducting pillar → heat sink. Heat is directly conducted from the metal-based composite main body layer to the upper surface of the molding compound through the heat-conducting pillar, avoiding obstruction by the low thermal conductivity molding compound, and the overall vertical thermal resistance can be reduced by more than 50%.

[0031] Preferably, the wiring layer 5 includes a first wiring layer 51, a silicon dielectric layer 52 and a second wiring layer 53 stacked sequentially along the direction away from the chip 2. The first wiring layer 51 has a plurality of through holes located on one side of the polymer composite interface layer 31. The through holes are filled with stress buffer material or thermally conductive material.

[0032] First wiring layer: Closest to the chip, using a polymer dielectric layer (such as PI, PBO) and copper metal wiring. Vias are incorporated within this layer, vertically aligned with the polymer composite interface layer. Vertical vias and a metal layer are formed within the silicon dielectric layer. Second wiring layer: Ultra-fine linewidth copper wiring is formed on the silicon dielectric layer using a damascus process to achieve high-density fan-out. Stress buffer material: Low-modulus polymers (such as PBO, BCB) are used to absorb thermomechanical stress. Thermally conductive material: High thermal conductivity metals (copper, silver) or thermally conductive composite materials (BN / epoxy) are used to conduct heat.

[0033] Forming a vertical thermal / mechanical coupling channel: The vias in the first wiring layer are vertically aligned with the polymer composite interface layer below. Heat can directly enter the vias from the interface layer, and then be conducted to the solder balls through the silicon dielectric layer and the second wiring layer, forming a second heat dissipation path (complementary to the body layer-thermal conductive pillar path).

[0034] More preferably, a stress buffer layer 62 is formed on the sidewall of the through hole, and a thermally conductive material layer 61 is formed within the stress buffer layer 62.

[0035] The system employs a coaxial dual-layer structure—the inner layer is a high thermal conductivity material (such as copper or silver paste), and the outer layer is a thin layer of stress-reducing polymer (such as PBO or BCB). The stress-reducing layer directly contacts the sidewall of the via (i.e., the dielectric material of the first wiring layer), and the thermally conductive material layer fills its interior. The formation process involves first etching the via, then forming a thin polymer layer on the via wall through spin coating or spraying and curing it, followed by filling with the thermally conductive material through electroplating or dispensing.

[0036] When filling through-holes with a traditional single material, high thermal conductivity materials (such as copper) are rigid and generate significant stress during thermal cycling; low modulus materials have poor thermal conductivity. The coaxial structure separates the two: the outer polymer absorbs stress, while the inner metal efficiently conducts heat, achieving a balance between rigidity and flexibility.

[0037] This embodiment also provides a method for fabricating a 2.5D packaging structure, which is described below in conjunction with... Figures 1 to 7 Each step is explained in detail.

[0038] Step 1: Preparation of temporary carrier board (e.g.) Figure 1 (As shown) A temporary carrier plate 1 is provided, which can be a glass carrier plate, a silicon carrier plate, or a metal carrier plate. A temporary bonding adhesive layer 11 is coated on the temporary carrier plate 1 by spin coating or spraying. The temporary bonding adhesive can be thermoplastic polyimide or photosensitive temporary bonding adhesive.

[0039] Step 2: Chip mounting and composite structure construction (e.g.) Figure 2 (As shown) Several chips 2 are mounted face down on the temporary bonding adhesive layer 11. Specifically, the active side (i.e., the pad side) of the chip 2 faces the temporary bonding adhesive layer 11, and the chip 2 is mounted in place using a high-precision pick-and-place device.

[0040] A polymer composite interface layer 31 is disposed in the gap between adjacent chips 2. The polymer composite interface layer 31 is in direct contact with the side of chip 2 closest to the subsequent wiring layer 5 (i.e., the active surface of the chip). In this embodiment, the polymer composite interface layer 31 is made of an epoxy resin composite material filled with aluminum nitride (AlN) particles (AlN-epoxy resin). This material is deposited by dispensing or screen printing, with a thickness controlled at 10-50 μm, and then cured at 150°C for 1 hour. Preferably, before the polymer composite interface layer 31, the temporary bonding adhesive layer 11 between adjacent chips 2 can be removed by selective etching or cleaning processes. After removal, the substrate surface in the chip gap area is completely exposed, while the temporary bonding adhesive layer directly under the chip is retained, and the chip is still fixed. The exposed substrate surface is flat, clean, and free of organic residue, providing an ideal substrate for the direct deposition of the subsequent polymer composite interface layer 31 and enhancing the adhesion between the interface layer and the substrate.

[0041] A metal-based composite host layer 32 is disposed above the polymer composite interface layer 31 (i.e., on the side away from the temporary carrier). A gap of 10-100 μm is maintained between the metal-based composite host layer 32 and the chip 2. In this embodiment, the metal-based composite host layer 32 is made of a copper-molybdenum-copper (Cu-Mo-Cu) sandwich composite material, formed by first depositing a seed layer on the polymer composite interface layer 31 by sputtering or electroplating, and then thickening it to the target thickness by electroplating, or by directly mounting a pre-fabricated Cu-Mo-Cu block. Preferably, the pre-fabricated block is fixed to the polymer composite interface layer 31 by thermo-press bonding.

[0042] In another embodiment, a high-precision pick-and-place device (such as a flip-chip bonding machine) is used to pick up the pre-fabricated composite structure and precisely place it in the gap between adjacent chips 2. Of course, in another embodiment, the composite structure can be formed first, and then the chips 2 can be attached.

[0043] Step 3: Form a stress-reducing polymer layer (e.g.) Figure 3 (As shown) A stress-reducing polymer layer 33 is coated on the sidewalls of the metal-based composite host layer 32. In this embodiment, photosensitive polybenzoxazole (PBO) is used as the material, and a uniform coating is formed on the exposed sidewalls of the metal-based composite host layer 32 by spraying or dip coating. Then, photolithography is performed to pattern the coating only on the sidewalls, and the coating is cured at a temperature below 200°C. In another embodiment, a composite structure of polymer composite interface layer 31, metal-based composite host layer 32 and stress-reducing polymer layer 33 is first prepared, and then a high-precision pick-and-place device (such as a flip-chip bonding machine) is used to pick up the pre-fabricated composite structure and accurately place it in the gap between adjacent chips 2.

[0044] Step 4: Plastic sealing (e.g.) Figure 4 (As shown) Using a compression molding process, an epoxy molding compound is used to cover the chip 2, polymer composite interface layer 31, metal matrix composite substrate layer 32, and stress-reducing polymer layer 33 under vacuum to form a molding compound layer 4. The molding compound layer 4 fills all gaps. Preferably, the curing conditions are: temperature 120-200℃, pressure 0.5-5MPa, and curing time 2-10 minutes.

[0045] The molding compound 4 firmly secures the chip and the composite island into a single unit. The molding compound filling the gaps cures to form physical "locks," mechanically anchoring the metal-based composite substrate 32 and preventing horizontal displacement of the chip 2 during subsequent processes or use. Simultaneously, the molding compound 4 provides environmental protection and mechanical support.

[0046] Step 5: Form a through-hole heat-conducting pillar (e.g.) Figure 5 (As shown) On the molding layer 4, corresponding to the position above the metal-based composite substrate layer 32, several through holes (50~200μm in diameter) are formed by laser drilling or reactive ion etching. Then, high thermal conductivity material is filled into the through holes to form particle-reinforced resin thermally conductive pillars 7. In this embodiment, a boron nitride (BN) particle-reinforced epoxy resin composite material is used, which is filled into the holes by vacuum dispensing or printing and cured at 150°C.

[0047] Step 6: Remove the temporary carrier board (e.g.) Figure 6 (As shown) The temporary carrier 1 is removed by laser debonding. Specifically, an ultraviolet laser is used to irradiate the temporary bonding adhesive layer 11 through the glass carrier, reducing the adhesion of the bonding adhesive, and then the carrier is mechanically separated. Afterwards, a special cleaning agent is used to remove any remaining temporary bonding adhesive on the active surface of the chip 2.

[0048] Step 7: Form the wiring layer (e.g.) Figure 7 (As shown) A multilayer wiring structure is formed on chip 2. In this embodiment, wiring layer 5 includes a first wiring layer 51, a silicon dielectric layer 52, and a second wiring layer 53, which are sequentially stacked along a direction away from chip 2. The specific formation method is as follows: First wiring layer 51: First, a dielectric layer (photosensitive polyimide can be used) is deposited on the active surface of chip 2 and the molding layer 4. I / O pads of the chip are exposed by photolithography. Then, a Ti / Cu seed layer is sputtered, and then copper is electroplated to form metal lines. Within the first wiring layer 51, corresponding to the position above the polymer composite interface layer 31, several vias are formed. These vias are filled with stress-reducing or thermally conductive materials. A stress-reducing layer 62 (material is low-modulus PBO) is first formed on the sidewalls of the vias, and then a thermally conductive material layer 61 (material is copper or high thermal conductivity silver paste) is filled inside the stress-reducing layer 62. This structure allows the vias to function as both stress-reducing and thermally conductive materials.

[0049] Silicon dielectric layer 52: A silicon dielectric layer is formed on the first wiring layer 51. Through-holes are fabricated in the silicon dielectric layer using photolithography and etching processes to connect the upper and lower metal layers. Second wiring layer 53: A second layer of copper wiring is formed on the silicon dielectric layer 52 using a damascene process to achieve high-density interconnection. Finally, a bump under metal layer (UBM) is fabricated on the second wiring layer 53 and solder balls are implanted to complete the packaging.

[0050] In another embodiment, the wiring layer 5 can be prepared first, and then the wiring layer 5 can be combined with the chip 2.

[0051] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A 2.5D package structure, comprising a plurality of chips (2) and a wiring layer (5), wherein each chip (2) is connected to the wiring layer (5), characterized in that, Also includes: A polymer composite interface layer (31) is disposed between adjacent chips (2) and connected to the side of the chip (2) near the wiring layer (5); A metal-based composite host layer (32) is connected to the polymer composite interface layer (31) and spaced apart from the chip (2); A molding layer (4) is provided to cover the chip (2), the polymer composite interface layer (31) and the metal-based composite host layer (32).

2. The 2.5D packaging structure according to claim 1, characterized in that, The polymer composite interface layer (31) is made of aluminum nitride-polymer composite material or boron nitride-epoxy resin composite material; the metal matrix composite host layer (32) is made of copper-molybdenum-copper material or aluminum-silicon carbide material.

3. The 2.5D packaging structure according to claim 1, characterized in that, It also includes a stress-relief polymer layer (33) covering the sidewall of the metal-based composite host layer (32).

4. The 2.5D packaging structure according to claim 3, characterized in that, The stress-relief polymer layer (33) is made of polyimide, benzocyclobutene or polybenzoxazole.

5. The 2.5D packaging structure according to claim 1, characterized in that, The molding layer (4) has several through holes located above the metal-based composite main body layer (32), and the through holes are filled with particle-reinforced resin thermal conductive columns (7).

6. The 2.5D packaging structure according to claim 1, characterized in that, The wiring layer (5) includes a first wiring layer (51), a silicon dielectric layer (52), and a second wiring layer (53) stacked sequentially along the direction away from the chip (2). The first wiring layer (51) has a plurality of through holes located on one side of the polymer composite interface layer (31). The through holes are filled with stress buffer material or thermal conductive material.

7. The 2.5D packaging structure according to claim 6, characterized in that, A stress buffer layer (62) is formed on the sidewall of the through hole, and a thermally conductive material layer (62) is formed inside the stress buffer layer (62).

8. A method for preparing a 2.5D packaging structure according to any one of claims 1-7, characterized in that, Includes the following steps: A temporary carrier plate (1) is provided, and a temporary bonding adhesive layer (11) is coated on the temporary carrier plate (1). Several chips (2) are attached to the temporary bonding adhesive layer (11) with their edges facing each other, and a polymer composite interface layer (31) connected to the side of the chip (2) near the wiring layer (5) is provided between adjacent chips (2), and a metal-based composite host layer (32) is connected to the polymer composite interface layer (31). A molding layer (4) is formed covering the chip (2), the polymer composite interface layer (31) and the metal matrix composite host layer (32). Remove the temporary carrier and the temporary bonding adhesive layer to form a wiring layer (5) on the back side of the chip.

9. The preparation method according to claim 8, characterized in that, It also includes the following steps: A stress-relief polymer layer (33) is formed covering the sidewall of the metal-based composite host layer (32); then a molding layer (4) is formed.

10. The preparation method according to claim 8, characterized in that, The step of forming a wiring layer (5) on the back side of the chip includes: sequentially stacking a first wiring layer (51), a silicon dielectric layer (52), and a second wiring layer (53) in a direction away from the chip (2); forming a plurality of through holes in the first wiring layer (51), the through holes being located on one side of the polymer composite interface layer (31); and filling the through holes with stress buffer material or thermal conductive material.

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