Electric field-thermal field synergistic optimization gallium oxide power device based on nanocrystalline diamond passivation and preparation method thereof

Abstract

This invention discloses a gallium oxide power device based on the synergistic optimization of electric and thermal fields using nanocrystalline diamond passivation, and its fabrication method. It primarily addresses the problems of severe heat accumulation in the gate-drain region, concentrated surface electric field, single-function top functional layer, and the impact of large-area coverage structures on gate control characteristics in existing devices. The device consists of a substrate, a buffer layer, a gallium oxide active layer, a MOS gate dielectric, a top P-type nanocrystalline diamond passivation thermal expansion layer, a drain-side spacer region, a second passivation layer, a thermal expansion metal layer, and metal electrodes. The MOS gate dielectric is retained in the channel region. A contact-type top P-type nanocrystalline diamond passivation thermal expansion layer is locally formed on the surface of the n-drift region between the gate and drain sides, followed by a second passivation layer and an independent thermal expansion metal layer. This invention effectively suppresses electric field concentration and heat accumulation through synergistic optimization of electric field modulation and thermal diffusion, significantly improving the stability and reliability of the device.

Description

Technical Field

[0001] This invention belongs to the field of ultra-wide bandgap semiconductor power device technology, and further relates to lateral gallium oxide metal oxide semiconductor field-effect transistor (MOSFET) devices. Specifically, it is a gallium oxide power device based on nanocrystalline diamond passivation with synergistic optimization of electric and thermal fields and its fabrication method, which can be used in high-voltage switching, power electronic conversion and high-temperature high-power-density integrated systems. Background Technology

[0002] Gallium oxide (GaO), as an ultrawide bandgap semiconductor material, possesses advantages such as a large bandgap, high theoretical critical breakdown field strength, and the ability to grow large-size single crystals via melt processing, making it a promising candidate for high-voltage, low-loss power devices. In particular, lateral GaO MOSFETs, due to their good compatibility with existing planar processes, show promising application prospects in high-voltage power integration and high-frequency power control.

[0003] However, existing gallium oxide MOSFETs still face two key problems in practical applications: significant self-heating effect and concentrated surface electric field. Among them, the self-heating effect has become a prominent bottleneck restricting the stable operation of the device at high power.

[0004] On the one hand, in the high reverse bias state, lateral gallium oxide MOSFETs are prone to electric field concentration at the gate-drain edge and the surface of the adjacent drift region. Due to the insufficiently smooth potential distribution on the device surface, the high electric field tends to concentrate preferentially at the gate-drain junction, preventing the main drift region from being fully depleted. This leads to premature surface breakdown of the device and limits the full utilization of the drift region's breakdown voltage potential.

[0005] On the other hand, gallium oxide has low intrinsic thermal conductivity, making it difficult to dissipate heat generated during device conduction and high-field operation from the channel region and gate-drain drift region in a timely manner. This easily leads to localized hot spots at the gate edge, current congestion region, and drain-side access region. As the junction temperature increases, the device further exhibits problems such as decreased carrier mobility, increased on-resistance, threshold voltage drift, interface state deterioration, and decreased reliability. Especially for lateral devices operating under high voltage and high power conditions, the electric field peak region and hot spot region are often spatially close. Traditional single optimization methods that only focus on heat dissipation or the terminal electric field are insufficient to effectively solve the device performance degradation problem.

[0006] To improve thermal management performance, some solutions have attempted to introduce a high thermal conductivity material layer on top of gallium oxide devices to shorten the path of heat diffusion from the surface heat source outwards; others have utilized surface termination layers to improve the surface electric field distribution of the device. However, most existing top heat dissipation layers mainly serve the functions of heat conduction or passive passivation, making it difficult to simultaneously address localized thermal expansion, surface protection, and electric field mitigation in the gate-drain hotspot region. Furthermore, if a high thermal conductivity functional layer covers a large area of ​​the channel region or directly intervenes in the gate control region, it can easily interfere with the MOS gate control characteristics and introduce additional leakage paths, which is detrimental to the long-term stable operation of the device.

[0007] Therefore, how to construct a local functional structure on the surface of the gate-drain drift region that is mainly characterized by high thermal conductivity expansion, while also having surface passivation and the ability to help improve the surface electric field distribution, while keeping the MOS gate control structure in the channel region unchanged, and thus achieve synergistic optimization of the electric and thermal fields, has become a key technical problem that urgently needs to be solved in the field of gallium oxide high-voltage power devices. Summary of the Invention

[0008] The purpose of this invention is to overcome the problems of severe heat accumulation in the gate-drain region, concentrated surface electric field, single function of the top functional layer, and the influence of large-area coverage structure on gate control characteristics in existing lateral gallium oxide MOSFETs. It provides a gallium oxide power device and its fabrication method based on the synergistic optimization of electric and thermal fields using nanocrystalline diamond passivation. By retaining the MOS gate dielectric in the device channel region and locally forming a top P-type nanocrystalline diamond passivation thermal expansion layer that directly contacts the n-drift region on the surface between the gate and drain sides, a second passivation layer and an independently formed thermal expansion metal layer are formed on top of this layer. This primarily enhances the thermal expansion and heat dissipation capabilities of the gate-drain region, while also providing surface passivation and, to some extent, improving the local surface electric field distribution, thereby enhancing the device's thermal stability, reliability, and high-voltage operating stability.

[0009] To achieve the above objectives, the technical solution of the present invention includes the following:

[0010] A gallium oxide power device based on electric field-thermal field synergistic optimization of nanocrystalline diamond passivation, the device being a lateral gallium oxide metal oxide semiconductor field-effect transistor MOSFET, comprising, from bottom to top, a substrate 1, a buffer layer 2, and a gallium oxide active layer 3, wherein the gallium oxide active layer 3 comprises, from left to right, an n+ source region 31, a channel region 32, an n- drift region 33, and an n+ drain region 34;

[0011] The n+ source region 31, channel region 32, and n+ drain region 34 are respectively provided with a source S, a MOS gate dielectric layer 4, and a drain D. The MOS gate dielectric layer 4 is provided with a gate G. The n- drift region 33 is provided with a top P-type nanocrystalline diamond passivation thermal expansion layer 6, and the two are in direct contact, which is used to enhance the thermal expansion and heat dissipation capabilities of the gate-drain drift region surface, and also has a surface passivation function. A drain-side gap region 7 is left between the right end of the top P-type nanocrystalline diamond passivation thermal expansion layer 6 and the drain D. The MOS gate dielectric layer 4 is provided between the channel region 32 and the gate G, which is used to realize the conduction and turn-off control of the channel region 32. The MOS gate dielectric layer 4 is not in direct contact with the source S.

[0012] The device is covered with a second passivation layer 8 to protect the surface area; and a thermal expansion metal layer 9 is provided on the second passivation layer 8 to enhance the thermal expansion capability of the top of the device; the source S, gate G and drain D are respectively led out to the upper surface of the second passivation layer 8 through corresponding vias.

[0013] Furthermore, the substrate 1 is any one of a semi-insulating β-Ga2O3 substrate, a lightly doped β-Ga2O3 substrate, a SiC substrate, an AlN substrate, or a high thermal conductivity support substrate, used to provide mechanical support and thermal conduction channels; the buffer layer 2 is made of β-Ga2O3, used to improve epitaxial quality, reduce interface defects, and improve device structural stability.

[0014] Furthermore, the aforementioned channel region 32 and n-drift region 33 are both n-type or unintentionally doped β-Ga2O3; the n+ source region 31 and n+ drain region 34 are heavily doped β-Ga2O3 regions.

[0015] Furthermore, the aforementioned MOS gate dielectric layer 4 is made of Al2O3, HfO2, SiO2, or SiN. x Or any one of its composite media, with a thickness of 5 nm to 150 nm.

[0016] Furthermore, the aforementioned top P-type nanocrystalline diamond passivation thermal extension layer 6 is a boron-doped nanocrystalline diamond thin layer with a thickness of 10 nm to 2000 nm and a length of 0.3 to 0.98 times the distance between the gate and the drain; a drain-side gap region 7 with a width of 0.1 μm to 10 μm is retained between its right end and the drain D.

[0017] Furthermore, the aforementioned source S, gate G, and drain D are respectively led out to the upper surface of the second passivation layer 8 through corresponding vias. Specifically, the tops of the source S, gate G, and drain D are led out through the source connection via 10, the gate connection via 11, and the drain connection via 15, respectively. The ports led out to the upper surface of the second passivation layer 8 include the source lead-out Pad 12, the gate lead-out Pad 13, and the drain lead-out Pad 14.

[0018] Furthermore, the aforementioned thermally extended metal layer 9 adopts a floating structure and maintains an insulating distance from the source lead-out Pad12, the gate lead-out Pad13, and the drain lead-out Pad14.

[0019] Simultaneously, a method for fabricating gallium oxide power devices based on the electric-thermal field synergistic optimization of nanocrystalline diamond passivation is proposed, including the following steps:

[0020] (1) Select a substrate material and pre-treat it to form a β-Ga2O3 buffer layer and a gallium oxide active layer on its surface;

[0021] (2) Construct an n+ source region, a channel region, an n- drift region and an n+ drain region in the gallium oxide active layer, and deposit a MOS gate dielectric on the surface of the channel region;

[0022] (3) A gate G metal is formed on the MOS gate dielectric, and a source S metal and a drain D metal are formed on the surfaces of the n+ source region and the n+ drain region, respectively.

[0023] (4) Define the pattern and pre-process the surface of the n-drift region between the gate G drain side and the drain D. In this region, a boron-doped nanocrystalline diamond thin layer is directly formed. The top P-type nanocrystalline diamond passivation thermal expansion layer that only locally covers the gate-drain drift region is obtained through the patterning process. At the same time, its left end is controlled to be close to the gate G drain side edge and not enter the channel region, and the right end is kept at a distance from the drain D to form a drain side gap region.

[0024] (5) A second passivation layer is formed on the device surface obtained in step (4), and the lead-out areas of the source, gate and drain are patterned and opened to form source, gate and drain connection vias respectively.

[0025] (6) A thermal expansion metal layer and source lead-out Pad12, gate lead-out Pad13 and drain lead-out Pad14 are formed above the second passivation layer. The three are connected to the lower electrode through corresponding connection vias and are kept insulated from the thermal expansion metal layer to complete the device fabrication.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] First, the present invention provides a top P-type nanocrystalline diamond passivation thermal expansion layer on the surface of the gate-drain drift region of the lateral gallium oxide MOSFET. With high thermal conductivity expansion and heat dissipation functions as the main features, it can more effectively perform functional design on the hot spot area of ​​the device surface and significantly improve the problem of heat accumulation in the gate-drain region.

[0028] Secondly, because the present invention retains the MOS gate dielectric above the channel region, the top P-type nanocrystalline diamond passivation thermal expansion layer does not enter the gate control region of the channel region. This enhances the thermal management capability while avoiding damage to the main structure of the MOS gate control, thereby helping to maintain the original conduction and turn-off characteristics of the device.

[0029] Third, in this invention, the top P-type nanocrystalline diamond passivation thermal expansion layer is only locally distributed above the gate-drain drift region, and a drain-side gap is retained between its right end and the drain electrode, which is more conducive to surface thermal expansion and hot spot conduction, and also has a surface passivation effect. At the same time, it also improves the local surface electric field distribution to a certain extent, avoiding unnecessary parasitic effects introduced by the whole-surface covering structure.

[0030] Fourth, the present invention forms a top composite thermal expansion structure through a second passivation layer and a thermal expansion metal layer, wherein the thermal expansion metal layer is disposed above the second passivation layer and maintains an insulating distance from the three-terminal Pad of the metal electrode. While improving the surface protection capability of the device, it further enhances the top heat dissipation and working stability, significantly improving the reliability of the device in high voltage, high power and high temperature application environments. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall structure of the device of the present invention;

[0032] Figure 2 This is a schematic diagram of the fabrication process of the device of the present invention. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0034] Example 1: Refer to Appendix Figure 1 The present invention proposes a gallium oxide power device based on electric field-thermal field synergistic optimization of nanocrystalline diamond passivation. The device is a lateral gallium oxide metal oxide semiconductor field-effect transistor (MOSFET), which includes a substrate 1, a buffer layer 2, and a gallium oxide active layer 3 from bottom to top. The gallium oxide active layer 3 includes an n+ source region 31, a channel region 32, an n- drift region 33, and an n+ drain region 34 from left to right.

[0035] The n+ source region 31, channel region 32, and n+ drain region 34 are respectively provided with a source S, a MOS gate dielectric layer 4, and a drain D. The MOS gate dielectric layer 4 is provided with a gate G. The n- drift region 33 is provided with a top P-type nanocrystalline diamond passivation thermal expansion layer 6, and the two are in direct contact, which is used to enhance the thermal expansion and heat dissipation capabilities of the gate-drain drift region surface, and also has a surface passivation function. A drain-side gap region 7 is left between the right end of the top P-type nanocrystalline diamond passivation thermal expansion layer 6 and the drain D. The MOS gate dielectric layer 4 is provided between the channel region 32 and the gate G, which is used to realize the conduction and turn-off control of the channel region 32. The MOS gate dielectric layer 4 is not in direct contact with the source S.

[0036] The device is covered with a second passivation layer 8 to protect the surface area; and a thermal expansion metal layer 9 is provided on the second passivation layer 8 to enhance the thermal expansion capability of the top of the device; the source S, gate G and drain D are respectively led out to the upper surface of the second passivation layer 8 through corresponding vias.

[0037] In this embodiment, the substrate 1 is any one of a semi-insulating β-Ga₂O₃ substrate, a lightly doped β-Ga₂O₃ substrate, a SiC substrate, an AlN substrate, or a high thermal conductivity support substrate, used to provide mechanical support and a heat conduction channel; the buffer layer 2 is made of β-Ga₂O₃, used to improve epitaxial quality, reduce interface defects, and improve device structural stability. Preferably, a semi-insulating β-Ga₂O₃ or lightly doped β-Ga₂O₃ substrate with a thickness of 100 μm to 500 μm is used as the substrate; a β-Ga₂O₃ layer with a thickness of 0.1 μm to 2 μm is used as the buffer layer to improve the epitaxial quality of the upper gallium oxide active layer and reduce the interface defect density.

[0038] In this embodiment, the gallium oxide active layer 3 is made of n-type or unintentionally doped β-Ga₂O₃, with a total thickness of 50 nm to 1000 nm; wherein, the channel region 32 is made of n-type or unintentionally doped β-Ga₂O₃, with a donor concentration of 1 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The n-drift region 33 is made of lightly doped n-type β-Ga₂O₃ with a donor concentration of 1×10⁻⁶. 15 cm -3 ~1×10 17 cm -3 Both the n+ source region 31 and the n+ drain region 34 are heavily doped β-Ga2O3, with doping elements being Si, Sn, Ge, or a combination thereof, and a doping concentration of 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3Furthermore, the junction depth of the n+ source region 31 and the n+ drain region 34 is 20 nm to 300 nm.

[0039] In this embodiment, the MOS gate dielectric 4 is made of Al2O3, HfO2, SiO2, or SiN. x Or any one of the composite media thereof, with a thickness of 5 nm to 150 nm; the MOS gate dielectric 4 is only disposed on the surface of the channel region 32 directly below the gate metal G, and is used to control the conduction and turn-off of the channel region 32.

[0040] In this embodiment, the top P-type nanocrystalline diamond passivation thermal expansion layer 6 is a boron-doped nanocrystalline diamond thin layer with a thickness of 10 nm to 2000 nm and a length of 0.3 to 0.98 times the distance between the gate and drain. A drain-side gap region 7 with a width of 0.1 μm to 10 μm is retained between its right end and the drain D. Preferably, the thickness of the top P-type nanocrystalline diamond passivation thermal expansion layer 6 is 50 nm to 1000 nm, and the boron doping concentration is 1 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 The length of the top P-type nanocrystalline diamond passivation thermal expansion layer 6 is 0.3 to 0.98 times the distance between the gate metal G and the drain metal D, and it is only locally disposed above the gate-drain drift region. The left end of the top P-type nanocrystalline diamond passivation thermal expansion layer 6 is close to the drain edge of the gate metal G and does not cover the surface of the channel region 32. The right end retains a drain-side spacing region 7 between itself and the drain metal D. The width of the drain-side spacing region 7 is 0.1 μm to 5 μm. The top P-type nanocrystalline diamond passivation thermal expansion layer 6 is in direct contact with the lower n-drift region 33. It is mainly used to enhance the surface heat diffusion capability of the gate-drain region of the device and also has a surface passivation effect. Its improvement on the local surface electric field distribution is a side effect. In this embodiment, no special protective intermediate layer or coupling dielectric layer is provided between the top P-type nanocrystalline diamond passivation thermal expansion layer 6 and the n-drift region 33, so as to shorten the heat conduction path of the hot spot region and reduce the additional interface thermal resistance.

[0041] In this embodiment, the source S, gate G, and drain D are respectively led out to the upper surface of the second passivation layer 8 through corresponding vias. Specifically, the tops of the source S, gate G, and drain D are led out through the source connection via 10, the gate connection via 11, and the drain connection via 15, respectively. The ports led out to the upper surface of the second passivation layer 8 include the source lead-out Pad 12, the gate lead-out Pad 13, and the drain lead-out Pad 14. The source metal S and drain metal D are any one of Ti / Au, Ti / Al / Ni / Au, Ti / Pt / Au, or other metal systems that form a low contact resistance with β-Ga2O3; when the source metal S and drain metal D are Ti / Au metal stacks, their thickness is 20 nm~80 nm / 50 nm~300 nm; when the source metal S and drain metal D are Ti / Al / Ni / Au metal stacks, their thickness is 10 nm~50 nm / 50 nm~200 nm / 10 nm~60 nm / 50 nm~300 nm; the source metal S forms an ohmic contact with the n+ source region 31, and the drain metal D forms an ohmic contact with the n+ drain region 34. The gate G is made of any one of Ni / Au, Pt / Au, W / Au or other metal systems suitable for MOS gate structures; when the gate metal G is a Ni / Au or Pt / Au metal stack, its thickness is 20 nm~60 nm / 50 nm~200 nm; the gate metal G is located between the source metal S and the drain metal D, and is correspondingly disposed with the channel region 32 through the MOS gate dielectric 4 to control the conduction and turn-off of the channel region 32.

[0042] In this embodiment, a second passivation layer 8 and a thermally expandable metal layer 9 are further provided on the surface of the device; wherein, the second passivation layer 8 is made of SiO2 or SiN. x The material is selected from Al2O3 or its composite medium, and its thickness is 20 nm to 500 nm. The thermal expansion metal layer 9 is selected from Al, Cu, Ni / Au or Ti / Au, and its thickness is 50 nm to 1000 nm. The thermal expansion metal layer 9 is disposed above the second passivation layer 8 and spans above the gate drain region to further enhance the thermal expansion capability of the top of the device. It is preferably a floating structure and maintains an insulating distance from each of the top lead-out Pads.

[0043] The top P-type nanocrystalline diamond passivation thermal expansion layer 6 preferably adopts a floating structure, meaning that the top P-type nanocrystalline diamond passivation thermal expansion layer 6 does not form a direct electrical connection with the source S, gate G, drain D, source lead-out Pad 12, gate lead-out Pad 13, and drain lead-out Pad 14; the thermal expansion metal layer 9 is isolated from the top P-type nanocrystalline diamond passivation thermal expansion layer 6 by a second passivation layer 8; the source, gate, and drain are led out to the top Pad through source connection via 10, gate connection via 11, and drain connection via 15, respectively. With this structure, hot spots in the gate-drain region can be efficiently channeled while maintaining the MOS gate control characteristics in the channel region, and the surface electric field distribution in the gate-drain region can be improved to a certain extent.

[0044] Example 2: Refer to Figure 2 This embodiment proposes a method for fabricating gallium oxide power devices based on the synergistic optimization of electric and thermal fields using nanocrystalline diamond passivation, specifically including the following steps:

[0045] Step 1) Select a substrate material and pretreat it to form a β-Ga2O3 buffer layer and a gallium oxide active layer on its surface;

[0046] Step 2) Construct an n+ source region, a channel region, an n- drift region, and an n+ drain region in the gallium oxide active layer, and deposit a MOS gate dielectric on the surface of the channel region;

[0047] Step 3) Form gate metal G on the MOS gate dielectric, and simultaneously form source metal S and drain metal D on the surfaces of the n+ source region and n+ drain region, respectively;

[0048] Step 4) The surface of the n-drift region between the gate G drain side and the drain D is patterned and pre-processed. A boron-doped nanocrystalline diamond thin layer is directly formed in this region. A top P-type nanocrystalline diamond passivation thermal expansion layer is obtained by patterning process, which only locally covers the gate-drift region. At the same time, its left end is controlled to be close to the gate G drain side edge and not enter the channel region, while the right end is kept at a distance from the drain D to form a drain side gap region. In this embodiment, in this step, only the surface of the n-drift region between the gate G drain side and the drain D is windowed and pre-processed. A top P-type nanocrystalline diamond passivation thermal expansion layer is directly formed in this windowed area. No protective intermediate layer or coupling dielectric layer is set between the top P-type nanocrystalline diamond passivation thermal expansion layer and the n-drift region, and its left end is close to the gate G drain side edge without covering the channel region surface and the area where the MOS gate dielectric layer is located.

[0049] In this embodiment, the thickness of the boron-doped nanocrystalline diamond thin layer formed above is 10 nm to 2000 nm, and the boron doping concentration is 1 × 10⁻⁶. 18 cm -3 ~5×10 20cm -3 And a drain-side gap region with a width of 0.1 μm to 10 μm is reserved between its right end and the drain D; the thermally extended metal layer formed in step (6) is located above the second passivation layer and is insulated from the source lead-out Pad12, the gate lead-out Pad13 and the drain lead-out Pad14, and is not electrically connected to the source S, the gate G and the drain D through the connecting via.

[0050] Step 5) A second passivation layer is formed on the device surface obtained in step 4), and the lead-out regions of the source, gate, and drain are patterned and opened to form source, gate, and drain connection vias, respectively.

[0051] Step 6) A thermal expansion metal layer, source lead-out Pad12, gate lead-out Pad13, and drain lead-out Pad14 are formed above the second passivation layer. The three are connected to the lower electrode through corresponding connecting vias and are kept insulated from the thermal expansion metal layer to complete the device fabrication.

[0052] Example 3: The overall implementation process of the preparation method proposed in this example is the same as in Example 2, and will now be referred to... Figure 2 The specific process steps for fabricating the final device are given below: after pretreating the surface of the gate-drain drift region, a localized top P-type nanocrystalline diamond passivation thermal expansion layer 6 is directly formed on the surface of the n-drift region 33, and a second passivation layer 8 and a thermal expansion metal layer 9 are further formed on top of it.

[0053] Step 1: Substrate preparation and formation of gallium oxide-based active structures, such as... Figure 2 (a) in the middle.

[0054] 1.1) A semi-insulating 4H-SiC substrate 1 with a thickness of 350 μm was selected and subjected to organic ultrasonic cleaning with acetone, isopropanol and deionized water in sequence. The cleaning times were 15 min, 10 min and 5 min respectively, and the ultrasonic power was 100 W. After cleaning, the substrate surface was dried with N2 and baked on a hot plate at 150℃ for 10 min to remove surface adsorbed water and organic residues.

[0055] 1.2) Select a pre-prepared β-Ga2O3 epitaxial wafer, which comprises, from bottom to top, an unintentionally doped β-Ga2O3 buffer layer 2 with a thickness of 0.3 μm and an n-type β-Ga2O3 active layer 3 with a thickness of 0.8 μm, wherein the donor concentration of the n-type β-Ga2O3 active layer 3 is 8 × 10⁻⁶. 16 cm -3 .

[0056] 1.3) The pre-prepared β-Ga2O3 structure layer was transferred to the surface of 4H-SiC substrate 1 using a surface activation bonding process. Before bonding, the surface of 4H-SiC substrate 1 and the back side of the β-Ga2O3 buffer layer 2 were subjected to Ar plasma activation treatment at a power of 80 W for 60 s. Subsequently, under a vacuum degree better than 5 × 10⁻⁶, the pre-prepared β-Ga2O3 structure layer was transferred to the surface of 4H-SiC substrate 1. Before bonding, the surface of 4H-SiC substrate 1 and the back side of β-Ga2O3 buffer layer 2 were subjected to Ar plasma activation treatment at a power of 80 W for 60 s. -3 Room temperature prebonding was performed under Pa conditions, followed by annealing at 300°C for 30 min to enhance interfacial bonding strength and improve the adhesion stability of the transfer layer.

[0057] 1.4) The transferred β-Ga2O3 structure layer was subjected to mechanical thinning and chemical mechanical polishing (CMP) treatment. The mechanical thinning rate was controlled at 0.5 μm / min, the CMP polishing slurry particle size was 50 nm, the polishing pressure was 2 psi, and the polishing time was 10 min, in order to obtain a flat β-Ga2O3 active layer surface with a surface roughness of less than 2 nm.

[0058] 1.5) After the above process, the basic structure of buffer layer 2 and gallium oxide active layer 3 is prepared on substrate 1, providing a flat semiconductor surface with high interface quality for subsequent active region formation, MOS gate structure fabrication and gate-drain thermal expansion functional layer integration.

[0059] Step 2: Active region construction and MOS gate dielectric formation, such as Figure 2 (b) in the middle.

[0060] 2.1) A positive photoresist was spin-coated onto the surface of the β-Ga2O3 active layer 3 at a spin speed of 3000 rpm for 30 s, followed by pre-baking at 100°C for 90 s; the source and drain windows were defined by exposure and development processes.

[0061] 2.2) The n+ source region 31 and n+ drain region 34 were formed using Si ion implantation. The implantation employed a dual-energy process, with the first-stage implantation energy at 60 keV and the implantation dose at 2 × 10⁻⁶. 14 cm -2 The second-stage injection energy was 120 keV, and the injection dose was 3 × 10⁻⁶. 14 cm -2 The implantation tilt angle was 7° to suppress the channel effect and improve the vertical doping distribution. The equivalent doping concentration in the n+ region after implantation was controlled to be 5 × 10⁻⁶. 19 cm -3 .

[0062] 2.3) The injected sample was placed in a rapid thermal annealing furnace under N2 atmosphere for activation annealing at a temperature of 900℃ for 60 s, in order to activate the injected impurities and reduce the contact resistance of the source and drain regions.

[0063] 2.4) Al₂O₃ was deposited as the MOS gate dielectric 4 on the surface of the channel region 32 using atomic layer deposition (ALD) technology. The deposition temperature was 250 °C, and the precursors used were trimethylaluminum (TMA) and deionized water (H₂O). The deposition thickness per cycle was approximately 1 Å, and the total number of deposition cycles was 250, resulting in a 25 nm thick Al₂O₃ layer. This MOS gate dielectric 4 is located only in the region directly below the gate metal G and does not extend to the surface of the n-drift region 33.

[0064] 2.5) After the above steps, the basic region distribution of n+ source region 31, channel region 32, n- drift region 33 and n+ drain region 34 is formed in the gallium oxide active layer 3, and the MOS gate dielectric 4 is fabricated on the surface of the channel region 32, thereby establishing the basic active region structure of the lateral gallium oxide MOSFET.

[0065] Step 3: Gate metal and source / drain metal formation, such as Figure 2 (c) in the middle.

[0066] 3.1) The gate region was defined by photolithography, and Ni / Au gate metal was deposited using electron beam evaporation (E-Beam) process, with thicknesses of 40 nm and 150 nm, respectively; the evaporation vacuum degree was better than 2 × 10⁻⁶. -4 Pa, the electron gun acceleration voltage is 6 kV, and the gate metal G is formed by a stripping process after deposition.

[0067] 3.2) The source and drain contact windows are defined by a second photolithography process. Then, Ti / Al / Ni / Au metal layers with thicknesses of 20 nm, 100 nm, 30 nm and 150 nm are deposited sequentially by electron beam evaporation to form source metal S and drain metal D. After deposition, excess metal is removed by a lift-off process.

[0068] 3.3) The sample after forming the source metal S and drain metal D was placed in a N2 atmosphere for rapid thermal annealing at a temperature of 470°C for 60 s to improve the ohmic contact characteristics between the metal and the n+ source region 31 and the n+ drain region 34.

[0069] 3.4) After the above steps, the basic three-terminal electrode structure of the lateral gallium oxide MOSFET is fabricated, so that the source metal S, gate metal G and drain metal D establish corresponding structural relationships with the source region, channel region and drain region of the device, respectively.

[0070] Step 4: Formation of a localized top P-type nanocrystalline diamond passivation thermal extension layer, such as... Figure 2 (d) in the middle.

[0071] 4.1) A temporary high-temperature resistant hard mask layer is formed on the device surface. Then, the n-drift region 33 surface window between the drain side of the gate metal G and the drain metal D is defined by photolithography. The temporary high-temperature resistant hard mask layer is selectively etched to expose the n-drift region 33 surface where the top P-type nanocrystalline diamond passivation thermal extension layer 6 is to be formed. After etching, the photoresist is removed, leaving only the patterned temporary high-temperature resistant hard mask layer.

[0072] 4.2) To improve the nucleation density of nanocrystalline diamond on the β-Ga2O3 surface, the exposed n-drift region 33 surface was first cleaned and activated, and then the sample was immersed in a suspension containing nanocrystalline diamond particles for ultrasonic treatment for 20 min; subsequently, it was rinsed with deionized water and dried with N2.

[0073] 4.3) A boron-doped nanocrystalline diamond thin layer was directly deposited on the exposed n-drift region 33 using a low-temperature microwave plasma chemical vapor deposition (MPCVD) process. The deposition temperature was 450℃, the chamber pressure was 40 Torr, the microwave power was 1200 W, the reaction gas was a mixture of H2 / CH4 / B2H6, with a CH4 volume fraction of 1.5% and a B2H6 / H2 doping ratio controlled at 3000 ppm. The deposition time was 90 min, forming a boron-doped nanocrystalline diamond thin layer with a thickness of 300 nm.

[0074] 4.4) After deposition, the temporary high-temperature resistant hard mask layer and any remaining boron-doped nanocrystalline diamond material on its surface are removed. The edges of the boron-doped nanocrystalline diamond thin layer are then trimmed using O2 / Ar mixed plasma as needed, thereby forming a localized top P-type nanocrystalline diamond passivation thermal expansion layer 6. The left end of the top P-type nanocrystalline diamond passivation thermal expansion layer 6 is located near the drain edge of the gate metal G. Its left end can be adjacent to or aligned with the drain edge of the MOS gate dielectric layer 4 in the lateral direction, but it does not cover the MOS gate dielectric layer 4, does not enter the channel region 32, and does not directly contact the gate metal G. A drain-side gap region 7 with a width of 1 μm is retained between the right end and the drain metal D.

[0075] 4.5) After the above steps, a local top P-type nanocrystalline diamond passivation thermal expansion layer 6 is formed on the surface of the n-drift region 33. This layer does not cover the MOS gate dielectric layer 4 and does not enter the channel region 32. This provides a basis for the subsequent top passivation and thermal expansion metal structure, and at the same time enables the device gate drain region to have stronger surface thermal expansion and heat dissipation capabilities.

[0076] Step 5: Formation of the second passivation layer and opening of the lead-out region, such as... Figure 2 (e) in the middle.

[0077] 5.1) SiN is deposited on the device surface using PECVD process. x As the second passivation layer 8, the deposition temperature was 300℃, the SiH4 flow rate was 15 sccm, the NH3 flow rate was 25 sccm, the RF power was 100 W, the cavity pressure was 100 Pa, and the deposition time was 10 min, forming a SiN layer with a thickness of 120 nm. x Thin layer.

[0078] 5.2) The source connection via 10, the gate connection via 11, and the drain connection via 15 are defined by photolithography. Then, the second passivation layer 8 is selectively etched with CHF3 / O2 plasma to expose the lead-out regions corresponding to the source metal S, the gate metal G, and the drain metal D.

[0079] 5.3) Based on the device design requirements, further define the layout areas of source lead-out Pad12, gate lead-out Pad13 and drain lead-out Pad14 to provide an interconnection basis for the subsequent formation of the three-terminal lead-out structure and the top thermal expansion metal layer 9.

[0080] 5.4) The device was placed in a N2 atmosphere for low-temperature annealing at a temperature of 300°C for 20 min to reduce the residual stress in the second passivation layer 8 and the surface functional layer, and to further stabilize the interface state.

[0081] 5.5) After the above steps, the device surface passivation and the preparation of the three-terminal lead-out channel structure are completed, thereby providing a reliable insulation and interface foundation for the formation of the top thermal expansion metal layer 9 and the external interconnect structure.

[0082] Step 6: Formation of thermally expanded metal layer and lead-out pad, such as Figure 2 (f) in the middle.

[0083] 6.1) Source connection via 10, gate connection via 11, and drain connection via 15 are formed using a conductive material filling process. Preferably, a Ti / Cu seed layer is first formed by sputtering, then Cu electroplating or W chemical vapor deposition is used to fill the vias, and finally CMP is used to remove excess metal from the surface.

[0084] 6.2) The source lead-out Pad12, gate lead-out Pad13 and drain lead-out Pad14 regions are defined by photolithography. Ti / Au metal layers with thicknesses of 50 nm and 500 nm are deposited by electron beam evaporation process, and three-terminal lead-out Pads are formed by lift-off process.

[0085] 6.3) A positive photoresist is spin-coated onto the surface of the second passivation layer 8, and the patterned area of ​​the thermally extended metal layer 9 is defined by exposure and development. The thermally extended metal layer 9 covers the gate-drain region and maintains an insulating distance from the source lead-out Pad 12, gate lead-out Pad 13, and drain lead-out Pad 14. Subsequently, Ti / Au metal layers with thicknesses of 50 nm and 500 nm are deposited using an electron beam evaporation process, and the thermally extended metal layer 9 is formed by a lift-off process.

[0086] 6.4) The device was placed in a N2 atmosphere for low-temperature annealing at a temperature of 300°C for 20 min to reduce the residual stress between the top P-type nanocrystalline diamond passivation thermal expansion layer 6, the second passivation layer 8 and the thermal expansion metal layer 9, and to further stabilize the interface state.

[0087] 6.5) After annealing, the device surface is cleaned. The cleaning solution is acetone, isopropanol and deionized water in sequence. After cleaning, it is dried with N2. Finally, a gallium oxide power device with nanocrystalline diamond passivation with top P-type nanocrystalline diamond passivation thermal extension layer 6, second passivation layer 8 and thermal extension metal layer 9 is obtained. The device is designed for electric field and thermal field co-optimization.

[0088] Example 4: Refer to Figure 1 and Figure 2 The overall structure of the device proposed in this embodiment is the same as in Embodiment 1, and its basic fabrication process is the same as in Embodiment 2. Further details regarding the relevant materials and specific parameters are provided below, with preferred examples to further illustrate the specific structure and process parameters of the final device prepared using the method of this invention:

[0089] Reference Figure 1 The device provided in this embodiment includes a substrate 1, a buffer layer 2, a gallium oxide active layer 3, a MOS gate dielectric 4, a top P-type nanocrystalline diamond passivation thermal expansion layer 6, a drain-side spacer region 7, a second passivation layer 8, a thermal expansion metal layer 9, a source connection via 10, a gate connection via 11, a drain connection via 15, a source lead-out Pad 12, a gate lead-out Pad 13, a drain lead-out Pad 14, and a source metal S, a gate metal G, and a drain metal D disposed on the surface of the gallium oxide active layer 3. Wherein:

[0090] The substrate 1 is made of semi-insulating 4H-SiC with a thickness of 350 μm; the buffer layer 2 is made of β-Ga₂O₃ with a thickness of 0.30 μm; the gallium oxide active layer 3 is made of n-type β-Ga₂O₃ with a total thickness of 0.80 μm and a donor concentration of 8 × 10⁻⁶. 16 cm -3 The n+ source region 31 and n+ drain region 34 are formed by Si ion implantation, and the equivalent doping concentration after activation is 5 × 10⁻⁶. 19 cm -3The junction depth is 120 nm; the equivalent donor concentration of the n-drift region 33 is controlled at 8 × 10⁻⁶. 16 cm -3 The MOS gate dielectric 4 is made of Al2O3 with a thickness of 25 nm; the top P-type nanocrystalline diamond passivation thermal extension layer 6 is a boron-doped nanocrystalline diamond thin layer with a thickness of 300 nm and a boron doping concentration of 1×10⁻⁶. 19 cm -3 The top P-type nanocrystalline diamond passivation thermal extension layer 6 is directly located on the surface of the n-drift region 33, and its length is 0.75 times the distance between the gate metal G and the drain metal D; its left end is 0.2 μm from the drain edge of the gate metal G, and its right end retains a drain-side gap region 7 with a width of 1.0 μm between it and the drain metal D; the second passivation layer 8 is made of SiN x The thickness of the thermal expansion metal layer 9 is 180 nm; the thermal expansion metal layer 9 is located above the second passivation layer 8, and adopts a Ti / Au metal stack with a thickness of 50 nm / 500 nm, and a total thickness of 550 nm; the thermal expansion metal layer 9 is disposed above the second passivation layer 8 and extends across the gate and drain regions to enhance the thermal expansion and surface protection capabilities of the top of the device; the thermal expansion metal layer 9 preferably adopts a floating structure and maintains an insulating distance from the source lead-out Pad12, the gate lead-out Pad13 and the drain lead-out Pad14, and is not directly electrically connected to the source metal S, the gate metal G and the drain metal D through a connecting via;

[0091] The source connection via 10, gate connection via 11, and drain connection via 15 all employ conductive filled via structures with a aperture of 1.0 μm. The source lead-out Pad 12, gate lead-out Pad 13, and drain lead-out Pad 14 all utilize Ti / Au metal stacks with thicknesses of 50 nm / 500 nm. The source connection via 10, gate connection via 11, and drain connection via 15 are only used for the top leads of the source metal S, gate metal G, and drain metal D, respectively. The thermally extended metal layer 9 is not connected to the three-terminal electrodes through these connection vias.

[0092] Reference Figure 2 This embodiment provides a specific implementation process for preparing the device described in this embodiment. Unless otherwise specified, the experimental methods described are conventional methods, and the reagents and materials described are commercially available unless otherwise specified.

[0093] Step A: Select a substrate and form a buffer layer and a gallium oxide active layer:

[0094] A1) A semi-insulating 4H-SiC substrate with a thickness of 350 μm was selected as substrate 1. It was cleaned by organic ultrasonic cleaning with acetone, isopropanol and deionized water in sequence for 15 min, 10 min and 5 min respectively, with an ultrasonic power of 100 W. After cleaning, the substrate surface was dried with N2 and baked on a hot plate at 150℃ for 10 min to remove residual moisture on the surface and improve the stability of the subsequent bonding interface.

[0095] A2) Select a pre-prepared β-Ga2O3 epitaxial wafer, wherein the epitaxial wafer comprises, from bottom to top, an unintentionally doped β-Ga2O3 buffer layer 2 with a thickness of 0.30 μm and an n-type β-Ga2O3 active layer 3 with a thickness of 0.80 μm, wherein the donor concentration of the n-type β-Ga2O3 active layer 3 is 8 × 10⁻⁶. 16 cm -3 .

[0096] A3) The β-Ga2O3 structure layer was transferred to the surface of the semi-insulating 4H-SiC substrate 1 using a surface activation bonding process. Before bonding, the surface of the 4H-SiC substrate 1 and the back side of the β-Ga2O3 buffer layer 2 were subjected to Ar plasma activation treatment at a power of 80 W for 60 s; subsequently, under a vacuum degree better than 5 × 10⁻⁶ W, the β-Ga2O3 structure layer was transferred to the surface of the semi-insulating 4H-SiC substrate 1. -3 Room temperature prebonding was performed under Pa conditions, followed by annealing at 300℃ for 30 min to enhance interfacial bonding strength.

[0097] A4) The transferred β-Ga2O3 structure layer was subjected to mechanical thinning and chemical mechanical polishing (CMP) treatment. The mechanical thinning rate was controlled at 0.5 μm / min, the CMP polishing pressure was 2 psi, and the polishing time was 10 min, so that the surface roughness of the β-Ga2O3 active layer 3 was less than 2 nm, in order to meet the surface flatness requirements of subsequent MOS gate dielectric and top P-type nanocrystalline diamond passivation thermal extension layer deposition.

[0098] Through step A above, a buffer layer 2 with controlled thickness and doping and a gallium oxide active layer 3 are formed on substrate 1, which lays a stable semiconductor foundation for the subsequent construction of n+ source region 31, channel region 32, n- drift region 33 and n+ drain region 34, and also ensures that the device has good thermal support conditions and interface quality.

[0099] Step B: Construct the n+ source region, channel region, n- drift region, and n+ drain region in the gallium oxide active layer, and deposit the MOS gate dielectric on the surface of the channel region:

[0100] B1) A positive photoresist was spin-coated onto the surface of the β-Ga2O3 active layer 3 at a spin speed of 3000 rpm for 30 s, followed by pre-baking at 100°C for 90 s; the ion implantation windows of the n+ source region 31 and the n+ drain region 34 were defined by exposure and development.

[0101] B2) The n+ source region 31 and n+ drain region 34 are formed using Si ion implantation. A dual-energy implantation process is employed, with the first-stage implantation energy at 60 keV and the implantation dose at 2 × 10⁻⁶. 14 cm -2 The second-stage injection energy was 120 keV, and the injection dose was 3 × 10⁻⁶. 14 cm -2 The implantation tilt angle is 7° to reduce the channel effect and improve the uniformity of doping distribution.

[0102] B3) The implanted sample was placed in a rapid thermal annealing furnace under N2 atmosphere for annealing at 900℃ for 60 s to activate the implanted impurities and achieve an equivalent doping concentration of 5×10⁻⁶. 19 cm -3 The system includes an n+ source region 31 and an n+ drain region 34 with a junction depth of approximately 120 nm. The undoped intermediate regions serve as the channel region 32 and the n-drift region 33, respectively, with the equivalent donor concentration of the n-drift region 33 controlled at 8 × 10⁻⁶. 16 cm -3 .

[0103] B4) The surface of the channel region 32 was patterned using photolithography, retaining only the area directly below the gate as the MOS gate dielectric deposition window. Subsequently, an atomic layer deposition (ALD) process was used to deposit a thin Al2O3 layer on the surface of the channel region 32 as the MOS gate dielectric 4. The deposition temperature was 250℃, the precursors were trimethylaluminum (TMA) and deionized water (H2O), the deposition thickness per cycle was approximately 1 Å, and the total number of deposition cycles was 250, ultimately forming an Al2O3 gate dielectric layer with a thickness of 25 nm.

[0104] Through step B above, heavily doped n+ source region 31 and n+ drain region 34 are formed in gallium oxide active layer 3, and the channel region 32 and n- drift region 33 connected to them are retained. At the same time, a position-restricted and thickness-controlled MOS gate dielectric 4 is formed on the surface of channel region 32, thus providing a foundation for the subsequent fabrication of three-terminal MOSFET electrode structure and gate-drain thermal expansion functional layer.

[0105] Step C: Forming the gate metal, source metal, and drain metal:

[0106] C1) The gate region was defined by photolithography, and Ni / Au metal layers were deposited using an electron beam evaporation (E-Beam) process with thicknesses of 40 nm and 150 nm, respectively; the evaporation vacuum degree was better than 2 × 10⁻⁶. -4 Pa, the electron gun acceleration voltage is 6 kV, and the gate metal G is formed by a stripping process after deposition.

[0107] C2) The source and drain contact areas are defined by a second photolithography process. Ti / Al / Ni / Au metal layers with thicknesses of 20 nm, 100 nm, 30 nm and 150 nm are deposited sequentially by electron beam evaporation to form source metal S and drain metal D. After deposition, excess metal is removed by a lift-off process.

[0108] (C3) The sample after forming the source metal S and drain metal D is placed in an N2 atmosphere for rapid thermal annealing at a temperature of 470°C for 60 s to improve the ohmic contact characteristics between the source metal S, drain metal D and the n+ source region 31 and n+ drain region 34. Through the above step C, the fabrication of the lateral gallium oxide MOSFET three-terminal electrode structure is completed.

[0109] Step D: Forming the top P-type nanocrystalline diamond passivation thermal expansion layer:

[0110] D1) A temporary high-temperature resistant hard mask layer is formed on the device surface, and an opening window is formed on the surface of the n-drift region 33 between the gate metal G drain side and the drain metal D through photolithography and selective etching processes. Then the photoresist is removed, leaving only the patterned temporary high-temperature resistant hard mask layer.

[0111] D2) Surface pre-cleaning, activation and nanodiamond seeding treatment are performed on the exposed n-drift region 33 to improve the nucleation density and adhesion stability of nanocrystalline diamond on the β-Ga2O3 surface.

[0112] D3) A boron-doped nanocrystalline diamond thin layer was directly deposited on the exposed n-drift region 33 using a low-temperature microwave plasma chemical vapor deposition (MPCVD) process. The deposition temperature was 450℃, the chamber pressure was 40 Torr, the microwave power was 1200 W, the reaction gas was a mixture of H2 / CH4 / B2H6, with a CH4 volume fraction of 1.5% and a B2H6 / H2 doping ratio controlled at 3000 ppm. The deposition time was 90 min, forming a boron-doped nanocrystalline diamond thin layer with a thickness of 300 nm.

[0113] D4) Remove the temporary high-temperature resistant hard mask layer and the boron-doped nanocrystalline diamond material remaining on its surface to form a localized top P-type nanocrystalline diamond passivation thermal expansion layer 6. The top P-type nanocrystalline diamond passivation thermal expansion layer 6 is located near the drain edge of the gate metal G on the left side, and does not cover the MOS gate dielectric layer 4, does not enter the channel region 32, and does not directly contact the gate metal G; a drain-side gap region 7 with a width of 1 μm is retained between the right end and the drain metal D.

[0114] Through step D above, a localized top P-type nanocrystalline diamond passivation thermal expansion layer 6 is formed on the surface of the n-drift region 33. This structure is mainly used to enhance the surface thermal expansion and heat dissipation capabilities of the gate-drain drift region, and also has a surface passivation effect. Its improvement on the local surface electric field distribution is a side effect.

[0115] Step E: Further form a second passivation layer on the device surface and create an lead-out region:

[0116] E1) SiN is deposited on the device surface using PECVD process. x As the second passivation layer 8, the deposition temperature was 300℃, the SiH4 flow rate was 15 sccm, the NH3 flow rate was 25 sccm, the RF power was 100 W, the cavity pressure was 100 Pa, and the deposition time was 15 min, forming a SiN layer with a thickness of 180 nm. x Thin layer.

[0117] E2) The source connection via 10, the gate connection via 11, and the drain connection via 15 are defined by photolithography. Then, the second passivation layer 8 is selectively etched using CHF3 / O2 plasma to expose the lead-out areas corresponding to the source metal S, the gate metal G, and the drain metal D.

[0118] E3) Based on the device design requirements, further define the layout areas of source lead-out Pad12, gate lead-out Pad13 and drain lead-out Pad14 to provide an interconnection basis for the subsequent formation of a three-terminal lead-out structure and the top thermal expansion metal layer 9.

[0119] E4) Through the above step E, the construction of the second passivation layer 8 and the lead-out channel structure is completed, thereby providing surface insulation and interconnection conditions for the subsequent formation of the thermal expansion metal layer 9 and device integration.

[0120] Step F: Form the thermally expanded metal layer and lead-out pads to complete device fabrication.

[0121] F1) The source connection via 10, the gate connection via 11, and the drain connection via 15 are formed using a conductive material filling process. Preferably, a Ti / Cu seed layer is first formed by sputtering, then the vias are filled by Cu electroplating or W chemical vapor deposition, and finally excess metal on the surface is removed by CMP.

[0122] F2) The source lead-out Pad12, gate lead-out Pad13 and drain lead-out Pad14 regions are defined by photolithography. Ti / Au metal layers with thicknesses of 50 nm and 500 nm are deposited by electron beam evaporation process, and three-terminal lead-out Pads are formed by lift-off process.

[0123] (F3) Positive photoresist is spin-coated onto the surface of the second passivation layer 8, and the patterned area of ​​the thermally extended metal layer 9 is defined by exposure and development. This area covers the gate and drain regions and maintains an insulating distance from the source lead-out Pad12, gate lead-out Pad13, and drain lead-out Pad14. Subsequently, Ti / Au metal layers with thicknesses of 50 nm and 500 nm are deposited using an electron beam evaporation process, and the thermally extended metal layer 9 is formed by a lift-off process.

[0124] F4) The device was placed in a N2 atmosphere for low-temperature annealing at a temperature of 300°C for 20 min to reduce the residual stress between the second passivation layer 8, the top P-type nanocrystalline diamond passivation thermal expansion layer 6 and the thermal expansion metal layer 9, and to further stabilize the interface state. After annealing, the device surface was cleaned sequentially with acetone, isopropanol and deionized water, and then dried with N2.

[0125] (F5) Through the above steps, a composite thermally extended gallium oxide power device is finally obtained, comprising a top P-type nanocrystalline diamond passivation thermal extension layer 6, a second passivation layer 8, a thermal extension metal layer 9, and a three-terminal independent lead-out structure. The thermal extension metal layer 9 preferably adopts a floating structure and maintains an insulating distance from the source lead-out Pad12, gate lead-out Pad13, and drain lead-out Pad14. This structure prioritizes high thermal conductivity for heat dissipation and thermal extension, while also considering surface passivation and assisting in improving the surface electric field distribution.

[0126] The above descriptions are merely a few specific examples of the present invention and do not constitute any limitation on the present invention. For those skilled in the art, after understanding the content and principles of the present invention, various modifications and changes can be made to its form and details without departing from the principles and essence of the present invention. For example, the substrate can be AlN or other highly insulating and highly thermally conductive support materials, in addition to semi-insulating β-Ga2O3, lightly doped β-Ga2O3, and 4H-SiC; the buffer layer and gallium oxide active layer can be gallium oxide semiconductor layers formed with different doping concentrations, different thicknesses, or different epitaxial methods, in addition to β-Ga2O3, according to device design requirements; the MOS gate dielectric can be HfO2, SiO2, or SiN, in addition to Al2O3. xIts composite medium; the top P-type nanocrystalline diamond passivation thermal extension layer can be made of boron-doped nanocrystalline diamond thin layer, and its thickness, length, doping concentration and local coverage can be adjusted according to the device's withstand voltage level, thermal management requirements and surface electric field improvement requirements; the second passivation layer can be made of SiO2, SiN x Besides Al2O3 and its composite media, other dielectric materials with both insulating and surface protection capabilities can also be used. The thermal expansion metal layer can be made of metal systems such as Al, Cu, Ni / Au, and Ti / Au, or other suitable metal or alloy systems selected according to thermal conductivity requirements and process compatibility. The top P-type nanocrystalline diamond passivation thermal expansion layer 6 is preferably a locally floating structure that is in direct contact with the n-drift region 33 and does not cover the surface of the channel region 32. The thermal expansion metal layer 9 is preferably configured as an independent top metal pattern located above the second passivation layer 8 and insulated from the source lead-out Pad 12, gate lead-out Pad 13, and drain lead-out Pad 14, to further enhance the top thermal expansion capability and avoid electrical connection interference to the three-terminal lead-out structure. However, these modifications and changes based on the inventive concept are still within the scope of protection of the claims of this invention.

Claims

1. A gallium oxide power device based on electric field-thermal field synergistic optimization using nanocrystalline diamond passivation, characterized in that: The device is a lateral gallium oxide metal oxide semiconductor field-effect transistor (MOSFET), which includes a substrate (1), a buffer layer (2), and a gallium oxide active layer (3) from bottom to top. The gallium oxide active layer (3) includes an n+ source region (31), a channel region (32), an n- drift region (33), and an n+ drain region (34) from left to right. The n+ source region (31), channel region (32), and n+ drain region (34) are respectively provided with a source S, a MOS gate dielectric layer (4), and a drain D. The MOS gate dielectric layer (4) is provided with a gate G. The n- drift region (33) is provided with a top P-type nanocrystalline diamond passivation thermal expansion layer (6), and the two are in direct contact. This layer is used to enhance the thermal expansion and heat dissipation capabilities of the gate-drain drift region surface and also has a surface passivation effect. A drain-side gap region (7) is left between the right end of the top P-type nanocrystalline diamond passivation thermal expansion layer (6) and the drain D. The MOS gate dielectric layer (4) is provided between the channel region (32) and the gate G to realize the conduction and turn-off control of the channel region (32). The MOS gate dielectric layer (4) is not in direct contact with the source S. The device is covered with a second passivation layer (8) to protect the surface area; and a thermal expansion metal layer (9) is provided on the second passivation layer (8) to enhance the thermal expansion capability of the top of the device; the source S, gate G and drain D are respectively led out to the upper surface of the second passivation layer (8) through corresponding vias.

2. The device according to claim 1, characterized in that: The substrate (1) is any one of a semi-insulating β-Ga2O3 substrate, a low-doped β-Ga2O3 substrate, a SiC substrate, an AlN substrate, or a high thermal conductivity support substrate, used to provide mechanical support and thermal conduction channels; the buffer layer (2) is β-Ga2O3, used to improve epitaxial quality, reduce interface defects and improve device structural stability.

3. The device of claim 1, wherein: The channel region (32) and the n-drift region (33) are both n-type or unintentionally doped β-Ga2O3; the n+ source region (31) and the n+ drain region (34) are heavily doped β-Ga2O3 regions.

4. The device of claim 1, wherein: The MOS gate dielectric layer (4) is made of Al2O3, HfO2, SiO2, and SiN. x Or any one of its composite media, with a thickness of 5 nm to 150 nm.

5. The device of claim 1, wherein: The top P-type nanocrystalline diamond passivation thermal extension layer (6) is a boron-doped nanocrystalline diamond thin layer with a thickness of 10 nm to 2000 nm and a length of 0.3 to 0.98 times the distance between the gate and the drain; a drain-side gap region (7) with a width of 0.1 μm to 10 μm is reserved between its right end and the drain D.

6. The device of claim 1, wherein: The source S, gate G and drain D are respectively led out to the upper surface of the second passivation layer (8) through corresponding vias. Specifically, the tops of the source S, gate G and drain D are led out through the source connection via (10), gate connection via (11) and drain connection via (15). The ports led out to the upper surface of the second passivation layer (8) include the source lead-out Pad12, the gate lead-out Pad13 and the drain lead-out Pad14.

7. The device of claim 6, wherein: The thermally extended metal layer (9) adopts a floating structure and maintains an insulating distance from the source lead-out Pad12, the gate lead-out Pad13 and the drain lead-out Pad14.

8. A method for preparing gallium oxide power devices based on the synergistic optimization of electric field-thermal field by nanocrystalline diamond passivation, characterized in that, Includes the following steps: (1) Select a substrate material and pre-treat it to form a β-Ga2O3 buffer layer and a gallium oxide active layer on its surface; (2) Construct an n+ source region, a channel region, an n- drift region and an n+ drain region in the gallium oxide active layer, and deposit a MOS gate dielectric on the surface of the channel region; (3) A gate G metal is formed on the MOS gate dielectric, and a source S metal and a drain D metal are formed on the surfaces of the n+ source region and the n+ drain region, respectively. (4) Define the pattern and pre-process the surface of the n-drift region between the gate G drain side and the drain D. In this region, a boron-doped nanocrystalline diamond thin layer is directly formed. The top P-type nanocrystalline diamond passivation thermal expansion layer that only locally covers the gate-drain drift region is obtained through the patterning process. At the same time, its left end is controlled to be close to the gate G drain side edge and not enter the channel region, and the right end is kept at a distance from the drain D to form a drain side gap region. (5) A second passivation layer is formed on the device surface obtained in step (4), and the lead-out areas of the source, gate and drain are patterned and opened to form source, gate and drain connection vias respectively. (6) A thermal expansion metal layer and source lead-out Pad12, gate lead-out Pad13 and drain lead-out Pad14 are formed above the second passivation layer. The three are connected to the lower electrode through corresponding connection vias and are kept insulated from the thermal expansion metal layer to complete the device fabrication.

9. The method of claim 8, wherein: In step (4), only the surface of the n-drift region between the drain side of the gate G and the drain D is windowed and pre-treated, and a top P-type nanocrystalline diamond passivation thermal expansion layer is directly formed in the windowed area. No protective intermediate layer or coupling dielectric layer is set between the top P-type nanocrystalline diamond passivation thermal expansion layer and the n-drift region, and its left end is close to the drain side edge of the gate G without covering the surface of the channel region and the area where the MOS gate dielectric layer is located.

10. The method of claim 8, wherein: The boron-doped nanocrystalline diamond thin layer formed in step (4) has a thickness of 10 nm to 2000 nm and a boron doping concentration of 1 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 And a drain-side gap region with a width of 0.1 μm to 10 μm is reserved between its right end and the drain D; the thermally extended metal layer formed in step (6) is located above the second passivation layer and is insulated from the source lead-out Pad12, the gate lead-out Pad13 and the drain lead-out Pad14, and is not electrically connected to the source S, the gate G and the drain D through the connecting via.

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