Power module package structure with low parasitic inductance

Abstract

This application provides a power module packaging structure with low parasitic inductance, relating to the field of power electronic device packaging technology. This application utilizes a copper plate assembly tightly coupled to the main power circuit to actively construct a mirror path opposite to the current direction of the main power circuit. It also directly reduces parasitic inductance from an electromagnetic perspective by utilizing mutual inductance cancellation, without introducing new insulation problems and ensuring heat dissipation. Furthermore, compared to traditional three-dimensional packaging of power modules, this application eliminates the need for complex vertical interconnects to compress space, effectively reducing the technological difficulty of power module packaging and improving production speed and yield. In short, this application achieves extremely low parasitic inductance, excellent thermal management capabilities, and higher structural reliability at a manufacturing cost and process complexity far lower than three-dimensional packaging, thus providing a more practical and easily industrialized technological path for high-performance, low-cost power modules.

Description

Technical Field

[0001] This application relates to the field of power electronic device packaging technology, and in particular to a power module packaging structure with low parasitic inductance. Background Technology

[0002] As the voltage levels of power semiconductor modules (hereinafter referred to as power modules) increase, the insulation distance between power semiconductor chips (hereinafter referred to as power chips) is usually increased to meet higher electrical insulation requirements. Furthermore, the layout and size of power chips also change to achieve better heat dissipation and current carrying capacity. These adjustments to the physical structure introduce parasitic inductance, which becomes more pronounced, especially in high-frequency, high-voltage, and high-current applications. While 3D packaging of power chips can reduce parasitic inductance to some extent, it still results in relatively high inductance. Moreover, 3D packaging relies on three-dimensional stacking, requiring the construction of compact, overlapping current loops and heat dissipation paths in the vertical (Z-axis) direction. This process is difficult, slow, and has low yield. At excessively high voltage levels (such as 6.5kV and 10kV), it can also easily cause insulation and heat dissipation problems, ultimately leading to impaired device performance and a serious lack of safety. Summary of the Invention

[0003] This application provides a power module packaging structure with low parasitic inductance, aiming to solve the problems of high parasitic inductance, poor safety, and high manufacturing difficulty of power modules in related technologies.

[0004] To address the aforementioned drawbacks in related technologies, this application provides a power module packaging structure with low parasitic inductance, comprising a ceramic substrate, a drain terminal, a source terminal, a power chip, and a copper plate assembly. A first copper layer is formed on one side of the ceramic substrate. The first copper layer includes drain copper and source copper layers that are opposite to and spaced apart from each other along the length of the ceramic substrate. The power chip is disposed on the drain copper layer and located at the edge of the drain copper layer near the source copper layer. The drain of the power chip is electrically connected to the drain copper layer. The drain terminal is conductively disposed on the drain copper layer and located at the edge of the drain copper layer away from the source copper layer. The source of the power chip is connected to the first copper plate assembly. The one-bonded wire is electrically connected to the source copper plating; the copper plate assembly includes a copper pillar, a lower copper plate, a side copper plate, and an upper copper plate. The copper pillar is electrically erected on the source copper plating. One end of the lower copper plate is electrically connected to the end of the copper pillar away from the source copper plating. The other end of the lower copper plate extends along the length of the ceramic substrate toward the drain terminal and is electrically connected to one end of the side copper plate. The side copper plate is arranged vertically and its other end is electrically connected to one end of the upper copper plate. The other end of the upper copper plate extends along the length of the ceramic substrate toward the copper pillar. The upper copper plate, the lower copper plate, and the ceramic substrate are parallel to each other. The source terminal is electrically erected on the upper copper plate and located at the end of the upper copper plate away from the drain terminal.

[0005] In some implementations, the packaging structure also includes a Kelvin source terminal, and the first copper layer also includes a Kelvin source copper layer. The Kelvin source copper layers are arranged around the source copper layer at intervals. The Kelvin source terminal is electrically erected on the Kelvin source copper layer and located on the side of the source copper layer away from the drain copper layer. The Kelvin source of the power chip is electrically connected to the Kelvin source copper layer through a second bonding wire.

[0006] In some implementations, the package structure also includes a gate terminal, the first copper layer also includes a gate copper layer, the gate copper layer is arranged around the Kelvin source copper layer and spaced apart from the Kelvin source copper layer, the gate terminal is electrically disposed on the gate copper layer and located on the side of the Kelvin source copper layer away from the drain copper layer, and the gate of the power chip is electrically connected to the gate copper layer through a third bonding wire.

[0007] In some implementations, both the gate terminal and the Kelvin source terminal are located on the central axis of the ceramic substrate extending in the length direction; the power chip includes two chips, which are opposite to each other and spaced apart in the width direction of the ceramic substrate, and the two power chips are symmetrical about the central axis.

[0008] In some implementations, the gate copper cladding includes a main gate copper cladding, two surface mount resistors, and two sub-gate copper claddings. The main gate copper claddings are arranged around the Kelvin source copper claddings at intervals. The main gate copper claddings have openings and are located on the central axis extending along the length of the ceramic substrate. The openings are located between the Kelvin source copper claddings and the drain copper claddings. The two sub-gate copper claddings are both located at the openings and are symmetrical about the central axis. The two sub-gate copper claddings are respectively close to both ends of the main gate copper claddings and are spaced apart from both ends of the main gate copper claddings. The two sub-gate copper claddings are electrically connected to both ends of the main gate copper claddings through two surface mount resistors. The gates of the two power chips are electrically connected to the two sub-gate copper claddings through two third bonding wires.

[0009] In some implementations, there are four drain terminals, with each pair of drain terminals forming a drain terminal group. The two drain terminal groups are opposite each other in the width direction of the ceramic substrate. The two drain terminal groups are respectively close to the two opposite edges of the drain copper plating in the width direction of the ceramic substrate. The two drain terminal groups are symmetrical about the central axis extending in the length direction of the ceramic substrate. The two drain terminals in each drain terminal group are opposite each other in the width direction of the ceramic substrate and spaced apart from each other.

[0010] In some implementation schemes, each drain terminal is covered with an electromagnetic shielding layer on its outer sidewall, and the two electromagnetic shielding layers in the same drain terminal group extend towards each other and are connected to each other between the two drain terminals.

[0011] In some implementation schemes, the two electromagnetic shielding layers in the same drain terminal group are integrally formed.

[0012] In some implementations, there are four source terminals, which are distributed in a matrix on the upper copper plate. The four source terminals are symmetrical about the central axis of the ceramic substrate extending in the length direction.

[0013] In some implementations, the packaging structure also includes a heat dissipation substrate, on which a ceramic substrate is disposed, and on the other side of the ceramic substrate opposite to the first copper layer, a second copper layer is formed that is in contact with the heat dissipation substrate.

[0014] The power module packaging structure provided in this application comprises a ceramic substrate, a drain terminal, a source terminal, a power chip, and a copper plate assembly. A first copper layer is formed on one side of the ceramic substrate. The first copper layer includes drain copper and source copper clads that are opposite to and spaced apart from each other along the length of the ceramic substrate. The power chip is disposed on the drain copper clads and located near the edge of the source copper clads. The drain of the power chip is electrically connected to the drain copper clads. The drain terminal is electrically disposed on the drain copper clads and located away from the edge of the source copper clads. The source of the power chip is electrically connected to the source copper clads via a first bonding wire. The copper plate assembly includes copper pillars, side copper plates, and a lower copper plate parallel to the ceramic substrate. The upper copper plate and copper pillar are electrically erected on the source copper cladding. One end of the lower copper plate is electrically connected to the end of the copper pillar away from the source copper cladding. The other end of the lower copper plate extends along the length of the ceramic substrate toward the drain terminal and is electrically connected to one end of the side copper plate. The side copper plate is arranged vertically and its other end is electrically connected to one end of the upper copper plate. The other end of the upper copper plate extends along the length of the ceramic substrate toward the copper pillar. The source terminal is electrically erected on the upper copper plate and located away from the drain terminal. In other words, the drain terminal is electrically connected to the source terminal in sequence through the drain copper cladding, power chip, first bonding wire, source copper cladding, copper pillar, lower copper plate, side copper plate and upper copper plate. In practical applications, during power module operation, the source current on the copper plate assembly and the current on the first copper layer are in opposite directions. The mutual magnetic flux and self-magnetic flux they generate cancel each other out. Similarly, the current on the upper copper plate and the current at the drain terminal are in opposite directions, and their mutual magnetic flux and self-magnetic flux also cancel each other out. This significantly reduces the parasitic inductance of the power module. In other words, the copper plate assembly forms a tight coupling with the main power circuit (i.e., the first copper layer), actively constructing a mirror path opposite to the current direction of the main power circuit. By utilizing mutual inductance cancellation, parasitic inductance is reduced directly at its source (i.e., electromagnetic principle). Furthermore, since the copper plate assembly is at a low potential, it does not introduce new insulation problems, and heat dissipation is guaranteed, preventing device performance degradation due to insulation and heat dissipation issues, thus enhancing safety. Moreover, compared to traditional three-dimensional packaging of power modules, this application eliminates the need for complex vertical interconnects to compress space (i.e., it eliminates the need to construct compact, overlapping current loops and heat dissipation paths in the vertical direction), effectively reducing the technological difficulty of power module packaging and improving production speed and yield. In short, this application achieves extremely low parasitic inductance, excellent thermal management capabilities, and higher structural reliability at a manufacturing cost and process difficulty far lower than that of 3D packaging, providing a more pragmatic and easily industrialized technical path for high-performance, low-cost power modules. Attached Figure Description

[0015] To more clearly illustrate the related technologies or the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the related technologies or the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application, and not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 An isometric view of the power module packaging structure provided in the embodiments of this application from one perspective;

[0017] Figure 2 This is a schematic diagram of the structure of the ceramic substrate provided in the embodiments of this application;

[0018] Figure 3 This is an exploded view of the power module packaging structure provided in the embodiments of this application;

[0019] Figure 4 This is a side view of the power module packaging structure provided in an embodiment of this application;

[0020] Figure 5 An isometric view of the power module packaging structure provided in an embodiment of this application from another perspective.

[0021] The labels in the above figures represent: 1-Ceramic substrate, 2-Drain terminal group, 3-Source terminal, 4-Power chip, 5-Copper plate assembly, 6-First bonding wire, 7-Kelvin source terminal, 8-Gate terminal, 9-Second bonding wire, 10-Third bonding wire, 20-Electromagnetic shielding layer, 11-First copper layer, 12-Second copper layer, 111-Drain copper plating, 112-Source copper plating, 113-Kelvin source copper plating, 114-Gate copper plating, 1141-Main gate copper plating, 1142-Sub-gate copper plating, 1143-Surface mount resistor, 1144-Opening, 21-Drain terminal, 51-Copper pillar, 52-Lower copper plate, 53-Side copper plate, 54-Upper copper plate. Detailed Implementation

[0022] While 3D packaging of power chips can reduce parasitic inductance to some extent in related technologies, the parasitic inductance remains relatively high. Furthermore, 3D packaging relies on three-dimensional stacking, i.e., constructing compact, overlapping current loops and heat dissipation paths in the vertical direction. This process is difficult, slow, and has low yield. At excessively high voltage levels, it can also easily cause insulation and heat dissipation problems, leading to performance degradation and a lack of safety. Therefore, this application proposes a power module packaging structure with low parasitic inductance in the embodiments below to address the aforementioned drawbacks of related technologies.

[0023] To make the objectives, technical solutions, and advantages of this application more apparent and understandable, this application will be clearly and completely described below in conjunction with its embodiments and corresponding drawings. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. It should be understood that the embodiments of this application described below are only for explaining this application and are not intended to limit this application. That is, all other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0024] Please see Figures 1 to 5 , Figure 1 This is an isometric view of the power module packaging structure from one perspective. Figure 2 This is a schematic diagram of the structure of a ceramic substrate. Figure 3 This is an exploded view of the power module packaging structure. Figure 4 This is a side view of the power module package structure. Figure 5 This is an isometric view of the power module packaging structure from another perspective. This embodiment provides a power module packaging structure with low parasitic inductance, which includes a ceramic substrate 1, a drain terminal 21, a source terminal 3, a power chip 4, and a copper plate assembly 5. The ceramic substrate 1 serves as the basic carrier of the entire packaging structure and is made of ceramic materials such as aluminum nitride (AlN), alumina (Al2O3), or silicon nitride (Si3N4). It has excellent electrical insulation, thermal conductivity, and structural rigidity, and can effectively isolate the conductive layer and achieve rapid heat conduction. Among them, alumina has the lowest cost, a thermal conductivity of approximately 180 W / (m·K), and high insulation strength, making it suitable for medium- and low-voltage, medium- and low-power applications. Aluminum nitride has a thermal conductivity of 200~230 W / (m·K), several times that of alumina, and its coefficient of thermal expansion matches copper very well, making it suitable for high-voltage, high-power, and high-heat-dissipation applications. Silicon nitride combines high thermal conductivity, high mechanical strength, and excellent thermal shock resistance, with a thermal conductivity of approximately 150 W / (m·K), making it suitable for industrial-grade power modules subjected to harsh conditions such as vibration and shock, such as power modules in rail transportation and aerospace equipment. It is understood that the ceramic substrate 1 in this embodiment can be flexibly selected from any of the above three materials according to the actual application scenario, and its thickness can be adjusted within the range of 0.25~1.0 mm. A thin ceramic substrate 1 can be used in low-voltage scenarios to reduce parasitic parameters, while a thick ceramic substrate 1 can be used in high-voltage scenarios to improve insulation performance. For example, the ceramic substrate 1 in this embodiment uses aluminum nitride.

[0025] A first copper layer 11 is formed on one side of the ceramic substrate 1. The first copper layer 11 is prepared on the surface of the ceramic substrate 1 by sputtering, electroplating or direct bonding, and provides the main path for current transmission of the power module. Its preparation process directly affects the current transmission efficiency and the connection reliability of the device. In the field of power electronics packaging, there are three mainstream processes for preparing copper layers on the surface of ceramic substrate 1: direct copper bonding (DBC), active metal brazing (AMB), and sputtering / electroplating. Among them, the DBC process directly bonds copper foil to the surface of ceramic substrate 1 at high temperature, and the resulting copper layer thickness can reach 0.1~0.5mm, with high bonding strength, low contact resistance, and excellent thermal conductivity. The AMB process connects the copper layer to the ceramic substrate 1 through active metal solder, which is suitable for ceramic substrates 1 made of difficult-to-bond materials such as silicon nitride, and the copper layer thickness can be 0.05~0.3mm, with stronger process compatibility. The sputtering / electroplating process first forms a thin copper seed layer by sputtering, and then thickens it by electroplating. The thickness of the copper layer can be precisely controlled within 0.01~0.1mm, which is suitable for scenarios with fine wiring. It should be noted that the fabrication process of the first copper layer 11 can be selected according to the material of the ceramic substrate 1 and the current requirements of the power module. The first copper layer 11 uses high-purity oxygen-free copper with a purity ≥99.99%, achieving a conductivity of ≥58 MS / m and a thermal conductivity ≥401 W / (m·K), which can minimize current transmission loss and improve heat conduction efficiency. For example, in this embodiment, the first copper layer 11 is fabricated on the surface of the ceramic substrate 1 using the DBC process.

[0026] The first copper layer 11 includes a drain copper layer 111 and a source copper layer 112 that are opposite to and spaced apart from each other along the length of the ceramic substrate 1. The space between the drain copper layer 111 and the source copper layer 112 is an insulating isolation strip, which can prevent short circuit faults in the main power circuit. Its width is a key parameter to ensure the insulation performance of the power module and needs to be designed according to the voltage level of the power module. For 6.5kV power modules, the width of the insulating isolation strip is not less than 3mm; for 10kV power modules, the width of the insulating isolation strip is not less than 5mm; for medium and low voltage (1.2~3.3kV) power modules, the width of the insulating isolation strip can be controlled between 1~2mm, which can ensure insulation safety and reduce the overall size of the power module, and avoid increasing parasitic inductance due to the longer current path caused by the insulating isolation strip being too wide.

[0027] The power chip 4 is located on the drain copper 111 and at the edge of the drain copper 111 near the source copper 112. This layout design can minimize the current path from the source of the power chip 4 to the source copper 112, thereby structurally reducing the parasitic inductance caused by the path length. Understandably, the connection method between the power chip 4 and the drain copper clad 111 directly affects the contact resistance, heat dissipation efficiency, and long-term reliability of the power module. In the field of power electronics packaging, there are three mainstream connection methods between the power chip 4 and the drain copper clad 111: solder welding, solder sintering, and silver paste sintering. Solder welding uses tin-based solder (such as SAC305), which is simple to process, but the solder has a low melting point (about 217°C), and is prone to thermal fatigue at high temperatures, and the contact resistance will increase with the operating time. Solder sintering uses high-temperature solder (such as CuSn solder with a melting point of 415°C and AgCu solder with a melting point of 779°C) to achieve the sintering connection between the power chip 4 and the drain copper clad 111 under high temperature and high pressure, resulting in high bonding strength, low contact resistance, and good thermal stability. Silver paste sintering uses nano silver paste to sinter at medium and high temperatures (200~300°C), and the resulting silver layer has excellent electrical and thermal conductivity, good thermal expansion matching, and is suitable for high-power, high-reliability power modules. For example, in this embodiment, the drain of the power chip 4 and the drain copper 111 are connected by surface contact. Specifically, solder (such as high-temperature solder CuSn or AgCu) sintering can be used. Compared with the traditional welding method, sintering connection has lower contact resistance and higher connection reliability, which can adapt to high current and high power working scenarios. In addition, for ultra-high voltage and ultra-high power scenarios, nano silver paste can also be used for sintering, and the sintering pressure is controlled at 5~15MPa and the sintering time is 30~60min, so as to ensure that the sintered layer is free of pores and cracks, and the contact resistance is controlled below 10μΩ.

[0028] The drain terminal 21 is electrically and upright on the drain copper clad 111 and located at the edge of the drain copper clad 111 away from the source copper clad 112. The source of the power chip 4 is electrically connected to the source copper clad 112 through the first bonding wire 6. Both the drain terminal 21 and the power chip 4 are sintered onto the drain copper clad 111 with solder, resulting in high connection strength and low contact resistance. The first bonding wire 6 is made of copper or aluminum wire. Copper wire bonding has lower resistivity and higher current carrying capacity than aluminum wire bonding, making it a preferred solution for medium and high voltage power module packaging. The number of first bonding wires 6 can be adjusted according to the current rating of the power chip 4. In high-current scenarios, the number of bonding wires can be increased to achieve current shunting and prevent single bonding wires from burning out due to overcurrent. In other words, the first bonding wire 6 is the current bridge between the source of the power chip 4 and the source copper cladding 112. Its material selection and arrangement have a significant impact on parasitic inductance and current carrying capacity. In the field of power electronic packaging, bonding wires are mainly divided into aluminum wires and copper wires. Aluminum wires have low cost, mature technology, and easy bonding. Their conductivity is about 37 MS / m, making them suitable for power modules with medium and low current. Copper wires have a conductivity of about 58 MS / m, which is much higher than that of aluminum wires. Their current carrying capacity is 1.5 to 2 times that of aluminum wires of the same diameter, and their parasitic inductance is lower. They are the preferred choice for medium and high voltage and high current power modules. However, copper wires have high hardness, which places higher demands on the bonding process, namely, higher bonding temperature and pressure. For example, the first bonding wire 6 in this embodiment is preferably a copper wire with a diameter of 0.2~0.5mm. For ultra-high current scenarios, multiple copper wires can also be bonded in parallel. As for the number of the first bonding wires 6, it can be determined according to the rated current of the power chip 4. Generally, 8~12 bonding wires are configured for every 100A rated current, and the arc height of the bonding wire is controlled at 0.5~1.5mm. If the arc height is too high, it will increase the current path length. If it is too low, it will be easy to short-circuit with the surrounding components. The tension of the bonding point needs to be ≥5g (g is the acceleration due to gravity) to ensure the reliability of the bonding connection.

[0029] Power chip 4 uses a SiC MOSFET chip. SiC MOSFETs are third-generation power semiconductor devices with a large bandgap (3.26 eV) and high breakdown electric field strength (2.5 × 10⁻⁶). 6With a high electron saturation drift velocity (V / cm), it possesses numerous excellent characteristics such as high temperature resistance, high voltage resistance, low on-resistance, and high-frequency switching, making it suitable for ultra-high voltage power modules such as 6.5kV and 10kV. Of course, the SiC MOSFET chip can also be replaced with power semiconductor chips such as Insulated Gate Bipolar Transistor (IGBT), Gallium Nitride (GaN) HEMT, and SiC JBS (Silicon Carbide Junction Barrier Schottky Diode) according to actual application requirements. All of these can adapt to the design logic of this package structure. In other words, different types of power chips 4 only need to be adjusted according to their size on the drain copper cladding 111. The core design of the package structure in this embodiment does not need to be changed, exhibiting extremely strong compatibility. Among them, IGBT chips are low in cost and mature in technology, and are suitable for medium- and low-voltage (1.2~3.3kV) and medium-power applications; GaN HEMT chips have higher switching frequencies and lower switching losses, and are suitable for high-frequency power modules, such as photovoltaic inverters and on-board chargers for new energy vehicles; SiC JBS can be used as a freewheeling diode in combination with SiC MOSFETs to form an all-SiC power module, which can improve the overall performance of the power module.

[0030] Furthermore, unless otherwise specified, the term "electrical connection" in this application refers to an electrical connection method that enables free conduction of charge, including known conductive connection methods such as welding, sintering, and integral molding. The "length direction" and "width direction" defined in this application are based on the horizontal placement of the ceramic substrate 1 and are two mutually perpendicular horizontal directions. The "length direction" is the direction of the long side extension of the ceramic substrate 1, the "width direction" is the direction of the short side extension of the ceramic substrate 1, and the "vertical direction" is the vertical direction perpendicular to the horizontal direction. These directions are defined only to clearly describe the spatial layout relationship of each component. In practical applications, the power module can be placed at any angle according to the equipment installation requirements. The relative positions of each component and the coupling relationship of the current loop are not affected by the placement angle, and the mutual inductance can still be reduced to achieve the effect of mutual inductance cancellation and parasitic inductance reduction.

[0031] Specifically, the copper plate assembly 5 includes an integrally formed copper pillar 51, a lower copper plate 52, a side copper plate 53, and an upper copper plate 54. The integral forming process can eliminate the connection gaps between the components, avoiding the introduction of additional contact resistance and parasitic inductance. In the field of power electronics packaging, commonly used integral forming processes include CNC milling, stamping, and metal injection molding (MIM). CNC milling is used to process a whole block of high-purity oxygen-free copper blank into the required copper plate assembly 5 through a CNC milling machine. It has high processing accuracy (±0.01mm), low surface roughness, and no connection gaps, and is suitable for small-batch, high-precision sample preparation. Stamping uses a mold to stamp copper foil or copper blank into the required structure. It has high production efficiency and low cost, and is suitable for mass industrial production. The processing accuracy can reach ±0.05mm, which can meet the structural requirements of the copper plate assembly 5 in this embodiment. Metal injection molding is suitable for copper plate assemblies with more complex structures. After injection molding of metal powder, it is sintered and densified to prepare irregular structures, but the cost is higher. For example, the copper plate assembly 5 in this embodiment is manufactured using a stamping process, which balances production efficiency and processing accuracy; of course, for high-precision customized power modules, the copper plate assembly 5 can also be manufactured using a CNC milling process.

[0032] The copper plate assembly 5 is made entirely of high-purity oxygen-free copper. Oxygen-free copper has the best electrical and thermal conductivity among metallic copper, ensuring low-loss current transmission and assisting the power module in heat dissipation. It is understood that oxygen-free copper is divided into two grades, TU1 and TU2, based on oxygen and impurity content. TU1 has an oxygen content ≤0.003% and a total impurity content ≤0.01%, with the highest electrical and thermal conductivity among metallic copper, making it the preferred grade for the copper plate assembly 5 in this embodiment. TU2 has an oxygen content ≤0.005% and a total impurity content ≤0.02%, with slightly lower performance than TU1 but lower cost, making it suitable for cost-sensitive low- to medium-power modules. The thickness of the copper plate assembly 5 can be adjusted according to the current level. The thickness of the lower copper plate 52 and the upper copper plate 54 is controlled at 0.5~2.0mm, the thickness of the side copper plate 53 is controlled at 0.3~1.0mm, the diameter of the copper column 51 is controlled at 2~5mm, and the height is controlled at 1~3mm. This ensures sufficient current carrying capacity and achieves tight coupling with the first copper layer 11, thereby improving the mutual inductance cancellation effect.

[0033] The copper pillar 51 is electrically erected on the source copper clad 112. One end of the lower copper plate 52 is electrically connected to the end of the copper pillar 51 away from the source copper clad 112. The other end of the lower copper plate 52 extends along the length of the ceramic substrate 1 toward the drain terminal 21 and is electrically connected to one end of the side copper plate 53. The side copper plate 53 is arranged vertically (extending along the vertical direction). The other end of the side copper plate 53 is electrically connected to one end of the upper copper plate 54. The other end of the upper copper plate 54 extends along the length of the ceramic substrate 1 toward the copper pillar 51. The upper copper plate 54, the lower copper plate 52, and the ceramic substrate 1 are parallel to each other. The source terminal 3 is electrically erected on the upper copper plate 54 and located at the end of the upper copper plate 54 away from the drain terminal 21. This spatial layout makes the copper plate assembly 5 and the first copper layer 11 below form a tightly coupled structure with corresponding upper and lower parts, providing a structural basis for the mutual inductance cancellation described later. As can be seen, the drain terminal 21 is electrically connected to the source terminal 3 in sequence through the drain copper cladding 111, the power chip 4, the first bonding wire 6, the source copper cladding 112, the copper pillar 51, the lower copper plate 52, the side copper plate 53 and the upper copper plate 54, forming a complete main power current loop.

[0034] Understandably, the spacing between the upper copper plate 54, the lower copper plate 52, and the ceramic substrate 1 is a key spatial parameter affecting the coupling coefficient between the copper plate assembly 5 and the first copper layer 11. The coupling coefficient is negatively correlated with the spacing; the smaller the spacing, the closer the coupling coefficient is to 1, and the better the mutual inductance cancellation effect. However, too small a spacing will lead to insufficient insulation distance between the copper plate assembly 5 and the first copper layer 11, causing insulation problems. In view of this, the spacing between the lower copper plate 52 and the ceramic substrate 1 is controlled at 0.5~2.0mm, and the spacing between the upper copper plate 54 and the lower copper plate 52 is determined by the height of the side copper plate 53 and controlled at 2~5mm. This spacing design not only ensures the insulation safety between the copper plate assembly 5 and the first copper layer 11 (the insulation distance meets the creepage distance requirements of the high voltage level), but also enables the coupling coefficient to reach more than 0.8, which is much higher than the coupling coefficient of traditional planar packaging (generally 0.3~0.5), thereby achieving excellent mutual inductance cancellation effect.

[0035] Copper pillar 51 is sintered onto the source copper plating 112 with solder, and source terminal 3 is sintered onto the upper copper plate 54 with solder. All connection nodes employ a sintering process to ensure the conductive continuity between the entire copper plate assembly 5 and the main power circuit. It is understood that the sintering connections between copper pillar 51 and source copper plating 112, and between source terminal 3 and upper copper plate 54, are consistent with the sintering processes of power chip 4 and drain copper plating 111. High-temperature CuSn or AgCu solder is preferentially used, and the sintering temperature is determined according to the solder type. The sintering temperature for CuSn solder is controlled at 420~450℃, and for AgCu solder at 780~800℃. The sintering atmosphere is an inert gas such as nitrogen or argon to prevent oxidation of the copper layer and solder at high temperatures. After sintering, the shear strength of the connection node is ≥20MPa, and the contact resistance is ≤5μΩ, ensuring the stability of the connection node during long-term operation and preventing increased contact resistance due to thermal expansion and contraction.

[0036] Furthermore, whether it's the drain terminal 21 and source terminal 3 mentioned earlier, or the gate terminal 8 and Kelvin source terminal 7 mentioned later, they all use cylindrical terminals. Cylindrical terminals have the characteristics of stable structure, easy connection to external circuits, and strong current carrying capacity. Their material is preferably high-purity copper, and the outer surface can be plated with nickel or tin according to actual needs, in order to prevent oxidation and improve soldering performance. It can be understood that compared with sheet-like and pin-like terminals, cylindrical terminals have a stronger current carrying capacity and are easier to connect to external busbars. They can be connected to external circuits through welding, bolting, etc. In this embodiment, the cylindrical terminals are made of high-purity oxygen-free copper (TU1 or TU2), with a diameter controlled at 3~8mm and a height controlled at 5~15mm, which can be adjusted according to the current level of the power module and the external connection requirements. The outer surface of the cylindrical terminals in this embodiment needs to be electroplated. The mainstream electroplating layers include nickel plating, tin plating, silver plating, etc., and the electroplating type can be flexibly selected according to the external connection method. The nickel plating layer is controlled at a thickness of 3~5μm, mainly to prevent oxidation of the copper terminals and improve their corrosion resistance; the tin plating layer is controlled at a thickness of 5~10μm, after which the terminals can be soldered to external circuits by wave soldering and reflow soldering, improving soldering performance; the silver plating layer is controlled at a thickness of 0.5~2μm, silver has extremely high conductivity, after which the contact resistance between the terminals and external circuits can be further reduced, making it suitable for high-frequency and high-current applications.

[0037] In this embodiment, when the power module is running, the source current on the copper plate assembly 5 and the current on the first copper layer 11 are in opposite directions, and the mutual magnetic flux and self magnetic flux they generate will cancel each other out. Similarly, the current on the upper copper plate 54 and the current on the drain terminal 21 are in opposite directions, and the mutual magnetic flux and self magnetic flux they generate will also cancel each other out. This can significantly reduce the parasitic inductance of the power module. The following are the relevant theoretical derivations and proofs. The calculation formulas for mutual inductance, self inductance, magnetic field energy, etc., involved are all well-known basic formulas in electromagnetism and are applicable to the calculation of parasitic parameters of all coupled current loops.

[0038] The mutual inductance between copper plate assembly 5 and first copper layer 11 is M:

[0039]

[0040] The total magnetic field energy of the two coupled loops (copper plate assembly 5 and first copper layer 11) is W. m :

[0041]

[0042] Substitution :

[0043]

[0044] Its equivalent inductance is L eq :

[0045]

[0046] Where k is the coupling coefficient, the magnitude of which is determined by the spatial position, shape, and size of the two coupled loops, and is usually 0 to 1; L ds For the self-inductance of the drain electrode 21 to the source electrode copper-clad 112, I ds For the current in this path segment; L sl For the self-inductance of the lower copper plate 52, I slThis refers to the current in this path segment (from the end where the lower copper plate 52 connects to the copper pillar 51 to the end where the lower copper plate 52 connects to the side copper plate 53). The above formula clearly demonstrates that, utilizing the principle of mutual inductance cancellation, the total parasitic inductance of the power module can be effectively reduced. Furthermore, the closer the coupling coefficient k is to 1, i.e., the tighter the coupling between the copper plate assembly 5 and the first copper layer 11, the more significant the reduction in parasitic inductance of the power module. This embodiment designs the copper plate assembly 5 and the first copper layer 11 as a tightly coupled structure with parallel vertical lines, which significantly increases the coupling coefficient k (reaching 0.8~0.95), far exceeding the coupling degree of traditional planar packaging (coefficient 0.3~0.5), achieving the design goal of extremely low parasitic inductance. Taking a 6.5kV SiC MOSFET power module as an example, the parasitic inductance of the main power circuit in traditional planar packaging is about 80~100nH, while that in stereo packaging can be reduced to 50~60nH. However, this embodiment can reduce the parasitic inductance to 10~20nH through mutual inductance cancellation, with extremely significant effect. The significant reduction in parasitic inductance can effectively suppress voltage overshoot during the switching process of the power module. For SiC MOSFETs, voltage overshoot can be controlled within 10% of the rated voltage, avoiding device damage due to overvoltage breakdown. At the same time, it can also reduce switching losses and improve the conversion efficiency of the power module. Taking a 10kV / 200A power module as an example, the switching loss can be reduced by 30~50%, significantly improving the high-frequency operating capability of the power module.

[0047] It is understood that the copper plate assembly 5 can form a tight coupling with the main power circuit (i.e., the first copper layer 11). In this embodiment, the copper plate assembly 5 actively constructs a mirror path opposite to the current direction of the main power circuit, and uses mutual inductance cancellation to directly reduce parasitic inductance from the root (i.e., electromagnetic principle). At the same time, since the copper plate assembly 5 is at a low potential, the potential difference between it and the surrounding high-potential components is small, so no new insulation problems are introduced. In other words, the copper plate assembly 5, as a mirror path of the source current, belongs to the low-potential region, while the drain copper cladding 111 and the drain terminal 21 both belong to the high-potential region. The insulating isolation strip on the ceramic substrate 1 and the air gap between the copper plate assembly 5 and the first copper layer 11 form an insulating barrier between the high and low potentials. The breakdown field strength of the air is only 3kV / mm. Combined with the insulation performance of the ceramic substrate 1, the insulation distance between the high and low potentials can meet the creepage distance and clearance requirements of ultra-high voltage levels such as 6.5kV and 10kV. Compared with the stacking of high and low potential components in the vertical direction in three-dimensional packaging, this planar layout does not have the problem of excessively thin insulation layer and reduced insulation performance, and will not introduce new insulation hazards. In this regard, the power module of this embodiment was subjected to a power frequency withstand voltage test at 1.5 times the rated voltage, and it could withstand 60 seconds without breakdown or flashover, demonstrating excellent insulation performance.

[0048] Furthermore, the copper plate assembly 5 in this embodiment is made of high thermal conductivity oxygen-free copper, which can serve as an auxiliary heat dissipation structure to quickly conduct the heat from the source copper cladding 112 to the surrounding area. This effectively ensures the heat dissipation of the power module, thereby preventing the device performance from being damaged due to insulation, heat dissipation and other issues, and improving the safety of the power module. In other words, the copper plate assembly 5 is not only a mirror path for current transmission, but also an important auxiliary heat dissipation structure for the power module. The copper plate assembly 5 is made of high-purity oxygen-free copper, which has a thermal conductivity of 401 W / (m·K), far exceeding that of air and organic encapsulation materials. The heat on the source copper cladding 112 can be quickly conducted to the lower copper plate 52, side copper plate 53 and upper copper plate 54 through the copper pillar 51. The large-area metal surface of the copper plate assembly 5 can dissipate heat to the surrounding environment through thermal convection and thermal radiation. According to thermal simulation analysis, for a 200A power module, the copper plate assembly 5 can remove about 20~30% of the source heat, effectively reducing the temperature of the source copper cladding 112 and the source of the power chip 4, reducing the junction temperature of the power chip 4 by 5~15℃, and improving the power cycle capability and long-term reliability of the power module.

[0049] Furthermore, compared to the traditional 3D packaging of power modules, this embodiment does not require complex vertical interconnects to compress space (i.e., it does not require building compact, overlapping current loops and heat dissipation paths in the vertical direction), which can effectively reduce the process difficulty of power module packaging and improve production speed and yield. It is understood that traditional 3D packaging uses a three-dimensional stacked structure, requiring chip stacking, vertical interconnects, and multi-layer insulation in the vertical direction. It also involves complex processes such as wafer bonding, through-silicon vias (TSVs), and vertical copper pillar interconnects. This results in large equipment investment, high difficulty in controlling process parameters, a production yield generally below 60%, and a long production cycle, with the production time for a single power module reaching several hours. In contrast, the packaging structure of this embodiment is based on the traditional planar DBC process, requiring only the addition of sintering of the copper plate assembly 5 and terminal welding to the existing process. This results in fewer new process steps, lower equipment investment, and existing planar packaging production lines requiring only minor modifications to achieve mass production. The yield can be increased to over 95%, the production time for a single power module can be shortened to less than 30 minutes, and the manufacturing cost is reduced by 50-70% compared to 3D packaging, significantly improving industrialization capabilities. In short, this embodiment achieves extremely low parasitic inductance, excellent thermal management capabilities, and higher structural reliability at a manufacturing cost and process complexity far lower than that of 3D packaging, providing a more pragmatic and easily industrialized technical path for high-performance, low-cost power modules.

[0050] In some embodiments, the power module package structure includes, in addition to the components described above, a gate terminal 8 and a Kelvin source terminal 7; accordingly, the first copper layer 11 includes, in addition to the drain copper layer 111 and the source copper layer 112, a gate copper layer 114 and a Kelvin source copper layer 113. It should be understood that adding the Kelvin source terminal 7 enables accurate detection of the potential of the power chip's four sources, avoiding voltage drops caused by large currents in the main power circuit in the detection circuit, which would lead to distortion of the detection potential. This is a well-known design scheme in medium- and high-voltage, high-precision power module control. In other words, accurate detection of the source potential is crucial for achieving overcurrent protection, short-circuit protection, and precise control of the gate drive voltage. The large current in the main power circuit generates a voltage drop at the source copper plating 112 and its bonding lines. Directly drawing power from the source of the main power circuit for detection results in a potential that includes this voltage drop, leading to potential distortion and causing malfunctions in the protection and drive circuits. In contrast, the Kelvin source terminal 7 achieves direct detection of the source potential through an independent Kelvin detection circuit. This circuit has no main power current flowing through it, does not generate a voltage drop, and has a detection accuracy of ±0.1V, accurately reflecting the actual source potential of the power chip 4. This is an indispensable design element in medium- and high-voltage, high-precision power module control. In the driving of power chips such as SiC MOSFETs and IGBTs, the error in Kelvin detection directly affects the protection response speed and drive reliability of the power module. Excessive error may prevent timely protection during overcurrent or short circuits, causing device damage.

[0051] Gate terminal 8 provides an independent current path for the gate drive of power chip 4, ensuring stable transmission of the drive signal. It is understandable that the gate drive of power chip 4 is a low-current, high-sensitivity signal loop, requiring electrical isolation and electromagnetic shielding from the high-current main power loop to prevent interference from the strong magnetic field generated by the high current in the main power loop. Gate terminal 8 provides a dedicated current path for the gate drive through independent gate copper 114 and its bonding wires. The drive current is typically several amperes to tens of amperes, and the voltage is within ±20V. This independent path design ensures stable transmission of the drive signal, avoids signal distortion and interference, and keeps the switching characteristics of power chip 4 stable. Especially in high-frequency switching scenarios, even minor interference with the gate drive signal can lead to increased switching losses, larger voltage overshoot, and even false turn-on of power chip 4.

[0052] Specifically, the Kelvin source copper cladding 113 is arranged around the source copper cladding 112 and spaced apart from it, with the spaced area forming an insulating isolation to prevent the main power circuit current from entering the Kelvin detection circuit; the Kelvin source terminal 7 is electrically mounted on the Kelvin source copper cladding 113 and located on the side of the source copper cladding 112 away from the drain copper cladding 111. The Kelvin source of the power chip 4 is electrically connected to the Kelvin source copper cladding 113 through the second bonding wire 9. That is, the Kelvin source of the power chip 4 is electrically connected to the Kelvin source terminal 7 in sequence through the second bonding wire 9 and the Kelvin source copper cladding 113, thereby forming an independent Kelvin detection circuit; the second bonding wire 9 is also preferably copper wire, and the arrangement is short and with few bends, further reducing the parasitic parameters of the Kelvin detection circuit.

[0053] Understandably, the spacing between the Kelvin source copper cladding 113 and the source copper cladding 112 must ensure the insulation performance between them, while avoiding an excessively large spacing that would increase the size of the power module. This spacing is generally controlled between 0.5 and 1.5 mm. The Kelvin source copper cladding 113 adopts a surrounding layout to bring it as close as possible to the source copper cladding 112, shortening the length of the second bonding wire 9 and reducing the parasitic inductance of the Kelvin detection circuit. The parasitic inductance of the Kelvin detection circuit is generally controlled between 1 and 3 nH to avoid the Kelvin detection signal oscillating at high frequencies due to excessive parasitic inductance, which would affect the detection accuracy. This surrounding layout also makes the arrangement of the second bonding wire 9 more uniform, ensuring that the Kelvin detection paths of the two power chips 4 are consistent and that the detection potential is without deviation. Furthermore, the second bonding wire 9, serving as the current path for the Kelvin detection circuit, is selected and arranged with the core goal of reducing parasitic parameters and improving detection accuracy. Fine-diameter copper wires with a diameter of 0.1~0.2mm are preferred, as they reduce the parasitic inductance and capacitance of the Kelvin detection circuit. Simultaneously, the second bonding wire 9 employs a short-distance, low-arc height arrangement, with its arc height controlled between 0.3~0.8mm. The bonding point is placed as close as possible to the Kelvin source pin of the power chip 4, thereby shortening the current path. Regarding the number of second bonding wires 9, generally 2~4 are configured for each power chip 4 to ensure the conductivity continuity of the Kelvin detection circuit and prevent detection failure caused by the breakage of a single second bonding wire 9. The second bonding wire 9 is also arranged separately from the first bonding wire 6, with a spacing of not less than 0.5mm, to avoid electromagnetic interference from the high-current magnetic field of the main power circuit to the Kelvin detection circuit.

[0054] The gate copper cladding 114 is arranged around the Kelvin source copper cladding 113 and is spaced apart from the Kelvin source copper cladding 113. The spaced area forms an insulating isolation to avoid interference between the signal circuit and the detection circuit. The gate terminal 8 is electrically disposed on the gate copper cladding 114 and is located on the side of the Kelvin source copper cladding 113 away from the drain copper cladding 111. The gate of the power chip 4 is electrically connected to the gate copper cladding 114 through the third bonding line 10. That is, the gate of the power chip 4 is electrically connected to the gate terminal 8 in sequence through the third bonding line 10 and the gate copper cladding 114, thereby forming an independent gate drive circuit. Understandably, the spacing between the gate copper cladding 114 and the Kelvin source copper cladding 113 is controlled at 0.5~1.5mm, which ensures both insulation between the two and allows the gate copper cladding 114 to be close to the Kelvin source copper cladding 113, shortening the length of the third bonding wire 10. The gate copper cladding 114 adopts a surrounding layout, which allows the gate drive signal to be transmitted evenly to the two power chips 4, ensuring the synchronization of the drive signal. The surrounding layout also increases the heat dissipation area of ​​the gate copper cladding 114, dissipating the small amount of heat from the gate drive circuit and preventing the gate copper cladding 114 from overheating and affecting the transmission of the drive signal. The thickness of the gate copper cladding 114 is the same as that of the first copper layer 11, which is 0.1~0.5mm, and high-purity oxygen-free copper is used to ensure low-loss transmission of the drive signal.

[0055] The third bonding wire 10 is made of fine-diameter aluminum or copper wire, which is suitable for the low current and high signal accuracy requirements of the gate drive. It is also arranged separately from the first bonding wire 6 of the main power circuit to avoid electromagnetic interference to the gate drive signal caused by the magnetic field generated by the large current of the main power circuit. Understandably, the third bonding wire 10 is the core component of the gate drive circuit. The gate drive is a small current signal (current between 1 and 10A, voltage between -5 and +20V). Therefore, the third bonding wire 10 is preferably made of fine-diameter aluminum or copper wire with a diameter of 0.08 to 0.15 mm. The fine-diameter third bonding wire 10 can reduce the parasitic inductance and parasitic capacitance of the drive circuit and avoid signal oscillation at high frequencies. Aluminum wire bonding technology is more mature and has a lower cost, making it the preferred choice for the gate drive circuit. Copper wire is suitable for high-frequency and high-reliability applications. The arc height of the third bonding wire 10 is controlled between 0.3 and 0.8 mm. The bonding point is close to the gate pin of the power chip 4. Each power chip 4 is generally equipped with 2 to 4 third bonding wires 10, which are spatially separated from the first bonding wire 6 and the second bonding wire 9 and arranged on different sides of the power chip 4 to avoid electromagnetic interference and ensure the purity of the drive signal.

[0056] Furthermore, the Kelvin source terminal 7 is sintered onto the Kelvin source copper plating 113 with solder, and the gate terminal 8 is sintered onto the gate copper plating 114 with solder, thereby ensuring the reliability of the connection between the signal circuit and the detection circuit. It should be noted that the sintering process of the Kelvin source terminal 7 and the gate terminal 8 is the same as that of the drain terminal 21 and the source terminal 3, and high-temperature solder sintering is preferred to ensure the reliability and stability of the connection. Since the Kelvin source terminal 7 and the gate terminal 8 transmit small current signals, the contact resistance of the connection node after sintering is required to be higher, which needs to be controlled below 3μΩ, and the porosity of the sintered layer should be ≤5% to avoid signal loss due to excessive contact resistance. The electroplating layer of the Kelvin source terminal 7 and the gate terminal 8 is preferably nickel-plated to improve corrosion resistance and prevent terminal oxidation from affecting signal transmission.

[0057] Furthermore, the power module of this application is a half-bridge structure, which includes a gate terminal 8, a Kelvin source terminal 7, two power chips 4, four drain terminals 21 and four source terminals 3. It adopts a symmetrical configuration to achieve balanced current distribution of the power module, avoid overcurrent in a single chip or terminal, and improve the current carrying capacity and operating stability of the power module. Understandably, symmetrical configuration is a core design principle in power module design for achieving current balance, reducing parasitic parameters, and improving module reliability. In a half-bridge structure, the two power chips 4 serve as the upper and lower bridge arms, respectively. The symmetrical layout ensures that the current paths, parasitic inductances, and heat dissipation conditions of the two power chips 4 are completely identical, avoiding uneven current during dynamic operation. Uneven current can cause one of the power chips 4 to overheat due to overcurrent, accelerating chip aging and even causing chip burnout. Symmetrical configuration also ensures that the current distribution at the terminals is uniform, avoiding overcurrent at a single terminal and improving the overall current carrying capacity of the power module. Tests have shown that with a symmetrical layout, the current deviation between the two power chips 4 can be controlled within 5%, and the current deviation at the terminals can be controlled within 3%, significantly improving the operational stability of the power module.

[0058] Based on this, the two power chips 4 are positioned opposite each other and spaced apart in the width direction of the ceramic substrate 1. The two power chips 4 are symmetrical about the central axis extending in the length direction of the ceramic substrate 1. This is beneficial for the current to pass through the two power chips 4 evenly and to achieve chip-level current shunting. At the same time, the symmetrical layout makes the parasitic parameters of the two power chips 4 consistent, which can avoid the problem of uneven current during dynamic operation. Understandably, the spacing between the two power chips 4 is controlled at 2~5mm, which ensures the insulation performance between the two power chips 4 and makes the layout of the two power chips 4 more compact, reducing the size of the power module. The two power chips 4 are symmetrical about the central axis extending in the length direction of the ceramic substrate 1, which makes the distances from the two power chips 4 to the gate terminal 8 and the Kelvin source terminal 7 completely consistent. The transmission paths of the gate drive signal and the Kelvin detection signal are the same, the signal delay is consistent, the synchronization is good, and the signal delay deviation can be controlled within 1ns. This avoids the switching asynchrony caused by different signal delays. Switching asynchrony will generate additional switching losses and voltage spikes, affecting the performance of the power module. At the same time, the symmetrical layout makes the heat dissipation conditions of the two power chips 4 consistent, and the junction temperature difference can be controlled within 3℃, improving the power cycle life of the module.

[0059] The four source terminals 3 are arranged in a matrix on the upper copper plate 54. The four source terminals 3 are symmetrical about the central axis extending along the length of the ceramic substrate 1. The matrix arrangement allows for multiple connections between the external circuit and the source terminals 3, reducing the parasitic inductance of the external connections. At the same time, the symmetrical layout ensures a balanced current distribution among the source terminals 3. It can be understood that the four source terminals 3 adopt a 2×2 matrix arrangement with a spacing of 3~8mm. This matrix arrangement allows for multiple connections with the external bus, meaning that the external bus can be connected to four source terminals 3 simultaneously, significantly reducing the parasitic inductance of the external connections. Traditional single-terminal or double-terminal connections have a parasitic inductance of approximately 30~50nH for the external bus, while the matrix connection of the four source terminals 3 in this application can reduce the parasitic inductance of the external connections to below 10nH, further reducing the total parasitic inductance of the entire power circuit. At the same time, the symmetrical distribution ensures that the current carrying capacity of each source terminal 3 is the same, which is 1 / 4 of the total current of the module, avoiding overcurrent in a single terminal and improving the service life of the terminals.

[0060] Two drain terminals 21 together form a drain terminal group 2. The two drain terminal groups 2 are opposite each other in the width direction of the ceramic substrate 1. The two drain terminal groups 2 are respectively close to the two opposite edges of the drain copper cladding 111 in the width direction of the ceramic substrate 1. The two drain terminal groups 2 are symmetrical about the central axis extending in the length direction of the ceramic substrate 1. The two drain terminals 21 in each drain terminal group 2 are opposite each other in the width direction of the ceramic substrate 1 and spaced apart from each other. This layout matches the symmetrical layout of the two power chips 4 and can ensure balanced current input on the drain side. Understandably, the symmetrical arrangement of the drain terminals 21 matches the symmetrical arrangement of the two power chips 4. Each drain terminal group 2 corresponds to one power chip 4, ensuring that the drain current of each power chip 4 is output through the corresponding drain terminal group 2, resulting in a consistent current path and identical parasitic inductance, thus avoiding uneven current distribution among the power chips 4. The spacing between the two drain terminals 21 in each drain terminal group 2 is controlled at 2~5mm, and the distance between two drain terminal groups 2 is controlled at 10~20mm. This ensures both the insulation performance between the drain terminals 21 and matches the arrangement of the drain terminals 21 with the position of the power chips 4, shortening the current path on the drain copper cladding 111 and further reducing parasitic inductance. The current distribution of the four drain terminals 21 is uniform, with each drain terminal 21 carrying 1 / 4 of the total module current, effectively reducing the current density of the drain terminals 21 and controlling it to 5A / mm². 2 To prevent the leakage tip 21 from overheating due to excessive Joule heating, the temperature should be avoided.

[0061] Both the gate terminal 8 and the Kelvin source terminal 7 are located on the central axis extending along the length of the ceramic substrate 1. This arrangement allows the gate drive signal and the Kelvin detection signal to be symmetrically transmitted to the two power chips 4, ensuring that the drive signals and detection potentials of the two power chips 4 are completely consistent, thereby avoiding parameter deviations during dynamic operation. It can be understood that arranging the gate terminal 8 and the Kelvin source terminal 7 on the central axis extending along the length of the ceramic substrate 1 ensures that the distances from the two power chips 4 to these two terminals are completely equal. The gate drive signal and the Kelvin detection signal are symmetrically transmitted from the power chips 4 on both sides of the central axis, with completely consistent transmission path lengths and parasitic parameters. This ensures that the amplitude and phase of the drive signals of the two power chips 4 are completely identical, and that there is no deviation in the detection potential. This is crucial for a half-bridge power module. Even a small deviation in the drive signal can cause the upper and lower bridge arms to switch out of sync, resulting in a bridge arm shoot-through fault and causing the power module to burn out. This central axis arrangement optimizes the synchronization of the drive signal and the detection signal, effectively preventing bridge arm shoot-through faults.

[0062] Furthermore, both the drain terminal 21 and the source terminal 3 have four terminals. This design effectively reduces parasitic inductance without increasing the size of the power module. Specifically, it reduces the current density of a single terminal by using multiple terminals to shunt the current, thereby lowering the parasitic inductance and Joule heat of the terminal itself. This is an effective design method for reducing parasitic parameters and improving heat dissipation in high-current power module packaging. It is understandable that multi-terminal shunt is a classic design method for reducing parasitic inductance and improving heat dissipation in high-current power module packaging. Its principle is mainly reflected in two aspects: First, it reduces the current density of a single terminal. With four terminals sharing the total module current, the current of a single terminal is only 1 / 4 of the total module current, significantly reducing the current density. According to electromagnetic principles, the parasitic inductance of a conductor is positively correlated with current density; reducing the current density directly reduces the parasitic inductance of the terminal itself. Second, it reduces the Joule heat of the terminal. The formula for calculating Joule heat is Q=I. 2 With Rt, the current I of a single terminal is reduced to 1 / 4, and the Joule heat is reduced to 1 / 16. The total Joule heat of the four terminals is only 1 / 4 of that of a single terminal, effectively reducing the terminal temperature and improving the terminal's heat dissipation capacity. At the same time, the multi-terminal layout can increase the connection points with external circuits, reduce the parasitic inductance of external connections, and ultimately achieve a dual reduction in the parasitic inductance of both the internal and external components of the power module.

[0063] As at least one embodiment, the gate copper cladding 114 includes a main gate copper cladding 1141, two surface mount resistors 1143 and two sub-gate copper claddings 1142. The surface mount resistors 1143 are current-limiting resistors for the gate drive circuit and are essential components for the gate drive of the power chip 4. They can limit the gate charging and discharging current, protect the gate oxide layer of the power chip 4, and prevent overcurrent breakdown. Understandably, the gate current-limiting resistor is an essential component of the gate drive circuit of the power chip 4. Its core function is to limit the gate charging and discharging current, protecting the gate oxide layer of the power chip 4. The gate oxide layer of the power chip 4 is extremely thin, typically tens to hundreds of nanometers thick. Excessive charging and discharging current can cause oxide layer breakdown, resulting in permanent damage to the chip. The current-limiting resistor can also adjust the switching speed of the chip. The larger the resistance value, the slower the gate charging and discharging speed, the lower the switching speed, and the smaller the voltage overshoot, but the greater the switching loss. Conversely, the smaller the resistance value, the faster the switching speed, the smaller the switching loss, but the greater the voltage overshoot. Therefore, the resistance value of the current-limiting resistor needs to be precisely matched according to the parameters of the power chip 4 and the actual application requirements, generally adjusted within the range of 10~100Ω. This application uses two independent surface-mount resistors 1143 to limit the current of the gate drive circuits of the two power chips 4 respectively, which can realize independent adjustment of the switching speed of the two chips. Even if there are slight parameter differences between the two chips, the switching characteristics of the two chips can be kept consistent by adjusting the resistance value.

[0064] The surface mount resistor 1143 is preferably a high-precision, small-size surface mount resistor, which is suitable for the miniaturization requirements of power module packaging structures. It is understood that compared to through-hole resistors, the surface mount resistor 1143 is smaller in size and more suitable for the miniaturization of power module packaging. The surface mount resistor 1143 in this application can be a 0402 or 0603 packaged surface mount thick-film resistor with an accuracy of ±1% and a temperature drift coefficient of ±50ppm / ℃. This high-precision resistor can ensure the stability of the gate drive current and reduce the gate drive current deviation between the two power chips 4. The power capacity of the surface mount thick-film resistor is 1 / 16~1 / 8W, which can meet the low power requirements of the gate drive circuit. Furthermore, the surface mount resistor 1143 can be directly soldered between the main gate copper cladding 1141 and the sub-gate copper cladding 1142 via reflow soldering. The soldering process is simple, the connection reliability is high, and it is suitable for industrial production.

[0065] The main gate copper cladding 1141 is arranged around the Kelvin source copper cladding 113 and is spaced apart from the Kelvin source copper cladding 113. The main gate copper cladding 1141 has an opening 1144 (i.e., the main gate copper cladding 1141 is not annularly closed). The opening 1144 is located between the Kelvin source copper cladding 113 and the drain copper cladding 111 and is located on the central axis of the ceramic substrate 1 extending in the length direction. In other words, one end of the main gate copper cladding 1141 is located between the Kelvin source copper cladding 113 and the drain copper cladding 111, and the other end extends around the Kelvin source copper cladding 113 and returns to the Kelvin source copper cladding 113 and the drain copper cladding 111. The two ends of the main gate copper cladding 1141 are opposite to each other and spaced apart in the width direction of the ceramic substrate 1, thereby forming an opening 1144 between the two ends of the main gate copper cladding 1141 to avoid the main gate copper cladding 1141 from forming a closed loop, and to prevent the generation of eddy currents in the closed loop under high frequency operating scenarios, which would cause signal interference and energy loss. Understandably, the main gate copper cladding 1141 is designed as a non-closed open structure to avoid eddy currents in the closed loop under high-frequency operating conditions. According to the principle of electromagnetic induction, a changing magnetic field will induce eddy currents in a closed metal loop. Eddy currents generate Joule heat, causing energy loss. At the same time, the magnetic field generated by the eddy currents will cause electromagnetic interference to the gate drive signal, resulting in signal distortion. This open structure of the main gate copper cladding 1141 can effectively cut off the flow path of eddy currents and avoid their generation. The width of the opening is controlled at 2~5mm, which can ensure that the eddy current path is cut off without making the current path of the main gate copper cladding 1141 too long. In addition, the opening is located between the Kelvin source copper cladding 113 and the drain copper cladding 111. The magnetic field in this region is relatively weak, which can minimize the impact of the opening on the transmission of the gate drive signal.

[0066] Based on this, both sub-gate copper clads 1142 are located at the opening 1144 and are symmetrical about the central axis extending in the length direction of the ceramic substrate 1. The two sub-gate copper clads 1142 are close to both ends of the main gate copper clad 1141 and are spaced apart from each other. The two sub-gate copper clads 1142 are electrically connected to both ends of the main gate copper clad 1141 through two chip resistors 1143. The gates of the two power chips 4 are electrically connected to the two sub-gate copper clads 1142 through two third bonding lines 10. That is, the gates of the power chips 4 are electrically connected to the gate terminal 8 in sequence through the third bonding line 10, the sub-gate copper clads 1142, the chip resistors 1143 and the main gate copper clad 1141. Understandably, the sub-gate copper cladding 1142 serves as a transition connection layer between the main gate copper cladding 1141 and the gate of the power chip 4. Its specifications need to be determined based on the pin positions of the gate of the power chip 4 and the package size of the surface mount resistor 1143. Its length is generally 2~5mm, and its width is generally 1~3mm. The two sub-gate copper claddings 1142 are symmetrical about the central axis extending in the length direction of the ceramic substrate 1, which ensures that their connection paths with the two power chips 4 are consistent. The sub-gate copper cladding 1142 and the main gate copper cladding 1141 are connected through the surface mount resistor 1143, without direct electrical contact, which can achieve electrical isolation between the two gate drive circuits and avoid mutual interference between the gate drive signals of the two power chips 4. The thickness of the sub-gate copper cladding 1142 is the same as that of the main gate copper cladding 1141, usually 0.1~0.5mm, and high-purity oxygen-free copper is used to ensure low-loss transmission of the gate drive signal.

[0067] In this process, the two ends of each chip resistor 1143 are sintered with solder onto the corresponding ends of the main gate copper clad 1141 and the corresponding sub-gate copper clad 1142. This sintering connection ensures the continuity of conductivity and the reliability of the connection. It is understood that the connection between the chip resistor 1143 and the main gate copper clad 1141 and sub-gate copper clad 1142 is achieved using a reflow soldering process. The solder is a tin-based solder (such as SAC305), the soldering temperature is controlled at 240~260℃, and the soldering time is controlled at 30~60s. This ensures that there are no cold solder joints or false solder joints, and the contact resistance is ≤10mΩ. The sintering connection (reflow soldering) ensures the continuity of conductivity and the reliability of the connection, and the reflow soldering process is suitable for industrial mass production with high production efficiency.

[0068] It should be noted that the two surface-mount resistors 1143 can be individually selected with different resistance values ​​based on the parameter characteristics of the two power chips 4, thereby ensuring the accuracy of gate drive. In actual production, even power chips 4 from the same batch may have slight deviations in parameters such as gate capacitance, turn-on voltage, and on-resistance. These deviations can lead to inconsistent switching characteristics between the two power chips 4. By equipping each chip with an independent surface-mount resistor 1143, the resistance value can be adjusted according to the actual parameters of the chip to compensate for the chip parameter deviations, ensuring that the switching speed, voltage overshoot, and switching losses of the two chips remain consistent. For example, if the gate capacitance of one power chip 4 is too large, a surface-mount resistor 1143 with a slightly smaller resistance value can be selected to accelerate the gate charging and discharging speed, thus matching the switching speed of that chip with that chip. This independent parameter compensation design can significantly improve the dynamic consistency and operational stability of the power module. Furthermore, the independent design of the sub-gate copper cladding 1142 avoids mutual interference between the gate drive signals of the two power chips 4, ultimately achieving independent current limiting and signal isolation of the gate drive circuits of the two power chips 4. This improves the dynamic operating performance of the power module, making it particularly suitable for high-frequency and high-voltage applications. Understandably, the electrical isolation of the two gate drive circuits effectively prevents a drive signal failure in one power chip 4 from affecting the other. For example, if a short-circuit fault occurs in the gate of one chip, the surface-mount resistor 1143 will quickly limit the fault current. Due to the isolation effect of the sub-gate copper cladding 1142, the fault will not be propagated to the other chip, ensuring that the other chip can still operate normally. This improves the fault tolerance and reliability of the power module. In industrial-grade power modules, fault tolerance is a crucial indicator of module reliability, and an independent gate drive circuit can improve the module's fault tolerance by more than 50%.

[0069] As at least one embodiment, the outer wall of the drain terminal 21 is covered with an electromagnetic shielding layer 20. The electromagnetic shielding layers 20 on the two drain terminals 21 in the same drain terminal group 2 extend towards each other and are connected to each other between the two drain terminals 21. That is, the electromagnetic shielding layers 20 of the two drain terminals 21 in the same drain terminal group 2 are integrally formed without connection gaps, and the electromagnetic shielding effect is more continuous and better. Understandably, the electromagnetic shielding layer 20 primarily serves to provide electromagnetic shielding and further reduce parasitic inductance. Essentially, it is a layer of material with good electrical or magnetic conductivity (such as copper foil, aluminum foil, or other highly conductive metal foils, or magnetically conductive materials like nickel-iron alloys). The electromagnetic shielding layer 20 provides electrical isolation from the drain terminal 21, preventing short circuits. According to Lenz's law, the large alternating current in the drain terminal 21 generates an alternating magnetic field. This alternating magnetic field induces eddy currents in the electromagnetic shielding layer 20 in the opposite direction to the original current. The reverse magnetic field generated by these eddy currents partially cancels out the original magnetic field, thus achieving the dual effect of reducing parasitic inductance and suppressing near-field magnetic radiation. The following is the relevant theoretical derivation and proof; the electromagnetic induction and eddy current effects involved are well-known principles in the electromagnetic compatibility design of power electronic devices.

[0070] When a changing magnetic field acts on the electromagnetic shielding layer 20, eddy currents I are generated. eddy Its magnetic field is opposite in direction to the original magnetic field, eddy current I eddy The induced electromotive force generated is ε:

[0071]

[0072] Electromagnetic shielding layer 20 can be considered as a short-circuit loop, and its self-inductance is L. shield Its mutual inductance with the drain pole 21 is M. shield eddy current I eddy Driven by a changing magnetic field:

[0073]

[0074] Eddy I eddy The generated magnetic flux cancels out the original magnetic flux, and the total parasitic inductance is reduced to:

[0075]

[0076] Among them, R shield Let R represent the resistance of the electromagnetic shielding layer 20, and ω represent the angular frequency. From the above formula, it can be clearly deduced that the smaller the resistance of the electromagnetic shielding layer 20, the higher the angular frequency ω and conductivity, the more significant the eddy current effect, and the better the reduction in parasitic inductance and electromagnetic shielding effect. High-purity electroplated copper can be used as the electromagnetic shielding layer 20, and its resistance R... shieldExtremely small electromagnetic shielding layer 20 can generate significant eddy current effects in high-frequency switching scenarios (high angular frequency ω). Taking a 6.5kV / 200A SiC MOSFET power module as an example, after adding the electromagnetic shielding layer 20, the parasitic inductance of the drain terminal 21 can be further reduced by 15-25%, and the total parasitic inductance of the module can be reduced to below 10nH. At the same time, near-field magnetic radiation can be reduced by 20-30dB, effectively improving the electromagnetic compatibility (EMC) performance of the power module and enabling the module to meet the requirements of EMC standards such as EN61000. No additional EMC filtering circuit is needed, reducing the size and cost of the equipment. In short, the electromagnetic shielding layer 20 is not a simple structural component, but a passive component with a clear electromagnetic shielding function. Its design directly serves the specific electrical goal of reducing high-frequency parasitic parameters and EMI (electromagnetic interference).

[0077] In some embodiments, the power module packaging structure includes, in addition to the components described above, a heat sink (not shown). The heat sink includes a heat dissipation substrate (not shown), and a ceramic substrate 1 is disposed on the heat dissipation substrate of the heat sink. The heat dissipation substrate is the basic load-bearing part of the heat sink, preferably a copper-based or aluminum-based composite heat dissipation substrate, which has high thermal conductivity and good structural rigidity, enabling rapid heat conduction and uniform diffusion. Specifically, a second copper layer 12 is formed on the opposite side of the ceramic substrate 1 and the first copper layer 11. The second copper layer 12 and the first copper layer 11 are symmetrical conductive layers on both sides of the ceramic substrate 1, both made of high-purity oxygen-free copper. The second copper layer 12 is bonded to the heat dissipation substrate, and the heat dissipation substrate and the second copper layer 12 are sintered together with solder. The contact thermal resistance of the sintered connection is much lower than that of traditional bonding and bolt connections, resulting in higher heat conduction efficiency. It is understandable that the typical "sandwich structure" of the first copper layer 11 + ceramic substrate 1 + second copper layer 12 is essentially a copper-clad ceramic substrate (such as DBC), which is a well-known high-performance substrate in the field of power electronic device packaging. It has excellent electrical insulation, high thermal conductivity and high mechanical strength, and can simultaneously meet the electrical isolation, heat conduction and structural load-bearing requirements of power modules.

[0078] Understandably, the heat generated during the operation of the power module is dissipated primarily through three paths: First, the drain of the power chip 4 is conducted to the heat dissipation substrate through the drain copper cladding 111, the ceramic substrate 1, and the second copper layer 12, forming the main heat dissipation path. This path is a surface-contact heat dissipation method, which has the highest heat dissipation efficiency. Second, the source of the power chip 4 diffuses to the surrounding air and external circuits through the first bonding wire 6, the source copper cladding 112, and the copper plate assembly 5, forming an auxiliary heat dissipation path. Third, the ceramic substrate 1 itself undergoes thermal radiation and convection, forming a natural heat dissipation path. In practical applications, these three heat dissipation paths work together to achieve efficient thermal management of the power module, solving the problem of insufficient heat dissipation in traditional three-dimensional packaging at high voltage levels, and better ensuring the long-term stable operation of the power module under high current and high power conditions.

[0079] The above embodiments are merely preferred implementations of this application and are not the only limitations on the power module packaging structure. Those skilled in the art can make flexible designs based on these embodiments and according to actual application scenarios. For example, the number of power chips 4, the number of bonding wires, and the number of terminals can be adjusted according to the power level. The thickness of the ceramic substrate 1 and the spacing between each copper layer can also be adjusted according to the voltage level. The material of the ceramic substrate 1 and the type of heat dissipation substrate can also be changed according to heat dissipation requirements. These adaptive adjustments do not deviate from the core design concept of this application and are all within the protection scope of this application. Understandably, compared to the pursuit of three-dimensional stacking in stereo packaging, this application, based on the traditional planar DBC process, uses the core design of "copper plate assembly 5 + electromagnetic shielding layer 20" to efficiently solve problems such as voltage overshoot, increased switching losses, and dynamic uneven current caused by significant parasitic inductance under high voltage conditions with lower process complexity and manufacturing cost. Specifically, this application does not compress space through complex vertical interconnects, but instead uses copper plate assembly 5 to actively construct a mirror path opposite to the current direction of the main power circuit, so that the mutual inductance flux generated between the circuits cancels out the self-inductance flux, directly reducing the total parasitic inductance of the power module from an electromagnetic principle perspective. At the same time, the electromagnetic shielding layer 20 further suppresses high-frequency magnetic fields and reduces parasitic inductance through the eddy current effect. Therefore, this application achieves a high-performance, high-reliability, and low-inductance design while avoiding the challenges of high cost, complex thermal stress, and low yield associated with 3D packaging. Furthermore, the packaging structure of this application is highly compatible with existing planar packaging processes, making it easy to mass-produce in the industrial sector. It provides a novel solution for power module packaging of medium- and high-voltage, high-power, and high-frequency power electronic devices, and can be widely used in new energy vehicles, rail transit, wind power converters, photovoltaic inverters, aerospace, and other fields, possessing extremely high industrial application value.

[0080] It should be noted that the several embodiments shown above in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in the textual description of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply such an actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements may include not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus; and, without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0081] Furthermore, those skilled in the art can implement or use this application by practicing the several embodiments shown above. Various modifications to the embodiments shown above will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments not shown without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the several embodiments shown above, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power module package structure having low parasitic inductance, characterized by, The device includes a ceramic substrate, a drain terminal, a source terminal, a power chip, and a copper plate assembly. A first copper layer is formed on one side of the ceramic substrate. The first copper layer includes drain copper and source copper clads that are opposite to and spaced apart from each other along the length of the ceramic substrate. The power chip is disposed on the drain copper clads and located near the edge of the source copper clads. The drain of the power chip is electrically connected to the drain copper clads. The drain terminal is electrically disposed on the drain copper clads and located away from the edge of the source copper clads. The source of the power chip is electrically connected to the source copper clads through a first bonding wire. The copper plate assembly includes a copper pillar, a side copper plate, and an upper copper plate and a lower copper plate parallel to the ceramic substrate. The copper pillar is electrically erected on the source copper plating. One end of the lower copper plate is electrically connected to the end of the copper pillar away from the source copper plating. The other end of the lower copper plate extends along the length of the ceramic substrate toward the drain terminal and is electrically connected to one end of the side copper plate. The side copper plate is vertically arranged and its other end is electrically connected to one end of the upper copper plate. The other end of the upper copper plate extends along the length of the ceramic substrate toward the copper pillar. The source terminal is electrically erected on the upper copper plate and located away from the drain terminal.

2. The power module package structure of claim 1, wherein, It also includes a Kelvin source terminal, and the first copper layer further includes a Kelvin source copper cladding. The Kelvin source copper claddings are arranged around the source copper claddings at intervals. The Kelvin source terminal is electrically erected on the Kelvin source copper claddings and located on the side of the source copper claddings away from the drain copper claddings. The Kelvin source of the power chip is electrically connected to the Kelvin source copper claddings through a second bonding wire.

3. The power module package structure of claim 2, wherein, It also includes a gate terminal, and the first copper layer further includes a gate copper layer, which is arranged around the Kelvin source copper layer and spaced apart from it. The gate terminal is electrically disposed on the gate copper layer and located on the side of the Kelvin source copper layer away from the drain copper layer. The gate of the power chip is electrically connected to the gate copper layer through a third bonding wire.

4. The power module packaging structure according to claim 3, characterized in that, Both the gate terminal and the Kelvin source terminal are located on the central axis extending along the length of the ceramic substrate; the power chip includes two chips, which are opposite to each other and spaced apart in the width direction of the ceramic substrate, and are symmetrical about the central axis.

5. The power module packaging structure according to claim 4, characterized in that, The gate copper cladding includes a main gate copper cladding, two surface mount resistors, and two sub-gate copper claddings. The main gate copper claddings are arranged around the Kelvin source copper claddings at intervals. The main gate copper claddings have an opening on the central axis, which is located between the Kelvin source copper claddings and the drain copper claddings. The two sub-gate copper claddings are located at the opening and are symmetrical about the central axis. The two sub-gate copper claddings are respectively spaced close to both ends of the main gate copper claddings. The two sub-gate copper claddings are electrically connected to both ends of the main gate copper claddings through the two surface mount resistors. The gates of the two power chips are electrically connected to the two sub-gate copper claddings through the two third bonding wires.

6. The power module packaging structure according to claim 1, characterized in that, The drain terminals include four, and every two drain terminals together form a drain terminal group. The two drain terminal groups are opposite each other in the width direction of the ceramic substrate. The two drain terminal groups are respectively close to the two opposite edges of the drain copper plating in the width direction of the ceramic substrate. The two drain terminal groups are symmetrical about the central axis extending in the length direction of the ceramic substrate. The two drain terminals in each drain terminal group are opposite each other in the width direction of the ceramic substrate and spaced apart from each other.

7. The power module packaging structure according to claim 6, characterized in that, Each of the drain terminals is covered with an electromagnetic shielding layer on its outer sidewall. The two electromagnetic shielding layers in the same drain terminal group extend towards each other and are connected to each other between the two drain terminals.

8. The power module packaging structure according to claim 7, characterized in that, The two electromagnetic shielding layers in the same drain terminal group are integrally formed.

9. The power module packaging structure according to claim 1, characterized in that, The source terminals include four, which are distributed in a matrix on the upper copper plate. The four source terminals are symmetrical about the central axis extending along the length of the ceramic substrate.

10. The power module packaging structure according to claim 1, characterized in that, It also includes a heat dissipation substrate, on which the ceramic substrate is disposed; a second copper layer is formed on the other side of the ceramic substrate opposite to the first copper layer, and the second copper layer is attached to the heat dissipation substrate.

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