A method for manufacturing a 3D alignment mark

Abstract

This invention provides a method for fabricating 3D alignment marks, which includes the following steps: providing multiple sets of data on different alignment mark sizes and corresponding butterfly recess depths, and obtaining the butterfly recess depth D based on data fitting; providing a semiconductor structure including a marking region and a short gate region, and estimating the butterfly recess depth D based on the alignment mark process requirements and the butterfly recess depth formula. 估 The invention calculates the grinding amount of the gate metal layer based on the process requirements of the dummy gate structure in the short gate region; it determines the risk level of the butterfly-shaped depression based on the risk coefficient x, and determines the distance between the short gate region and the marking region, as well as the size of the dummy gate structure to be fabricated in the region between the short gate region and the marking region based on the risk level; and it then fabricates alignment marks. This invention judges the risk level based on the fitted relationship between the depth of the butterfly-shaped depression and the size of the alignment marks, and determines the size of the dummy gate structure around the marking region based on the risk level, thereby improving metal residue.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a method for fabricating 3D alignment marks. Background Technology

[0002] 3D Mark clearance is a specific area at the edge of a chip or wafer, such as... Figure 1 As shown, critical 3D alignment marks (such as cascade marks, crosshair marks) or process monitoring structures are placed in the 3D mark clearance area. No circuits, metal layers, or interference structures are allowed to be placed in the clearance area to ensure lithographic alignment accuracy and signal integrity.

[0003] The bottom layer of the 3D mark area is typically composed of stacked STI OX (shallow trench filled oxide layer) and ILD0 OX (silicon oxide zero layer interlayer dielectric layer). The 3D mark clearance area is very large. Due to the chemical mechanical polishing (CMP) process for the oxide layer (OX) in STI, the oxide selectivity in the CMP process is relatively high. After STICMP, large butterfly-shaped dishing forms on the large STI OX area. Although the oxide selectivity is low during ILD0 CMP, the large feature size (CD) of the 3D mark clearance area means that ILD0 CMP cannot repair the incoming butterfly-shaped dishing. The selectivity of the hard mask layer on top of the polysilicon is greater than 1. After removing the hard mask layer, the dishing in the ILD0 OX further increases. This large-area OX dishing accumulates layer by layer. For metal gate (MG) CMP, the incoming dishing is too large, and the metal in the dishing cannot be completely removed during the chemical mechanical polishing planarization process, forming metal residue in the dishing of the ILD0 layer. Figure 2 and Figure 3 As shown, residual metal residue can interfere with the test signal and affect the precise interlayer alignment during subsequent multilayer lithography.

[0004] Therefore, there is an urgent need to find a method for fabricating 3D alignment markers that can improve the metal residue on the top of the alignment markers. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for manufacturing 3D alignment marks, which solves the problem that the top of the 3D alignment marks in the prior art is prone to residual metal due to butterfly-shaped indentations.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating 3D alignment markers, comprising the following steps:

[0007] Multiple sets of data on different alignment mark sizes and the depths of the corresponding butterfly-shaped depressions are provided. The depth of the butterfly-shaped depression is obtained by fitting the data. Where L is the length of the alignment mark, and a, b, c, and d are constants;

[0008] A semiconductor structure is provided that includes an edge clearance region comprising a marker region and a short gate region surrounding the marker region. The depth of the butterfly recess is estimated based on the process requirements of the alignment markers in the marker region and a formula for the depth of the butterfly recess. Simultaneously, the grinding amount of the gate metal layer is calculated based on the process requirements of the dummy gate structure in the short gate region. , The height of the gate metal layer before grinding. The height of the gate metal layer after grinding;

[0009] Based on risk coefficient The risk level of the butterfly-shaped indentation is determined, and based on the risk level, the distance between the short gate area and the marking area and the size of the dummy gate structure to be fabricated in the area between the short gate area and the marking area are determined;

[0010] The dummy gate structure and the alignment mark are fabricated within the clearance area.

[0011] Optionally, the risk level includes safe zones, risk zones, and high-risk zones.

[0012] Optionally, the risk level is within the safe zone, the risk coefficient x = [0, 1), and the short grid area is adjacent to the marking area.

[0013] Optionally, the risk level is within the risk zone, the risk coefficient x = [-1, 0), a long grid zone is spaced between the short grid zone and the marking zone, the length of the long grid zone between the edge of the marking zone and the edge of the adjacent short grid zone is a first dimension in the length direction of the marking zone, and the width of the long grid zone is not less than a second dimension in the width direction of the marking zone, and the length and width of the dummy grid structure in the long grid zone are respectively within the first range and the second range.

[0014] Optionally, the first size is not less than 50 μm and the second size is not less than 10 μm; or the first range is 240 nm to 900 nm and the second range is 200 nm to 2000 nm.

[0015] Optionally, the risk level is in the high-risk zone, the risk coefficient x < -1, a long grid area is spaced between the short grid area and the marking area, the length of the long grid area between the edge of the marking area and the edge of the adjacent short grid area is a third dimension in the length direction of the marking area, the width of the long grid area is not less than a fourth dimension in the width direction of the marking area, and the length and width of the dummy grid structure in the long grid area are in the third range and the fourth range, respectively.

[0016] Optionally, the third dimension is not less than 50 μm, and the fourth dimension is not less than 10 μm; or the third range is 900 nm to 50000 nm, and the fourth range is 200 nm to 2000 nm.

[0017] Optionally, the length of the dummy gate structure formed in the short gate region is no greater than 240 nm, and the width of the dummy gate structure ranges from 200 nm to 2000 nm.

[0018] Optionally, the dummy gate structure includes a gate metal layer and a gate dielectric layer.

[0019] Optionally, the alignment mark includes a trench embedded in the marking area and a dielectric layer filling the trench.

[0020] As described above, the method for fabricating 3D alignment marks of the present invention, before fabricating the dummy gate structure around the marking area, fits the relationship between the length of the alignment mark and the depth of the butterfly recess, evaluates the depth of the butterfly recess at the top of the ILD0 layer in the alignment mark based on the length of the alignment mark and the relationship, and then determines the risk level of the butterfly recess based on the depth of the butterfly recess and the amount of metal grinding of the gate metal layer of the dummy gate structure in the short gate area. Finally, based on the risk level, it determines whether to set a long gate area and the size of the dummy gate structure in the long gate area, so that the amount of grinding of the gate metal layer around the marking area is not less than the depth of the butterfly recess. Then, in the CMP process of the gate metal layer in the clearance area, the metal grinding rate above the alignment mark is increased, and the metal residue caused by the butterfly recess at the top of the alignment mark is improved, which has high industrial application value. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the clearance zone.

[0022] Figure 2 This is a schematic cross-sectional view of the clearance area after the CMP process for the gate metal layer.

[0023] Figure 3 This is a partial structural diagram of the alignment mark area after the gate metal layer CMP process.

[0024] Figure 4The diagram shows the process flow of the method for fabricating the 3D alignment mark of the present invention.

[0025] Figure 5 The graph shows the variation of the butterfly-shaped indentation depth with the length of the comparison mark in the method for fabricating 3D alignment marks according to the present invention.

[0026] Figure 6 The diagram shows the clearance zone within the safe zone for the method of creating 3D alignment marks according to the present invention.

[0027] Figure 7 The diagram shows the clearance area of ​​the risk zone in the method for producing 3D alignment marks according to the present invention.

[0028] Figure 8 The diagram shows a clearance zone where the risk level of the method for producing 3D alignment marks according to the present invention is in the high-risk zone.

[0029] Figure 9 The diagram shows a cross-sectional view of the clearance area after the CMP process of the gate metal layer, which is a method for fabricating 3D alignment marks according to the present invention.

[0030] Explanation of reference numerals: 01 Substrate, 011 STI OX, 012 ILD0 OX, 013 Gate metal layer, 014 Alignment mark, 02 Marker region, 021 Short gate region, 1 Clearance region, 11 Short gate region, 12 Marker region, 13 Long gate region, 14 Dummy gate structure, 2 Semiconductor structure, 21 Alignment mark, 22 ILD0 layer, 23 Gate metal layer. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Please see Figures 4 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] This embodiment provides a method for creating 3D alignment markers, such as... Figure 4The diagram shown is a process flow chart of the method for fabricating the 3D alignment mark, including the following steps:

[0034] S1: Provide multiple sets of data on different alignment mark sizes and the depth of the butterfly-shaped indentation corresponding to the alignment mark, and obtain the butterfly-shaped indentation depth based on the data. Where L is the length of the alignment mark, and a, b, c, and d are constants;

[0035] S2: Provide a semiconductor structure with an edge clearance region including a marking region and a short gate region surrounding the marking region, and estimate the depth of the butterfly recess based on the process requirements of the alignment mark in the marking region and the depth formula of the butterfly recess. Simultaneously, the grinding amount of the gate metal layer is calculated based on the process requirements of the dummy gate structure in the short gate region. , The height of the gate metal layer before grinding. The height of the gate metal layer after grinding;

[0036] S3: Based on risk coefficient The risk level of the butterfly-shaped indentation is determined, and based on the risk level, the distance between the short gate area and the marking area and the size of the dummy gate structure to be fabricated in the area between the short gate area and the marking area are determined;

[0037] S4: The dummy gate structure and the alignment mark are made in the clearance area.

[0038] Please see Figure 5 Perform steps S1 and S2: Provide multiple sets of data on different alignment mark sizes and the depth of the corresponding butterfly-shaped depression, and obtain the depth of the butterfly-shaped depression through data fitting. Where L is the length of the alignment mark, and a, b, c, and d are constants; a semiconductor structure 2 is provided, comprising an edge clearance region 1 including a marking region 12 and a short gate region 11 surrounding the marking region 12. The depth of the butterfly recess is estimated based on the process requirements of the alignment mark in the marking region 12 and the butterfly recess depth formula. Simultaneously, the grinding amount of the gate metal layer 23 is calculated based on the process requirements of the dummy gate structure in the short gate region. , The height of gate metal layer 23 before grinding. The height of the gate metal layer 23 after grinding (i.e., the target height after grinding).

[0039] Specifically, the clearance area 1 is typically a specific region at the edge of the semiconductor structure 2. The marking area 12 within the clearance area 1 is used to create critical alignment marks or process monitoring structures, i.e., to create Mark points. The fabrication of any circuitry, metal layers, or interfering structures is prohibited to ensure photolithographic alignment accuracy and signal integrity. In this embodiment, the alignment mark is a Frame 3D Mark.

[0040] As an example, the alignment mark includes a trench embedded in the marking region 12 and a dielectric layer filling the trench.

[0041] Specifically, the trenches in the alignment mark are typically formed through multiple processes, including STI trenches embedded in the substrate and upper trenches stacked on top of the STI trenches. The dielectric layer is also implemented through multiple processes based on process requirements, meaning the dielectric layer also includes multiple dielectric film layers. In this embodiment, the dielectric layer in the alignment mark includes an oxide layer filling the STI trenches and an interlayer dielectric layer ILD0 stacked on its upper surface. Here, the butterfly-shaped depression refers to the depression (dishing) generated on the upper surface of the ILD0 layer in the alignment mark after the CMP process, and its butterfly-shaped depression depth refers to the height difference between the lowest point and the edge of the depression region on the upper surface of the ILD0 layer.

[0042] It should be noted that during CMP polishing, the larger the size of the alignment mark, the deeper the butterfly-shaped recess usually is. Therefore, there is a strong correlation between the size of the alignment mark and the depth of the butterfly-shaped recess.

[0043] Specifically, the shapes of the alignment markers corresponding to different groups of samples can be the same or different. Within the same group of samples, the shapes and structures of the alignment markers are the same, with only one variable changing. For example, only the length of the alignment marker changes, or the width of the alignment marker changes. In this embodiment, only the length of the alignment marker changes in each group of samples, while the width of the alignment marker remains unchanged.

[0044] Specifically, in order to ensure that the obtained fitting formula has a high degree of correlation, a sufficient number of samples is usually required, that is, each group of samples needs to include a large number of butterfly-shaped indentation data of different sizes (lengths) and the same shape of alignment markers.

[0045] It should be noted that due to the different shapes of the alignment markers, the values ​​of a, b, c, and d in the fitted formula are usually different. Therefore, the specific values ​​of a, b, c, and d in the fitted formula are not restricted here. In this embodiment, using... Figure 1 Taking the alignment mark of a regular quadrilateral as an example, a scatter plot is generated based on the statistical values ​​of the butterfly-shaped indentation depth corresponding to alignment marks of different sizes, as shown below. Figure 5 As shown, in the formula for the depth of the butterfly-shaped depression obtained by fitting, a = 2 × 10 -7b = -0.0005, c = 0.511, d = 12.434, that is... .

[0046] Specifically, semiconductor structure 2 is usually the wafer structure for fabricating the device. The specific structure, size and shape of semiconductor structure 2 can be selected according to the actual situation.

[0047] Specifically, provided that subsequent processes can proceed normally, the size and shape of the clearance area 1 can be selected according to the actual situation; the size and shape of the marking area 12 in the clearance area 1 can be selected according to the actual situation.

[0048] It should be noted that before device fabrication, the size of the alignment mark is usually known based on process requirements. Based on the size of the alignment mark corresponding to the marking region 12 and the relationship between the depth of the butterfly recess and the length of the alignment mark obtained through fitting, the depth of the butterfly recess corresponding to the alignment mark of that size can be obtained. Then, based on the subsequent gate process requirements, the amount of polishing required for the gate metal layer 23 in the subsequent process can be obtained. .

[0049] Specifically, the short gate area 11 in the clearance area 1 is used to form a short dummy gate structure 14 to assist in monitoring the process.

[0050] As an example, the dummy gate structure 14 includes a gate metal layer 23, a gate dielectric layer, and an isolation sidewall.

[0051] Specifically, an insulating layer is spaced between adjacent dummy gate structures 14, the gate dielectric layer is located on the upper surface of the substrate in the semiconductor structure 2, the gate metal layer 23 is located on the upper surface of the gate dielectric layer, and the isolation sidewalls cover the sidewalls of the gate metal layer 23 and the gate dielectric layer.

[0052] Specifically, the gate metal layer 23 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the gate dielectric layer is made of tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium silicate, silicon oxide, or other suitable dielectric materials; and the isolation sidewalls are made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Preferably, the gate metal layer 23 can be an aluminum gate or a tungsten gate.

[0053] As an example, the length of the dummy gate structure 14 formed in the short gate region 11 is no greater than 240 nm, and the width of the dummy gate structure 14 ranges from 200 nm to 2000 nm.

[0054] It should be noted that the length of the dummy gate structure 14 here refers to the subsequent... Figures 6 to 9 The dimension in the X direction, the width of the dummy gate structure 14 refers to the subsequent... Figures 6 to 9 The dimension in the Y direction.

[0055] Please see Figures 6 to 9 Perform steps S3 and S4: based on the risk coefficient The risk level of the butterfly-shaped depression is determined, and the distance between the short grid area 11 and the marking area 12 and the size of the dummy grid to be made in the area between the short grid area 11 and the marking area 12 are determined based on the risk level; the dummy grid structure 14 and the alignment mark 21 are made in the clearance area 1.

[0056] As an example, the risk level includes a safe zone, a risk zone, and a high-risk zone. That is, the risk level can be divided into three levels based on the relationship between the amount of grinding of the gate metal layer 23 in the short gate region 11 and the depth of the butterfly-shaped recess.

[0057] It should be noted that the metal gate fabricated in the short gate region 11 is usually located outside the alignment mark 21. The CMP process of the gate metal layer 23 of the metal gate is after the ILD0 layer fabrication process of the alignment mark 21. Therefore, the grinding amount of the CMP process of the gate metal layer 23 will affect the grinding rate of the metal layer on top of the ILD0 layer.

[0058] As an example, the risk level is in the safe zone, with a risk coefficient x = [0, 1). The short gate region 11 is adjacent to the marker region 12, meaning that the grinding amount of the gate metal layer 23 is greater than the estimated depth of the butterfly-shaped depression formed in the ILD0 layer and less than twice the depth of the butterfly-shaped depression.

[0059] Specifically, when the risk factor is between 0 and 1, due to the large grinding amount of the CMP process for the gate metal layer 23, the metal grinding rate in the area directly above the ILD0 layer can be increased, preventing metal residue from forming on the upper surface of the ILD0 layer due to the butterfly-shaped depression. This allows the short gate region 11 to be adjacent to the marking region 12. For example, taking the rectangular alignment mark 21 as an example, based on... Figure 1 The formula obtained by fitting the data corresponding to the middle structure, when the length L of the alignment mark 21 (the dimension of the mark region 12 in the X direction) is 50 μm, Å, based on the process requirements of the dummy gate structure 14 in the short gate region 11, the gate metal layer 23 is obtained. Å shows that the grinding amount of gate metal layer 23 is greater than the estimated depth of the butterfly-shaped depression, indicating a higher risk factor. The subsequent CMP process of the gate metal layer 23 in the short gate region 11 can increase the metal polishing rate above the ILD0 layer and improve the metal residue caused by the butterfly-shaped depression at the top of the ILD0 layer. Therefore, it is not necessary to set a long gate region 13 between the short gate region 11 and the marking region 12. Figure 6 As shown.

[0060] As an example, the risk level is in the risk zone, with a risk coefficient x = [-1, 0]. A long gate area 13 separates the short gate area 11 from the marking area 12. In the length direction of the marking area 12, the length of the long gate area 13 between the edge of the marking area 12 and the adjacent short gate area 11 is a first dimension. In the width direction of the marking area 12, the width of the long gate area 13 is not less than a second dimension. The length and width of the dummy gate structure 14 in the long gate area 13 are within the first and second ranges, respectively. Here, the length direction refers to... Figures 6 to 9 The X-direction and the width direction refer to Figures 6 to 9 Center Y direction.

[0061] It should be noted that the specific structure of the dummy gate structure 14 in the long gate region 13 is usually the same as that of the dummy gate structure 14 in the short gate region 11, only the size of the dummy gate structure 14 is different.

[0062] Specifically, when the risk level is in the risk zone, the grinding amount of the gate metal layer 23 is less than the depth of the butterfly recess but greater than half of the depth of the butterfly recess. Because the grinding amount of the gate metal layer 23 is relatively small compared to the depth of the butterfly recess, it is difficult to increase the grinding rate of the metal layer in the area directly above the ILD0 layer during the CMP process of the gate metal layer 23, easily resulting in metal residue at the top of the ILD0 layer. Therefore, a long gate structure of appropriate size is set in the preset area between the short gate region 11 and the marking region 12. Utilizing the thin thickness of the gate metal layer 23 in the dummy gate structure of the long gate region 13, the grinding rate of the metal directly above the marking region 12 can be effectively increased during the simultaneous CMP process of the gate metal layer 23 in the short gate region 11 and the long gate region 13, thereby improving the metal residue caused by the butterfly recess at the top of the ILD0 layer. For example, taking the rectangular alignment mark 21 as an example, based on... Figure 1 The formula obtained by fitting the data corresponding to the middle structure, when the size L of the alignment mark 21 is 500 μm, yields the following evaluation results. Å, based on the process requirements of the short gate region 11 and the dummy gate structure 14, the gate metal layer 23 is obtained. Å shows that the grinding amount of the gate metal layer 23 in the short gate region 11 is less than the estimated depth of the butterfly-shaped depression, indicating a risk factor. When the marking region 12 is adjacent to the short gate region 11, the gate metal layer 23 of the dummy gate structure 14 in the short gate region 11 is relatively thick. During the CMP process of the gate metal layer 23, it is difficult to increase the metal polishing rate directly above the marking region 12. This results in metal residue remaining on the surface of the ILD0 layer above the alignment mark 21 after the subsequent CMP process of the gate metal layer 23. Therefore, a long gate region 13 needs to be set between the marking region 12 and the short gate region 11. Figure 7As shown, by utilizing the long linewidth, large area, and thin thickness of the gate metal layer 23 of the dummy gate structure 14 in the long gate region 13, the deposition thickness of the metal layer around the marker region 12 can be effectively reduced. The marker region 12 is affected by the thin thickness of the gate metal layer 23 of the dummy gate structure 14 in the long gate region 13, which effectively increases the metal grinding rate directly above the alignment mark 21 and improves the metal residue caused by the butterfly-shaped depression at the top of the ILD0 layer of the alignment mark 21.

[0063] As an example, when the first size is not less than 50 μm and the second size is not less than 10 μm, that is, when the risk coefficient x = [-1, 0), in the X direction, the distance between the endpoint of either side of the marking area 12 and the short gate area 11 is not less than 50 μm, and in the Y direction, the size of the marking area 12 is not greater than the size of the long gate area 13, and the size of the long gate area 13 is not less than 10 μm.

[0064] As an example, when the first range is 240 nm to 900 nm and the second range is 200 nm to 2000 nm, i.e. when the risk coefficient x = [-1, 0), the size range of the dummy gate structure 14 in the long gate region 13 is 240 nm to 900 nm in the X direction and 200 nm to 2000 nm in the Y direction.

[0065] Specifically, when the risk coefficient x = [-1, 0), by ensuring that the first size is not less than 50 μm and the second size is not less than 10 μm, and that the first range is 240 nm to 900 nm and the second range is 200 nm to 2000 nm, the size of the long gate region 13 is sufficient while ensuring that the size of the dummy gate structure 14 in the long gate region 13 is large enough. This ensures that during the CMP process of the gate metal layer 23, the grinding amount of the gate metal layer 23 directly above the marking region 12 is greater than the estimated depth of the butterfly-shaped recess at the top of the ILD0 layer, thus avoiding the generation of metal residue directly above the ILD0 layer.

[0066] As an example, the risk level is in the high-risk zone, with a risk coefficient x < -1. A long grid area 13 separates the short grid area 11 from the marking area 12. Along the length of the marking area 12, the length of the long grid area 13 between the edge of the marking area 12 and the adjacent short grid area 11 is the third dimension. Along the width of the marking area 12, the width of the long grid area 13 is not less than the fourth dimension. The length and width of the dummy grid structure 14 in the long grid area 13 are within the third and fourth ranges, respectively. For example, taking a rectangular alignment mark 21 as an example, based on... Figure 1 The formula obtained by fitting the data corresponding to the middle structure, when the size L of the alignment mark 21 is 900 μm, yields the following evaluation results. Å, based on the process requirements of the short gate region 11 and the dummy gate structure 14, the gate metal layer 23 is obtained. Å shows that the grinding amount of gate metal layer 23 is less than the depth of the butterfly-shaped depression, indicating a risk factor. When the marking region 12 is adjacent to the short gate region 11, the gate metal layer 23 of the dummy gate structure 14 in the short gate region 11 is relatively thick. During the CMP process of the gate metal layer 23, it is difficult to increase the metal polishing rate directly above the marking region 12. This results in metal residue remaining on the surface of the ILD0 layer above the alignment mark 21 after the subsequent CMP process of the gate metal layer 23. Therefore, a long gate region 13 needs to be set between the marking region 12 and the short gate region 11. Figure 8 As shown, by utilizing the long linewidth, large area, and thin thickness of the gate metal layer 23 of the dummy gate structure 14 in the long gate region 13, the deposition thickness of the metal layer around the marker region 12 can be effectively reduced. The marker region 12 is affected by the thin thickness of the gate metal layer 23 of the dummy gate structure 14 in the long gate region 13, which effectively increases the metal grinding rate directly above the alignment mark 21 and improves the metal residue caused by the butterfly-shaped depression at the top of the ILD0 layer of the alignment mark 21.

[0067] Specifically, when the risk level is in the high-risk zone, the grinding amount of the gate metal layer 23 is less than half the depth of the butterfly-shaped depression. Since the thickness of the gate metal layer 23 is relatively thick, the metal grinding amount in the CMP process of the gate metal layer 23 is relatively small compared to the depth of the butterfly-shaped depression. During the CMP process of the gate metal layer 23, the metal grinding rate in the area directly above the ILD0 layer cannot be increased, as metal residue is easily generated at the top of the ILD0 layer. Therefore, a long gate structure of appropriate size needs to be set in the preset area between the short gate area 11 and the marking area 12. By utilizing the thinner thickness of the gate metal layer 23 in the long gate structure, the grinding amount in the CMP process is larger, thereby increasing the metal grinding rate in the area directly above the marking area 12 surrounded by the long gate area 13, and thus removing the metal residue at the top of the ILD0 layer due to the butterfly-shaped depression.

[0068] As an example, the third dimension is not less than 50 μm and the fourth dimension is not less than 10 μm. That is, when the risk coefficient x < -1, in the X direction, the distance between the endpoint of either side of the marking area 12 and the short gate area 11 is not less than 50 μm, and in the Y direction, the size of the marking area 12 is not greater than the size of the long gate area 13, and the size of the long gate area 13 is not less than 10 μm.

[0069] As an example, the third range is 900 nm to 50000 nm, and the fourth range is 200 nm to 2000 nm. That is, when the risk factor x < -1, the size range of the dummy gate structure 14 in the long gate region 13 is 900 nm to 50000 nm in the X direction and 200 nm to 2000 nm in the Y direction.

[0070] Specifically, when the risk factor x < -1, by ensuring that the third dimension is not less than 50 μm and the fourth dimension is not less than 10 μm, and that the third dimension ranges from 900 nm to 50000 nm and the fourth dimension ranges from 200 nm to 2000 nm, the size of the long gate region 13 is sufficient while ensuring that the size of the dummy gate structure 14 in the long gate region 13 is large enough. This ensures that during the CMP process of the gate metal layer 23, the grinding amount of the gate metal layer 23 directly above the marking region 12 is greater than the estimated depth of the butterfly-shaped recess at the top of the ILD0 layer, thus avoiding metal residue directly above the ILD0 layer.

[0071] Specifically, after obtaining the risk coefficient of the butterfly-shaped recess based on the size of the alignment mark 21, before fabricating the dummy grid structure 14, it is usually necessary to select the corresponding size of the long grid area 13 and the size of the dummy grid structure 14 in the long grid area 13 based on the risk level, and modify the pattern in the corresponding photomask based on the size of the long grid area 13 and the size of the grid structure in the long grid area 13, so as to facilitate the subsequent fabrication of the dummy grid structure 14.

[0072] It should be noted that before fabricating the dummy gate structure 14 in the clearance area 1, a photomask with the corresponding process needs to be fabricated. Therefore, the risk factor assessment can be conducted before device fabrication or after the STI structure in the 3D alignment mark 21 is fabricated and before the dummy gate structure 14 is fabricated.

[0073] Specifically, in the process of fabricating the dummy gate structure 14, a gate dielectric layer, a dummy gate layer and an isolation sidewall are usually formed on the upper surface of the semiconductor structure 2. Then, the corresponding doped regions in the device structure are doped and the ILD0 layer 22 is fabricated. Finally, the dummy gate layer is removed and the gate metal layer 23 is formed.

[0074] It should be noted that when etching the dummy gate layer and the risk factor is not greater than 0, the pattern of the mask used to fabricate the dummy gate layer needs to be improved accordingly based on the evaluation results. For example, if the risk factor is between -1 and 0, a long gate region 13 of appropriate size is added between the short gate region 11 and the marking region 12, and a pattern of dummy gate structure 14 with X-direction dimensions and Y-direction dimensions in the long gate region 13 is set. If the risk factor is less than -1, a long gate region 13 of appropriate size is added between the short gate region 11 and the marking region 12, and a pattern of dummy gate structure 14 with X-direction dimensions and Y-direction dimensions in the long gate region 13 is set.

[0075] Specifically, the methods for forming the gate dielectric layer include thermal oxidation, chemical vapor deposition, physical vapor deposition, atomic layer deposition and atomic vapor deposition or other suitable methods; the methods for forming the pseudo gate layer include chemical vapor deposition, physical vapor deposition or other suitable methods; the methods for forming the ILD0 layer 22 include chemical vapor deposition, physical vapor deposition or other suitable methods.

[0076] Specifically, in the process of forming the isolation sidewall after etching the pseudo gate layer and before forming the ILD0 layer 22, it is usually necessary to first deposit the corresponding film structure and then obtain the isolation sidewall through the etching process.

[0077] It should be noted that after the deposition of ILD0 layer 22, ILD0 layer 22 covers the exposed surfaces of the dummy gate layer and isolation sidewalls, and its upper surface is higher than the upper surface of the dummy gate layer. Therefore, after forming ILD0 layer 22, it is necessary to thin ILD0 layer 22 using a CMP process to expose the upper surface of the dummy gate layer. After the CMP process, the dummy gate layer is removed to obtain the corresponding trenches. Then, the gate metal layer 23, which fills the trenches and covers the exposed upper surface of ILD0 layer 22, is formed, followed by a CMP process on the gate metal layer 23 on the upper surface of ILD0 layer 22. Figure 9 As shown.

[0078] Specifically, before fabricating the dummy gate structure 14 in the clearance area 1, the depth of the butterfly-shaped recess at the top of the ILD0 layer 22 in the alignment mark 21 is evaluated based on the length of the marking area 12. Then, based on the depth of the butterfly-shaped recess and the amount of metal grinding of the gate metal layer 23 of the dummy gate structure 14 in the short gate area 11, the risk level of the butterfly-shaped recess is determined. Finally, based on the risk level, it is determined whether to set a long gate area 13 and the size of the dummy gate structure 14 in the long gate area 13, so that in the subsequent CMP process of the gate metal layer 23 of the dummy gate structure 14, the grinding amount of the gate metal layer 23 is greater than the depth of the butterfly-shaped recess, thereby increasing the metal grinding rate above the alignment mark 21 and improving the metal residue caused by the butterfly-shaped recess at the top of the alignment mark 21.

[0079] In summary, the 3D alignment mark fabrication method of the present invention evaluates the depth of the butterfly-shaped recess at the top of the ILD0 layer in the alignment mark based on the fitted relationship between the depth of the butterfly-shaped recess and the length of the alignment mark before fabricating the dummy gate structure around the marking area. Then, based on the butterfly-shaped recess depth and the amount of metal grinding in the gate metal layer of the dummy gate structure in the short gate area, the risk level of the butterfly-shaped recess is determined. Finally, based on the risk level, it is determined whether to set a long gate area and the size of the dummy gate structure in the long gate area. This ensures that in the subsequent CMP process of the gate metal layer of the dummy gate structure, the grinding amount of the gate metal layer is greater than the depth of the butterfly-shaped recess, thereby increasing the metal grinding rate above the alignment mark and improving the metal residue caused by the butterfly-shaped recess at the top of the alignment mark. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating 3D alignment markers, characterized in that, Includes the following steps: Multiple sets of data on different alignment mark sizes and the depth of the corresponding butterfly-shaped depression are provided. The depth of the butterfly-shaped depression is obtained by fitting the data. Where L is the length of the alignment mark, and a, b, c, and d are constants; A semiconductor structure is provided that includes an edge clearance region comprising a marker region and a short gate region surrounding the marker region. The depth of the butterfly recess is estimated based on the process requirements of the alignment markers in the marker region and a formula for the depth of the butterfly recess. Simultaneously, the grinding amount of the gate metal layer is calculated based on the process requirements of the dummy gate structure in the short gate region. , The height of the gate metal layer before grinding. The height of the gate metal layer after grinding; Based on risk coefficient The risk level of the butterfly-shaped indentation is determined, and based on the risk level, the distance between the short gate area and the marking area and the size of the dummy gate structure to be fabricated in the area between the short gate area and the marking area are determined; The dummy gate structure and the alignment mark are fabricated within the clearance area.

2. The method for fabricating 3D alignment markers according to claim 1, characterized in that: The risk levels are categorized into safe zones, risk zones, and high-risk zones.

3. The method for fabricating 3D alignment markers according to claim 2, characterized in that: The risk level is within the safe zone, the risk coefficient x = [0, 1), and the short gate area is adjacent to the marked area.

4. The method for fabricating 3D alignment markers according to claim 2, characterized in that: The risk level is within the risk zone, the risk coefficient x = [-1, 0), a long grid zone is spaced between the short grid zone and the marking zone, the length of the long grid zone between the marking zone and the edge of the adjacent short grid zone is a first dimension in the length direction of the marking zone, and the width of the long grid zone is not less than a second dimension in the width direction of the marking zone, and the length and width of the dummy grid structure in the long grid zone are respectively within the first range and the second range.

5. The method for fabricating 3D alignment markers according to claim 4, characterized in that: The first dimension is not less than 50 μm, and the second dimension is not less than 10 μm; or the first range is 240 nm to 900 nm, and the second range is 200 nm to 2000 nm.

6. The method for fabricating 3D alignment markers according to claim 2, characterized in that: The risk level is in the high-risk zone, the risk coefficient x < -1, a long grid area is spaced between the short grid area and the marking area, the length of the long grid area between the edge of the marking area and the edge of the adjacent short grid area is the third dimension in the length direction of the marking area, the width of the long grid area is not less than the fourth dimension in the width direction of the marking area, and the length and width of the dummy grid structure in the long grid area are in the third range and the fourth range, respectively.

7. The method for fabricating 3D alignment markers according to claim 6, characterized in that: The third dimension is not less than 50 μm, and the fourth dimension is not less than 10 μm; or the third range is 900 nm to 50000 nm, and the fourth range is 200 nm to 2000 nm.

8. The method for fabricating 3D alignment markers according to claim 1, characterized in that: The length of the dummy gate structure formed in the short gate region is no greater than 240 nm, and the width of the dummy gate structure ranges from 200 nm to 2000 nm.

9. The method for fabricating 3D alignment markers according to claim 1, characterized in that: The dummy gate structure includes a gate metal layer and a gate dielectric layer.

10. The method for fabricating 3D alignment markers according to claim 1, characterized in that: The alignment mark includes a trench embedded in the marking area and a dielectric layer filling the trench.

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