Semiconductor package with identification pattern

Abstract

A semiconductor package includes: a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; a molding layer on the package substrate and covering the semiconductor chip; and a marking pattern on the molding layer. The marking pattern has an upper surface, a lower surface opposite to the upper surface, and a side surface connecting the upper and lower surfaces. In a plan view, the marking pattern has a planar shape corresponding to a marking, and the distance from the upper end of the side surface of the marking pattern to the upper surface of the package substrate is equal to the distance from the upper surface of the semiconductor package to the upper surface of the package substrate. The semiconductor package further includes: a connection terminal below the package substrate and electrically connected to the package substrate.

Description

Technical Field

[0001] Some example embodiments of this disclosure relate to semiconductor packages with identification display functionality. Background Technology

[0002] With the development of the electronics industry, semiconductor chips have been widely used due to their small size and multifunctionality. Semiconductor chips are typically used in the form of packages to ensure their reliability during application. A semiconductor package includes a semiconductor chip disposed on a package substrate. A molding layer can be disposed on the package substrate and can cover the semiconductor chip to protect it from external factors (e.g., impact, foreign matter, corrosion, etc.), thereby improving the reliability of the semiconductor chip.

[0003] For product identification, it may be necessary to identify or include various product-related information (such as brand, model, production date, batch number, country of origin, etc.) on the semiconductor package, which includes the semiconductor chip. Typically, the identification information is located on the top of the semiconductor package and may include product-related information. Summary of the Invention

[0004] Some example embodiments of this disclosure provide semiconductor packages that can have reduced size (e.g., reduced thickness) and / or improved reliability (e.g., improved thermal reliability and / or EMI shielding characteristics) while including structures for identifying information.

[0005] Some example embodiments of this disclosure provide semiconductor packages that can have improved reliability (e.g., improved structural stability) while including structures for identifying information.

[0006] Some example embodiments of this disclosure provide semiconductor packages that can have improved productivity while including structures for identifying information.

[0007] Some example embodiments of this disclosure provide a method for manufacturing a semiconductor package that can form an information identification structure for the semiconductor package and may have improved process reliability and / or improved productivity.

[0008] According to some example embodiments of this disclosure, a semiconductor package includes: a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; a molding layer on the package substrate and covering the semiconductor chip; a marking pattern on the molding layer, the marking pattern having an upper surface, a lower surface opposite to the upper surface, and a side surface connecting the upper and lower surfaces, the marking pattern having a shape corresponding to a marking in a plan view, and the distance from the upper end of the side surface of the marking pattern to the upper surface of the package substrate is equal to the distance from the upper surface of the semiconductor package to the upper surface of the package substrate; and a connection terminal below the package substrate and electrically connected to the package substrate.

[0009] In some example embodiments, the marking pattern may have a thickness ranging from about 3 μm to about 7 μm.

[0010] In some example embodiments, the distance between the lower surface of the marking pattern and the upper surface of the semiconductor chip may be less than about 75 μm (e.g., less than or equal to about 50 μm, or less than or equal to about 45 μm).

[0011] In some example embodiments, the marking pattern may include at least one of phase change material, EMI shielding material, and insulating material.

[0012] In some example embodiments, the marking pattern may include solder or EMI shielding metal.

[0013] In some example embodiments, the logo pattern may cover the semiconductor chip over the molding layer.

[0014] In some example embodiments, the marking pattern may include epoxy insulating resin.

[0015] In some example embodiments, the semiconductor package may further include an insulating layer extending on the molding layer, the insulating layer covering the lower and side surfaces of the marking pattern and exposing the upper surface of the marking pattern, and the semiconductor chip may be located below the marking pattern.

[0016] In some example embodiments, the upper surface of the marking pattern may be substantially coplanar with the upper surface of the insulating layer.

[0017] In some example embodiments, the lower surface of the marking pattern may be spaced apart from the upper surface of the molding layer.

[0018] In some example embodiments, the insulating layer may include a bare die attachment film.

[0019] In some example embodiments, the insulating layer may have a thickness ranging from about 5 μm to about 40 μm.

[0020] In some example embodiments, the insulating layer may have a thickness ranging from about 5 μm to about 12 μm.

[0021] In some example embodiments, the molding layer may cover the lower and side surfaces of the logo pattern and expose the upper surface of the logo pattern.

[0022] In some example embodiments, the upper surface of the logo pattern may be coplanar with the upper surface of the molding layer.

[0023] In some example embodiments, the molding layer may cover the upper surface of the semiconductor chip and space the marking pattern from the semiconductor chip.

[0024] In some example embodiments, the semiconductor package may further include: bonding wires between a chip pad of the semiconductor chip and a substrate pad of the package substrate, electrically connecting the semiconductor chip and the package substrate, wherein the chip pad is on the upper surface of the semiconductor chip and the substrate pad is on the upper surface of the package substrate.

[0025] In some example embodiments, the semiconductor package may further include an insulating layer extending on the molding layer. The insulating layer may cover the lower and side surfaces of the marking pattern and expose the upper surface of the marking pattern, and the bonding wires may contact the lower surface of the insulating layer.

[0026] In some example embodiments, the bonding wires may be between the semiconductor chip and the marking pattern, and the bonding wires may be spaced apart from the marking pattern.

[0027] In some example embodiments, the connection terminal may be coupled to a substrate underpad of the package substrate, and the substrate underpad may be on the lower surface of the package substrate.

[0028] In some example embodiments, the identifier (e.g., a predetermined identifier) ​​may include an identifier that indicates product-related information about the semiconductor package, and the identifier may consist of one or more of text, numbers, and graphics.

[0029] In some example embodiments, the identification pattern may include a plurality of sub-patterns that are spaced apart in the horizontal direction and extend continuously, and the identification may be composed of at least one of the plurality of sub-patterns.

[0030] In some example embodiments, the marking pattern may include a plurality of sub-patterns spaced apart in a horizontal direction and extending continuously, each of the plurality of sub-patterns including an upper surface, a lower surface opposite to the upper surface and a side surface between the upper and lower surfaces, and in each of the plurality of sub-patterns, the upper surface, lower surface and side surface of the sub-pattern may define a single closed three-dimensional shape.

[0031] In some example embodiments, the upper surface of the identification pattern may include the upper surfaces of the plurality of sub-patterns, the lower surface of the identification pattern may include the lower surfaces of the plurality of sub-patterns, and the side surface of the identification pattern may include the side surfaces of the plurality of sub-patterns.

[0032] According to some example embodiments of this disclosure, a method of manufacturing a semiconductor package includes: forming an identification pattern on a first substrate, the identification pattern having at least partially a shape corresponding to an identification in a plan view; disposing a semiconductor chip on a first side of a second substrate and electrically connecting the semiconductor chip to the second substrate; applying a molding material to the first substrate; placing the second substrate on the first substrate such that the semiconductor chip and the identification pattern are between the second substrate and the first substrate; molding the molding material to form a molding layer covering the semiconductor chip; forming a connection terminal electrically connected to the second substrate on a second side of the second substrate without the semiconductor chip; and removing the first substrate.

[0033] In some example embodiments, the first substrate may have the same coefficient of thermal expansion as the second substrate.

[0034] In some example embodiments, the method may further include: bonding an insulating layer to one side of a first substrate that includes a marking pattern. The insulating layer may cover the marking pattern, wherein the marking pattern may include a phase change material or an EMI shielding material, and wherein the application may involve applying a molding compound to the insulating layer. In some example embodiments, the method may further include: placing a laminated structure including a first substrate, a marking pattern, and an insulating layer on a release film within a mold, such that the first substrate contacts the release film; applying a molding compound to the insulating layer; and placing a second substrate on the molding compound such that a semiconductor chip contacts the molding compound, and the molding compound is positioned between the second substrate and the insulating layer.

[0035] In some example embodiments, the insulating layer may cover the surfaces of the marking pattern other than the surface in contact with the first substrate.

[0036] In some example embodiments, the marking pattern may include an insulating material, and the application may involve applying a molding material onto a first substrate to cover the marking pattern.

[0037] In some example embodiments, the molding material may cover the remaining surfaces of the marking pattern except for the surface that contacts the first substrate.

[0038] In some example embodiments, the step of removing the first substrate may include irradiating the first substrate with ultraviolet light and then removing the first substrate.

[0039] In some example embodiments, the first substrate may include an adhesive layer, and the first substrate may be secured to the marking pattern by the adhesive layer.

[0040] In some example embodiments, the adhesive layer may be configured to have reduced adhesion after exposure to ultraviolet light.

[0041] In some example embodiments, the adhesive layer may include an adhesive resin that is capable of decomposing under ultraviolet light conditions.

[0042] In some example embodiments, the step of electrically connecting the semiconductor chip to the second substrate may include: using bonding wires to electrically connect the semiconductor chip to the second substrate, the bonding wires being between the chip pads of the semiconductor chip and the substrate pads of the second substrate.

[0043] In some example embodiments, the step of forming a connection terminal may include: forming a connection terminal to attach the connection terminal to the substrate pad of the second substrate.

[0044] In some example embodiments, a semiconductor package may include: a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; a molding layer on the package substrate and covering the semiconductor chip; an insulating layer on the molding layer, the insulating layer defining an identification pattern on the upper surface of the insulating layer, the upper end of the identification pattern being at a distance from the upper surface of the package substrate equal to the distance from the upper surface of the semiconductor package to the upper surface of the package substrate, and the thickness of the identification pattern being less than the distance between the lower surface of the identification pattern and the upper surface of the semiconductor chip; and a connection terminal below the package substrate and electrically connected to the package substrate.

[0045] In some example embodiments, the insulating layer may cover the lower and side surfaces of the marking pattern and expose the upper surface of the marking pattern, and the semiconductor chip may be located below the marking pattern.

[0046] In some example embodiments, the semiconductor package may further include: bonding wires between a chip pad of the semiconductor chip and a substrate pad of the package substrate, electrically connecting the semiconductor chip and the package substrate, wherein the chip pad is on the upper surface of the semiconductor chip and the substrate pad is on the upper surface of the package substrate.

[0047] In some example embodiments, the bonding wire may define at least one bend, and the at least one bend may contact the insulating layer.

[0048] In some example embodiments, the bonding wire may be defined at least one bend between the semiconductor chip and the marking pattern, and the at least one bend may be spaced apart from the marking pattern.

[0049] In some example embodiments, the area of ​​the marking pattern may be larger than the area of ​​the semiconductor chip. Attached Figure Description

[0050] The above and other aspects and features will become clearer from the following description of exemplary embodiments in conjunction with the accompanying drawings.

[0051] Figure 1 This is a schematic cross-sectional view showing a semiconductor package.

[0052] Figure 2 This is a schematic cross-sectional view of a semiconductor package according to some example embodiments of the present disclosure.

[0053] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F This is a schematic cross-sectional view of operations in a method of manufacturing a semiconductor package according to some example embodiments of the present disclosure.

[0054] Figure 4 This is a schematic cross-sectional view of a semiconductor package according to some example embodiments of the present disclosure.

[0055] Figure 5A , Figure 5B and Figure 5C This is a schematic cross-sectional view of operations in a method of manufacturing a semiconductor package according to some example embodiments of the present disclosure. Detailed Implementation

[0056] The exemplary embodiments will be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments. The exemplary embodiments described herein are provided as examples, and therefore, this disclosure is not limited thereto, but can be implemented in various forms. Each embodiment provided in the following description does not exclude association with another example or another embodiment also provided herein or not provided herein but consistent with this disclosure. In the drawings, various elements, components, layers, regions, etc., may be drawn out of scale for clarity. In the drawings, the same or similar reference numerals denote the same or similar components.

[0057] For descriptive purposes, spatial relative terms such as “below,” “lower,” “bottom,” “above,” “upper,” and “top” may be used herein to describe the relationship between one element and another (or more) of elements as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to include different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” other elements or features would subsequently be positioned “above” said other elements or features. Thus, the exemplary term “below” can include both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0058] As used herein, the terms “basically,” “about,” “approximately,” and other similar terms are used as approximate terms rather than as terms of degree, so that they are used to account for inherent deviations in measured, calculated, and / or provided values ​​that would be recognized by one of ordinary skill in the art. When the terms “about” or “approximately” are used in conjunction with numerical values, it means that the associated numerical value includes manufacturing tolerances (e.g., ±10%) near the stated numerical value. Furthermore, when the terms “basically” and “approximately” are used in conjunction with shape, it means that no precision in geometry is required, and the tolerance of the shape is within the disclosed range. Moreover, regardless of whether a numerical value or shape is modified with “basically,” “about,” or “approximately,” it will be understood that such numerical values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near the stated numerical value or shape.

[0059] It will be understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on said other element, or an intervening element may be present. Conversely, when an element is referred to as "directly on" another element, no intervening element is present. It will also be understood that when an element is referred to as "on" another element, the element may be above, below, or adjacent to said other element (e.g., horizontally adjacent).

[0060] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” when appended to (before) a list of elements modify the entire list, not individual elements within that list. For example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”, “at least one of A, B, or C”) can be understood as only A, only B, only C, or any combination of two or more of A, B, and C (e.g., ABC, AB, BC, and AC).

[0061] As used herein, elements described as being "spaced apart" from another element generally and / or in a particular direction (e.g., vertically spaced apart, laterally (laterally) spaced apart, etc.), and / or described as being separated from another element, can be understood as being isolated from direct contact with said other element generally and / or in a particular direction (e.g., isolated from direct contact with said other element in the vertical direction, isolated from direct contact with said other element in the lateral (lateral) or horizontal direction, etc.). Similarly, elements described as being "spaced apart" from each other generally and / or in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.), and / or described as being "separated" from each other, can be understood as being isolated from direct contact with each other generally and / or in a particular direction (e.g., isolated from direct contact with each other in the vertical direction, isolated from direct contact with each other in the lateral or horizontal direction, etc.). Similarly, structures described herein as being between two other structures to separate said two other structures from each other can be understood as being configured to isolate said two other structures from direct contact with each other.

[0062] Figure 1 This is a schematic cross-sectional view of a semiconductor package.

[0063] Reference Figure 1 The semiconductor package 10 may include a package substrate 110, a semiconductor chip 120, a molding layer 130, and a connection terminal 160.

[0064] like Figure 1As shown, a semiconductor chip 120 may be disposed on a package substrate 110. The semiconductor chip 120 may be electrically connected to the package substrate 110 via wire bonding. For example, as shown, a bonding wire 140 may be disposed between the semiconductor chip 120 and the package substrate 110 to electrically connect the semiconductor chip 120 to the package substrate 110. A connection terminal 160 may be bonded to the package substrate 110 below the package substrate 110 and may be electrically connected to and via the package substrate 110 to the semiconductor chip 120. The connection terminal 160 may serve as an external connection terminal of the semiconductor package 10 to allow the semiconductor package 10 (e.g., semiconductor chip 120) to receive power and / or signals from external devices (e.g., motherboard, intermediate substrate, external electronic components, etc.) and to transmit signals to external devices.

[0065] like Figure 1 As shown, the molding layer 130 may be disposed on the package substrate 110 and cover the semiconductor chip 120. For example, as shown, the molding layer 130 may encapsulate the semiconductor chip 120 and may also encapsulate the bonding wires 140 that electrically connect the semiconductor chip 120 to the package substrate 110, thereby protecting the semiconductor chip 120 and the bonding wires 140 from external factors (e.g., impact, foreign matter, corrosion, etc.).

[0066] To identify product-related information or other identifying marks, such as Figure 1 As shown, a groove G may be formed on the top of the molding layer 130 in the semiconductor package 10. The groove G may be formed with a planar shape in a planar view corresponding to the product-related information to be identified, such that the product-related information of the semiconductor package 10 can be visually identified when viewed from the side of the molding layer 130 of the semiconductor package 10 (e.g., in a top view). In the semiconductor package 10, the display of product-related information can be achieved by forming a groove G with a planar shape corresponding to the planar shape of the product-related information on the top of the molding layer 130 using a laser process (such as laser ablation, laser engraving, or laser printing).

[0067] Due to the characteristics of laser processing (e.g., precision, power, etc.), the manageable depth (i.e., processing precision in depth) of laser processing can be no less than 10 micrometers (μm). For example, the manageable depth of laser processing can range from about 10 μm to about 50 μm. Therefore, the groove G formed using laser processing can also have a depth Dp greater than or equal to 10 μm (e.g., from about 10 μm to about 50 μm). In this case, the molding layer 130 may need to have a sufficiently large thickness to provide sufficient space at its top (or upper part) for forming the groove G. Therefore, the semiconductor package 10 with the groove G formed in the molding layer 130 can have an increased thickness compared to a semiconductor package 10 without a groove formed in its molding layer.

[0068] Furthermore, during the laser process used to form the groove G, problems such as heat concentration and overcutting can occur near the location where the groove G is formed in the molding layer 130 due to the high energy characteristics of the laser. In the semiconductor package 10 using wire bonding, the portion of the semiconductor chip 120 where the functional circuit layer is formed (e.g., the portion adjacent to the active surface) and the protruding portion of the bonding wire 140 can be easily affected by heat concentration and / or overcutting due to their proximity to the bottom of the groove G. Therefore, in the semiconductor package 10, the portion of the molding layer 130 above the semiconductor chip 120 and / or the bonding wire 140 can be formed relatively thick to maintain a relatively large spacing between the semiconductor chip 120 and / or the bonding wire 140 and the bottom of the groove G.

[0069] For the reasons mentioned above, such as Figure 1 As shown, the semiconductor package 10 may need to be configured to have a sufficient mold gap Gm. Here, the term "mold gap" may refer to the distance in the vertical direction VD between the bottom surface Gb of the groove G and the chip surface 120u of the semiconductor chip 120, wherein the vertical direction VD may be the thickness direction of the semiconductor package 10 or a direction perpendicular to the chip surface 120u of the semiconductor chip 120 or the substrate surface 110u of the package substrate 110. In some cases (e.g., in wire bonding and / or in cases where the groove is formed by laser process), the mold gap Gm of the semiconductor package 10 may be configured to be greater than about 75 μm. As a result, when the semiconductor package 10 includes the above-described structure for displaying product-related information (e.g., the groove G formed by laser process), the semiconductor package 10 may have a relatively large thickness. For the above-described semiconductor package 10, simultaneously achieving the display of product-related information and a thin package thickness can be challenging.

[0070] Furthermore, the molding layer 130 can be formed using a molding process employing a molding material. However, since the coefficient of thermal expansion (CTE) of the molding material and the molding layer 130 formed therethrough can differ from that of the package substrate 110, warping can occur in the resulting stacked assembly when the molding process is performed with only the molding material covering the semiconductor chip on the package substrate 110. As a result, the formed semiconductor package 10 may also exhibit warping problems.

[0071] Hereinafter, some exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0072] Figure 2 This is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.

[0073] Reference Figure 2 According to some example embodiments, the semiconductor package 100 may include a package substrate 110, a semiconductor chip 120, a molding layer 130, a marking pattern 150, and a connection terminal 160.

[0074] The package substrate 110 can be any suitable substrate for a semiconductor package. For example, the package substrate 110 can be a printed circuit board, a glass substrate, a ceramic substrate, a semiconductor substrate, etc., in which conductive paths are formed, but is not limited thereto.

[0075] like Figure 2 As shown, the encapsulation substrate 110 may have an upper substrate surface 110u and a lower substrate surface 110b. Each of the upper substrate surface 110u and the lower substrate surface 110b may be substantially flat or planar. For example, each of the upper substrate surface 110u and the lower substrate surface 110b may extend in a horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2), and the upper substrate surface 110u and the lower substrate surface 110b may be opposite each other in a vertical direction VD. As used herein, the first horizontal direction HD1 and the second horizontal direction HD2 may be different from each other and parallel to either the upper substrate surface 110u or the lower substrate surface 110b of the encapsulation substrate 110, and the vertical direction VD may be substantially perpendicular or orthogonal to either the upper substrate surface 110u or the lower substrate surface 110b. The first horizontal direction HD1 and the second horizontal direction HD2 may intersect each other (e.g., substantially perpendicular or orthogonal to each other), and the vertical direction VD may be substantially perpendicular or orthogonal to both the first horizontal direction HD1 and the second horizontal direction HD2. For example, the vertical direction VD can be the thickness direction of the semiconductor package 100 or the package substrate 110.

[0076] The package substrate 110 may include a substrate pad 110Pu. The substrate pad 110Pu may be disposed at the upper surface 110u of the package substrate 110. For example, as Figure 2 As shown, the substrate pad 110Pu may be disposed in a portion of the package substrate 110 adjacent to or close to the substrate upper surface 110u, and may be exposed from the substrate upper surface 110u. However, the example embodiments are not limited thereto, and in some example embodiments, the substrate pad 110Pu may be configured to protrude above the substrate upper surface 110u.

[0077] In some example embodiments, the package substrate 110 may include a plurality of on-substrate pads 110Pu. The plurality of on-substrate pads 110Pu may be disposed at the substrate upper surface 110u of the package substrate 110 in any suitable planar layout, and may, for example, surround the semiconductor chip 120, which will be described later, in a plan view. The planar layout of the plurality of on-substrate pads 110Pu may be determined based on the connection of the semiconductor chip 120 to the package substrate 110, and is not particularly limited thereto.

[0078] The package substrate 110 may further include a substrate underpad 110Pb. The substrate underpad 110Pb may be disposed at the lower substrate surface 110b of the package substrate 110. For example, as Figure 2 As shown, the under-substrate pad 110Pb may be disposed in a portion of the package substrate 110 adjacent to or close to the under-substrate surface 110b, and may be exposed from the under-substrate surface 110b. However, the example embodiments are not limited thereto, and in some example embodiments, the under-substrate pad 110Pb may be configured to protrude below the under-substrate surface 110b of the package substrate 110.

[0079] In some example embodiments, the package substrate 110 may include a plurality of underbase pads 110Pb. The plurality of underbase pads 110Pb may be disposed at the underbase surface 110b of the package substrate 110 in any suitable planar layout. The planar layout of the plurality of underbase pads 110Pb may be determined based on the planar layout of the connection terminals 160, which will be described later, and is not particularly limited thereto.

[0080] Each of the upper substrate pad 110Pu and the lower substrate pad 110Pb may include a conductive material. In some example embodiments, each of the upper substrate pad 110Pu and the lower substrate pad 110Pb may include a metal, an alloy, and / or a metal nitride, but the example embodiments are not limited thereto.

[0081] The encapsulation substrate 110 may also include a plurality of conductive paths. These conductive paths may extend within the encapsulation substrate 110 and may be electrically insulated or isolated from each other by an insulating material (e.g., one or more insulating layers) further included in the encapsulation substrate 110. In some example embodiments, the plurality of conductive paths may be respectively disposed between a plurality of upper substrate pads 110Pu and a plurality of lower substrate pads 110Pb in the encapsulation substrate 110 to respectively connect the plurality of upper substrate pads 110Pu to the plurality of lower substrate pads 110Pb. For example, one end of a conductive path adjacent to the upper substrate surface 110u may be connected to the corresponding upper substrate pad 110Pu, and the other end of a conductive path adjacent to the lower substrate surface 110b may be connected to the corresponding lower substrate pad 110Pb, thereby forming an electrical path between the upper substrate surface 110u and the lower substrate surface 110b of the encapsulation substrate 110.

[0082] Each of the conductive paths can have any suitable construction. For example, each of the conductive paths can consist of one or more wirings and one or more vias. Each wiring can extend within the package substrate 110 in a horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2), and each via can extend within the package substrate 110 in a vertical direction VD, and corresponding wirings and vias can be coupled to each other and electrically connected to form a conductive path. In some example embodiments, the components constituting the conductive path (e.g., wirings and vias) can include conductive materials. For example, the components constituting the conductive path (e.g., wirings and vias) can include, but are not limited to, metals, alloys, and / or metal nitrides.

[0083] Reference Figure 2 The semiconductor chip 120 may be disposed on the package substrate 110 and electrically connected to the package substrate 110. For example, the semiconductor chip 120 may be disposed on the substrate upper surface 110u of the package substrate 110 and electrically connected to the substrate upper pad 110Pu of the package substrate 110.

[0084] like Figure 2 As shown, the semiconductor chip 120 may have an upper chip surface 120u and a lower chip surface 120b. Each of the upper chip surface 120u and the lower chip surface 120b may be substantially flat or planar. For example, each of the upper chip surface 120u and the lower chip surface 120b may extend in a horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2), and the upper chip surface 120u and the lower chip surface 120b may be opposite each other in a vertical direction (e.g., a vertical direction VD).

[0085] The semiconductor chip 120 may include a circuit structure (also called a functional circuit layer) for implementing a predetermined or set function, and the circuit structure or functional circuit layer may be disposed inside the semiconductor chip 120. Figure 2 In the example embodiment shown, the circuit structure or functional circuit layer may be considered to be formed in the portion of the semiconductor chip 120 adjacent to the upper surface 120u of the chip.

[0086] The semiconductor chip 120, including functional circuit layers, can be configured to implement various functions such as logic functions and storage functions. For example, the semiconductor chip 120 may include or be a central processing unit, graphics processing unit, digital signal processor, microprocessor, or volatile or non-volatile memory, but is not limited thereto. Depending on the type of semiconductor chip 120, the circuit structure in the semiconductor chip 120 can be composed of various suitable active and / or passive components. For example, the circuit structure in the semiconductor chip 120 can be formed from, for example, transistors, capacitors, resistors, inductors, contacts, and / or interconnects, but is not limited thereto.

[0087] In some example embodiments, a desired circuit structure or functional circuit layer can be formed within the semiconductor chip 120 by performing various suitable semiconductor processes on the wafer (e.g., a silicon wafer). For example, semiconductor processes used herein may include, but are not limited to, ion implantation processes, deposition processes, masking processes, etching processes, planarization processes, dicing processes, etc. For example, each of the components constituting the circuit structure or functional circuit layer can be formed using various suitable materials (e.g., but not limited to, elemental or compound semiconductors, metals, oxides, nitrides, silicides, carbides, etc.).

[0088] The semiconductor chip 120 may also include a chip pad 120P. The chip pad 120P is electrically connected to a functional circuit layer inside the semiconductor chip 120. For example... Figure 2 As shown, chip pad 120P may be disposed at the upper surface 120u of semiconductor chip 120. For example, as shown, chip pad 120P may be disposed in a portion of semiconductor chip 120 adjacent to the upper surface 120u and may be exposed from the upper surface 120u. However, the example embodiments are not limited thereto, and in some example embodiments, chip pad 120P may be configured to protrude above the upper surface 120u of semiconductor chip 120.

[0089] Additional connectors may be further disposed between the chip pad 120P and the contacts of the functional circuit layer to electrically connect the chip pad 120P to the functional circuit layer. The functional circuit layer inside the semiconductor chip 120 can receive power and / or signals from the outside through the chip pad 120P, and can transmit signals to the outside through the chip pad 120P. The chip pad 120P may be a chip terminal for electrically connecting the semiconductor chip 120 to the outside.

[0090] In some example embodiments, the semiconductor chip 120 may include a plurality of chip pads 120P. The plurality of chip pads 120P may be disposed at the upper surface 120u of the semiconductor chip 120 in any suitable planar layout. The planar layout of the plurality of chip pads 120P may be determined according to the interconnection requirements of the semiconductor chip 120 itself. Furthermore, the plurality of chip pads 120P may be divided as needed into signal pads for signal transmission and / or power pads for power transmission, but are not limited thereto. In addition to signal pads and power pads, the plurality of chip pads 120P may also include pads for other functions.

[0091] Chip pad 120P may include a conductive material. For example, chip pad 120P may include metals, alloys and / or metal nitrides, but is not limited thereto.

[0092] exist Figure 2In the example embodiments shown, the semiconductor chip 120 may be disposed, positioned, or arranged on the upper substrate surface 110u of the package substrate 110. When arranged, the lower chip surface 120b of the semiconductor chip 120 may face the package substrate 110. In some example embodiments, the semiconductor package 100 may further include an inner adhesive layer disposed between the semiconductor chip 120 and the package substrate 110. One of the opposite sides of the inner adhesive layer may be attached to the lower chip surface 120b of the semiconductor chip 120, and the other of the opposite sides of the inner adhesive layer may be attached to the upper substrate surface 110u of the package substrate 110. Using the inner adhesive layer, the semiconductor chip 120 may be more securely or firmly disposed on the package substrate 110. In some example embodiments, the inner adhesive layer may be or include an adhesive resin film or double-sided adhesive tape. In an embodiment, the inner adhesive layer may be a die attach film (DAF).

[0093] although Figure 2 A semiconductor chip 120 disposed on a package substrate 110 is shown, but the example embodiments are not limited thereto. In some example embodiments, a plurality of semiconductor chips 120 may be disposed on the package substrate 110, and at least a portion of the plurality of semiconductor chips 120 may be arranged side-by-side along a horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2) or stacked on top of each other along a vertical direction VD on the package substrate 110. In some example embodiments, the plurality of semiconductor chips 120 may have the same predetermined or configured function, or at least one of the plurality of semiconductor chips 120 may have a different predetermined or configured function from the remaining semiconductor chips 120. In some example embodiments, each of the plurality of semiconductor chips 120 may be electrically connected to another semiconductor chip 120 or electrically connected to the package substrate 110.

[0094] Reference Figure 2 A molding layer 130 may be disposed on a package substrate 110 and may cover a semiconductor chip 120. The molding layer 130 may cover and contact the portion of the upper substrate surface 110u of the package substrate 110 where the semiconductor chip 120 is not disposed. The molding layer 130 may also cover at least a portion of the exposed surface of the substrate pad 110Pu of the package substrate 110. The molding layer 130 may cover and contact the upper chip surface 120u and the chip side surface 120s of the semiconductor chip 120. The molding layer 130 may also cover and contact at least a portion of the exposed surface of the chip pad 120P of the semiconductor chip 120.

[0095] like Figure 2As shown, the molding layer 130 may have a molding upper surface 130u and a molding lower surface 130b. The molding upper surface 130u and the molding lower surface 130b may be opposite each other in the vertical direction VD. The molding lower surface 130b may face the substrate upper surface 110u of the package substrate 110 and may be bonded to (e.g., contact) the substrate upper surface 110u of the package substrate 110. The molding upper surface 130u may be located at a height higher than the chip upper surface 120u of the semiconductor chip 120. The molding upper surface 130u may extend above the plane including the chip upper surface 120u of the semiconductor chip 120 and may be substantially flat or planar. The molding upper surface 130u may therefore be vertically spaced from the chip upper surface 120u of the semiconductor chip 120.

[0096] like Figure 2 As shown, the outer surface of the molding layer 130 in the horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2) may be substantially aligned in the vertical direction VD with the side surface of the package substrate 110 in the horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2). However, the example embodiments are not limited thereto. In some example embodiments, the molding layer 130 may extend beyond the side surface of the package substrate 110 and may cover the side surface of the package substrate 110.

[0097] In some example embodiments, the molding layer 130 may include a molding material. For example, the molding layer 130 may include an epoxy molding compound (EMC). For example, the molding layer 130 may be formed by a molding process described later.

[0098] Reference Figure 2The semiconductor package 100 may include an identification pattern 150. In the semiconductor package 100, the identification pattern 150 may be a structure, feature, or identifier used to display product-related information or other product identification markings of the semiconductor package 100, and may (e.g., in a planar view or when viewed from above the semiconductor package 100) have a shape (e.g., a planar shape) corresponding to a predetermined or desired identifier determined based on the product-related information. In some example embodiments, the product-related information of the semiconductor package 100 may include, but is not limited to, product information (such as manufacturer name, trade name, product model, production batch number, place of origin, functional parameters, etc.), certification marks or warning marks required to be marked according to relevant standards or regulations, anti-counterfeiting marks for product anti-counterfeiting, and other suitable additional information related to the product. In some example embodiments, the predetermined identifier determined based on the product-related information may include one or more identifiers, and the identifier included in the predetermined identifier may consist of any one or more of characters, numbers, graphics, and any identification marks. For example, each of the identifiers included in the predetermined or desired identifier can be one or more of text, symbol, logo, two-dimensional barcode, and sign, but is not limited thereto.

[0099] In a semiconductor package 100, an identification pattern 150 may be disposed on a molding layer 130. The identification pattern 150 may be a solid component comprising one or more sub-patterns extending in the same plane. For example, the identification pattern 150 may have a patterned upper surface and a patterned lower surface opposite to each other in a vertical direction VD, and a patterned side surface (e.g., a patterned outer surface and / or a patterned inner surface) connecting the patterned upper surface and the patterned lower surface. The patterned upper surface, patterned lower surface, and patterned side surface of the identification pattern 150 may together define one or more closed three-dimensional shapes. For example, the sub-patterns included in the identification pattern 150 may be spaced apart in a horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2) and may each extend continuously in the horizontal direction. Each sub-pattern may include an upper surface and a lower surface opposite to each other in a vertical direction VD, and a side surface (e.g., an outer surface and / or an inner surface) connecting the upper surface and the lower surface. The upper surface, lower surface, and side surface of each sub-pattern may together define a single closed three-dimensional shape. One or more sub-patterns may constitute a single identification. Thus, when viewed in a planar view, the marking pattern 150, which has a planar shape corresponding to a predetermined or desired marking, can be visually identified as a predetermined marking, thereby displaying product-related information of the semiconductor package 100.

[0100] In the semiconductor package 100, the marking pattern 150 may have a thickness Th in the vertical direction VD. For example, the thickness Th of the marking pattern 150 may be in the range of 3 μm (or about 3 μm) to 7 μm (or about 7 μm). For example, the thickness Th of the marking pattern 150 may be 5 μm (or about 5 μm), but is not limited thereto. Furthermore, in the semiconductor package 100, the distance in the vertical direction VD between the lower surface of the marking pattern 150 and the upper surface of the semiconductor chip 120 (e.g., the molding gap Gm of the semiconductor package 100) may be less than 75 μm (or about 75 μm). For example, the molding gap Gm of the semiconductor package 100 may be less than or equal to about 50 μm (or 50 μm). For example, as referenced... Figure 1 Compared to the grooves formed in the molding layer by a laser process, the semiconductor package 100 according to some example embodiments may have a reduced molding gap Gm, and the marking pattern 150 included in the semiconductor package 100 may have a reduced thickness, thus the semiconductor package 100 may have a reduced thickness.

[0101] exist Figure 2 In the example embodiments shown, the marking pattern 150 may include or be formed of a phase change material. In the semiconductor package 100, the phase change material constituting the marking pattern 150 may be a material that is solid or near-solid (e.g., paste-like) at the operating temperature of the semiconductor package 100 and is capable of absorbing and storing heat when heated (e.g., a solid-solid phase change material). For example, the phase change material constituting the marking pattern 150 may be solder, but is not limited thereto. When the marking pattern 150 includes a phase change material, the marking pattern 150 can absorb and store heat generated from internal components (e.g., semiconductor chip 120) of the semiconductor package 100, thereby reducing or suppressing temperature rise of the semiconductor package 100 during operation. Furthermore, when the marking pattern 150 includes a phase change material, the marking pattern 150 may also provide additional or increased heat dissipation paths for the semiconductor package 100, thereby improving the heat dissipation efficiency of the semiconductor package 100. Therefore, the semiconductor package 100 may have improved reliability (e.g., improved thermal reliability).

[0102] exist Figure 2In the example embodiments shown, the identification pattern 150 may also include or be formed of EMI shielding material. In the semiconductor package 100, the EMI shielding material constituting the identification pattern 150 can be any suitable material (e.g., a metallic material) capable of shielding electromagnetic interference (EMI). For example, the EMI shielding material constituting the identification pattern 150 can be an EMI shielding metal. For example, the EMI shielding material constituting the identification pattern 150 can be copper (Cu), but is not limited thereto. When the identification pattern 150 includes EMI shielding material, the identification pattern 150 can block or impede the transmission of electromagnetic waves from the outside to the internal components of the semiconductor package 100 (e.g., the semiconductor chip 120), thereby improving the EMI shielding characteristics of the semiconductor package 100. Therefore, the semiconductor package 100 can have improved reliability.

[0103] When the marking pattern 150 includes phase change materials and / or EMI shielding materials, such as Figure 2 As shown, the marking pattern 150 may be configured to have a relatively large size (e.g., planar area). For example, internal components of the semiconductor package 100 that may benefit from temperature control or EMI shielding (such as internal components of the semiconductor chip 120) may be located below the area including the marking pattern 150 in the vertical direction VD. For example, when viewed in a plan view, the semiconductor chip 120 may be located within the area (or area) where the marking pattern 150 is disposed, and the marking pattern 150 may occupy a major area or portion of the area where the marking pattern 150 is located. For example, when viewed in a plan view corresponding to the marking pattern 150 side of the semiconductor package 100, the marking pattern 150 may be superimposed on the chip upper surface 120u of the semiconductor chip 120, for example, covering or obscuring the entire chip upper surface 120u of the semiconductor chip 120. For example, the area occupied by the marking pattern 150 may be larger than the area of ​​the semiconductor chip 120, and the marking pattern 150 may extend beyond the semiconductor chip 120 in the horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2). In some example embodiments, the planar shape of the identification pattern 150 may be adjusted (e.g., scaled, rearranged, etc.) so that the identification pattern 150 may have an increased planar area and / or a reduced cutout ratio. Through such adjustments, for example, the identification pattern 150 may have a relatively small (e.g., minimized) pattern gap while having a planar shape corresponding to a predetermined identification, so that the identification pattern 150 may occupy the space above the semiconductor chip 120 to the greatest extent possible.

[0104] Furthermore, adjustments to the planar shape of the sign pattern 150 may include pattern extension. Through pattern extension, for example, the sign pattern 150 may include a sign portion for displaying a predetermined sign, and an extension portion for increasing the coverage area (e.g., planar coverage area) of the sign pattern 150. For example, in a plan view, the sign portion of the sign pattern 150 may have a shape corresponding to the predetermined sign, and the extension portion of the sign pattern 150 may be disposed around the sign portion (e.g., in the sign portion or in the gaps between sub-parts of the sign portion, and / or in the peripheral area of ​​the sign portion). The extension portion of the sign pattern 150 may or may not be connected to the sign portion of the sign pattern 150. The extension portion of the sign pattern 150 may be made of the same material and formed using the same process as the sign portion of the sign pattern 150. The extension portion of the sign pattern 150 may have any suitable planar shape, as long as the arrangement of the extension portion does not affect the visual recognizability of the sign portion of the sign pattern 150. By further including an extension portion, the identification pattern 150 can have greater adjustment margin when adjusted, and thus can be more easily implemented to more fully cover or shield (or additionally, overlap with the internal components of the semiconductor package 100) for temperature control and / or EMI shielding of the internal components. Furthermore, although the identification pattern 150 is described herein as including a separate extension portion, this is merely an example, and the exemplary embodiments are not limited thereto. In some exemplary embodiments, a portion of the identification portion of the identification pattern 150 may also be configured to serve the same function as the extension portion described herein while simultaneously displaying a predetermined identification (e.g., a portion of the predetermined identification). As an example, when the predetermined identification corresponding to the identification pattern 150 may include, for example, an anti-counterfeiting mark, the portion of the identification pattern 150 corresponding to the anti-counterfeiting mark may be appropriately adjusted to further increase the planar coverage area of ​​the identification pattern 150 while achieving the display of the anti-counterfeiting mark. For example, the portion of the identification pattern 150 corresponding to the anti-counterfeiting mark may be pre-designed or dynamically adjusted to have a planar shape that is distributed throughout the area where the identification pattern 150 is located and surrounds (or encloses) the rest of the identification pattern 150 (e.g., the portion of the identification pattern 150 corresponding to the mark other than the anti-counterfeiting mark), but is not limited thereto.

[0105] In the semiconductor package 100 according to some example embodiments, since the marking pattern 150 can be formed by a transfer method as discussed below, the marking pattern 150 and its planar shape can be adjusted relatively easily and as desired (e.g., planar scaling, planar repositioning, planar pattern expansion, etc.). Therefore, the marking pattern 150 can be constructed to have a sufficiently or desiredly large coverage area (e.g., planar coverage area) while having a planar shape corresponding to a predetermined marking, thereby more effectively and easily achieving temperature control and / or EMI shielding for components (e.g., semiconductor chip 120, etc.) below it. Furthermore, the adjusted marking pattern 150 can still maintain a thin thickness compared to before adjustment. Therefore, the semiconductor package 100 can have a reduced thickness even when including the adjusted marking pattern 150.

[0106] When the marking pattern 150 includes phase change materials or EMI shielding materials, such as Figure 2 As shown, the logo pattern 150 may be disposed above the molding layer 130 and may be spaced apart from the molding layer 130 in the vertical direction VD.

[0107] In some example embodiments, the semiconductor package 100 may also include an insulating layer 170. For example... Figure 2 As shown, the insulating layer 170 may extend on the molding layer 130. For example, the insulating layer 170 may extend along the molded upper surface 130u of the molding layer 130. For example, the insulating layer 170 may cover and contact the entire molded upper surface 130u of the molding layer 130. Furthermore, the insulating layer 170 may be disposed on the lower and side surfaces of the marking pattern 150. For example, the insulating layer 170 may cover and contact the entire lower and side surfaces (e.g., the outer and inner surfaces) of the marking pattern 150. The insulating layer 170 may expose the upper surface of the marking pattern 150. For example, the upper surface of the insulating layer 170 may be substantially coplanar with the upper surface of the marking pattern 150. When the marking pattern 150 includes one or more sub-patterns, the insulating layer 170 may cover and contact the lower and side surfaces of each sub-pattern and may expose the upper surface of each sub-pattern. In some example embodiments, the insulating layer 170 may be configured such that the marking pattern 150 is embedded in the upper part of the insulating layer 170 and such that the marking pattern 150 is spaced apart from the molded upper surface 130u of the molding layer 130.

[0108] In addition, such as Figure 2As shown, both the upper surface 150u of the marking pattern 150 and the upper surface 170u of the insulating layer 170 are exposed at the upper surface 100u of the semiconductor package 100. For example, the upper surface 100u of the semiconductor package 100 may be provided or defined by the upper surface 150u of the marking pattern 150 and the upper surface 170u of the insulating layer 170. Therefore, the predetermined or desired marking displayed by the marking pattern 150 can be visually observed directly from above the semiconductor package 100 (e.g., in a plan view). Figure 2 As shown, the distance D1 from the upper end (e.g., the upper vertex) of the side surface of the marking pattern 150 to the upper surface 110u of the package substrate 110 can be equal to or substantially equal to the distance D2 from the upper surface 100u of the semiconductor package 100 to the upper surface 110u of the package substrate 110. Therefore, the opening (exposed area) of the marking pattern 150 is flush with (or at the same height) the upper surface 100u of the semiconductor package 100.

[0109] In some example embodiments, the insulating layer 170 may include or may be a die attachment film. When the insulating layer 170 includes a die attachment film, the insulating layer 170 may have a relatively thin thickness. For example, the insulating layer 170 may have a thickness in the range of, for example, 5 μm (or about 5 μm) to 40 μm (or about 40 μm). For example, the insulating layer 170 may have a thickness in the range of, for example, 5 μm (or about 5 μm) to 12 μm (or about 12 μm). Therefore, even though the insulating layer 170 is disposed between the marking pattern 150 and the molding layer 130, the semiconductor package 100 may have a relatively small molding gap Gm as described above. In some example embodiments, the insulating layer 170 may be a cured die attachment film, but is not limited thereto.

[0110] The marking pattern 150 can be spaced apart from the internal components of the semiconductor package 100 (e.g., the semiconductor chip 120 and the bonding leads 140, which will be described later) via the insulating layer 170. In this case, the marking pattern 150 can be configured to be disposed above the semiconductor chip 120 and the bonding leads 140 with a relatively small pitch. Therefore, even when the marking pattern 150 includes a phase change material and / or an EMI shielding material, the semiconductor package 100 can have a reduced thickness.

[0111] Reference Figure 2In some example embodiments, the semiconductor chip 120 may be electrically connected to the package substrate 110 using wire bonding. In some example embodiments, the semiconductor package 100 may also include bonding leads 140 that electrically connect the semiconductor chip 120 to the package substrate 110. The bonding leads 140 may extend from the semiconductor chip 120 to the package substrate 110. For example, the bonding leads 140 may be disposed or connected between chip pads 120P of corresponding semiconductor chips 120 and substrate pads 110Pu of the package substrate 110. In some example embodiments, the bonding leads 140 may comprise a metallic material. For example, the bonding leads 140 may comprise gold (Au), aluminum (Al), copper (Cu), or alloys thereof, but are not limited thereto. In some example embodiments, the bonding leads 140 may have an insulating layer or passivation layer disposed on their outer peripheral surface, but are not limited thereto.

[0112] exist Figure 2 In the example embodiment shown, the bonding lead 140 may contact the insulating layer 170. For example, the uppermost end of the bonding lead 140 may contact the lower surface 170b of the insulating layer 170. For example, the bonding lead 140 may define a bend or curve that forms the uppermost end of the bonding lead 140, and the bonding lead 140 may contact the lower surface 170b of the insulating layer 170 via the bend or curve. For example, when the molding gap Gm of the semiconductor package 100 is configured to have a smaller value within the range described above, the bonding lead 140 may contact the insulating layer 170 due to the relatively small molding gap Gm during the molding process of forming the molding layer 130 (discussed below). In this case, the portion of the bonding lead 140 other than the portion contacting the insulating layer 170 may be buried in the molding layer 130.

[0113] In some example embodiments, the insulating layer 170 may be configured to have a modulus (e.g., elastic modulus) greater than that of the bonding lead 140. Because the modulus of the insulating layer 170 is greater than that of the bonding lead 140, the insulating layer 170 can restrict or block the bonding lead 140 from penetrating into the insulating layer 170. Therefore, even when the semiconductor package 100 is configured with a relatively small molding gap Gm as described above, the insulating layer 170 can effectively space the bonding lead 140 from the marking pattern 150, thereby reducing or limiting undesirable contact or shorting between the bonding lead 140 and the marking pattern 150.

[0114] In some example embodiments, the bonding wire 140 may not contact the insulating layer 170. For example, when the molding gap Gm of the semiconductor package 100 is configured to have a larger value within the range described above, the bonding wire 140 may be spaced apart from the insulating layer 170 due to the relatively large molding gap Gm. In some example embodiments, the bonding wire 140 may be completely buried in the molding layer 130 and further spaced apart from the marking pattern 150 by the insulating layer 170 and the molding layer 130.

[0115] Reference Figure 2 The connection terminal 160 may be disposed beneath the package substrate 110 and electrically connected to the package substrate 110. For example, the connection terminal 160 may be disposed on the lower substrate surface 110b of the package substrate 110 and may be attached to the undersubstrate pad 110Pb of the package substrate 110. The connection terminal 160 may be electrically connected to the semiconductor chip 120 electrically connected to the package substrate 110 via the package substrate 110 (e.g., the undersubstrate pad 110Pb, internal conductive paths, and upper substrate pad 110Pu) for electrical connection from the semiconductor chip 120 to an external device (e.g., a motherboard or intermediate substrate). The connection terminal 160 may be an external connection member of the semiconductor package 100 for electrical connection to the outside.

[0116] In some example embodiments, the connection terminal 160 may have any suitable construction. For example, the connection terminal 160 may be in the form of a ball or a bump. In some example embodiments, the connection terminal 160 may include, for example, solder.

[0117] In some example embodiments, the semiconductor package 100 may include a plurality of connection terminals 160. The plurality of connection terminals 160 may be arranged on the lower substrate surface 110b of the package substrate 110 in any suitable or desired planar layout. The planar layout of the plurality of connection terminals 160 may be appropriately selected based on the connection requirements or specifications between the semiconductor package 100 and an external device (e.g., a motherboard or interposer substrate) to which it will be connected, without particular limitation. In some example embodiments, the plurality of connection terminals 160 may be arranged in the form of a ball grid array (BGA), a fine ball grid array (FBGA), or a planar grid array (LGA), but is not limited thereto.

[0118] Next, we will refer to Figures 3A to 3F A method for manufacturing a semiconductor package 100 is described. Figures 3A to 3F This is a schematic cross-sectional view illustrating operations in a method of manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure. In the following description with reference to the accompanying drawings, the same or similar reference numerals as used in the above description may denote the same or similar components, and the associated descriptions will be simplified or omitted.

[0119] Reference Figure 3A CS, a carrier substrate, can be prepared.

[0120] The carrier substrate CS can be a substrate that has both supporting and adhesive functions. The adhesive side of the carrier substrate CS can be arranged facing upwards for fixing the marking pattern 150 to be formed on the carrier substrate CS.

[0121] In some example embodiments, the carrier substrate CS may include a substrate layer for support and an adhesive layer on the substrate layer for adhesion. As an example, the substrate layer of the carrier substrate CS may be a rigid transparent glass layer, and the adhesive layer of the carrier substrate CS may be formed of an adhesive having initial adhesive strength that decreases under predetermined or given conditions. For example, the adhesive layer of the carrier substrate CS may include a UV-degradable adhesive whose adhesive strength decreases after exposure to ultraviolet (UV) light, and the type of UV-degradable adhesive used herein is not particularly limited. In some example embodiments, the carrier substrate CS may be configured to have the same or substantially the same coefficient of thermal expansion (CTE) as the encapsulation substrate 110 described below. For example, the CTE of the carrier substrate CS may be adjusted to an appropriate value by adjusting the thickness and / or properties of the layers included in the carrier substrate CS (e.g., the thickness and / or tempering degree of the transparent glass layer), but is not limited thereto.

[0122] Then, the marking pattern 150 can be formed on the carrier substrate CS.

[0123] Before forming the identification pattern 150, one or more product-related information items that are expected to be displayed can be determined from the product-related information of the semiconductor package to be formed. Then, the determined product-related information can be laid out according to the planar dimensions (e.g., area and aspect ratio) of the semiconductor package to be formed, thereby obtaining a predetermined, desired, or given identification corresponding to the determined product-related information. Here, the method for obtaining the predetermined, desired, or given identification can employ any suitable method capable of being used for identification pre-layout, and can be performed by any suitable device or program (e.g., computer device or program), without particular limitation.

[0124] After obtaining a predetermined, desired, or given mark, the mark pattern 150 can be formed on a carrier substrate CS using a suitable process based on the predetermined mark and according to the material used to form the mark pattern 150, having at least a partial shape (e.g., planar shape) corresponding to the predetermined mark.

[0125] In some example embodiments, the marking pattern 150 may include a phase change material. For example, the marking pattern 150 may include solder. The marking pattern 150 may be formed on a carrier substrate CS by, for example, a printing process (e.g., screen printing or stencil printing). For example, a mask may be made according to a predetermined, desired, or given marking, and the mask may be placed over the adhesive side of the carrier substrate CS. The phase change material may then be transferred onto the carrier substrate CS in a shape (e.g., a planar shape) corresponding to the predetermined, desired, or given marking to form the marking pattern 150. Optionally, when solder paste is used to form the marking pattern 150, cryogenic heating may be performed on the marking pattern 150 after its formation to increase the hardness of the marking pattern 150.

[0126] In some example embodiments, the identification pattern 150 may include an EMI shielding material. For example, the identification pattern 150 may include an EMI shielding metal such as copper. In this case, the identification pattern 150 may be formed by a metal transfer process using a metal film, but is not limited thereto.

[0127] In some example embodiments, the marking pattern 150 formed as described above may have a relatively small thickness. For example, the marking pattern 150 may have a thickness in the range of 3 μm (or about 3 μm) to 7 μm (or about 7 μm).

[0128] As an example, such as Figure 3A As shown in the dashed-lined planar frame (which may correspond to the upper surface of the carrier substrate CS), the identification pattern 150 may be formed to include a plurality of sub-patterns, wherein each of the plurality of sub-patterns may correspond to an English letter or Arabic numeral, and the plurality of sub-patterns may be arranged in desired combinations to form a predetermined or desired or given identification including, for example, “SCE”, “1234”, and “JKLP”. However, the exemplary embodiments are not limited thereto. In some exemplary embodiments, the identification pattern 150 may, as described above, include various forms of sub-patterns in various arrangements and combinations to form various types of predetermined identification for displaying desired product-related information.

[0129] Furthermore, despite Figure 3A The logo pattern 150 is shown closer to one side within the planar frame, but this is merely an example, and the logo pattern 150 can be distributed on the carrier substrate CS in any suitable form (e.g., size or area). For example, considering that the logo pattern 150 constitutes as follows... Figure 3AThe predetermined identifiers “SCE,” “1234,” and “JKLP” shown can be appropriately enlarged to the size proportion of the predetermined identifiers corresponding to the identifier pattern 150, so that the identifier pattern 150 can be distributed throughout the upper surface of the carrier substrate CS. This can facilitate a more adequate or desired coverage of other components (e.g., the semiconductor chip 120 described later) by the identifier pattern 150. Furthermore, in some example embodiments, in addition to the portion corresponding to the predetermined identifier, the identifier pattern 150 may also include an extension portion for increasing the planar coverage area of ​​the identifier pattern 150. For example, in the operation of determining the predetermined identifier described above, the planar shape and arrangement of the extension portion of the identifier pattern 150 may be determined and laid out together with the predetermined identifier, and in the operation of forming the identifier pattern 150 described above, the determined planar shape and arrangement of the extension portion may be used together with the determined predetermined identifier to determine the planar shape of the identifier pattern 150.

[0130] Next, refer to Figure 3B and Figure 3C An insulating layer 170 may be provided to cover the marking pattern 150. For example, the insulating layer 170 may be bonded to a carrier substrate CS (e.g., a surface of the carrier substrate CS on which the marking pattern 150 is provided) to cover the marking pattern 150.

[0131] like Figure 3A As shown, an insulating layer 170 can be prepared and placed on a support platform. The insulating layer 170 can be deformable. For example, the insulating layer 170 can be a semi-cured bare film. Furthermore, the insulating layer 170 can have a thickness greater than that of the marking pattern 150.

[0132] Then, the carrier substrate CS on which the marking pattern 150 is formed can be placed upside down on the insulating layer 170, so that the marking pattern 150 faces the insulating layer 170.

[0133] Then, the carrier substrate CS can be brought close to the insulating layer 170. As the distance between the carrier substrate CS and the insulating layer 170 decreases, the marking pattern 150 can contact the insulating layer 170 and deform the insulating layer 170, and the insulating layer 170 can be recessed to accommodate the marking pattern 150. Figure 3CAs shown, the carrier substrate CS and the insulating layer 170 can contact each other, such that the marking pattern 150 can be embedded in the upper portion (e.g., the upper surface) of the insulating layer 170. Since the marking pattern 150 is formed on the surface of the carrier substrate CS, and the insulating layer 170 contacts this surface of the carrier substrate CS, the surface of the marking pattern 150 facing the carrier substrate CS (e.g., the upper surface) and the surface of the insulating layer 170 facing the carrier substrate CS (e.g., the upper surface) can be substantially coplanar. For example, the insulating layer 170 can expose the upper surface of the marking pattern 150. Furthermore, since, as described above, the thickness of the insulating layer 170 can be greater than the thickness of the marking pattern 150, the insulating layer 170 can cover the lower and side surfaces of the marking pattern 150.

[0134] Next, refer to Figure 3D Semiconductor chips 120 can be disposed or arranged on the packaging substrate 110, and semiconductor chips 120 can be electrically connected to the packaging substrate 110.

[0135] First, a packaging substrate 110 can be prepared. For example... Figure 3D As shown, the package substrate 110 may have an upper substrate surface 110u and a lower substrate surface 110b opposite to each other, and may include a substrate upper pad 110Pu and a substrate lower pad 110Pb respectively disposed on the substrate upper surface 110u and substrate lower surface 110b. In some example embodiments, the package substrate 110 may be a printed circuit board, but is not limited thereto.

[0136] Then, a semiconductor chip 120 can be prepared, and the semiconductor chip 120 can be disposed on the upper surface 110u of the package substrate 110. For example... Figure 3D As shown, the semiconductor chip 120 may have an upper chip surface 120u and a lower chip surface 120b opposite to each other, and may include chip pads 120P disposed on the upper chip surface 120u. In some example embodiments, the semiconductor chip 120 may be various types of chips for performing predetermined or set functions. For example, the semiconductor chip 120 may include or may be a processor chip, a memory chip, an analog chip, a digital chip, etc., but is not limited thereto.

[0137] exist Figure 3D In the example embodiments shown, the semiconductor chip 120 may be placed on the package substrate 110 with its lower chip surface 120b facing the package substrate 110, and may be secured or attached to the package substrate 110 by an inner adhesive layer between the semiconductor chip 120 and the package substrate 110. In some example embodiments, the inner adhesive layer may be attached to either the lower chip surface 120b of the semiconductor chip 120 or the upper substrate surface 110u of the package substrate 110 before the semiconductor chip 120 is disposed or placed on the package substrate 110.

[0138] Then, the semiconductor chip 120 can be electrically connected to the package substrate 110. Figure 3D In the example embodiment shown, wire bonding can be used to electrically connect the semiconductor chip 120 to the package substrate 110. For example, a bonding wire 140 electrically connecting the semiconductor chip 120 and the package substrate 110 can be formed between the semiconductor chip 120 and the package substrate 110. For example, the bonding wire 140 can be formed between the chip pad 120P of the semiconductor chip 120 and the substrate pad 110Pu of the package substrate 110. Figure 3D As shown, the ends of the bonding wire 140 can be bonded to the chip pad 120P and the substrate pad 110Pu, respectively.

[0139] In some example embodiments, metallic materials (such as, but not limited to, copper (Cu), gold (Au), or aluminum (Al)) may be used to form the bonding wires 140. In embodiments, wire bonding equipment may be used to perform the process of forming the bonding wires 140.

[0140] Next, refer to Figure 3E A molding die MD can be prepared, and a release film RL can be set on the inner surface of the molding die MD.

[0141] Then, you can Figure 3C The obtained stacked structure, including the carrier substrate CS, the marking pattern 150 and the insulating layer 170, is placed inverted on the release film RL in the molding die MD, so that the carrier substrate CS can face the release film RL (or be placed on the release film RL) and the upper surface of the insulating layer 170 can be exposed.

[0142] Then, a preliminary molding compound 130p may be applied to the upper surface of the insulating layer 170. The preliminary molding compound 130p may have a certain or desired flowability and may utilize the flowability to fill gaps. In some example embodiments, the preliminary molding compound 130p may comprise uncured epoxy molding compound (EMC).

[0143] Then, you can Figure 3D The obtained structure, including the packaging substrate 110, the semiconductor chip 120 and the bonding wires 140, is placed in an inverted manner on the insulating layer 170, such that the semiconductor chip 120 can face the insulating layer 170 and the preliminary molding compound 130p thereon.

[0144] During placement, the semiconductor chip 120 and bonding leads 140 gradually come into contact with the preliminary molding compound 130p, and the preliminary molding compound 130p can be cast between the package substrate 110 and the insulating layer 170 and fill the gap space between the package substrate 110 and the insulating layer 170. Therefore, after placement is completed, the package substrate 110 can be spaced apart from the insulating layer 170, and the semiconductor chip 120, bonding leads 140, and preliminary molding compound 130p can be placed between the package substrate 110 and the insulating layer 170.

[0145] Furthermore, as described above, the insulating layer 170 can be configured to have a modulus (e.g., elastic modulus) greater than that of the bonding lead 140. Because the insulating layer 170 prevents the bonding lead 140 from penetrating into it, the gap between the package substrate 110 and the insulating layer 170 can be formed relatively small, and the ends (e.g., curved or bent portions) of the bonding lead 140 facing the insulating layer 170 in the vertical direction VD can contact the insulating layer 170. The insulating layer 170 can limit or prevent the bonding lead 140 from contacting the marking pattern 150.

[0146] The preliminary molding compound 130p can then be heat-treated at the molding temperature to cure it. The molding temperature can be appropriately selected without particular limitation, depending on the material and composition of the preliminary molding compound 130p.

[0147] Next, with Figure 3E Refer to together Figure 3F After molding is completed, a molding layer 130 can be formed from the initial molding compound 130p. During the molding process of forming the molding layer 130 as described above, since the carrier substrate CS and the package substrate 110 can have the same or substantially the same coefficient of thermal expansion (CTE), the carrier substrate CS and the package substrate 110 can have the same or substantially the same amount of expansion at the molding temperature, so that the carrier substrate CS and the package substrate 110 can maintain a uniform (consistent) gap between them. Therefore, the possibility of warping in the resulting structure due to high temperature can be reduced. Therefore, the warping of the semiconductor package 100 to be formed can be reduced, so that the semiconductor package 100 to be formed can have improved reliability (e.g., structural stability).

[0148] The structure obtained after the molding process can then be separated from the release film RL within the molding die MD. Then, connection terminals 160 can be disposed or attached to the surface of the encapsulation substrate 110 where the substrate underlay 110Pb is located (e.g., the substrate underside). For example, as... Figure 3FAs shown, multiple connection terminals 160 can be disposed on multiple substrate pads 110Pb. In some example embodiments, the connection terminals 160 can be solder balls and can be formed by a ball-mounting process, but are not limited thereto.

[0149] The carrier substrate CS can then be irradiated with a UV lamp LM. As described above, the carrier substrate CS may include an adhesive layer whose adhesive strength decreases after exposure to UV light. When the carrier substrate CS includes a material or material layer whose adhesive strength decreases after exposure to UV light, the carrier substrate CS can be removed relatively easily after irradiation with a UV lamp LM.

[0150] In some example embodiments, when the carrier substrate CS is irradiated with a UV lamp LM, a portion of the UV light can penetrate the carrier substrate CS and irradiate the insulating layer 170. The insulating layer 170 can be further cured by irradiation with UV light. For example, the uncured die attachment film included in the insulating layer 170 can be UV-curable and can be further cured after irradiation with UV light. However, the example embodiments are not limited thereto. In some example embodiments, the insulating layer 170 can also be cured during the molding process. For example, the uncured die attachment film included in the insulating layer 170 can be thermosetting and can be further cured at the molding temperature during the molding process. Therefore, in the finally formed semiconductor package 100, the insulating layer 170 may include a cured die attachment film.

[0151] After UV light irradiation, the carrier substrate CS can be removed, exposing the upper surface of the marking pattern 150 and the upper surface of the insulating layer 170.

[0152] Through the above process, a reference can be obtained. Figure 2 The semiconductor package 100 is described.

[0153] By reference Figures 3A to 3F By appropriately selecting or adjusting the physical and / or chemical characteristics of the materials used to form the component, the process and process parameters used to form the component, etc., the semiconductor package 100 can be formed having the above-mentioned reference. Figure 2 One or more of the various characteristics described.

[0154] Next, some exemplary embodiments according to this disclosure will be described with reference to the accompanying drawings.

[0155] Figure 4 This is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure. For brevity, [the following text is missing]. Figure 4 Used with Figure 2 The same or similar reference numerals in the figures are used to indicate the same as or similar to the reference numerals in the figures. Figure 2The components in the text are the same or similar components, and the description of the same or similar components can be simplified or omitted. Figure 4 Semiconductor package 200 can be referenced Figure 2 The best understanding is obtained from the description of the semiconductor package 100.

[0156] Reference Figure 4 According to some example embodiments, a semiconductor package 200 may include a package substrate 110, a semiconductor chip 120, a molding layer 230, a marking pattern 250, and connection terminals 160. The semiconductor package 200 may not include an insulating layer 170, and the marking pattern 250 may be disposed in the upper portion or top surface of the molding layer 230.

[0157] like Figure 4 As shown, the marking pattern 250 may have an upper surface exposed from the upper surface 230u of the molding layer 230. For example, the upper surface of the marking pattern 250 may be substantially coplanar with the upper surface of the molding layer 230. Figure 4 In the embodiments shown, the upper surface of the semiconductor package 200 may be provided by the upper surface of the marking pattern 250 and the upper surface of the molding layer 230. For example, the distance between the upper surface of the marking pattern 250 and the substrate upper surface 110u of the package substrate 110 may be equal to or substantially equal to the distance between the upper surface of the semiconductor package 200 and the substrate upper surface 110u of the package substrate 110. For example, the distance between the upper end (upper vertex) of the side surface of the marking pattern 250 and the substrate upper surface 110u of the package substrate 110 may be equal to or substantially equal to the distance between the upper surface of the semiconductor package 200 and the substrate upper surface 110u of the package substrate 110. Furthermore, as Figure 4 As shown, the lower and side surfaces of the logo pattern 250 can contact and be defined by the molding layer 230. As a result, the logo pattern 250 can be embedded in the top or upper part of the molding layer 230.

[0158] exist Figure 4 In the example embodiments shown, the marking pattern 250 may include or be formed of an insulating material. For example, the marking pattern 250 may include an insulating resin. For example, the marking pattern 250 may include an epoxy-based insulating resin.

[0159] In addition to the fact that the logo pattern 250 may be located in the molding layer 230 and may include insulating material, the logo pattern 250 may be associated with the reference. Figure 2 and Figure 3A The described marking pattern 150 has the same or similar features in some respects. For example, the marking pattern 250 may have a thickness Th in the range of 3 μm (or about 3 μm) to 7 μm (or about 7 μm). For example, the marking pattern 250 may have a thickness Th of 5 μm (or about 5 μm), but is not limited thereto.

[0160] like Figure 4 As shown, the lower surface of the marking pattern 250 may be spaced apart from the upper surface 120u of the semiconductor chip 120 in the vertical direction VD. For example, the lower surface of the marking pattern 250 may be located at a height higher than the upper surface 120u of the semiconductor chip 120 in the vertical direction VD. For example, a portion of the molding layer 230 may be located between the marking pattern and the semiconductor chip 120.

[0161] In semiconductor package 200, such as Figure 4 As shown, the semiconductor chip 120 may be electrically connected to the package substrate 110 via bonding leads 140, for example, using wire bonding. For example, the bonding leads 140 may be connected between a chip pad 120P on the upper surface 120u of the semiconductor chip 120 and a substrate pad 110Pu on the upper surface 110u of the package substrate 110.

[0162] like Figure 4 As shown, the bonding wire 140 may include a portion (e.g., a bend or curve) adjacent to the identification pattern 250. For example, the portion of the bonding wire 140 adjacent to the identification pattern 250 may be spaced apart from the identification pattern 250 by a relatively small distance. However, the example embodiments are not limited thereto. In some example embodiments, the portion of the bonding wire 140 adjacent to the identification pattern 250 may contact the identification pattern 250. In some example embodiments, the portion of the bonding wire 140 adjacent to the identification pattern 250 may extend to be within (e.g., through) the identification pattern 250 or between subpatterns of the identification pattern 250. For example, the portion of the bonding wire 140 adjacent to the identification pattern 250 may extend into the space defined by the side surfaces (e.g., inner and / or outer surfaces) of the identification pattern 250 in the horizontal direction (e.g., a first horizontal direction HD1 and / or a second horizontal direction HD2). In some example embodiments, because the marking pattern 250 includes an insulating material, there is no short-circuit problem in the bonding leads 140 due to the marking pattern 250. Therefore, the positional relationship between the bonding leads 140 and the marking pattern 250 can be set relatively flexibly. As a result, the semiconductor package 200 can have improved structural reliability.

[0163] like Figure 4As shown, because the marking pattern 250 and the bonding wire 140 can have a relatively small gap between them, or the bonding wire 140 can contact the marking pattern 250 or even extend into the marking pattern 250 or the gap between sub-patterns of the marking pattern 250, the distance between the lower surface of the marking pattern 250 and the upper surface 120u of the semiconductor chip 120 can be further reduced. For example, the molding gap Gm of the semiconductor package 200 can be further reduced. For example, the molding gap Gm of the semiconductor package 200 can be less than or equal to 45 μm (or about 45 μm). Therefore, the semiconductor package 200 can have a further reduced thickness.

[0164] In addition to the above, the semiconductor package 200 may be referenced Figure 2 The semiconductor package 100 described is the same as or similar in some respects, and therefore can be best understood by referring to the semiconductor package 100.

[0165] Next, we will refer to Figures 5A to 5C as well as Figure 3D A method for manufacturing a semiconductor package 200 is described. Figures 5A to 5C This is a schematic cross-sectional view illustrating operations in a method of manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure. In the following description with reference to the accompanying drawings, the same or similar reference numerals as used in the above description may denote the same or similar components, and the associated descriptions will be simplified or omitted.

[0166] Reference Figure 5A A carrier substrate CS can be prepared, and an identification pattern 250 can be formed on the carrier substrate CS. The carrier substrate CS may include relatively rigid portions (e.g., transparent glass portions) and portions with adhesive properties (e.g., adhesive portions), and may be configured to have the same or substantially the same coefficient of thermal expansion (CTE) as the package substrate 110 to be described. The identification pattern 250 may be formed to have a shape (e.g., a planar shape) corresponding to a predetermined, desired, or given identification for displaying product-related information of the semiconductor package 200. The identification pattern 250 may be formed to have a thickness in the range of 3 μm (or about 3 μm) to 7 μm (or about 7 μm).

[0167] In some example embodiments, an insulating material (e.g., an epoxy-based insulating resin) may be used to form the marking pattern 250. For example, a preliminary marking pattern having a planar shape corresponding to a predetermined marking may be formed on a carrier substrate CS by, for example, a printing process (e.g., screen printing or stencil printing), and then the preliminary marking pattern may be cured by heat treatment to form the marking pattern 250. The temperature of the heat treatment used herein is not particularly limited and may be appropriately determined depending on the insulating material used to form the marking pattern 250.

[0168] Next, executable and reference Figure 3D The same process described is used to place the semiconductor chip 120 on the package substrate 110 and form bonding leads 140 that electrically connect the semiconductor chip 120 to the package substrate 110.

[0169] Next, refer to Figure 5B can Figure 5A The obtained stacked structure, including the carrier substrate CS and the marking pattern 250, is placed in an inverted manner (or in an inverted state) on the release film RL inside the molding die MD, so that the carrier substrate CS can face the release film RL, and the upper and side surfaces of the marking pattern 250 can be exposed.

[0170] Then, a preliminary molding compound 230p can be applied to the carrier substrate CS. The preliminary molding compound 230p can cover the marking pattern 250 and fill the gaps between the marking patterns 250. In some example embodiments, the preliminary molding compound 230p may include uncured epoxy molding compound (EMC).

[0171] Then, the structure obtained as described above, including the packaging substrate 110, the semiconductor chip 120 and the bonding wires 140, can be placed on the carrier substrate CS in an inverted form or in an inverted state, such that the semiconductor chip 120 can face the carrier substrate CS and the preliminary molding compound 230p thereon.

[0172] During placement, the semiconductor chip 120 and bonding leads 140 gradually come into contact with the preliminary molding compound 230p, and the preliminary molding compound 230p can be cast between the package substrate 110 and the carrier substrate CS to fill the gap between them. Therefore, after placement is complete, the package substrate 110 can be spaced a certain distance from the carrier substrate CS, and the semiconductor chip 120, bonding leads 140, and preliminary molding compound 230p can be positioned between the package substrate 110 and the carrier substrate CS.

[0173] In some example embodiments, when the spacing between the encapsulation substrate 110 and the carrier substrate CS is small enough or has a desired size, the bonding wire 140 may contact the identification pattern 250 and / or extend into the identification pattern 250 or into the gap space between the subpatterns of the identification pattern 250.

[0174] The preliminary molding compound 230p can then be heat-treated at the molding temperature to cure it. The molding temperature can be appropriately selected without particular limitation, depending on the material and composition of the preliminary molding compound 230p.

[0175] Next, with Figure 5B Refer to together Figure 5C After molding is completed, a molding layer 230 can be formed from the initial molding material 230p. Then, the resulting structure can be separated from the release film RL within the molding die MD. Then, connection terminals 160 can be provided on the surface of the encapsulation substrate 110 where the substrate underpad 110Pb is provided (e.g., the lower surface of the substrate).

[0176] Then, the carrier substrate CS can be irradiated with a UV lamp (LM). After exposure to UV light, the carrier substrate CS exhibits reduced adhesion. Therefore, the carrier substrate CS can be removed relatively easily.

[0177] After UV light irradiation, the carrier substrate CS can be removed to expose the upper surface of the marking pattern 250 and the upper surface of the molding layer 230.

[0178] Through the above process, a reference can be obtained. Figure 4 The semiconductor package 200 is described.

[0179] By reference Figures 5A to 5C as well as Figure 3D By appropriately selecting or adjusting the physical and / or chemical characteristics of the materials used to form the component, the process and process parameters used to form the component, etc., the semiconductor package 200 can be formed having the above-mentioned characteristics. Figure 4 One or more of the various characteristics described.

[0180] In semiconductor packages according to some example embodiments of this disclosure, as described above, structures (e.g., identification patterns) for identifying information (e.g., displaying product-related information) can be formed by first forming them on a separate carrier substrate and then transferring them over the carrier substrate, without involving laser processes. Therefore, the formed identification pattern can have a small thickness, and the semiconductor package including the identification pattern can have a small molding gap. Thus, the semiconductor package can have a reduced thickness while including structures for identifying information. Since the aforementioned transfer method is simpler and easier to control in forming thin patterns (e.g., thin and complex patterns corresponding to complex identification) compared to laser grooving methods, the semiconductor package including the identification pattern formed via this transfer method can have improved productivity (e.g., product yield and / or production efficiency) while including structures for identifying information.

[0181] Furthermore, as described above, the carrier substrate used for transferring the marking pattern can be configured to have a coefficient of thermal expansion substantially the same as that of the packaging substrate of the semiconductor package, and can be positioned on the opposite side of the semiconductor package from the packaging substrate during the molding process of the semiconductor package, thus reducing or limiting warpage of the stacked assembly that may occur at the molding temperature together with the packaging substrate. Since the warpage that may occur during the molding process is reduced or limited, the final semiconductor package can have reduced warpage. Therefore, the semiconductor package can have improved structural reliability.

[0182] Furthermore, as mentioned above, the marking pattern can include various types of functional materials as needed. For example, the marking pattern can include a phase change material. When the marking pattern includes a phase change material, the semiconductor package including the marking pattern can have improved thermal reliability due to the heat storage properties of the phase change material and / or the heat dissipation path provided by the phase change material. As another example, the marking pattern can include an EMI shielding material. When the marking pattern includes an EMI shielding material, the semiconductor package including the marking pattern can have improved EMI shielding characteristics due to the EMI shielding provided by the marking pattern. Yet another example, the marking pattern can include an insulating material. When the marking pattern includes an insulating material, the semiconductor package including the marking pattern can have a further reduced molding gap (e.g., even when wire bonding is used to form the electrical connection between the semiconductor chip and the package substrate in the semiconductor package), and therefore can have a further reduced thickness and improved structural reliability.

[0183] In a method for manufacturing a semiconductor package according to some example embodiments of the present disclosure, as described above, a marking pattern can be introduced into the semiconductor package by forming the marking pattern separately and then transferring it. As a result, processes (e.g., laser processes) that might adversely affect other functional components of the semiconductor package (e.g., semiconductor chips and / or bonding wires) can be avoided. Furthermore, the carrier substrate used for transferring the marking pattern can participate in the molding process of the semiconductor package and can be used together with the package substrate to reduce or limit warpage that may occur in the stacked structure. The carrier substrate can be relatively easily removed after the molding process is completed. Therefore, this method can have improved process reliability and / or improved productivity while forming a thin marking pattern for marking information.

[0184] While several embodiments have been provided in this disclosure, it should be understood that the disclosed systems and methods may be implemented in many other specific forms without departing from the spirit or scope of this disclosure. The examples presented are to be understood as illustrative rather than limiting, and are not intended to be limited to the details given herein. For example, various elements or components may be combined or integrated in another system, or some features may be omitted or not implemented.

Claims

1. A semiconductor package, comprising: Packaging substrate; A semiconductor chip is on a package substrate and is electrically connected to the package substrate; A molding layer, on the packaging substrate, covering the semiconductor chip; The marking pattern, on the molding layer, has an upper surface, a lower surface opposite to the upper surface, and a side surface connecting the upper and lower surfaces. The marking pattern has a shape corresponding to the marking in a plan view, and the distance from the upper end of the side surface of the marking pattern to the upper surface of the packaging substrate is equal to the distance from the upper surface of the semiconductor package to the upper surface of the packaging substrate. The connection terminal is located below the package substrate and is electrically connected to the package substrate.

2. The semiconductor package according to claim 1, wherein: The marking pattern has a thickness ranging from 3μm to 7μm; or The distance between the lower surface of the marking pattern and the upper surface of the semiconductor chip is less than 75 μm.

3. The semiconductor package according to claim 1, in, The marking pattern includes at least one of phase change material, EMI shielding material, and insulating material.

4. The semiconductor package according to claim 1, further comprising: An insulating layer extends over the molding layer. The insulating layer covers the lower and side surfaces of the marking pattern, while exposing the upper surface of the marking pattern. The semiconductor chip is located below the logo.

5. The semiconductor package according to claim 1, in, The molding layer covers the lower and side surfaces of the logo pattern and exposes the upper surface of the logo pattern.

6. The semiconductor package according to claim 1, further comprising: Bonding wires are placed between the chip pads of the semiconductor chip and the substrate pads of the packaging substrate, electrically connecting the semiconductor chip and the packaging substrate. The chip pads are on the upper surface of the semiconductor chip, and the substrate pads are on the upper surface of the packaging substrate.

7. The semiconductor package according to claim 6, further comprising: An insulating layer extends over the molding layer, wherein the insulating layer covers the lower and side surfaces of the logo pattern and exposes the upper surface of the logo pattern. The bonding wire contacts the lower surface of the insulating layer.

8. The semiconductor package according to claim 6, wherein, The bonding wires are positioned between the semiconductor chip and the marking pattern, and the bonding wires are spaced apart from the marking pattern.

9. A semiconductor package, comprising: Packaging substrate; A semiconductor chip is on a package substrate and is electrically connected to the package substrate; A molding layer, on the packaging substrate, covering the semiconductor chip; An insulating layer, on a molding layer, defines an marking pattern on the upper surface of the insulating layer, the upper end of the marking pattern being at a distance from the upper surface of the package substrate equal to the distance from the upper surface of the semiconductor package to the upper surface of the package substrate, and the thickness of the marking pattern being less than the distance between the lower surface of the marking pattern and the upper surface of the semiconductor chip. as well as The connection terminal is located below the package substrate and is electrically connected to the package substrate.

10. The semiconductor package according to claim 9, in, The insulating layer covers the lower and side surfaces of the logo pattern, and exposes the upper surface of the logo pattern. The semiconductor chip is located below the logo.

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