A method for dicing inter-pixel spacing in integrated circuits

Abstract

This invention discloses a method for creating dicing channels in a PI (polyimide) layer of an integrated circuit. Belonging to the field of integrated circuit manufacturing, the method includes: Step 1: Forming a release layer on top of the wafer and depositing a sputtering layer on top of the release layer; Step 2: Forming a redistribution layer on top of the sputtering layer; Step 3: When forming the dicing channel, retaining at least one first dielectric layer corresponding to the redistribution layer on the dicing channel. This invention solves the problem of difficult photoresist cleaning in multilayer redistribution layers, while protecting the underlying structure and preventing delamination.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically a method for separating PI-spaced dicing channels in integrated circuits. Background Technology

[0002] In integrated circuit manufacturing and wafer-level packaging processes, redistribution layers (RDLs) typically use polyimide (PI) as the dielectric material. To control wafer warpage and facilitate subsequent processes, typically only the first PI dielectric layer in the relevant structure does not have dicing channels, while all other PI dielectric layers have dicing channels.

[0003] When the number of redistribution layers is high (more than four), the photoresist (PR) remaining in the cleavage paths formed by the redistribution circuit fabrication process is difficult to effectively clean using photoresist removal. This typically requires extended rinsing or soaking times to ensure cleaning effectiveness. Prolonged and repeated rinsing can lead to the penetration of photoresist removal chemicals, and under high-pressure rinsing conditions, it can reduce the adhesion between the bottom PI dielectric layer of the unit and the sputtered layer below it. The sputtered layer, formed on the release layer, protects the release layer from chemical corrosion during photoresist removal and other processes. If the sputtered layer is damaged, it will lose its adhesion to the release layer, leading to delamination above the release layer, causing severe peeling defects, and affecting product yield and structural reliability. Summary of the Invention

[0004] To address the above issues and overcome the shortcomings of existing technologies, this invention provides a method for separating PI (polyimide) dicing channels in integrated circuits. This method effectively solves the problem that in the current market, only the first PI layer is not diced, and when the number of redistribution layers exceeds four, the photoresist inside the dicing channels is difficult to clean, requiring extended rinsing or soaking time. This can easily lead to the penetration of photoresist removal chemicals, reducing the adhesion between the underlying PI and the sputtered layer. Furthermore, damage to the sputtered layer can cause it to lose adhesion with the release layer, leading to delamination and affecting product yield.

[0005] The technical solution adopted by the present invention is as follows: The present invention proposes a method for dicing PI-spaced channels in integrated circuits, including step one: a release layer is formed on the upper part of the wafer, and a sputtering layer is disposed on the upper part of the release layer;

[0006] Step 2: A redistribution layer is formed above the sputtered layer;

[0007] Step 3: When forming the cut track, retain at least one first dielectric layer of the corresponding redistribution layer on the cut track.

[0008] Preferably, the redistribution layer includes a metal wiring layer and a dielectric layer, the dielectric layer includes a first dielectric layer and a bottom dielectric layer, and both the metal wiring layer and the dielectric layer are provided with several layers.

[0009] Preferably, in step three, the number of metal wiring layers or dielectric layers between the first dielectric layer and the sputtered layer is less than or equal to four.

[0010] Preferably, the first dielectric layer is a liquid resin, and the first dielectric layer hangs in a U-shape under the action of gravity, and the first dielectric layer protects the metal wiring layers from the first layer to the third layer.

[0011] Preferably, in step three, the first dielectric layer is disposed above the sputtered layer.

[0012] Preferably, the sputtered layer is a copper layer.

[0013] Furthermore, a release layer is disposed above the wafer, a sputtering layer is disposed above the release layer, and a redistribution layer is disposed above the sputtering layer. The redistribution layer includes a metal wiring layer and a dielectric layer, and a dicing track is disposed on the redistribution layer. A first dielectric layer is retained on the dicing track.

[0014] The beneficial effects of the present invention using the above structure are as follows: This solution proposes a method for PI-spaced dicing of integrated circuits. This method can effectively improve the warping problem of multilayer redistribution layers by using a method of dicing without spacing, while mitigating the erosion attack of photoresist removal chemicals on the structure, thus solving the two major technical problems of warping and chemical attack. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall structure of a method for separating PI-spaced dicing channels in an integrated circuit proposed in this invention.

[0016] Among them, 1. wafer; 2. release layer; 3. sputtering layer; 4. redistribution layer; 41. metal wiring layer; 42. dielectric layer; 421. first dielectric layer; 422. bottom dielectric layer; 5. dicing track.

[0017] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0020] like Figure 1 As shown, this invention proposes a method for separating dicing channels in integrated circuit PI, including step one: forming a release layer 2 on the surface of wafer 1 to provide a basis for the precise separation of the subsequent packaging structure from wafer 1; then, setting a sputtering layer 3 on top of the release layer 2, which can be deposited by magnetron sputtering process. The sputtering layer 3 protects the release layer 2 in steps such as photoresist removal, so that the release layer 2 is not corroded by chemical solutions. If the sputtering layer 3 is damaged, its bonding force with the release layer 2 will be weakened, causing delamination problems.

[0021] Step 2: A redistribution layer 4 is formed above the sputtered layer 3. Metal wiring layer 41 and dielectric layer 42 are alternately fabricated to form redistribution layer 4.

[0022] Specifically, the number of metal wiring layers 41 or dielectric layers 42 between the first dielectric layer 421 and the sputtered layer 3 is less than or equal to four. This avoids the accumulation of photoresist residue in the dicing area 5 due to excessive layer count, significantly reducing the risk of photoresist stripping solution penetrating to the underlying layers. Simultaneously, this design disperses interlayer thermal and mechanical stresses, and in conjunction with the subsequent dicing area 5, further alleviates wafer warpage caused by multilayer stacking, balancing the integration of the redistribution layer with the feasibility of the process.

[0023] Step 3: When forming the dicing track 5, the method of forming the dicing track 5 is achieved through the circuit design and photomask process during the formation of the redistribution layer 4. At least one first dielectric layer 421 of the redistribution layer 4 corresponding to the dicing track 5 is retained. This method of separating the dicing tracks can effectively release the internal stress accumulated during the stacking process of the redistribution layer 4, significantly improving the wafer warpage problem from a structural perspective. Furthermore, the at least one first dielectric layer 421 retained on the dicing track 5 serves as a protective spacer, preventing the resist remover from directly penetrating into the sputtered layer 3 below the bottom dielectric layer 422, causing corrosion and other damage to the sputtered layer 3, and thus causing the release layer 2 and the sputtered layer 3 to delaminate. This solves the problem of easy delamination between the release layer 2 and the upper layer after resist removal and cleaning. It should be noted that, due to the certain fluidity of the liquid resin material, the at least one first dielectric layer 421 retained on the dicing track 5 hangs in a U-shaped state under the action of gravity, which can completely fill the dicing track 5 without dead corners, completely eliminating gaps and cavities within the dicing track 5. This structure further mitigates the risk of chemical penetration caused by the opening of the dicing channel 5, and forms a double protection with the uncut dielectric layer 42 at the bottom, ensuring that the resist remover cannot penetrate into the bottom sputtering layer 3 and the release layer 2, fundamentally solving the delamination problem caused by the difficulty in cleaning the photoresist in the redistribution layer. This invention discloses an integrated circuit PI spaced-out dicing structure. A release layer 2 is disposed above a wafer 1, a sputtering layer 3 is disposed above the release layer 2, and a redistribution layer 4 is disposed above the sputtering layer 3. The redistribution layer 4 includes a metal wiring layer 41 and a dielectric layer 42. A dicing track 5 is disposed on the redistribution layer 4, and a first dielectric layer 421 is retained on the dicing track 5. This spaced-out dicing structure can effectively release the internal stress accumulated during the stacking process of the redistribution layer 4, significantly improving the wafer warpage problem from a structural perspective. Furthermore, the at least one first dielectric layer 421 retained on the dicing track 5 serves as a spacer protection, preventing the resist remover from directly penetrating into the sputtering layer 3 below the bottom dielectric layer 422, causing corrosion and other damage to the sputtering layer 3, and thus causing delamination between the release layer 2 and the sputtering layer 3. This solves the problem of easy delamination between the release layer 2 and the layer above after resist removal and cleaning.

[0024] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0025] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0026] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for dicing interlaced tracks in an integrated circuit, characterized in that: The method for separating the PI-spaced dicing channels of the integrated circuit includes the following steps: Step 1: A release layer (2) is formed on the wafer (1), and a sputtering layer (3) is disposed on the release layer (2); Step 2: A redistribution layer (4) is formed on top of the sputtered layer (3); Step 3: When forming the cut track (5), retain at least one first dielectric layer (421) of the corresponding redistribution layer (4) on the cut track (5).

2. The method for dicing interlaced PI channels in an integrated circuit according to claim 1, characterized in that: The redistribution layer (4) includes a metal wiring layer (41) and a dielectric layer (42). The dielectric layer (42) includes a first dielectric layer (421) and a bottom dielectric layer (422). Both the metal wiring layer (41) and the dielectric layer (42) are provided with several layers.

3. The method for dicing interlaced PI tracks in an integrated circuit according to claim 2, characterized in that: In step three, the number of metal wiring layers (41) or dielectric layers (42) between the first dielectric layer (421) and the sputtered layer (3) is less than or equal to four.

4. The method for dicing interlaced PI channels in an integrated circuit according to claim 1, characterized in that: The first dielectric layer (421) is a liquid resin. The first dielectric layer (421) hangs in a U-shape under the action of gravity, and the first dielectric layer (421) protects the metal wiring layers (41) from the first layer to the third layer.

5. The method for dicing interlaced PI tracks in an integrated circuit according to claim 1, characterized in that: In step three, the first dielectric layer (421) is disposed above the sputtered layer (3).

6. The method for dicing interlaced PI tracks in an integrated circuit according to claim 1, characterized in that: The sputtered layer (3) is a copper layer.

7. An integrated circuit PI-spaced dicing structure according to any one of claims 1 to 6, characterized in that: A release layer (2) is disposed above the wafer (1), a sputtering layer (3) is disposed above the release layer (2), a redistribution layer (4) is disposed above the sputtering layer (3), the redistribution layer (4) includes a metal wiring layer (41) and a dielectric layer (42), a dicing track (5) is disposed on the redistribution layer (4), and a first dielectric layer (421) is retained on the dicing track (5).

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