High heat dissipation chip stack semiconductor package structure and method of manufacturing the same

Abstract

This invention relates to the field of semiconductor packaging technology, and provides a high-heat-dissipation chip stacked semiconductor packaging structure and its fabrication method. The semiconductor packaging structure includes: a horizontally arranged carrier; at least one stacked chip group, including: multiple first chips stacked sequentially along a horizontal direction, each first chip being perpendicular to the upper surface of the carrier; each first chip in the stacked chip group has a metal pad on its surface; leads, one end of each lead being connected to each of the metal pads respectively, and the other end of each lead being connected to a connection point on the carrier through a conductive interconnect structure. This invention achieves end-face electrical connection by vertically supporting multiple stacked chips on a horizontal carrier and using lead bridging. Its advantages include: significantly reducing the horizontal projected area of ​​the package and increasing integration density; direct heat dissipation along the high thermal conductivity direction of the chip, significantly enhancing heat dissipation capacity; and simultaneously ensuring manufacturing compatibility and connection reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a high heat dissipation chip stacked semiconductor packaging structure and its fabrication method. Background Technology

[0002] The 3D integration technology of semiconductor chips has evolved from horizontal expansion to vertical stacking. Horizontal planar expansion technology involves multiple chips arranged side-by-side on the same horizontal layer of the carrier surface, with their main surfaces (active layers or back surfaces) parallel to the carrier surface. The center points of all chips are at the same height, differing only in horizontal position. The bottom or top surface of the chips (i.e., the main surface itself) faces the carrier, and electrical interconnection is achieved through wire bonding or flip-chip bonding. This technology is mature but has fundamental drawbacks: the horizontal footprint increases linearly with the number of chips, limiting package size; the interconnects between chips are long, resulting in significant signal delay; and the heat flux density distribution is uneven, making it difficult to control local hot spots. The core limitation of this technology is that the chips connect to the carrier with their large bottom or top surfaces, failing to utilize the spatial efficiency in the chip thickness direction, and the connection interface is limited to the main surface of the chip.

[0003] 3D stacking involves multiple chips stacked vertically, with their main surfaces parallel to the substrate surface, but arranged vertically perpendicular to the substrate surface. The center points of each chip are at different heights, forming a multi-layer structure. Interlayer interconnects are achieved using through-silicon vias (TSVs) and micro-bumps. This technology shortens the vertical transmission path and increases bandwidth density. However, as the number of stacked layers increases, the cumulative thermal resistance effect intensifies, making heat dissipation difficult for the bottom chips. Once the overall stacked structure is connected to the bottom substrate, it forms a rigid, non-removable unit; a single point failure renders the entire assembly unusable, resulting in extremely high repair costs. The core limitation of this technology is that the chips remain in a flat position with the bottom or top surface as the connection interface, merely repeating the vertical stacking without changing the interface morphology between the chips and the substrate.

[0004] The common essence of the two technologies mentioned above is that the connection interface between the chip and the carrier (or between chips) is always the large bottom or top surface of the chip, with the chip using its main surface itself as the interface for electrical connection and mechanical support.

[0005] In recent years, the industry has proposed a new three-dimensional integration approach that differs from the two branches mentioned above: changing the connection interface between the chip and the carrier, replacing the traditional "bottom / top surface contact" with "end / side surface contact," and exchanging the height of the chip in the planar direction for the horizontal area occupied to achieve high-density integration. Specifically, the chip's end face or side surface is perpendicular to the carrier surface, and multiple chips are arranged in an array along the horizontal direction of the carrier.

[0006] However, this technical approach faces a critical challenge regarding the interface. Both traditional technical branches mentioned above rely on parallel contact between the chip's large bottom or top surface and the carrier, with I / O routing, alignment processes, and thermal management schemes all designed around this "surface contact" form. When the chip is repositioned to an "end-face support" configuration, the contact interface with the carrier changes from a large bottom surface to a narrow end face, drastically reducing the contact area (typically to a fraction of the original bottom surface area). This end face is originally a non-functional edge formed by the chip dicing process, with a rough surface, no metallization, and lacking I / O routing capabilities. Traditional solutions have not yet solved how to effectively route the chip's I / O to the end face and achieve reliable electrical interconnection between the end face and the upper surface of the carrier.

[0007] Traditional solutions include: simple mechanical clamping structures, which only provide physical support without addressing electrical connectivity; chip edge metallization solutions, which cannot achieve precise electrical contact with the carrier; and flexible circuit board adapter solutions, which are complex, costly, and difficult to mass-produce. In particular, traditional publicly available contact-based connection solutions have failed to achieve the interface transformation from large-area bottom-side connections to narrow end-side connections, making it difficult to balance electrical performance and mechanical stability. These solutions essentially still attempt to apply the "surface contact" connection concept, failing to innovatively design for the unique characteristics of "end-side support" postures, such as narrow interfaces, directional heterogeneity, and rough surfaces. They also fail to provide a contact-based connection solution that can form reliable I / O leads on the chip end-side and achieve low-stress, high-density electrical interconnection with the carrier. Summary of the Invention

[0008] The purpose of this invention is to solve at least one technical problem in the background art and to provide a high heat dissipation chip stacked semiconductor packaging structure and its preparation method.

[0009] To achieve the above objectives, the present invention provides a high heat dissipation chip stacking semiconductor package structure, comprising: Horizontally arranged load-bearing components; At least one stacked chipset, comprising: a plurality of first chips stacked sequentially in a horizontal direction, each first chip being perpendicular to the upper surface of the carrier; The surface of each of the first chips in the stacked chipset is provided with metal pads. Each lead has one end connected to one of the metal pads respectively, and the other end of each lead is connected to a connection point on the carrier through a conductive interconnection structure.

[0010] According to one aspect of the invention, adjacent first chips in the stacked chipset are bonded together by an adhesive.

[0011] According to one aspect of the invention, the conductive interconnect structure includes at least one of conductive solder balls, conductive adhesive, or nano-metal paste.

[0012] According to one aspect of the invention, the stacked chipset further includes a spacer disposed between adjacent first chips.

[0013] According to one aspect of the invention, it further includes: A first molding compound covers at least the sidewalls of the stacked chipset; The other end face of each lead is exposed on the bottom surface of the first encapsulation and connected to the connection point on the carrier through the conductive interconnect structure.

[0014] According to one aspect of the invention, it further includes: a second molding compound, the second molding compound at least covering the bonding region of the stacked chipset, the first molding compound, and the carrier.

[0015] According to one aspect of the invention, the end of each first chip in the stacked chipset away from the carrier is exposed outside the package structure and is thermally connected to a heat dissipation device.

[0016] To achieve the above objectives, the present invention also provides a method for fabricating a high-heat-dissipation chip stacked semiconductor package structure, comprising: S1. Provide a horizontally arranged temporary carrier plate; S2. Multiple first chips are stacked vertically on the temporary carrier, each first chip being parallel to the temporary carrier. During the stacking process, a wire bonding process is performed to connect one end of the wire to the metal pad on the surface of the corresponding first chip, and to cut off the other end of the wire at a predetermined position beyond the edge of the corresponding first chip. The stacking order is as follows: after the first layer of chips is bonded, wire bonding and cutting are performed, then the second layer of chips is bonded and wire bonding and cutting are performed, and so on. S3. Form a first molding compound to encapsulate the stacked plurality of first chips and the leads; S4. Process the first molding compound to expose the cross-section of the other end of the lead, forming a stacked chipset unit; S5. Provide a horizontally arranged load-bearing component; S6. The stacked chipset unit is mounted on the carrier, such that each of the first chips is perpendicular to the carrier, and the cross-section of the other end of the exposed lead is electrically connected to the connection point on the carrier through a conductive interconnect structure. S7. Secure and cover the bonding area by using a base filler or forming a second sealant.

[0017] According to one aspect of the invention, step S2 further includes: placing a spacer between adjacent first chips.

[0018] According to one aspect of the invention, it further includes: By using a grinding or etching process, the ends of each first chip in the stacked chipset unit that are away from the horizontal support are exposed, and the exposed ends are thermally connected to a heat dissipation device.

[0019] According to the present invention, by supporting multiple first chips vertically on a horizontal carrier and stacking them sequentially along the horizontal direction, the contact interface between the chips and the carrier is transformed from a large main surface area in traditional solutions to a narrow end face. The horizontal projected area occupied by a single chip is reduced from chip length × width to chip thickness × width, a reduction of more than an order of magnitude. More chips can be integrated within the same carrier area, significantly improving packaging density. Furthermore, the carrier can be a substrate or another chip, and is not limited to a single chip; it can also be in the form of a module, further supporting the collaborative integration of multiple packaging units and enhancing the compatibility and scalability of the solution in system-level packaging.

[0020] When the chip is placed vertically, heat can be conducted along the chip's planar direction, rather than through the thickness of the interlayer dielectric layer. Because the chip's bulk material has high intrinsic thermal conductivity along the planar direction, the heat conduction path within the chip is within a high-conductivity channel. In the stacked chipset, the end of each first chip furthest from the carrier is exposed outside the package and thermally connected to the heat dissipation device, establishing an independent, short-path, low-thermal-resistance heat conduction channel for each chip, effectively reducing the temperature rise inside the package. Adjacent chips can be connected using colloids with different thermal conductivity coefficients depending on heat dissipation requirements; high-thermal-conductivity colloids can form lateral thermal bridging channels between chips. The leads are made of metal, forming auxiliary thermal conduction paths while completing electrical connections, further enhancing the overall heat dissipation capability.

[0021] This invention effectively solves the problem of not being able to directly form I / O on the end face when the chip is vertically supported by leading wires from the chip surface pads to the carrier connection point. The lead shape and material can be flexibly selected according to requirements; metal leads have good flexibility and are suitable for dense wiring, while metal strips have a large cross-sectional area and are suitable for high current transmission. The electrical paths of each chip are independent, reducing the risk of signal crosstalk. The first molding compound encapsulates the stacked chipset and exposes the lead end face to the bottom surface, forming a planar, shortest path, low contact resistance I / O connection interface. The lead is fully encapsulated and fixed, effectively dispersing connection stress. The carrier connection point size is larger than the lead cross-sectional area and the bridging of conductive interconnects compensates for alignment misalignment and improves connection yield.

[0022] Adjacent first chips are bonded together with adhesive to connect multiple independent chips into a single unit. The placement of spacers between the bottom surface of the later-stacked chips and the pad area of ​​the earlier-stacked chips creates a defined clearance, fundamentally preventing physical interference from lead pressure. The first molding compound protects the stacked chip structure and cures the leads, while the second molding compound covers the bonding area between the stacked chipset and the carrier, fixing the vertically placed stacked chipset, buffering thermal expansion mismatch stress, protecting the connection interface from environmental corrosion, and significantly improving the long-term reliability of the package under vibration, shock, and temperature cycling conditions.

[0023] The entire fabrication process utilizes mature wire bonding equipment and processes, completing the stacking and wire bonding on a temporary carrier with the chips lying flat, eliminating the need for developing dedicated equipment. After molding and dicing, the stacked chipset forms independent units, allowing for pre-testing before installation to eliminate faulty units and improve overall packaging yield. The wire bonding materials, types, and spacing can be flexibly configured. Liquid adhesives or films can be used as the bonding agent, and solder balls, conductive adhesives, or nano-metal pastes can be selected for the conductive interconnect structure. The pad thickness can be adjusted according to the wire specifications, enabling the same process framework to cover various packaging product needs, from high-bandwidth storage and in-memory computing to heterogeneous integration, demonstrating excellent technical versatility and adaptability to product iteration.

[0024] In summary, this invention, through its core architecture of vertical chip support, horizontal stacking, and lead-bridging connections, combined with a series of technical means such as adhesive bonding, gasket adjustment, layered protection of the encapsulation, and top heat dissipation coupling, significantly improves the packaging integration density and heat dissipation capacity while ensuring electrical connection reliability, mechanical structural strength, and manufacturing process compatibility. It provides a systematic solution for high power density, high bandwidth, and heterogeneous integrated semiconductor packaging. Attached Figure Description

[0025] Figure 1 This schematic diagram illustrates the overall structural layout of a high-heat-dissipation chip stacked semiconductor package structure according to an embodiment of the present invention. Figure 2 This schematic diagram illustrates a partial structural arrangement of a padless, high-heat-dissipation stacked semiconductor package structure according to another embodiment of the present invention. Figure 3 This schematic diagram illustrates a partial structural arrangement of a padless, high-heat-dissipation chip stack semiconductor package structure according to a third embodiment of the present invention. Figure 4 Schematic representation Figure 3 A partial structural layout diagram of a high-heat-dissipation stacked semiconductor package structure with added particle structure; Figures 5-12 The flowchart schematically illustrates a method for fabricating a high-heat-dissipation chip stacked semiconductor package structure according to an embodiment of the present invention. Detailed Implementation

[0026] The invention will now be discussed with reference to exemplary embodiments. It should be understood that the described embodiments are merely intended to enable those skilled in the art to better understand and thus implement the invention, and are not intended to imply any limitation on the scope of the invention.

[0027] As used herein, the term "comprising" and its variations are to be interpreted as open-ended terms meaning "including but not limited to". The term "based on" is to be interpreted as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment".

[0028] Figure 1 This schematic diagram illustrates the overall structural layout of a high-heat-dissipation stacked semiconductor package structure according to an embodiment of the present invention. Figure 1 As shown, in this embodiment, the high heat dissipation chip stack semiconductor package structure includes: Horizontally arranged load-bearing component 1; At least one stacked chipset, including: a plurality of first chips 2 stacked sequentially in a horizontal direction, each first chip 2 being perpendicular to the upper surface of the carrier 1; Each first chip 2 in the stacked chipset has a metal pad on its surface; Lead 3, one end of each lead 3 is connected to each metal pad respectively, and the other end of each lead 3 is connected to the connection point on the carrier 1 through the conductive interconnection structure 4.

[0029] In this embodiment, the above structure achieves significant technical effects in terms of space utilization through a combination of vertical chip support, horizontal stacking, and lead-connected bridging: multiple first chips are stacked sequentially in the horizontal direction, and each chip is supported on the upper surface of the carrier in a vertical posture. The contact interface between the chip and the carrier is changed from a large-area main surface in the traditional solution to a narrow end face. The horizontal projected area occupied by a single chip is reduced from chip length × width to chip thickness × width, and the reduction ratio can reach more than an order of magnitude. Thus, the number of chips that can be integrated is greatly increased within the same carrier area, effectively improving the packaging density.

[0030] Regarding the heat dissipation path, when the chip is placed vertically, heat can be conducted along the chip's planar direction, rather than through the thickness direction of the interlayer dielectric layer. Because the chip's main material has high intrinsic thermal conductivity along the planar direction, the heat conduction path within the chip is in a high-conductivity channel, reducing the internal thermal resistance of the package and helping to alleviate hotspot issues in high-density integration scenarios.

[0031] Regarding electrical connections, the aforementioned structure effectively solves the problem of inability to directly form I / O on the end face when the chip is vertically supported. The end face where the chip contacts the carrier is a non-functional edge formed by cutting, which originally lacks electrical lead-out capability. The aforementioned structure bypasses the obstacle of direct end face connection by setting metal pads on the surface of each chip, connecting one end of a lead to the pad, and the other end to the connection point of the carrier through a conductive interconnect structure, thus achieving reliable chip I / O lead-out. The electrical paths of each chip are independent, reducing the risk of signal crosstalk, and the lead length and direction can be flexibly adjusted according to design requirements, exhibiting strong design adaptability.

[0032] In terms of mechanical support, the chip is supported vertically on the upper surface of the carrier, with its center of gravity close to the carrier surface. The overall structure's resistance to lateral overturning is superior to that of a multi-layer cantilever structure where chips are stacked flat. The main load-bearing direction is the chip thickness direction, and the chip has high intrinsic mechanical strength along this direction. The structural stress is transformed from bending stress in traditional solutions into compressive stress, reducing the risk of chip breakage.

[0033] In terms of manufacturing and maintenance, leaded connections can use mature wire bonding technology, eliminating the need to develop entirely new connection equipment or material systems, thus reducing manufacturing costs and mass production difficulties, and ensuring yield and reliability.

[0034] Furthermore, such as Figure 1 As shown, in this embodiment, adjacent first chips 2 in the stacked chipset are bonded together by adhesive 5. Adhesive materials with different thermal conductivity can be selected according to requirements, such as non-conductive adhesive, conductive silver paste, etc.

[0035] In this embodiment, adjacent first chips are bonded together with an adhesive to connect multiple physically separate independent chips into a single stacked chip group.

[0036] In terms of thermal management, colloidal materials can be selected with different thermal conductivity coefficients according to heat dissipation requirements, such as non-conductive adhesives or conductive silver pastes, making the heat conduction path adjustable. When a high thermal conductivity colloid is used, the colloid not only acts as an adhesive but also becomes a lateral thermal bridging channel between adjacent chips. The heat generated by the chip can be transferred between chips through the colloid layer, increasing the parallel heat dissipation path and further reducing the overall thermal resistance of the package. When a low thermal conductivity colloid is used, the colloid layer can act as a thermal barrier, reducing thermal crosstalk between adjacent chips and preventing heat from high-power chips from being conducted to adjacent low-power or heat-sensitive chips, thus achieving thermal zoning management within the chipset. In addition, the elastic modulus of the colloid is usually lower than that of silicon chips, and it can absorb the stress caused by thermal expansion mismatch through its own deformation during temperature cycling, balancing the stability of the heat conduction path and the protection of the chip structure.

[0037] In terms of process adaptability and design flexibility, the adhesive can be in the form of liquid adhesive or film, suitable for dispensing or pre-attachment processes respectively. The most economical application method can be selected based on the number of stacked layers, chip size, and production volume, without changing the overall packaging process. By controlling the adhesive thickness, the gap between adjacent chips can be precisely adjusted, reserving space for subsequent wire bonding or adjusting the overall size of the stacked chipset to adapt to different packaging space requirements. Adhesive bonding is not sensitive to the type of metallization on the chip surface and is compatible with common pad materials such as aluminum, copper, and gold, requiring no additional surface treatment of the chip.

[0038] In terms of electrical isolation, when the selected colloid is a non-conductive adhesive, the colloid provides electrical insulation between adjacent chips while achieving mechanical fixation, preventing short circuits or leakage paths caused by accidental contact of the chip sidewalls, and ensuring the independence of the electrical paths of each chip and the integrity of the signals.

[0039] In summary, the adjacent first chips are bonded together with an adhesive, and the type of adhesive can be selected according to the thermal conductivity requirements. While achieving overall fixation of the stacked chipset, it provides an adjustable thermal conductivity path, effective thermal stress buffering, flexible process adaptability, and reliable electrical isolation effect, which significantly enhances the mechanical reliability, thermal management flexibility, and manufacturing compatibility of the packaging structure.

[0040] Furthermore, in this embodiment, the lead wire includes a metal lead wire or a metal strip; the material of the lead wire includes a metal or an alloy, including at least one of metals such as gold, silver or copper, or alloys thereof.

[0041] In this embodiment, in terms of electrical performance, gold, silver, copper, aluminum, palladium and other materials have excellent conductivity, which can effectively reduce the resistance loss of the lead wire itself, reduce the voltage drop and heat loss during signal transmission, and ensure the signal integrity and power transmission efficiency of the electrical connection between the chip and the carrier.

[0042] In terms of thermal management, gold, silver, and copper are all excellent thermal conductors, and the leads not only complete the electrical connection but also form auxiliary heat conduction paths. Some of the heat generated by the chip can be conducted to the carrier or surrounding medium through the leads, increasing the parallel heat dissipation channels inside the package. In particular, when metal strips are used, their flat cross-section increases the contact area with the molding compound or air, which is conducive to the dissipation of heat to the surrounding environment and further enhances the heat dissipation effect.

[0043] In terms of process adaptability, both metal leads and metal strips can be achieved through mature wire bonding processes, making them highly compatible with existing packaging manufacturing processes. Metal leads offer better flexibility and bending capabilities, making them suitable for dense pad layouts and complex routing requirements. In terms of material selection flexibility, metals or alloys such as gold, silver, and copper can be selected individually or in combination based on the specific application scenario's cost budget, conductivity requirements, and oxidation resistance. For example, gold has excellent oxidation resistance and bonding process window, making it suitable for high-reliability scenarios; copper has lower cost and good conductivity, making it suitable for cost-sensitive products; silver combines high conductivity with moderate cost, serving as a compromise solution for specific needs. This flexibility in material selection allows packaging solutions to adapt to product requirements with different performance and cost gradients without altering the overall structural design.

[0044] In this embodiment, the above-mentioned limitations on lead shape and material ensure low electrical resistance and high signal quality, while also taking into account auxiliary heat dissipation, process compatibility and cost control flexibility, thereby improving the overall performance and design adaptability of the packaging structure.

[0045] Furthermore, in this embodiment, the conductive interconnect structure 4 includes at least one of conductive solder balls (metal or metal composites such as SnAg, SnAgCu, etc.), conductive adhesive, or nano-metal paste.

[0046] In this embodiment, conductive solder balls (such as SnAg, SnAgCu, etc.) form a metallurgical bond through reflow soldering, resulting in high connection strength; conductive adhesive and nano-metal paste form a conductive path through curing, with a low elastic modulus, which can effectively absorb the thermal expansion coefficient mismatch stress between the chip and the carrier, reducing the risk of fatigue failure at the connection point.

[0047] All of the above materials can be applied via dotting, printing, or ball-mounting processes, and are compatible with existing packaging equipment. The conductive solder balls and conductive adhesive are fluid in their molten or uncured state, which can compensate for alignment misalignment between the lead cross-section and the carrier pads to some extent, reducing alignment accuracy requirements and improving mass production yield.

[0048] Conductive solder balls, conductive adhesives, and nano-metal pastes all possess low resistivity characteristics, ensuring a low-impedance electrical path is formed between the lead and the carrier connection point, reducing signal transmission loss and IR voltage drop, and compensating for alignment misalignment.

[0049] Furthermore, such as Figure 1 As shown, in this embodiment, the stacked chipset further includes a spacer 6 (e.g., a dummy silicon wafer) disposed between adjacent first chips 2. The spacer 6 is connected to the first chips 2 on both sides through the aforementioned colloid 5, reserving lead space.

[0050] In this embodiment, during the manufacturing process, multiple first chips are stacked sequentially along a direction perpendicular to the temporary carrier. After the first stacked chips complete surface wire bonding, the leads are pulled out from the pads and form an upward-convex arch. If the later stacked chips are placed directly on top of the first stacked chips, the bottom surface of the later stacked chips will encroach on the arch space above the pads of the first stacked chips, causing the leads to be deformed under pressure, the insulation layer to break, or the root solder joints to peel off, resulting in electrical short circuits or connection failures.

[0051] The spacers placed between adjacent first chips provide a safe clearance area for lead arches by increasing the vertical spacing between the chips. Specifically, the spacers elevate the bottom surface of the subsequently stacked chip from the surface of the previously stacked chip, ensuring that the space above the pads is greater than the minimum clearance required for the lead arches. Leads can freely bulge, turn, and extend to the chip edge within this clearance area, avoiding physical contact with the bottom surface of the subsequently stacked chip.

[0052] In this embodiment, the additional interlayer gap provided by the spacer ensures that the leads have a complete arc height and a free routing path within the stacked structure, preventing the leads from being mechanically compressed in subsequent processes. The lead shape remains unchanged, the insulation layer is intact, and the solder joint root is not subjected to additional stress, thereby ensuring a long-term stable and reliable electrical connection path from the chip pads to the carrier.

[0053] Wire bonding processes have specific requirements for dome height and trace space. Without spacers, fluctuations in adhesive layer thickness and die placement pressure during chip stacking can easily lead to wire stress and batch failures. The introduction of spacers transforms the interlayer gap from a difficult-to-control adhesive layer thickness into a deterministic dimension determined by the spacer thickness. The spacer thickness can be pre-selected and kept stable according to the lead specifications, significantly reducing the sensitivity of the stacking process to lead interference and improving mass production consistency and yield.

[0054] As a rigid support, the spacer can provide local or full-area support points within the chip stacking surface, creating a parallel and uniform gap between the bottom surface of the later-stacked chip and the surface of the earlier-stacked chip. This helps the molding compound to smoothly fill the gap in subsequent molding processes, reducing filling voids or air bubbles caused by uneven gaps, and improving the overall mechanical strength and reliability of the package.

[0055] In this embodiment, different application scenarios may use metal leads of different diameters or metal strips of different thicknesses, resulting in varying requirements for arch height space. By selecting spacers of different thicknesses, the interlayer gap can be flexibly adjusted to meet the space requirements of the corresponding lead specifications without changing the chip design or core parameters of the bonding process, thus enhancing the adaptability of this packaging structure to different product needs.

[0056] In this embodiment, the gasket can be made of a material with good thermal conductivity, such as silicon. When the gasket is bonded to an adjacent chip using an adhesive, a second thermal path, in addition to the edge leads, can be formed between the chips. Heat can be dissipated through the gasket to alleviate localized hotspots, further improving the overall heat dissipation capability of the package structure.

[0057] Of course, in this invention, the gasket may be omitted depending on the situation. By selecting appropriate metal wires and adhesive materials, the lead wire and adhesive application can be completed. For example... Figure 2 As shown, chip stacking and wiring are accomplished using wire-in-film (polymer mask) technology; further, as shown in example 3, the space between the two chips can be cut out using photolithography, mechanical methods, or lasers, and then wire bonding can be used to complete the wiring. Figure 2 and Figure 3 In both examples, the thickness of the adhesive layer needs to be considered to ensure that the adhesive layer can guarantee the actual bonding effect and the encapsulation thickness requirements, while also ensuring the capacity of the wire bonding space, for example, 30~200 micrometers.

[0058] Furthermore, such as Figure 4 As shown above, in the above Figure 3 Based on this, a particle structure 14 (circular particles, which can be metal particles, ceramic particles, etc.) can be filled in the colloid between the two chips. This particle structure has at least thermal conductivity.

[0059] Furthermore, such as Figure 1 As shown, in this embodiment, the high heat dissipation chip stack semiconductor package structure further includes: The first molding compound 7 covers at least the sidewalls of the stacked chipset; The other end face of each lead 3 is exposed on the bottom surface of the first encapsulation 7 and connected to the connection point on the carrier through the conductive interconnection structure 4.

[0060] In this embodiment, a first molding compound covers the sidewalls of the stacked chipset, solidifying multiple chips and leads into a single unit, providing structural stability and environmental protection. The end faces of each lead are exposed on the bottom surface of the first molding compound, forming a planar I / O contact array. This allows the chipset to connect to the carrier with the shortest path and low contact resistance, while the leads are fully encapsulated and fixed, effectively dispersing connection stress. The bottom surface is ground flat, providing a uniform and consistent bonding reference surface for subsequent connections, and also serving as an auxiliary heat dissipation surface to conduct heat from the chip sidewalls outwards.

[0061] Furthermore, in this embodiment, the size of the connection point on the carrier 1 is recommended to be larger than the cross-sectional area of ​​the lead wire 3.

[0062] In this embodiment, when the stacked chipset is mounted vertically to the carrier, the lead end face must be aligned with the connection point on the carrier. Due to manufacturing tolerances, molding compound warpage, and limitations in the precision of the mounting equipment, the actual position of the lead end face may be offset. The connection point size is larger than the lead cross-sectional area, providing a larger contact area for the lead end face. Even with some misalignment, the lead end face can still fall completely within the connection point range, ensuring that the conductive interconnect material can fully bridge the two, avoiding loose connections or open circuits caused by misalignment. This improves connection yield and reliability while reducing reliance on high-precision mounting equipment.

[0063] Furthermore, in this embodiment, mechanical strength can be reinforced subsequently with underfill or MUF (Molded Underfill) if necessary.

[0064] Furthermore, such as Figure 1 As shown, in this embodiment, the high heat dissipation chip stack semiconductor package structure further includes: a second molding compound 8, which at least covers the bonding area of ​​the stacked chipset, the first molding compound, and the carrier.

[0065] In this embodiment, the second molding compound completely covers the connection area between the stacked chipset (including the first molding compound) and the carrier, creating a large-area molding compound bonding interface between the stacked chipset and the carrier, which were originally supported only by lead connection points and conductive interconnect structures. After the molding compound cures, the bottom of the stacked chipset is firmly bonded to the upper surface of the carrier, effectively dispersing the shear force and bending moment generated by vibration, impact, or thermal stress, and preventing the connection points from cracking and failing due to stress concentration.

[0066] The electrical connection area between the lead end face and the carrier component is the weakest point of the package, susceptible to intrusion of moisture, contaminants, and corrosive gases. The second molding compound completely seals this area, isolating it from the external environment and preventing oxidation, electrochemical corrosion, or insulation degradation of the metal connection points, significantly improving the long-term reliability of the package in harsh operating environments.

[0067] There is a significant difference in the coefficients of thermal expansion between stacked chipsets (silicon-based materials) and carrier components (such as organic substrates). During temperature cycling, the relative displacement of the interface between the two will transfer stress through the bonding points. After the second molding compound covers the bonding area, its own coefficient of thermal expansion is between the two or it absorbs part of the strain through elastic deformation, acting as a stress buffer layer and reducing the accumulation of thermal fatigue damage at the bonding points.

[0068] The second molding compound fills the gaps between the stacked chipset and the carrier, as well as the open space around the chipset, forming a continuous, high-rigidity package profile. This helps control warpage of the package during subsequent surface mounting or system-level assembly, maintains the coplanarity of the bottom solder balls, and improves board-level assembly yield.

[0069] Although the second molding compound has limited thermal conductivity, it increases the contact area between the bottom of the chipset and the molding compound by covering the bonding area between the stacked chipset and the carrier. Heat conducted from the chip to the connection point via the leads can be further diffused towards the plane of the carrier through the second molding compound, forming an additional heat dissipation path and helping to reduce the temperature of local hot spots.

[0070] The plastic sealing protection mentioned above can be achieved using other non-plastic sealing methods, such as potting cover.

[0071] Furthermore, such as Figure 1 As shown, in this embodiment, the end of each first chip 2 in the stacked chipset away from the carrier 1 is exposed outside the packaging structure and is thermally connected to a heat dissipation device 9 (e.g., a cooling plate).

[0072] In this embodiment, each first chip is supported vertically on a carrier, with its end furthest from the carrier directly exposed outside the package. Heat generated inside the chip can be efficiently conducted along the chip plane (i.e., the direction of high intrinsic thermal conductivity of the chip) to the exposed end face, and then quickly discharged to the external environment of the package through a heat dissipation device thermally connected thereto. This reduces the heat transfer path through low thermal conductivity materials such as molding compound, underfill adhesive, or interlayer dielectric, significantly reducing the thermal resistance of the heat conduction path and greatly improving heat dissipation efficiency.

[0073] Silicon, silicon carbide, and other chip substrate materials have high thermal conductivity along the wafer plane. When the chip is placed vertically, its plane points directly away from the package exterior, away from the carrier. Exposing the top and connecting it to a heat dissipation device allows heat from inside the chip to be directly dissipated along the direction of highest thermal conductivity, avoiding the path loss in traditional horizontal stacking schemes where heat must pass through the chip thickness and multiple layers of dielectric material to reach the heat dissipation surface.

[0074] In this stacked chipset, the top of each first chip is exposed outside the package and can be thermally connected to either the same heat sink or their own independent heat sink. This means that each chip has an independent heat dissipation path directly to the outside of the package. The direct exposure and connection of the chip top to the heat sink compresses the heat transfer distance from the active area of ​​the chip to the cold end outside the package to a portion of the chip's length. This structure results in a shorter heat transfer path and lower thermal resistance, effectively reducing the chip junction temperature and the overall temperature rise inside the package, providing a foundation for thermal management in high power density applications.

[0075] The exposed chip tip can be polished or etched to obtain a highly flat contact surface, which can be tightly fitted with the heat dissipation device or filled with efficient thermal interface material to reduce contact thermal resistance.

[0076] Furthermore, such as Figure 1 As shown, in this embodiment, the horizontally arranged carrier 1 is a substrate or a second chip. Solder balls 10 can be placed on the back of the bottom chip or substrate to prepare for future electrical connections; the bottom chip or substrate is not limited to a single chip, but can also be a module. This configuration allows the packaging structure to flexibly adapt to different interconnection requirements: when the carrier is a substrate, it can be directly soldered to the system motherboard via back solder balls to achieve standardized surface mount; when the carrier is another chip or chip module, it can form a direct stacking or side-by-side integration of chips, shortening the signal transmission path and increasing integration density. The carrier's ability to expand into a module further supports the collaborative work of multiple packaging units, enhancing the compatibility and scalability of the packaging solution in system-level integration.

[0077] In this embodiment, the first chip can be a homogeneous memory chip or a hybrid stack of heterogeneous memory chips and logic control chips; the second chip can be a logic control chip or an interposer chip, etc. This configuration provides the package structure with extremely high functional integration flexibility. When the first chip is a homogeneous memory chip, a large-capacity memory array can be vertically stacked within a very small horizontal area; when the first chip is a hybrid stack of memory and logic control chips, computing and storage units can be tightly coupled and integrated in three-dimensional space, significantly shortening the data access path and reducing transmission latency and power consumption. When the second chip acts as a logic control chip, it can directly form a vertical interconnect with the first chip stacked above, constructing a compact in-memory computing structure; when the second chip acts as an interposer chip, it can adapt to different communication protocols or perform signal shaping, enhancing the interconnect compatibility between the package and external systems. This configurable chip type design allows the same package architecture to cover various application scenarios, from high-bandwidth storage to edge computing, significantly improving the versatility of the technical solution and the convenience of product iteration.

[0078] Furthermore, in this embodiment, the stacked chipset is vertically placed on a horizontal chip or substrate with interconnect points for fixed connection. If necessary, underfill adhesive 12 or MUF can be used to reinforce the mechanical strength.

[0079] Furthermore, to achieve the above objectives, the present invention also provides a method for fabricating a high-heat-dissipation chip stacked semiconductor packaging structure, such as... Figures 5-12 As shown, it includes: S1. Provide a horizontally arranged temporary carrier plate 11, on which a release layer is applied; S2. Multiple first chips 2 are stacked sequentially in the vertical direction on the temporary carrier board 11. Each first chip 2 is parallel to the temporary carrier board 11. During the stacking process, wire bonding (ribbon bonding) is performed to connect one end of the lead 3 to the metal pad on the surface of the corresponding first chip 2, and to extend the other end of the lead 3 to a preset position beyond the edge of the corresponding first chip 2. S3. Form a first molding compound 7 to encapsulate the stacked first chips 2 and leads 3; S4. Remove the temporary carrier board 11 and process the first molding compound 7 to expose the cross-section of the other end of the lead 3 to form a stacked chipset unit; S5. Provide a horizontally arranged load-bearing member 1; S6. The stacked chipset unit is mounted on the carrier 1, with each first chip 2 perpendicular to the carrier 1, and the cross-section of the other end of the exposed lead 3 is electrically connected to the connection point on the carrier 1 through the conductive interconnect structure 4.

[0080] Furthermore, in this embodiment, the lead is cut midway, and after cutting, it must be ensured that: the lead extends beyond the lower edge of the vertically aligned chip; and the lead remains relatively horizontal with respect to the chip. Single-strand, double-strand, or multi-strand wires can be led out from each pad. The wire bonding materials can be different metals (gold / silver / copper, etc., or alloys), and different forms (wire / strip, etc.); the form and materials of the wire bonding connection can be combined, and the spacing is widely adjustable.

[0081] Furthermore, in this embodiment, after the first molding and curing of the stacked chipset, the molded end with the lead output can be de-smeared to clearly expose the metal lead points, and then the temporary carrier board is removed. If necessary, the exposed lead points are surface protected to prevent oxidation.

[0082] Furthermore, in this embodiment, one or more stacked chip groups formed in this manner are vertically placed on a horizontal chip or substrate with interconnect points and fixedly connected. If necessary, the mechanical strength can be reinforced subsequently with underfill 12 or MUF (Molded Underfill).

[0083] MUF stands for Mud-Fill, which forms a basefill simultaneously with the plastic seal. When using MUF, the separate basefill process can be omitted.

[0084] Furthermore, in this embodiment, step S2 above also includes: placing a spacer 6 between adjacent first chips 2.

[0085] Furthermore, in this embodiment, the first molding compound 7 is processed by cutting, grinding or deburring to expose the cross-section of the other end of the lead 3, and the cross-section is subjected to surface anti-oxidation treatment (e.g., chemical gold plating, tin plating or OSP).

[0086] Furthermore, in this embodiment, after mounting the stacked chipset units onto the horizontal support, the method further includes: A second molding process is performed to form a second molding body 8, which covers the bonding area between the stacked chipset units and the horizontal carrier 1.

[0087] Furthermore, in this embodiment, the preparation method further includes: By using a grinding or etching process, the ends of each first chip 2 in the stacked chipset unit away from the horizontal carrier 1 are exposed, and the exposed ends are thermally connected to a heat dissipation device 9.

[0088] According to the above-described fabrication method of the present invention, the stacking and wire bonding are completed on a temporary carrier with the chip lying flat. The entire process utilizes mature wire bonding equipment and processes, eliminating the need to develop specialized equipment for vertical chip bonding. The wires are cut midway and their extension length is controlled. Process parameters can be directly adjusted using existing bonding equipment, reducing equipment modification costs.

[0089] During the wire bonding stage of chip stacking, the leads are required to extend beyond the lower edge of the chip after it is upright and remain relatively horizontal with the chip. This process control ensures that when the chipset is subsequently flipped and mounted upright, the lead ends can accurately reach the plane of the carrier connection point and form effective contact with the connection point. The lead length and direction are precisely set before molding, and the lead shape is completely locked after molding, avoiding the problems of lead suspension, stress deformation, or position drift caused by wire bonding after the chip is upright in traditional processes. Each pad can lead out single or multiple strands of leads, and the flexible combination of lead materials and forms further enhances the adaptability of the connection structure to different current carrying requirements and spatial layouts.

[0090] After the initial molding process, the lead cross-section is exposed through cutting, grinding, and descaling. The exposed cross-section undergoes surface anti-oxidation treatment to ensure the lead end face metal is clean, free of molding compound residue, and free of oxide layer coverage. This series of processes creates a direct, low-impedance metal connection between the lead end face and the conductive interconnect material, preventing increased contact resistance or decreased connection strength due to interface contamination. The connection point size on the carrier is larger than the combined area of ​​the lead cross-section and the conductive interconnect points, compensating for mounting misalignment, reducing reliance on precision alignment equipment, and improving the fault tolerance of the connection points under thermal stress cycling.

[0091] After the stacked chipset is mounted on the carrier, either underfill or integrated molding and underfill materials can be used to reinforce the connection interface. The underfill penetrates around the lead connection points, dispersing thermal expansion mismatch stress and protecting the connection points from shear fatigue. When using an integrated molding and underfill process, the underfill and molding are completed in the same step, simplifying the process and creating a seamless continuum between the chipset bottom and the carrier, eliminating the risk of delamination between the underfill and molding compound. The second molding process completely encapsulates the stacked chipset, the first molding compound, and the carrier bonding area, further solidifying the components into a single rigid body and enhancing the package's vibration and warpage resistance during subsequent surface mounting and system-level assembly.

[0092] This method exposes the ends of the first chips at the top of the stacked chipset through grinding or etching processes, and then thermally connects them to a heat dissipation device. The exposed chip ends directly serve as heat dissipation interfaces, allowing heat to be conducted to the heat dissipation device without passing through the molding compound, thus fully utilizing the inherent high thermal conductivity of the chip material.

[0093] During the fabrication process, spacers can be selectively placed between adjacent first chips. By adjusting the thickness of the spacers, different lead arch height requirements can be accommodated. This allows for compatibility with different chip thicknesses and lead specifications without modifying the chip design or bonding core parameters. The number of chips, lead types, colloid types, interconnect materials, etc., of the stacked chipset can all be flexibly configured within the same process framework. This enables the fabrication method to cover various packaging product requirements, from high-bandwidth storage and in-memory computing to heterogeneous integration, demonstrating good technical versatility and adaptability to product iteration.

[0094] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

[0095] It should be understood that the sequence number of each step in the invention and its embodiments does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A high-heat-dissipation chip stacked semiconductor package structure, characterized in that, include: Horizontally arranged load-bearing components; At least one stacked chipset, comprising: a plurality of first chips stacked sequentially in a horizontal direction, each first chip being perpendicular to the upper surface of the carrier; The surface of each of the first chips in the stacked chipset is provided with metal pads. Each lead has one end connected to one of the metal pads respectively, and the other end of each lead is connected to a connection point on the carrier through a conductive interconnection structure.

2. The high heat dissipation chip stacked semiconductor packaging structure according to claim 1, characterized in that, The adjacent first chips in the stacked chipset are bonded together with an adhesive.

3. The high heat dissipation chip stacked semiconductor packaging structure according to claim 1, characterized in that, The conductive interconnect structure includes at least one of conductive solder balls, conductive adhesive, or nano-metal paste.

4. The high heat dissipation chip stacked semiconductor packaging structure according to claim 1, characterized in that, The stacked chipset further includes a spacer disposed between adjacent first chips.

5. The high heat dissipation chip stacked semiconductor packaging structure according to claim 1, characterized in that, Also includes: A first molding compound covers at least the sidewalls of the stacked chipset; The other end face of each lead is exposed on the bottom surface of the first encapsulation and connected to the connection point on the carrier through the conductive interconnect structure.

6. The high heat dissipation chip stacked semiconductor packaging structure according to claim 5, characterized in that, Also includes: The second molding compound covers at least the bonding area of ​​the stacked chipset, the first molding compound, and the carrier.

7. The high heat dissipation chip stacked semiconductor packaging structure according to claim 1, characterized in that, In the stacked chipset, the end of each first chip away from the carrier is exposed outside the packaging structure and is thermally connected to a heat dissipation device.

8. A method for fabricating a high-heat-dissipation chip stacked semiconductor package structure, characterized in that, include: S1. Provide a horizontally arranged temporary carrier plate; S2. Multiple first chips are stacked sequentially in a vertical direction on the temporary carrier, each first chip being parallel to the temporary carrier. During the stacking process, a wire bonding process is performed to connect one end of the wire to the metal pad on the surface of the corresponding first chip, and to extend the other end of the wire to a preset position beyond the edge of the corresponding first chip before cutting it off. The stacking order is as follows: after the first layer of chips is bonded, the leads are cut, then the second layer of chips is bonded and the leads are cut, and so on. S3. Form a first molding compound to encapsulate the stacked plurality of first chips and the leads; S4. Process the first molding compound to expose the cross-section of the other end of the lead, forming a stacked chipset unit; S5. Provide a horizontally arranged load-bearing component; S6. The stacked chipset unit is mounted on the carrier, such that each of the first chips is perpendicular to the carrier, and the cross-section of the other end of the exposed lead is electrically connected to the connection point on the carrier through a conductive interconnect structure. S7. Secure and cover the bonding area by using a base filler or forming a second sealant.

9. The preparation method according to claim 8, characterized in that, The S2 step also includes: placing a spacer between adjacent first chips.

10. The preparation method according to claim 8, characterized in that, Also includes: By using a grinding or etching process, the ends of each first chip in the stacked chipset unit that are away from the horizontal support are exposed, and the exposed ends are thermally connected to a heat dissipation device.

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