Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The semiconductor structure includes: a dielectric layer on a substrate located on the side of an isolation region; an isolation structure on the substrate of the isolation region; and an interconnect structure located in the dielectric layer of the interconnect region. The interconnect structure includes an interconnect layer and a via interconnect structure located at the bottom of the interconnect layer. The interconnect structure covers the sidewall of the isolation structure, and the sidewalls of the interconnect layer and the via interconnect structure facing the isolation structure are in the same plane. Compared to a scheme where the sidewall of the interconnect layer facing the isolation region protrudes relative to the via interconnect structure and has an end extension, this method ensures that the sidewalls of the interconnect layer and the via interconnect structure facing the isolation region are in the same plane. This helps to reduce the influence of the end morphology of the interconnect layer on the morphology of the via interconnect structure, thereby improving the quality of the via interconnect structure. Simultaneously, this helps to reduce the area occupied by the interconnect layer, correspondingly reducing the chip area and thus improving the chip integration density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In recent years, with the development of integrated circuit technology, the requirements for the integration density of chips in integrated circuits have become increasingly higher, which has led to the continuous shrinking of chip size and the continuous reduction of the linewidth of interconnect structures in back end of line (BEOL) processes.

[0003] The formation of interconnect structures in back-end process technology typically includes the formation of through-hole interconnect structures and interconnect layers, but the performance of interconnect structures and the integration density of chips still need to be improved. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure while increasing the integration density of the chip.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, the substrate including an isolation region and an interconnect region adjacent to the isolation region; a dielectric layer located on the substrate at the side of the isolation region; an isolation structure located on the substrate of the isolation region; and an interconnect structure located in the dielectric layer of the interconnect region, the interconnect structure including an interconnect layer and a via interconnect structure located at the bottom of the interconnect layer, the interconnect structure covering the sidewall of the isolation structure, and the interconnect layer and the via interconnect structure facing the sidewall of the isolation structure being in the same plane.

[0006] This invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a dielectric layer is formed on the substrate, the substrate including a partition region and an interconnect region adjacent to the partition region; forming a partition mask structure located in the partition region in the dielectric layer or on top of the dielectric layer; forming an interconnect opening located on the side of the partition mask structure in the dielectric layer of the interconnect region, the interconnect opening including a trench and a via connected to the bottom of the trench; and forming an interconnect structure in the interconnect opening, including an interconnect layer located in the trench and a via interconnect structure located in the via.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a semiconductor structure, comprising: a substrate including a partition region and an interconnect region adjacent to the partition region; a dielectric layer located on the substrate at the side of the partition region; a partition structure located on the substrate of the partition region; and an interconnect structure located in the dielectric layer of the interconnect region. The interconnect structure includes an interconnect layer and a via interconnect structure located at the bottom of the interconnect layer. The interconnect structure covers the sidewall of the partition structure, and the interconnect layer and the via interconnect structure are coplanar with respect to the sidewall of the partition structure. Compared to solutions where the sidewall of the interconnect layer facing the partition region protrudes relative to the via interconnect structure and has an end extension, this invention ensures that the interconnect layer and the sidewall of the via interconnect structure facing the partition region are coplanar. This improves the impact of the end morphology of the interconnect layer on the morphology of the via interconnect structure, thereby improving the quality of the via interconnect structure. Simultaneously, this reduces the area occupied by the interconnect layer, correspondingly reducing the chip area and thus increasing the chip's integration density.

[0009] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a dielectric layer is formed on the substrate, the substrate including a partition region and an interconnect region adjacent to the partition region; forming a partition mask structure located in the partition region in the dielectric layer or on top of the dielectric layer; forming an interconnect opening located on the side of the partition mask structure in the dielectric layer of the interconnect region, the interconnect opening including a trench and a via connected to the bottom of the trench; and forming an interconnect structure in the interconnect opening, including an interconnect layer located in the trench and a via interconnect structure located in the via. In this embodiment of the invention, a partition mask structure located in the partition region is formed in or on top of the dielectric layer. Therefore, during the formation of interconnect openings, the partition mask structure can act as a self-alignment device, limiting the position of the interconnect openings towards the sidewalls of the partition region. This increases the process window for forming vias and also increases the process window for aligning trenches and vias, ensuring the morphological quality of the vias. Consequently, it improves the formation quality and performance of the interconnect structure, thereby enhancing the performance of the semiconductor structure. Furthermore, compared to solutions where the sidewalls of the interconnect layer facing the partition region protrude relative to the via structure and have end extensions, this method places the sidewalls of the interconnect layer and the via structure facing the partition region on the same plane. This helps to mitigate the influence of the trench end morphology on the via morphology, thereby improving the quality of the via interconnect structure. Simultaneously, this reduces the area occupied by the interconnect layer, correspondingly reducing the chip area and thus improving the chip integration density. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a semiconductor structure.

[0011] Figure 2 yes Figure 1 A sectional view along position AA1;

[0012] Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention;

[0013] Figures 15 to 23 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention;

[0014] Figures 24 to 26 This is a schematic diagram of the structure corresponding to each step in the third embodiment of the semiconductor structure formation method of the present invention;

[0015] Figures 27 to 28 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0016] Figure 29 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0017] Currently, both the performance of semiconductor structures and the integration density of chips need improvement. This paper analyzes the reasons why both the performance of semiconductor structures and the integration density of chips need further improvement, using a schematic diagram of a semiconductor structure as an example. Figure 1 This is a schematic diagram of a semiconductor structure. Figure 2 yes Figure 1 A sectional view along position AA1.

[0018] refer to Figures 1 to 2 The semiconductor structure includes: a substrate (not shown); a dielectric layer 10 located on the substrate; and an interconnect structure 12 located in the dielectric layer 10. The interconnect structure 12 includes an interconnect layer 13 and a via interconnect structure 14 located at the bottom of the interconnect layer 13. In the extending direction of the interconnect layer 13, the sidewall at the end position of the interconnect layer 13 protrudes relative to the via interconnect structure 14, and the protruding portion serves as an end extension 15.

[0019] Research has revealed that during the formation of the semiconductor structure, the interconnect layer 13 is formed in the trench (not shown), and the via interconnect structure 14 is formed in the via (not shown). In order to ensure the normal progress of the etching process for forming the via and to ensure that the material of the via interconnect structure 14 can be properly filled in the via, the sidewall at the end of the interconnect layer 13 protrudes relative to the via interconnect structure 14. The end extension 15 provides sufficient space for the formation of the via interconnect structure 14. Otherwise, the morphology of the via may become abnormal, resulting in void defects in the formed via interconnect structure 14. Consequently, the morphological quality of the via interconnect structure 14 is poor, and the connection between the via interconnect structure 14 and the interconnect layer 13 may fail.

[0020] However, the presence of the end extension 15 significantly reduces the usable area on the substrate, thereby limiting the reduction of the linewidth of the subsequent interconnect layer 13.

[0021] Moreover, the top of the via is connected to the bottom of the trench, and the via is usually near the end of the trench. As the chip size shrinks, the linewidth of the interconnect structure 12 in the subsequent process is also decreasing. During the photolithography process, due to the optical proximity effect, the size of the trench near the end gradually decreases, and the size at the end is the smallest, thus squeezing the formation area of ​​the via.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a dielectric layer is formed on the substrate, the substrate including a partition region and an interconnect region adjacent to the partition region; forming a partition mask structure located in the partition region in the dielectric layer or on top of the dielectric layer; forming an interconnect opening located on the side of the partition mask structure in the dielectric layer of the interconnect region, the interconnect opening including a trench and a via connected to the bottom of the trench; and forming an interconnect structure in the interconnect opening, including an interconnect layer located in the trench and a via interconnect structure located in the via.

[0023] In the scheme disclosed in this embodiment of the invention, an isolation mask structure located in the isolation region is formed in or on top of the dielectric layer. Therefore, during the formation of interconnect openings, the isolation mask structure can play a self-aligning role, limiting the position of the interconnect openings toward the sidewalls of the isolation region, increasing the process window for forming vias, and also increasing the process window for aligning trenches and vias, thus ensuring the morphological quality of the vias, thereby improving the formation quality and performance of the interconnect structure, and thus improving the performance of the semiconductor structure. In addition, compared with the scheme where the sidewalls of the interconnect layer toward the isolation region protrude relative to the via structure and have end extensions, this method makes the sidewalls of the interconnect layer and the via structure toward the isolation region on the same plane, which helps to improve the influence of the end morphology of the trench on the morphology of the via, thereby improving the quality of the via interconnect structure. At the same time, this helps to reduce the area occupied by the interconnect layer, thereby reducing the chip area and improving the chip integration density.

[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figures 3 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0026] refer to Figure 3A substrate (not shown) is provided, on which a dielectric layer 100 is formed, the substrate including a partition region I and an interconnect region II adjacent to the partition region I.

[0027] The substrate serves as a process platform for forming semiconductor structures. Depending on the specific process, the substrate includes a substrate (not shown) and functional structures formed on the substrate, such as semiconductor devices like MOS field-effect transistors, resistor structures, etc.

[0028] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator or germanium-on-insulator.

[0029] The dielectric layer 100 is used to provide space for the subsequent formation of interconnect structures and isolation mask structures, and also to achieve electrical isolation between adjacent interconnect structures.

[0030] Specifically, the dielectric layer 100 is used to provide a process basis for the subsequent formation of interconnect openings, wherein the interconnect openings include trenches and through holes communicating with the bottom of the trenches.

[0031] In this embodiment, the dielectric layer 100 is made of an insulating material, including a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). As an example, the dielectric layer 100 is made of a low-k dielectric material; for example, the dielectric layer 100 may also be made of SiOCH.

[0032] Isolation region I refers to the area where interconnect structures do not need to be formed, that is, the area used to define the isolation between interconnect structures in their extension direction. Specifically, isolation region I is used to achieve isolation between interconnect structures and also to provide formation space for forming isolation mask structures.

[0033] Interconnection region II is used to provide formation space for forming interconnect structures.

[0034] In this embodiment, the step of providing the substrate includes a partition region I and an interconnection region II located on both sides of the partition region I and adjacent to the partition region I.

[0035] It should be noted that the interconnect region II is located on both sides of the partition region I and is adjacent to the partition region I. That is, the partition region I is located between adjacent interconnect regions II. This is beneficial for the partition mask structure formed in the partition region I to separate the adjacent interconnect structures, thereby avoiding the need to use etching process to separate the interconnect structures and reducing the probability of the interconnect structures being damaged.

[0036] It should also be noted that, in the step of providing the substrate, an etch stop layer (not shown) is also formed at the bottom of the dielectric layer 100.

[0037] The dielectric layer 100 is formed on the etch stop layer. During the process of forming vias in the dielectric layer 100, the top surface of the etch stop layer is used to define the etch stop position when etching the dielectric layer 100. That is, the top surface of the etch stop layer is used as the etch stop position first to etch the dielectric layer 100, and then the etch stop layer is etched.

[0038] Continue to refer to Figure 3 In the step of providing the substrate, a hard mask layer 101 is formed on the dielectric layer 100. A mask opening 102 is formed in the hard mask layer 101, which is located in the interconnect region II and the isolation region I and is transversely connected. The portion of the mask opening 102 located in the interconnect region II corresponds to the position of the trench in the interconnect opening.

[0039] Here, "lateral" refers to the arrangement direction parallel to the interconnection region II and the partition region I; "lateral penetration" means that a part of the same mask opening 102 is located in the interconnection region II and the remaining part is located in the partition region I.

[0040] The hard mask layer 101 serves as a mask for forming trenches, and the mask openings 102 define the shape and location of the trenches. As an example, the material of the hard mask layer 101 includes one or more of TiN, WC, Al2O3, SiN, SiON, and SiOC.

[0041] It should be noted that before forming the hard mask layer 101 on the substrate, the formation method further includes forming a pattern definition layer 104 on the substrate. The pattern definition layer 104 is used to improve the adhesion between the hard mask layer 101 and the dielectric layer 100, preventing the hard mask layer 101 from being directly formed on the substrate and causing large stress that could lead to defects or other problems. As an example, the material of the pattern definition layer 104 includes silicon oxide.

[0042] It should be noted that, in this embodiment, a partition mask structure located in the partition region I is subsequently formed in the dielectric layer 100.

[0043] refer to Figures 4 to 6Before forming the isolation mask structure, the method for forming the semiconductor structure further includes: forming a first transversely penetrating opening 105 in the dielectric layer 100 of the interconnect region II and the isolation region I, the first opening 105 being located in a portion of the dielectric layer 100, the portion of the first opening 105 located in the interconnect region II corresponding to the position of a trench or via in the interconnect opening, and the depth of the first opening 105 being less than or equal to a preset depth of the trench.

[0044] The portion of the first opening 105 located in the interconnect region I corresponds to the position of the trench or via in the interconnect opening, which can ensure the accuracy of subsequent interconnect openings formed along the first opening 105.

[0045] The depth of the first opening 105 is less than or equal to the preset depth of the trench, so that the depth of the subsequently formed trench can meet its preset depth.

[0046] When the interconnect opening is formed by forming a trench first, the portion of the first opening 105 located in the interconnect region II corresponds to the position of the trench in the interconnect opening. The depth of the first opening 105 is equal to the preset depth of the trench, and the first opening 105 is the trench in the interconnect opening.

[0047] When an all-in-one (AIO) etching method is used to form interconnect openings, the portion of the first opening 105 located in interconnect region II corresponds to the position of the via in the interconnect opening. The depth of the first opening 105 is less than or equal to the preset depth of the trench, and the first opening 105 is an initial via. It should be noted that the depth of the first opening 105 being less than or equal to the preset depth of the trench mainly depends on the depth relationship between the trench and the via.

[0048] In this embodiment, the interconnect opening is formed by integral etching as an example. Therefore, the portion of the first opening 105 located in the interconnect region II corresponds to the position of the via in the interconnect opening, and the first opening 105 is an initial via. Accordingly, the lateral dimension of the first opening 105 is smaller than the lateral dimension of the mask opening 102.

[0049] Specifically, the steps for forming the first opening 105 include: (Refer to...) Figure 4 A first mask layer 106 having a fourth opening 107 is formed on the hard mask layer 101. The lateral dimension of the fourth opening 107 is smaller than the lateral dimension of the mask opening 102. The first mask layer 106 covers the mask opening 102 (e.g., Figure 3 The fourth opening 107 spans the interconnect region II and the partition region I and exposes a portion of the bottom of the mask opening 102; Reference Figures 5 to 6 Using the first mask layer 106 as a mask, a first opening 105 is formed in the dielectric layer 100 at the bottom of the fourth opening 107 (e.g., ...). Figure 6 As shown), the lateral dimension of the first opening 105 is smaller than the lateral dimension of the mask opening 102; continuing to refer to Figure 6 After forming the first opening 105, the first mask layer 106 is removed.

[0050] The first mask layer 106 is used as a mask to form the first opening 105.

[0051] In this embodiment, the material of the first mask layer 106 may include photoresist.

[0052] refer to Figures 7 to 10 An isolation mask structure 108 located in the isolation region I is formed in the dielectric layer 100 or on top of the dielectric layer 100.

[0053] By forming an isolation mask structure 108 located in the isolation region I, the isolation mask structure 108 can play a self-aligning role during the formation of interconnect openings, thereby limiting the position of the interconnect openings facing the sidewalls of the isolation region I. This increases the process window for forming vias and also increases the process window for aligning trenches and vias, ensuring the morphological quality of the vias and correspondingly improving the formation quality and performance of the interconnect structure, thereby improving the performance of the semiconductor structure. Furthermore, compared to a scheme where the sidewalls of the interconnect layer facing the isolation region protrude relative to the via structure and have end extensions, this method makes the sidewalls of the interconnect layer and the via structure facing the isolation region I on the same plane. This helps to reduce the influence of the end morphology of the trench on the morphology of the via, thereby improving the quality of the via interconnect structure. At the same time, this helps to reduce the area occupied by the interconnect layer, correspondingly reducing the chip area and thus improving the chip integration density.

[0054] In this embodiment, a partition mask structure 108 located in the partition region I is formed in the dielectric layer 100. Forming the partition mask structure 108 in the dielectric layer 100 means that the bottom surface of the partition mask structure 108 is lower than the top surface of the dielectric layer 100. This allows the partition mask structure 108 to better function as a separator for interconnect structures.

[0055] In other embodiments, a partition mask structure located on top of the dielectric layer in the partition region may also be formed. Forming a partition mask structure on top of the dielectric layer means that the partition mask structure protrudes from the top surface of the dielectric layer.

[0056] In this embodiment, since a first transversely penetrating opening 105 is first formed in the dielectric layer 100 of the interconnect region II and the isolation region I, in the step of forming the isolation mask structure 108 located in the isolation region I in the dielectric layer 100, the isolation mask structure 108 located in the isolation region I is formed on the dielectric layer 100 at the bottom of the first opening 105.

[0057] It should be noted that since the isolation mask structure 108 is located on the dielectric layer 100 at the bottom of the first opening 105 and is located in the isolation region I, the isolation mask structure 108 can be located on the side of the interconnect region II, thereby achieving better isolation between interconnect structures.

[0058] Specifically, the steps for forming the partition mask structure 108 include: referencing Figure 7 A second mask layer 109 is formed covering the dielectric layer 100; Reference Figures 7 to 8 An opening 111 is formed in the partition region I, penetrating the second mask layer 109; Reference Figures 9 to 10 A partition mask structure 108 is formed in the partition opening 111.

[0059] The second mask layer 109 provides a process basis for forming the partition opening 111, which provides a spatial location for forming the partition mask structure 108.

[0060] It should also be noted that, compared with the scheme of patterning the material layer after depositing the partition mask structure, in this embodiment, the partition opening 111 is formed first, and then the material of the partition mask structure 108 is filled into the partition opening 111. This helps to reduce the amount of material layer to be removed from the partition mask structure 108, thereby reducing the process difficulty.

[0061] In this embodiment, the material of the second mask layer 109 includes photoresist. Photoresist has high resolution, allowing precise control of the opening size of the isolation opening 111; moreover, using photoresist reduces the complexity of forming the isolation opening 111, and the photoresist is easy to remove, thereby reducing process complexity and improving production efficiency. In other embodiments, the second mask layer may also be made of other materials that can serve as etching masks and are easily removable.

[0062] In this embodiment, the partition opening 111 is also located in or penetrates the dielectric layer 100 of a certain thickness.

[0063] It should be noted that the isolation opening 111 is also located in or through a portion of the dielectric layer 100, which in turn makes the isolation mask structure 108 located in or through a portion of the dielectric layer 100, thereby enabling the isolation mask structure 108 to better function as a separator for interconnection structures.

[0064] Specifically, the step of forming a partition opening 111 penetrating the second mask layer 109 in the partition region I includes: referencing Figure 7 A second opening 110 is formed in the partition region I, penetrating the second mask layer 109; Reference Figure 8 A third opening 120 is formed in the dielectric layer 100 at the bottom of the second opening 110. The third opening 120 is located in or penetrates the dielectric layer 100 of a certain thickness. The connected third opening 120 and the second opening 110 constitute a partition opening 111.

[0065] The second opening 110 is used to define the shape and position of the partition opening 111.

[0066] like Figure 8 As shown, as an example, the third opening 120 is located in a portion of the dielectric layer 100 to reduce the amount of dielectric layer 100 removed, thereby facilitating the formation of interconnect openings in the subsequent process where the material of the via sidewalls is all dielectric layer 100, thus improving the morphological quality of the formed interconnect openings.

[0067] In this embodiment, the process of forming the third opening 120 in the dielectric layer 100 at the bottom of the second opening 110 includes a dry etching process. The dry etching process has anisotropic etching characteristics, and the etching is more directional, which is beneficial to improving the morphology and dimensional accuracy of the isolation opening 111.

[0068] In other embodiments, the partition opening may also penetrate only the second mask layer. Accordingly, the step of forming a partition opening penetrating the second mask layer in the partition region includes: forming a second opening penetrating the second mask layer in the partition region, the second opening serving as the partition opening.

[0069] In this embodiment, the step of forming the partition mask structure 108 in the partition opening 111 includes: referring to Figure 9 The partition opening 111 is filled with a partition mask material 112; Reference Figure 10 Remove a portion of the partition mask material 112 from the partition opening 111, and the remaining partition mask material 112 serves as the partition mask structure 108.

[0070] First, a thicker partition mask material 112 is formed, and then a portion of the height of the partition mask material 112 is removed, which helps to improve the quality and thickness uniformity of the partition mask structure 108.

[0071] Furthermore, by removing a portion of the partition mask material 112 from the partition opening 111, it is beneficial to appropriately reduce the height of the partition mask structure 108, thereby reducing the probability of the partition mask structure 108 collapsing.

[0072] In this embodiment, the process of filling the partition mask material 112 in the partition opening 111 includes one or both of atomic layer deposition and chemical vapor deposition.

[0073] Both atomic layer deposition (ALD) and chemical vapor deposition (CVD) processes have good filling capabilities, which allows the partition mask material 112 to be deposited better in the partition opening 111.

[0074] In this embodiment, the process of removing a portion of the height of the partition mask material 112 in the partition opening 111 includes a dry etching process. The dry etching process has anisotropic etching characteristics, enabling high profile control and pattern transfer accuracy, which is beneficial for ensuring that the morphology and dimensions of the partition mask structure 108 meet process requirements.

[0075] It should be noted that in other embodiments, only the barrier mask material above the top surface of the second mask layer may be removed. As an example, the barrier mask material above the top surface of the second mask layer can be removed by a planarization process (e.g., chemical mechanical polishing).

[0076] In this embodiment, during the step of forming the isolation mask structure 108, the height of the isolation mask structure 108 should not be too high or too low. If the height of the isolation mask structure 108 is too high, the aspect ratio of the isolation mask structure 108 is likely to increase, which may increase the probability of the isolation mask structure 108 collapsing. If the height of the isolation mask structure 108 is too low, during the subsequent process of forming the interconnect opening located on the side of the isolation mask structure 108 in the dielectric layer 100 of the interconnect region II using the hard mask layer 101 and the isolation mask structure 108 together as a mask, the masking effect of the isolation mask structure 108 may be poor, thereby increasing the risk of loss of the dielectric layer 100 in the isolation region I. Therefore, in this embodiment, the height of the isolation mask structure 108 is 200 angstroms to 1500 angstroms.

[0077] In this embodiment, during the step of forming the isolation mask structure 108, the lateral dimension of the isolation mask structure 108 should not be too large or too small along the arrangement direction of the isolation region I and the interconnect region II. If the lateral dimension of the isolation mask structure 108 is too large, the lateral dimension of the subsequent vias will be reduced accordingly, thereby increasing the difficulty of forming through vias and increasing the probability of open circuit problems. If the lateral dimension of the isolation mask structure 108 is too small, the effect of the isolation mask structure 108 in dividing adjacent interconnect structures will be poor. Therefore, in this embodiment, the lateral dimension of the isolation mask structure 108 is 10 nanometers to 100 nanometers along the arrangement direction of the isolation region I and the interconnect region II.

[0078] In this embodiment, in the step of forming the partition mask structure 108 located in the partition region I, in a direction parallel to the substrate and perpendicular to the arrangement direction of the interconnect region II and the partition region I, the width of the partition mask structure 108 is at least equal to the preset width of the trench in the interconnect opening, so that adjacent interconnect openings can be separated by the partition mask structure 108.

[0079] Accordingly, in a direction parallel to the substrate and perpendicular to the arrangement direction of interconnection region II and partition region I, the partition mask structure 108 covers the sidewall of the mask opening 102.

[0080] In this embodiment, the material of the partition mask structure 108 in the step of forming the partition mask structure 108 includes metal oxide.

[0081] Because metal oxides have high mechanical strength and hardness, in the step of forming interconnect openings located on the side of the isolation mask structure 108 in the dielectric layer 100 of the interconnect region II, it is easy to have a high etching selectivity between the dielectric layer 100 and the isolation mask structure 108, so that the isolation mask structure 108 can play a better masking role.

[0082] Specifically, the metal oxide may include one or more of hafnium oxide, titanium oxide, copper oxide, and aluminum oxide.

[0083] Continue to refer to Figure 10 The forming method further includes removing the second mask layer 109.

[0084] The second mask layer 109 is removed in preparation for the subsequent formation of interconnect openings.

[0085] As an example, the second mask layer 109 is removed by an ashing process. In other embodiments, the second mask layer may also be removed by a wet process.

[0086] In this embodiment, in the step of removing a portion of the height of the partition mask material 112 in the partition opening 111, the second mask layer 109 is removed.

[0087] It should be noted that removing a portion of the height of the partition mask material 112 and removing the second mask layer 109 in the same step helps to reduce process steps, improve manufacturing efficiency, and reduce process costs.

[0088] It should also be noted that by removing a portion of the partition mask material 112 in the partition opening 111, it is also beneficial to ensure that the second mask layer 109 on both sides of the partition mask structure 108 is removed simultaneously.

[0089] In other embodiments, the second mask layer may be removed after the partition mask structure is formed.

[0090] refer to Figure 11 An interconnection opening 113 is formed in the dielectric layer 100 of the interconnection region II, located on the side of the isolation mask structure 108. The interconnection opening 113 includes a trench 114 and a through hole 115 communicating with the bottom of the trench 114.

[0091] Interconnect openings 113 provide space for the subsequent formation of interconnect structures. Trench 114 provides space for the subsequent formation of interconnect layers, and via 115 provides space for the subsequent formation of via interconnect structures.

[0092] In this embodiment, the interconnect opening 113 is an opening of a dual damascene structure. Therefore, in the step of forming the interconnect opening 113 located on the side of the isolation mask structure 108 in the dielectric layer 100 of the interconnect region II, the interconnect opening 113 includes a trench 114 and a through hole 115 communicating with the bottom of the trench 114.

[0093] In this embodiment, the interconnect opening 113 is formed by integral etching.

[0094] Specifically, an interconnection opening 113 is formed on the side of the partition mask structure 108 via the first opening 105.

[0095] A portion of the first opening 105 is located in the interconnect region II, and the remaining portion is located in the isolation region I. Compared to the scheme of etching only the interconnect region, this embodiment forms the interconnect opening 113 via the first opening 105. Therefore, when etching the dielectric layer 100, the etching area is increased, thereby increasing the process window for forming the interconnect opening 113. At the same time, the presence of the isolation mask structure 108 ensures that the interconnect opening 113 is formed in the interconnect region II, and not in the isolation region I.

[0096] It should be noted that the first opening 105 is an initial through hole. Correspondingly, using the isolation mask structure 108 as a mask, a trench 114 is formed in the dielectric layer 100 of the interconnect region II. During the formation of the trench 114, the dielectric layer 100 at the bottom of the initial through hole is removed to form a through hole 115 that communicates with the trench 114. The interconnected through hole 115 and the trench 114 constitute an interconnect opening 113.

[0097] Specifically, the hard mask layer 101 and the isolation mask structure 108 are used together as a mask to form an interconnection opening 113 located on the side of the isolation mask structure 108 in the dielectric layer 100 of the interconnection region II.

[0098] It should also be noted that an etch stop layer (not shown) is also formed at the bottom of the dielectric layer 100, therefore, the via 115 also penetrates the etch stop layer.

[0099] In this embodiment, the substrate includes a partition region I and an interconnect region II located on both sides of the partition region I and adjacent to the partition region I. Correspondingly, the interconnect opening 113 is located on both sides of the partition mask structure 108 and is isolated by the partition mask structure 108.

[0100] refer to Figure 12 After forming the interconnect opening 113, the process further includes: removing the hard mask layer 101.

[0101] By removing the hard mask layer 101, the aspect ratio that affects the filling performance of the interconnect material layer during the formation of the interconnect material layer is the aspect ratio of the interconnect opening 113. In other words, the aspect ratio of the space used to form the interconnect material layer is reduced, thereby reducing the difficulty of the subsequent process of filling the interconnect material layer in the interconnect opening 113.

[0102] refer to Figures 13 to 14 An interconnect structure 116 is formed in the interconnect opening 113. The interconnect structure 116 includes an interconnect layer 117 located in the trench 114 and a through-hole interconnect structure 118 located in the through hole 115.

[0103] Interconnect layer 117 is used to implement circuit layout.

[0104] The through-hole interconnect structure 118 is used to connect the interconnect layer 117 and the internal circuitry of the semiconductor structure, thereby realizing the electrical connection between the interconnect layer 117 and the internal circuitry of the semiconductor structure.

[0105] Specifically, the steps of forming the interconnect layer 117 and the via interconnect structure 118 include: referencing Figure 13 An interconnect material layer 119 is formed in the interconnect opening 113; Reference Figure 14 The interconnect material layer 119 is planarized so that the top of the interconnect material layer 119 is flush with the top of the dielectric layer 100. The remaining interconnect material layer 119 in the trench 114 serves as the interconnect layer 117, and the remaining interconnect material layer 119 in the via 115 serves as the via interconnect structure 118.

[0106] It should be noted that when the bottom of the interconnect layer 117 is lower than the bottom of the isolation mask structure 108, the planarization process of the interconnect material layer 119 will make the top of the interconnect material layer 119 flush with the top of the dielectric layer 100.

[0107] The planarization process for the interconnect material layer 119 includes chemical mechanical polishing (CMP). Specifically, CMP combines the advantages of chemical polishing and mechanical polishing, reducing surface undulations and improving device reliability, speed, and yield. It also improves step coverage and removes surface defects. Therefore, it ensures simultaneous and efficient planarization of the interconnect material layer 119, resulting in a superior interconnect structure 116 surface.

[0108] In other embodiments, during the planarization process of the interconnect material layer, the top of the interconnect material layer may be made flush with the top of the partition mask structure.

[0109] It should be noted that, in this embodiment, the top of the interconnect material layer 119 is flush with the top of the dielectric layer 100. Therefore, the remaining dielectric layer 100 located in the partition region I serves as a partition structure.

[0110] Figures 15 to 23 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention.

[0111] The similarities between this embodiment and the first embodiment will not be repeated here. The difference between this embodiment and the first embodiment is that the portion of the first opening 205 located in the interconnect region ii corresponds to the position of the trench 206 in the interconnect opening (e.g., ...). Figure 16 (As shown).

[0112] Specifically, the first opening 205 is a trench 206 in the interconnect opening.

[0113] It should be noted that before forming the isolation mask structure 208, a trench 206 that is laterally connected in the interconnect region ii and the isolation region i is first formed. Then, the subsequent interconnect layer 215 is automatically separated by the isolation mask structure 208. At the same time, the isolation mask structure 208 can be used as a mask to form a through hole 209 on the side of the isolation mask structure 208, thereby saving photomask.

[0114] The steps for forming the trench 206, the partition mask structure 208, and the through hole 209 are described in detail below with reference to the accompanying drawings.

[0115] refer to Figure 15 In the step of providing the substrate, a hard mask layer 201 is formed on the dielectric layer 200. A mask opening 202 is formed in the hard mask layer 201, which is located in the interconnect region ii and the isolation region i and is transversely connected. The portion of the mask opening 202 located in the interconnect region ii corresponds to the position of the trench in the interconnect opening.

[0116] For a detailed description of the substrate, dielectric layer 200, hard mask layer 201, and mask opening 202, please refer to the relevant content of the first embodiment, which will not be repeated here.

[0117] refer to Figure 16 Using the hard mask layer 201 as a mask, the dielectric layer 200 is etched along the mask opening 202 to form a first transversely penetrating opening 205 in the dielectric layer 200 of the interconnect region ii and the isolation region i. The first opening 205 is located in a portion of the dielectric layer 200, and the portion of the first opening 205 located in the interconnect region ii corresponds to the position of the trench in the interconnect opening.

[0118] Specifically, the first opening 205 is a trench 206 in the interconnect opening, and the trench 206 is used to provide spatial location for subsequent interconnect layers.

[0119] Reference Figures 17 to 19 An isolation mask structure 208 located in the isolation region i is formed on the dielectric layer 200 at the bottom of the first opening 205.

[0120] If the isolation mask structure 208 is located in the isolation region i, then after etching the dielectric layer 200 at the bottom of the first opening 205 using the isolation mask structure 208 as a mask, a through hole located on the side of the isolation mask structure 208 can be formed.

[0121] Specifically, refer to Figure 17A second mask layer 203 is formed to cover the dielectric layer 200, and an isolation opening 207 is formed in the isolation region i that penetrates the second mask layer 203.

[0122] In this embodiment, the step of forming a partition opening 207 penetrating the second mask layer 203 in the partition region i includes: forming a second opening 204 penetrating the second mask layer 203 in the partition region i, the projection of the second opening 204 on the dielectric layer 200 being located in a first opening 205 (i.e., a trench 206); forming a third opening 213 in the dielectric layer 200 at the bottom of the second opening 204, the third opening 213 being located in or penetrating a portion of the thickness of the dielectric layer 200, the connected third opening 213 and the second opening 204 constituting the partition opening 207.

[0123] For a detailed description of the second mask layer 203, the second opening 204, the third opening 213 and the partition opening 207, please refer to the relevant content in the first embodiment, which will not be repeated here.

[0124] In other embodiments, the partition opening may also penetrate only the second mask layer. Accordingly, the step of forming a partition opening penetrating the second mask layer in the partition region includes: forming a second opening penetrating the second mask layer in the partition region, the second opening serving as the partition opening.

[0125] refer to Figures 18 to 19 A partition mask structure 208 is formed in the partition opening 207.

[0126] Specifically, the step of forming the partition mask structure 208 in the partition opening 207 includes: referring to Figure 18 The partition opening 207 is filled with partition mask material 211; Reference Figure 19 Remove a portion of the partition mask material 211 from the partition opening 207, and the remaining partition mask material 211 serves as the partition mask structure 208.

[0127] For a detailed description of the step of forming the partition mask structure 208 in the partition opening 207, please refer to the relevant content of the first embodiment, which will not be repeated here.

[0128] Continue to refer to Figure 19 The forming method further includes: removing the second mask layer 203.

[0129] Specifically, the second mask layer 203 is removed to prepare for the subsequent formation of vias.

[0130] In this embodiment, in the step of removing a portion of the partition mask material 211 in the partition opening 207, the second mask layer 203 is removed, which helps to reduce process steps, improve manufacturing efficiency, and reduce process costs.

[0131] In other embodiments, the second mask layer may be removed after the partition mask structure is formed.

[0132] refer to Figures 20 to 21 Using the isolation mask structure 208 as a mask, a through hole 209 is formed in the dielectric layer 200 at the bottom of the trench 206, and the interconnected through hole 209 and the trench 206 constitute an interconnection opening 210.

[0133] Specifically, the step of forming a through-hole 209 in the dielectric layer 200 at the bottom of the first opening 205 (i.e., trench 206) using the isolation mask structure 208 as a mask includes: referencing Figure 20 A first mask layer 212 with a fourth opening (not shown) is formed on the hard mask layer 201. The lateral dimension of the fourth opening is smaller than the lateral dimension of the mask opening 202. The first mask layer 212 covers the sidewalls of the mask opening 202 and the sidewalls of the first opening 205. The fourth opening spans the interconnect region ii and the partition region i and exposes a portion of the bottom of the first opening 205 and the partition mask structure 208. (Reference) Figure 21 Using the first mask layer 212 and the isolation mask structure 208 together as a mask, the dielectric layer 200 is patterned, and a through hole 209 located on the side of the isolation mask structure 208 is formed in the dielectric layer 200.

[0134] It should be noted that, under the blocking effect of the partition mask structure 208, even if the fourth opening exposes the partition mask structure 208, the through hole 209 can still be formed on the side of the partition mask structure 208.

[0135] As an example, the interconnection area ii is located on both sides of the partition area i, therefore, the through hole 209 is located on the side of the partition mask structure 208.

[0136] In this embodiment, after forming the through hole 209, the method further includes: removing the first mask layer 212.

[0137] For a detailed description of the through hole 209 and the interconnection opening 210, please refer to the relevant content of the foregoing embodiments, which will not be repeated here.

[0138] refer to Figures 22 to 23 An interconnect structure 214 is formed in the interconnect opening 210. The interconnect structure 214 includes an interconnect layer 215 located in the trench 206 and a through-hole interconnect structure 216 located in the through hole 209.

[0139] Specifically, the steps of forming the interconnect layer 215 and the via interconnect structure 216 include: referencing Figure 22 An interconnect material layer 217 is formed in the interconnect opening 210; Reference Figure 23 The interconnect material layer 217 is planarized so that the top of the interconnect material layer 217 is flush with the top of the isolation mask structure 208. The remaining interconnect material layer 217 in the trench 206 serves as the interconnect layer 215, and the remaining interconnect material layer 217 in the via 209 serves as the via interconnect structure 216.

[0140] It should be noted that when the bottom of the trench 206 is higher than the bottom of the partition mask structure 208, the planarization process of the interconnect material layer 217 will make the top of the interconnect material layer 217 flush with the top of the partition mask structure 208.

[0141] For a detailed description of the interconnect structure 214 formed in the interconnect opening 210, please refer to the relevant content of the first embodiment, which will not be repeated here.

[0142] In other embodiments, during the planarization process of the interconnect material layer, the top of the interconnect material layer may be made flush with the top of the dielectric layer.

[0143] It should be noted that, in this embodiment, the top of the interconnect material layer 217 is flush with the top of the isolation mask structure 208. Therefore, the remaining dielectric layer 200 and the isolation mask structure 208 located in the isolation region i serve as the isolation structure.

[0144] It should also be noted that in both the first and second embodiments, the isolation mask structure is formed after a first transversely penetrating opening is formed in the dielectric layer of the interconnect region and the isolation region. In other embodiments, the isolation mask structure can also be pre-embedded in the dielectric layer of the isolation region before forming the first opening. As an example, after the pre-embedded isolation mask structure is formed in the dielectric layer of the isolation region, the top of the isolation mask structure can be flush with the top of the isolation mask structure. As another example, the top of the isolation mask structure can also be higher than the top of the isolation mask structure.

[0145] Figures 24 to 26 This is a schematic diagram of the structure corresponding to each step in the third embodiment of the semiconductor structure formation method of the present invention.

[0146] The difference between this embodiment and the previous embodiment is that a partition mask structure 308 located in the partition region i' is formed on top of the dielectric layer 300.

[0147] The steps for forming the partition mask structure 308 and the interconnection opening 309 are described in detail below with reference to the accompanying drawings.

[0148] refer to Figure 24 In the step of providing a substrate (not shown), a hard mask layer 301 is formed on the dielectric layer 300. A mask opening 302 is formed in the hard mask layer 301, which is located in the interconnect region ii' and the isolation region i' and is transversely connected. The portion of the mask opening 302 located in the interconnect region ii' corresponds to the position of the trench in the subsequently formed interconnect opening.

[0149] refer to Figure 25 A second mask layer 303 is formed to cover the dielectric layer 300, and an isolation opening 304 is formed in the isolation region i' that penetrates the second mask layer 303. The projection of the isolation opening 304 on the dielectric layer 300 is located in the mask opening 302.

[0150] It should be noted that in this embodiment, the isolation opening 304 only penetrates the second mask layer 303.

[0151] refer to Figure 26 A partition mask structure 308 is formed in the partition opening 304.

[0152] For a detailed description of the partition mask structure 308 formed in the partition opening 304, please refer to the relevant content of the foregoing embodiments, which will not be repeated here.

[0153] Continue to refer to Figure 26 In this embodiment, the step of forming the partition mask structure 308 further includes: removing the second mask layer 303.

[0154] In other embodiments, the second mask layer may be removed after the partition mask structure is formed.

[0155] Subsequently, the hard mask layer 301 and the isolation mask structure 308 can be used together as a mask to form an interconnection opening located on the side of the isolation mask structure 308 in the dielectric layer 300 of the interconnection region ii'.

[0156] Taking the formation of interconnect openings using an integrated etching method as an example, the steps for forming the interconnect openings include: forming a first mask layer (not shown) with a fourth opening (not shown) on the hard mask layer 301, wherein the lateral dimension of the fourth opening is smaller than the lateral dimension of the mask opening 302, the first mask layer covers the sidewall of the mask opening 302, the fourth opening spans the interconnect region ii' and the isolation region i' and exposes part of the bottom of the mask opening 302 and the isolation mask structure 308; using the patterned first mask layer as a mask, on the fourth... An initial via (not shown) is formed in the dielectric layer 300 at the bottom of the opening; after the initial via is formed, the first mask layer is removed; after the first mask layer is removed, the hard mask layer 301 and the isolation mask structure 308 are used together as a mask to form a trench (not shown) in the dielectric layer 300 of the interconnect region ii', and during the formation of the trench, the dielectric layer 300 at the bottom of the initial via is removed to form a via (not shown) connected to the trench, and the connected via and the trench constitute an interconnect opening (not shown).

[0157] It is understood that in other embodiments, interconnect openings may also be formed by first forming trenches.

[0158] For a detailed description of the specific steps involved in forming the interconnect openings and the interconnect structures within those openings, please refer to the relevant content in the foregoing embodiments; they will not be repeated here.

[0159] Accordingly, the present invention also provides a semiconductor structure. Figures 27 to 29 This is a schematic diagram of the semiconductor structure according to an embodiment of the present invention, wherein, Figure 27 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 28 yes Figure 27 sectional view, Figure 29 This is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0160] refer to Figures 27 to 29 The semiconductor structure includes: a substrate (not shown), the substrate including a partition region I' and an interconnect region II' adjacent to the partition region I'; a dielectric layer 500 located on the substrate on the side of the partition region I'; a partition structure 501 located on the substrate of the partition region I'; and an interconnect structure 502 located in the dielectric layer 500 of the interconnect region II', the interconnect structure 502 including an interconnect layer 503 and a via interconnect structure 504 located at the bottom of the interconnect layer 503, the interconnect structure 502 covering the sidewall of the partition structure 501, and the interconnect layer 503 and the via interconnect structure 504 facing the sidewall of the partition structure 501 are in the same plane.

[0161] It should be noted that, compared to the design where the sidewall of the interconnect layer facing the isolation region protrudes relative to the via interconnect structure and has an end extension, this method makes the sidewalls of the interconnect layer 503 and the via interconnect structure 504 facing the isolation region I' in the same plane. This helps to reduce the influence of the end morphology of the interconnect layer 503 on the morphology of the via interconnect structure 504, thereby improving the quality of the via interconnect structure 504. At the same time, this helps to reduce the area occupied by the interconnect layer 503, thereby reducing the chip area and improving the chip integration density.

[0162] The substrate serves as a process platform for forming semiconductor structures. Depending on the specific process, the substrate includes a substrate (not shown) and functional structures formed on the substrate, such as semiconductor devices like MOS field-effect transistors, resistor structures, etc.

[0163] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator or germanium-on-insulator.

[0164] The dielectric layer 500 provides spatial location for forming the interconnect structure 502 and the isolation structure 501, and also provides electrical isolation between adjacent interconnect structures 502. In this embodiment, the dielectric layer 500 is made of an insulating material, including a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6). As an example, the dielectric layer 500 is made of a low-k dielectric material; for example, the dielectric layer 500 may also be made of SiOCH.

[0165] In this embodiment, the substrate includes a partition region I' and an interconnect region II' adjacent to the partition region I'.

[0166] The isolation region I' refers to the area where the interconnect structure 502 does not need to be formed, that is, the area used to define the isolation between the interconnect structures 502 in their extension direction. Specifically, the isolation region I' is used to achieve isolation between the interconnect structures 502, and also to provide forming space for the formation of the isolation structure 501.

[0167] Interconnection region II' is used to provide forming space for forming interconnection structure 502.

[0168] In this embodiment, the interconnect region II' is located on both sides of the partition region I' and is adjacent to the partition region I'. That is, the partition region I' is located between adjacent interconnect regions II'. This is beneficial for the partition structure 501 formed in the partition region I' to separate the adjacent interconnect structures 502, thereby avoiding the need to use etching process to separate the interconnect structures 502, and thus reducing the probability of the interconnect structures 502 being damaged.

[0169] The partition structure 501 is used to better separate the interconnect structure 502.

[0170] In this embodiment, the width of the partition structure 501 is equal to the width of the interconnect layer 503 in a direction parallel to the substrate and perpendicular to the arrangement direction of the interconnect region II' and the partition region I'.

[0171] It should be noted that the width of the partition structure 501 is at least equal to the width of the interconnect layer 503, which helps to better separate adjacent interconnect structures 502.

[0172] In one embodiment, reference Figure 28 The dielectric layer 500 is also located on the substrate of the partition region I' and serves as the partition structure 501, that is, the top of the interconnect layer 503 is flush with the top of the dielectric layer 500 located in the partition region I'.

[0173] In other embodiments, reference is made to... Figure 29 The dielectric layer 500 is also located on the substrate of the partition region I', and the top of the dielectric layer 500 in the partition region I' is lower than the top of the dielectric layers 500 in the remaining regions. Specifically, the partition structure 501 includes a dielectric layer 500 located on the substrate of the partition region I', and a partition mask structure 602 located on the dielectric layer 500 of the partition region I', that is, the top of the interconnect layer 503 is flush with the top of the partition mask structure 602.

[0174] It should be noted that the interconnect structure 502 is formed in the interconnect opening, and the interconnect opening includes a trench for accommodating the interconnect layer 503 and a through hole for accommodating the via interconnect structure 504. During the formation of the interconnect opening, the isolation mask structure 602 located in the isolation region I' can play a self-aligning role to limit the position of the interconnect opening toward the sidewall of the isolation region I', thereby increasing the process window for forming the through hole and also increasing the process window for aligning the trench and the through hole, and ensuring the morphological quality of the through hole, thereby improving the formation quality and performance of the interconnect structure 502. Accordingly, this method makes the sidewall of the interconnect layer 503 and the through hole interconnect structure 504 facing the isolation region I' lie on the same plane.

[0175] Specifically, when the bottom of the interconnect layer 503 is higher than the bottom of the partition mask structure 602, the material of the interconnect layer 503 is planarized so that the top of the interconnect layer is flush with the top of the partition mask structure 602.

[0176] In this embodiment, the material of the isolation mask structure 602 includes metal oxide. Because metal oxide has high mechanical strength and hardness, in the process of forming the interconnect structure 502 located on the side of the isolation mask structure 602 in the dielectric layer 500 of the interconnect region II', it is easy to achieve a high etching selectivity between the dielectric layer 500 and the isolation mask structure 602, thereby enabling the isolation mask structure 602 to function effectively as a mask.

[0177] In this embodiment, along the arrangement direction of the partition region I' and the interconnect region II', the lateral dimension of the partition mask structure 602 should not be too large or too small. The via interconnect structure 504 is formed in the via. If the lateral dimension of the partition mask structure 602 is too large, the lateral dimension of the via is likely to decrease, increasing the difficulty of forming a through-hole and thus increasing the probability of open circuit problems. If the lateral dimension of the partition mask structure 602 is too small, the partition mask structure 602 may not effectively divide adjacent interconnect structures 502. Therefore, in this embodiment, along the arrangement direction of the partition region I' and the interconnect region II', the lateral dimension of the partition mask structure 602 is 10 nanometers to 100 nanometers.

[0178] In other embodiments, depending on actual process requirements, the partition structure may also be a partition mask structure that penetrates the dielectric layer.

[0179] Interconnect structure 502 is used to achieve electrical connection with the internal circuitry of the semiconductor structure. In this embodiment, the interconnect structure 502 is a double damask structure, and the interconnect structure 502 includes an interconnect layer 503 and a via interconnect structure 504 located at the bottom of the interconnect layer 503.

[0180] Interconnect layer 503 is used to implement circuit layout. Through-hole interconnect structure 504 is used to connect interconnect layer 503 and internal circuitry of semiconductor structure, thereby realizing electrical connection between interconnect layer 503 and internal circuitry of semiconductor structure.

[0181] In this embodiment, the interconnection region II' is located on both sides of the isolation region I' and is adjacent to the isolation region I'. Correspondingly, the interconnection structure 502 is located on both sides of the isolation mask structure 602 and is isolated through the isolation mask structure 602.

[0182] It should be noted that the semiconductor structure of the present invention can be formed by any of the formation methods of the foregoing embodiments, or by other formation methods.

[0183] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: A substrate, the substrate including a partition region and an interconnect region adjacent to the partition region; A dielectric layer is located on a substrate on the side of the partition area; A partition structure is located on the base of the partition area; An interconnect structure is located in the dielectric layer of the interconnect region. The interconnect structure includes an interconnect layer and a via interconnect structure located at the bottom of the interconnect layer. The interconnect structure covers the sidewall of the partition structure, and the interconnect layer and the via interconnect structure are in the same plane facing the sidewall of the partition structure.

2. The semiconductor structure of claim 1, wherein, In a direction parallel to the substrate and perpendicular to the arrangement direction of the interconnect and partition regions, the width of the partition structure is equal to the width of the interconnect layer.

3. The semiconductor structure of claim 1, wherein, The dielectric layer is also located on the substrate of the partition area and serves as the partition structure; or, The dielectric layer is also located on the substrate of the partition region, and the top of the dielectric layer in the partition region is lower than the top of the dielectric layer in the other regions; the partition structure includes a dielectric layer located on the substrate of the partition region and a partition mask structure located on the dielectric layer of the partition region; or, The partition structure is a partition mask structure that penetrates the dielectric layer.

4. The semiconductor structure of claim 3, wherein, The material of the partition mask structure includes metal oxides.

5. The semiconductor structure of claim 3, wherein, Along the arrangement direction of the partition region and the interconnect region, the lateral dimension of the partition mask structure is 10 nanometers to 100 nanometers.

6. The semiconductor structure of claim 3, wherein, The substrate includes a partition area and an interconnection area located on both sides of the partition area and adjacent to the partition area; The interconnect structure is located on both sides of the isolation mask structure and is isolated by the isolation mask structure.

7. A method of forming a semiconductor structure, characterized by, include: A substrate is provided on which a dielectric layer is formed, the substrate including a partition region and an interconnect region adjacent to the partition region; A partition mask structure located in the partition region is formed in the dielectric layer or on top of the dielectric layer; An interconnect opening is formed in the dielectric layer of the interconnect region, located on the side of the isolation mask structure. The interconnect opening includes a trench and a through hole communicating with the bottom of the trench. An interconnect structure is formed in the interconnect opening, including an interconnect layer located in the trench and a through-hole interconnect structure located in the through hole.

8. The method of forming a semiconductor structure of claim 7, wherein, In the case where a partition mask structure located in the partition region is formed in the dielectric layer, before forming the partition mask structure, the method for forming the semiconductor structure further includes: forming a first laterally through opening in the dielectric layer of the interconnect region and the partition region, the first opening being located in a dielectric layer of a certain thickness, the portion of the first opening located in the interconnect region corresponding to the position of a trench or via in the interconnect opening, and the depth of the first opening being less than or equal to a preset depth of the trench; In the step of forming the isolation mask structure in the dielectric layer, an isolation mask structure located in the isolation region is formed on the dielectric layer at the bottom of the first opening; An interconnection opening is formed on the side of the partition mask structure via the first opening.

9. The method of forming a semiconductor structure of claim 8, wherein, The first opening is a trench in the interconnection opening, and the depth of the first opening is equal to the preset depth of the trench; Using the isolation mask structure as a mask, through holes are formed in the dielectric layer at the bottom of the trench, and the interconnected through holes and the trench constitute interconnecting openings; or, The first opening is an initial through hole, and the depth of the first opening is less than or equal to the preset depth of the trench; Using the isolation mask structure as a mask, a trench is formed in the dielectric layer of the interconnect region. During the formation of the trench, the dielectric layer at the bottom of the initial via is removed to form a via that communicates with the trench. The communicating via and the trench constitute an interconnect opening.

10. The method of forming a semiconductor structure according to one of claims 7 to 9, wherein The steps for forming the partition mask structure include: A second mask layer is formed to cover the dielectric layer; An opening penetrating the second mask layer is formed in the partition area; A partition mask structure is formed in the partition opening; The formation method further includes: removing the second mask layer.

11. The method of forming a semiconductor structure of claim 10, wherein, The step of forming a partition opening penetrating the second mask layer in the partition area includes: forming a second opening penetrating the second mask layer in the partition area, the second opening serving as a partition opening; or, The step of forming a partition opening penetrating the second mask layer in the partition region includes: forming a second opening penetrating the second mask layer in the partition region; forming a third opening in the dielectric layer at the bottom of the second opening, the third opening being located in or penetrating the dielectric layer of a portion of its thickness, the connected third opening and the second opening constituting a partition opening.

12. The method of forming a semiconductor structure of claim 11, wherein, The process of forming the third opening in the dielectric layer at the bottom of the second opening includes a dry etching process.

13. The method of forming a semiconductor structure of claim 10, wherein, The step of forming a partition mask structure in the partition opening includes: The partition opening is filled with a partition mask material; Remove a portion of the partition mask material from the partition opening, leaving the remaining partition mask material as the partition mask structure.

14. The method of forming a semiconductor structure of claim 13, wherein, In the step of removing a portion of the partition mask material at the partition opening, the second mask layer is removed; Alternatively, after forming the isolation mask structure, the method may further include: removing the second mask layer.

15. The method of forming a semiconductor structure of claim 13, wherein, The process of filling the partition opening with a partition mask material includes one or both of atomic layer deposition and chemical vapor deposition processes.

16. The method of forming a semiconductor structure of claim 13, wherein, The process for removing a portion of the partition mask material from the partition opening includes a dry etching process.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the second mask layer includes photoresist.

18. The method for forming a semiconductor structure as described in any one of claims 8 to 9, characterized in that, In the step of providing the substrate, a hard mask layer is formed on the dielectric layer, and a mask opening that is laterally through the interconnect region and the isolation region is formed in the hard mask layer. The portion of the mask opening in the interconnect region corresponds to the position of the trench in the interconnect opening. In the step of forming the partition mask structure located in the partition area, the partition mask structure covers the sidewall of the mask opening in a direction parallel to the substrate and perpendicular to the arrangement direction of the interconnect area and the partition area. Using the hard mask layer and the isolation mask structure together as a mask, an interconnection opening located on the side of the isolation mask structure is formed in the dielectric layer of the interconnection region.

19. The method of forming a semiconductor structure of claim 18, wherein, When the location of the first opening in the interconnect region corresponds to the location of the via in the interconnect opening, the step of forming the first opening includes: forming a first mask layer having a fourth opening on the hard mask layer, the first mask layer covering the sidewall of the mask opening, the fourth opening spanning the interconnect region and the partition region and exposing a portion of the bottom of the mask opening; using the first mask layer as a mask, forming the first opening in the dielectric layer at the bottom of the fourth opening; and removing the first mask layer after forming the first opening. or, When the portion of the first opening located in the interconnect region corresponds to the position of the trench in the interconnect opening, the step of forming the via includes: forming a first mask layer having a fourth opening on the hard mask layer, the first mask layer covering the sidewall of the mask opening and the sidewall of the first opening, the fourth opening spanning the interconnect region and the partition region and exposing a portion of the bottom of the first opening and the partition mask structure; patterning the dielectric layer using the first mask layer and the partition mask structure together as a mask, forming a via located on the side of the partition mask structure in the dielectric layer; and removing the first mask layer after forming the via.

20. The method for forming a semiconductor structure according to any one of claims 7 to 9, characterized in that, The steps of forming the interconnect layer and via interconnect structure include: forming an interconnect material layer in the interconnect opening; The interconnect material layer is planarized so that the top of the interconnect material layer is flush with the top of the dielectric layer or the top of the isolation mask structure. The remaining interconnect material layer in the trench serves as the interconnect layer, and the remaining interconnect material layer in the via serves as the via interconnect structure.

21. The method of forming a semiconductor structure of claim 20, wherein, The planarization process for the interconnect material layer includes chemical mechanical polishing.

22. The method of forming a semiconductor structure of claim 7, wherein, In the step of forming the partition mask structure, the height of the partition mask structure is 200 angstroms to 1500 angstroms.

23. The method of forming a semiconductor structure of claim 7, wherein, In the step of forming the isolation mask structure on the dielectric layer, the material of the isolation mask structure includes metal oxides.

24. The method of forming a semiconductor structure of claim 7, wherein, In the step of providing a substrate, the substrate includes a partition region and an interconnection region located on both sides of the partition region and adjacent to the partition region; In the step of forming the interconnection opening, the interconnection opening is located on both sides of the isolation mask structure and is isolated by the isolation mask structure.

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