Intermediate structures and their manufacturing methods, packaging structures, electronic devices

Abstract

This disclosure provides an intermediary structure, its manufacturing method, packaging structure, and electronic device. The intermediary structure is used for interconnecting an optical chip and an electrical chip, and includes: a carrier board having a first surface and a second surface opposite to each other, and the first surface having a groove; a plurality of metal pillars penetrating the carrier board; an embedded waveguide located within the first surface of the carrier board and having a predetermined distance from the first surface of the carrier board, and located on one side of the groove; a first interconnection structure located above the second surface of the carrier board, with a first end of the first interconnection structure connected to a metal pillar and a second end of the first interconnection structure connected to an electrical chip; and a second interconnection structure located within the groove, with a first end of the second interconnection structure connected to a metal pillar and a second end of the second interconnection structure connected to an optical chip; wherein the optical chip is optically coupled to the embedded waveguide. Using the above technical solution can improve the signal integrity of the optoelectronic interconnection and enhance the quality and performance of the optoelectronic interconnection structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to an interposer structure and its manufacturing method, a packaging structure, and an electronic device. Background Technology

[0002] In the field of semiconductor packaging, with the continuous development of integrated circuit technology, advanced packaging technology has become a key path to perpetuate Moore's Law and improve chip system performance. Among them, co-packaging optical technology, because it can integrate photonic integrated circuits and electronic integrated circuits in the same package, realizes short-distance, low-loss interconnection of photoelectric signals, thereby significantly improving system bandwidth density and energy efficiency, and has become an important development direction in data centers, high-performance computing and other fields.

[0003] However, in traditional optoelectronic interconnect structures, optical modules and electrical chips are usually laid out separately, resulting in excessively long electrical interconnect paths, high signal loss, and high power consumption. At the same time, the coupling between optical chips and waveguides is easily affected by temperature fluctuations, causing mode-field mismatch and reduced coupling efficiency. In addition, the surface silver precipitation phenomenon in the traditional ion-exchange waveguide fabrication process also introduces additional light absorption loss, which restricts the further improvement of overall optoelectronic interconnect performance.

[0004] Therefore, how to enable the intermediary structure to improve the signal integrity of optoelectronic interconnects and enhance the quality and performance of optoelectronic interconnect structures has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the technical problem solved by the embodiments of this disclosure is to provide an intermediate structure and its manufacturing method, packaging structure and electronic device, which can improve the signal integrity of optoelectronic interconnects and improve the quality and performance of optoelectronic interconnect structures.

[0006] This disclosure provides an intermediary structure for interconnecting an optical chip and an electrical chip, comprising: a carrier plate having a first surface and a second surface opposite to each other, and the first surface having a groove; a plurality of metal pillars penetrating the carrier plate; an embedded waveguide located within the first surface of the carrier plate and having a predetermined distance from the first surface of the carrier plate, and located on one side of the groove; a first interconnection structure located above the second surface of the carrier plate, with a first end of the first interconnection structure connected to the metal pillars and a second end of the first interconnection structure connected to the electrical chip; and a second interconnection structure located within the groove, with a first end of the second interconnection structure connected to the metal pillars and a second end of the second interconnection structure connected to the optical chip; wherein the optical chip is optically coupled to the embedded waveguide.

[0007] Optionally, the embedded waveguide is a silver-containing ion-exchange waveguide, and the carrier plate contains sodium ions; the intermediate structure further includes a potassium ion layer located above the embedded waveguide and flush with the carrier plate; wherein the embedded waveguide is formed by the diffusion of silver ions through the potassium ion layer and the exchange of silver ions with sodium ions below the potassium ion layer.

[0008] Optionally, the intermediate structure satisfies one or more of the following: the material of the carrier plate includes borosilicate glass; the preset spacing is the thickness of the potassium ion layer.

[0009] Optionally, the embedded waveguide is a silver-containing ion-exchange waveguide; the intermediate structure further includes a silicon nitride waveguide, the first end of which is optically coupled to the optical chip, and the projection of the second end of the silicon nitride waveguide on the first surface of the carrier overlaps with the projection of the embedded waveguide on the first surface of the carrier, so as to achieve optical coupling with the embedded waveguide.

[0010] Optionally, the first interconnect structure includes: a first wiring layer located above a second surface of the carrier board and connected to the metal pillar; a first ball grid array located above the first wiring layer and coupled to the first wiring layer; wherein the electrical chip is connected to the first ball grid array.

[0011] Optionally, the first interconnect structure further includes: a first intermediate wiring layer, located above the first wiring layer and connected to the first ball grid array and the first wiring layer.

[0012] Optionally, the second interconnect structure includes: a second wiring layer located above the bottom of the groove and connected to the metal pillar; a second ball grid array located above the second wiring layer and coupled to the second wiring layer; wherein the optical chip is connected to the second ball grid array.

[0013] Optionally, the second interconnect structure further includes: a second intermediate wiring layer, located above the second wiring layer and connected to the second ball grid array and the second wiring layer.

[0014] Optionally, the intermediary structure further includes a third interconnection structure located in the non-grooved region of the first surface of the carrier plate and connected to the metal pillar.

[0015] Optionally, the third interconnect structure includes: a third wiring layer located in the non-recessed area of ​​the first surface of the carrier board and connected to the metal pillar; and a third ball grid array located above the third wiring layer and connected to the third wiring layer.

[0016] Optionally, the metal pillar includes: a first metal pillar that penetrates the carrier plate and has one end located at the bottom of the groove, connecting the first interconnect structure and the second interconnect structure; and a second metal pillar that penetrates the carrier plate and has one end located in the non-groove area of ​​the first surface of the carrier plate, connecting the first interconnect structure and the third interconnect structure.

[0017] Optionally, the second interconnect structure includes: a second wiring layer located above the bottom of the groove and connected to the metal pillar; a second ball grid array located above the second wiring layer and coupled to the second wiring layer; wherein the optical chip is connected to the second ball grid array; the intermediary structure further includes: an insulating dielectric layer covering part or all of the first and second surfaces of the carrier board, and in contact with the first interconnect structure and the second interconnect structure, and exposing the first ball grid array and the second ball grid array.

[0018] Optionally, the embedded waveguide is a silver-containing ion-exchange waveguide; the intermediate structure further includes a silicon nitride waveguide, the first end of which is located on the top surface of the insulating dielectric layer; wherein, the first end of the optical chip covers the first end of the silicon nitride waveguide and is optically coupled to the silicon nitride waveguide.

[0019] Optionally, the top surface of the insulating dielectric layer is flush with the surface of the first side of the carrier plate.

[0020] Optionally, the insulating dielectric layer satisfies one or more of the following: the insulating dielectric layer is a multilayer dielectric layer; the material of the insulating dielectric layer includes at least one of benzocyclobutene, epoxy resin, polyimide, or silicon dioxide. This disclosure also provides a method for manufacturing an interposer structure for interconnecting an optical chip and an electrical chip, comprising: providing a carrier plate having opposing first and second surfaces, and the first surface having a groove; forming a plurality of metal pillars penetrating the carrier plate; forming a first interconnect structure located above the second surface of the carrier plate, a first end of the first interconnect structure connected to the metal pillar, and a second end of the first interconnect structure connected to the electrical chip; forming a second interconnect structure located within the groove, a first end of the second interconnect structure connected to the metal pillar, and a second end of the second interconnect structure connected to the optical chip; forming a buried waveguide located within the first surface of the carrier plate and having a predetermined distance from the first surface of the carrier plate, and located on one side of the groove; wherein the optical chip is optically coupled to the buried waveguide.

[0021] Optionally, the step of forming the embedded waveguide includes: forming a mask on a first surface of the substrate, in a region near the groove; patterning the mask to form an ion exchange channel; forming a potassium ion layer on the surface of the substrate at the ion exchange channel, the top surface of the potassium ion layer being flush with the substrate; and forming an embedded waveguide below the potassium ion layer; wherein the substrate contains sodium ions, and the embedded waveguide is formed by silver ions diffusing through the potassium ion layer and exchanging with sodium ions below the potassium ion layer.

[0022] Optionally, the method satisfies one or more of the following: the mask is an aluminum mask; the carrier material includes borosilicate glass; the potassium ion layer is formed by thermal ion exchange; and the preset spacing is the thickness of the potassium ion layer.

[0023] Optionally, the step of forming the first interconnect structure includes: forming a first wiring layer above a second surface of the carrier board, the first wiring layer being connected to the metal pillar; forming a first ball grid array above the first wiring layer, the first ball grid array being coupled to the first wiring layer; wherein the electrical chip is connected to the first ball grid array.

[0024] Optionally, the step of forming the first interconnect structure further includes: forming a first intermediate wiring layer, the first intermediate wiring layer being located above the first wiring layer and connected to the first ball grid array and the first wiring layer.

[0025] Optionally, the step of forming the second interconnect structure includes: forming a second wiring layer above the bottom of the groove, the second wiring layer being connected to the metal pillar; forming a second ball grid array above the second wiring layer, the second ball grid array being coupled to the second wiring layer; wherein the optical chip is connected to the second ball grid array.

[0026] Optionally, the step of forming the second interconnect structure further includes: forming a second intermediate wiring layer, wherein the second intermediate wiring layer is located above the second wiring layer and is connected to the second ball grid array and the second wiring layer.

[0027] Optionally, a first wiring layer is formed above the second surface of the carrier plate, and the first wiring layer is connected to the metal pillar; wherein the first wiring layer and the second wiring layer are formed in the same step.

[0028] Optionally, the method further includes: forming a third interconnect structure, the third interconnect structure being located in a non-groove region on a first surface of the carrier plate and connected to the metal pillar; wherein the third interconnect structure includes: a third wiring layer, located in a non-groove region on the first surface of the carrier plate and connected to the metal pillar; and a third ball grid array, located above the third wiring layer and connected to the third wiring layer.

[0029] Optionally, the method further includes: forming an insulating dielectric layer that covers part or all of the first and second surfaces of the carrier plate, and contacts the first interconnect structure and the second interconnect structure, and exposes the first ball grid array and the second ball grid array.

[0030] Optionally, the method further includes: forming a silicon nitride waveguide, wherein a first end of the silicon nitride waveguide is located on the top surface of the insulating dielectric layer, and a second end of the silicon nitride waveguide is located above the embedded waveguide; wherein a first end of the optical chip covers the first end of the silicon nitride waveguide and is optically coupled to the silicon nitride waveguide, and the top surface of the insulating dielectric layer is flush with the surface of the first side of the carrier.

[0031] This disclosure also provides a packaging structure, including the intermediary structure described in any of the above embodiments.

[0032] This disclosure also provides an electronic device including any of the intermediary structures described above.

[0033] Compared with the prior art, the technical solution of the present disclosure has the following advantages: The intermediate structure provided in this embodiment includes: a carrier plate having a first surface and a second surface opposite to each other, and the first surface having a groove; a first interconnect structure located above the second surface of the carrier plate and connected to an electrical chip; a second interconnect structure located within the groove and connected to an optical chip; the first interconnect structure and the second interconnect structure are connected by a metal pillar penetrating the carrier plate, and the optical chip is optically coupled to the embedded waveguide. This invention constructs a vertically integrated optoelectronic interconnect architecture by placing the optical chip within the groove on the first surface of the carrier plate and directly optically coupling it to the embedded waveguide, while simultaneously arranging the electrical chip on the second surface of the carrier plate and achieving electrical interconnection with the optical chip through the first interconnect structure and the metal pillar. The groove provides physical positioning and installation space for the optical chip, which is beneficial for increasing bandwidth density. This allows the second interconnect structure to be directly and closely connected to the metal pillar penetrating the carrier plate in the vertical direction, thereby compressing the electrical signal transmission path between the optical chip and the electrical chip to the shortest possible length, significantly reducing the delay, parasitic effects, and energy loss of high-speed electrical signal transmission. The electrical chip is interconnected with the optical chip through a first interconnect structure and metal pillars, forming a vertical power supply and signal channel from the electrical chip to the optical chip. This avoids long-distance planar wiring, and the compact layout of "lateral coupling of optical signals and vertical transmission of electrical signals" can improve the integration of the optical chip and the electrical chip. Therefore, the intermediary structure can improve the signal integrity of the optoelectronic interconnect and enhance the quality and performance of the optoelectronic interconnect structure. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments disclosed in this specification, the drawings used in the description of the embodiments disclosed in this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of a method for manufacturing an intermediate structure according to an embodiment of the present disclosure; Figures 2 to 16 This is a cross-sectional schematic diagram of some steps in a method for manufacturing an intermediate structure according to an embodiment of the present disclosure; Figures 17 to 21 This is a cross-sectional schematic diagram of some steps in the manufacturing method of an embedded waveguide according to an embodiment of this disclosure. Figure 22 This is a schematic diagram of a waveguide connection according to an embodiment of the present disclosure. Detailed Implementation

[0036] The technical solutions of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings. The embodiments described herein are specific implementations of the present invention and are used to illustrate the concept of the present invention. These descriptions are explanatory and exemplary and should not be construed as limiting the implementation of the present invention or the scope of protection of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.

[0037] It should be noted that the accompanying drawings in this embodiment are schematic diagrams, used to illustrate the concept of the invention and to schematically show the shapes of the various parts and their interrelationships. It should be understood that, in order to clearly show the structure of the various components of the invention, the drawings are not drawn to the same scale, and the same reference numerals are used to indicate the same parts in the drawings.

[0038] As described in the background section, in the field of semiconductor packaging, with the continuous development of integrated circuit technology, advanced packaging technology has become a key path to extend Moore's Law and improve chip system performance. Among them, co-packaging optical technology, because it can integrate photonic integrated circuits and electronic integrated circuits in the same package, realizes short-distance, low-loss interconnection of photoelectric signals, thereby significantly improving system bandwidth density and energy efficiency, and has become an important development direction in fields such as data centers and high-performance computing.

[0039] However, in traditional optoelectronic interconnect structures, optical modules and electrical chips are usually laid out separately, resulting in excessively long electrical interconnect paths, high signal loss, and high power consumption. At the same time, the coupling between optical chips and waveguides is easily affected by temperature fluctuations, causing mode-field mismatch and reduced coupling efficiency. In addition, the surface silver precipitation phenomenon in the traditional ion-exchange waveguide fabrication process also introduces additional light absorption loss, which restricts the further improvement of overall optoelectronic interconnect performance.

[0040] Therefore, how to enable the intermediary structure to improve the signal integrity of optoelectronic interconnects and enhance the quality and performance of optoelectronic interconnect structures has become an urgent technical problem to be solved.

[0041] The intermediate structure provided in this embodiment includes: a carrier plate having a first surface and a second surface opposite to each other, and the first surface having a groove; a first interconnect structure located above the second surface of the carrier plate and connected to an electrical chip; a second interconnect structure located within the groove and connected to an optical chip; the first interconnect structure and the second interconnect structure are connected by a metal pillar penetrating the carrier plate, and the optical chip is optically coupled to the embedded waveguide. This invention constructs a vertically integrated optoelectronic interconnect architecture by placing the optical chip within the groove on the first surface of the carrier plate and directly optically coupling it to the embedded waveguide, while simultaneously arranging the electrical chip on the second surface of the carrier plate and achieving electrical interconnection with the optical chip through the first interconnect structure and the metal pillar. The groove provides physical positioning and installation space for the optical chip, which is beneficial for increasing bandwidth density. This allows the second interconnect structure to be directly and closely connected to the metal pillar penetrating the carrier plate in the vertical direction, thereby compressing the electrical signal transmission path between the optical chip and the electrical chip to the shortest possible length, significantly reducing the delay, parasitic effects, and energy loss of high-speed electrical signal transmission. The electrical chip is interconnected with the optical chip through a first interconnect structure and metal pillars, forming a vertical power supply and signal channel from the electrical chip to the optical chip. This avoids long-distance planar wiring, and the compact layout of "lateral coupling of optical signals and vertical transmission of electrical signals" can improve the integration of the optical chip and the electrical chip. Therefore, the intermediary structure can improve the signal integrity of the optoelectronic interconnect and enhance the quality and performance of the optoelectronic interconnect structure.

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be clearly and completely illustrated below with reference to the accompanying drawings.

[0043] See Figure 1 , Figure 1 This is a flowchart of a method for manufacturing an intermediate structure according to an embodiment of the present disclosure.

[0044] The method can be performed by steps S101 to S105.

[0045] In step S101, a carrier plate is provided, the carrier plate having opposing first and second surfaces, and the first surface having a groove.

[0046] In step S102, a plurality of metal pillars are formed penetrating the carrier plate.

[0047] In step S103, a first interconnect structure is formed. The first interconnect structure is located above the second surface of the carrier board. The first end of the first interconnect structure is connected to the metal pillar, and the second end of the first interconnect structure is connected to the electrical chip.

[0048] In step S104, a second interconnect structure is formed. The second interconnect structure is located in the groove. The first end of the second interconnect structure is connected to the metal pillar, and the second end of the second interconnect structure is connected to the optical chip.

[0049] In step S105, an embedded waveguide is formed. The embedded waveguide is located within the first surface of the carrier plate and has a preset distance from the first surface of the carrier plate, and is located on one side of the groove.

[0050] The following is for reference only. Figures 2 to 22 The above methods will be explained.

[0051] Reference Figures 2 to 16 , Figures 2 to 16 This is a cross-sectional schematic diagram of some steps in a method for manufacturing an intermediate structure according to an embodiment of the present disclosure.

[0052] See Figure 2 Provides a carrier board 200.

[0053] The carrier plate 200 has opposing first surfaces 201 and second surfaces 202, as shown in the figure as an upper and lower surface. Specifically, the lower surface is the first surface 201 of the carrier plate 200, which has a groove 203. The upper surface is the second surface 202 of the carrier plate 200.

[0054] The carrier plate 200 is made of glass.

[0055] Specifically, the carrier 200 is preferably made of borosilicate glass, whose coefficient of thermal expansion can be adjusted by adjusting the composition to match the silicon chip (including optical and electrical chips) within a range (e.g., 2.5-4.5 ppm / ℃). This effectively alleviates packaging warpage and interface stress problems caused by thermal mismatch when integrating heterogeneous chips, ensuring the long-term mechanical stability and thermal reliability of the intermediate structure. The glass carrier has extremely high transmittance (typically >90%) in the optical communication band (e.g., 1550 nm), providing an ideal transparent medium environment for low-loss transmission of optical signals through the subsequently formed embedded waveguide. In addition, the excellent electrical insulation, extremely low dielectric loss, and low crosstalk characteristics of the glass carrier create a high-purity electrical channel for the transmission of high-speed electrical signals in the metal pillars and interconnect structures, fundamentally supporting the high signal integrity, low power consumption, and high bandwidth potential of the final optoelectronic interconnect structure.

[0056] The carrier plate 200 contains sodium ions.

[0057] The carrier plate 200 needs to contain a certain amount of migratable sodium ions (e.g., in the form of sodium oxide, with a content of approximately 8.8 wt%), which is a necessary prerequisite for the subsequent formation of an embedded waveguide through a specific thermal ion exchange process. Sodium ions, as an exchange matrix, can selectively exchange with externally introduced potassium or silver ions in a high-temperature molten salt environment, thereby forming a waveguide region with a higher refractive index below the surface of the carrier plate 200 without significantly affecting the surface smoothness and chemical stability of the carrier plate 200. The content, distribution, and activity of sodium ions in the carrier plate 200 directly affect the depth and rate of ion exchange and the optical properties of the formed waveguide (such as mode field diameter and transmission loss). Those skilled in the art can adjust these parameters as needed, and this should not constitute a limitation of this disclosure.

[0058] The formation process of the groove 203 can be one or a combination of laser-induced deep etching, dry etching or wet etching, photolithography, etc.

[0059] Specifically, for example, the substrate 200 can be irradiated with a laser of a specific wavelength (e.g., 1064 nm) to modify it, and then the modified area can be selectively removed by chemical etching (e.g., using a diluted HF solution) to form a groove with precise depth and sidewall morphology.

[0060] The groove 203 structurally serves as a mounting cavity for the optical chip, providing precise physical positioning, mechanical support, and a thermal interface. This allows the active surface of the optical chip (the side with optical devices such as grating couplers and electrical pads) to be precisely aligned with the embedded waveguide and second interconnect structure on the substrate surface. The depth of the groove 203 is designed so that the top surface of the mounted optical chip is approximately coplanar with the surface of the non-groove area of ​​the substrate or at a predetermined relative height. This facilitates the planarization of the subsequent overall structure, dielectric layer filling, and the formation of other interconnect structures, ultimately optimizing the overall size of the package, thermal management performance, and signal transmission path.

[0061] In some embodiments, the lower surface is a first surface 201 of the carrier 200, and the first surface 201 has a groove 203. The upper surface is a second surface 202 of the carrier 200, and the second surface 202 also has a groove 203 (not shown). This allows the intermediary structure to freely select whether the second surface 202 of the carrier 200 is close to or far from the external circuit. In other words, the intermediary structure can freely select whether the optical chip on the second surface 202 of the carrier 200 is close to or far from the external circuit.

[0062] See Figure 3 This forms a through hole 204 that penetrates the carrier plate 200.

[0063] The through hole 204 penetrates the carrier plate 200. One end of a portion of the through hole 204 is located on the first surface 201 of the carrier plate 200, and the other end is located on the second surface 202 of the carrier plate 200. Another portion of the through hole 204 has one end located at the bottom of the groove 203 on the first surface 201 of the carrier plate 200, and the other end is located on the second surface 202 of the carrier plate 200.

[0064] The through-hole 204 can be formed by a combination of one or more processes such as laser ablation, photolithography, wet etching, or dry etching.

[0065] Specifically, a laser beam with a wavelength of approximately 1064 nm can be focused onto the surface of the carrier plate 200. By controlling the laser energy density, scanning speed, and number of pulses, a through-hole pattern can be formed on the carrier plate 200. Subsequently, the carrier plate 200 is immersed in or sprayed with a suitable etching solution (e.g., a 5% HF solution) and etched under controlled temperature (e.g., 40°C) and pressure (e.g., a spray pressure of 3 kg / cm²) to remove the laser-modified material, thereby forming a through-hole 204 extending from the first surface 201 to the second surface 202. After the through-hole is formed, a cleaning step is usually required, such as ultrasonic cleaning with NaOH solution and ultrapure water, to remove etching residues and ensure the cleanliness of the inner wall of the through-hole. The through-hole 204 provides the necessary space for the subsequent formation of a metal pillar penetrating the carrier plate 200.

[0066] See Figure 4 , forming a metal column material layer 210a.

[0067] The metal column material layer 210a fills the through hole 204 and covers the first surface 201, the second surface 202, and the sidewalls and bottom of the groove 203 of the carrier plate 200.

[0068] The process of forming the metal pillar material layer 210a may include seed layer deposition and electroplating filling.

[0069] Specifically, a conductive seed layer (not shown in the figure), such as a Ti / Cu composite layer or titanium nitride, tantalum nitride, etc., is first deposited on the first surface 201, the second surface 202, the inner surface of the groove 203, and the inner wall surface of the through hole 204 of the carrier plate 200 by methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The seed layer is used to provide a conductive path and enhance the adhesion between the subsequent electroplated metal and the carrier plate.

[0070] On the seed layer, the through-holes 204 are filled by electroplating, and the metal pillar material layer 210a is formed on the surface of the carrier plate 200 (including the first surface 201, the second surface 202, and the interior of the groove 203). Specifically, the electroplating process can use an acidic copper sulfate electrolyte, performed under appropriate current density. The electroplating time can be controlled according to the required metal thickness, for example, 60 minutes, to form a sufficiently thick metal pillar material layer 210a to ensure complete filling of the through-holes 204. After electroplating, annealing can be performed to improve the crystal quality and mechanical properties of the metal and reduce internal stress.

[0071] The metal material of the metal pillar material layer 210a is preferably copper, due to its good electrical and thermal conductivity and mature process compatibility. Those skilled in the art may also select other conductive metals or alloys, such as one or more combinations of aluminum, gold, silver, nickel, tungsten, ruthenium, and cobalt, depending on the actual situation.

[0072] The metal column material layer 210a provides a material basis for the subsequent formation of the metal column.

[0073] See Figure 5 Multiple metal pillars 210 are formed.

[0074] The metal column 210 penetrates the carrier plate 200.

[0075] The metal pillar 210 includes: The first metal pillar 211 penetrates the carrier plate 200, with one end located at the bottom of the groove; The second metal pillar 212 penetrates the carrier plate, with one end located in the non-groove area of ​​the first surface of the carrier plate.

[0076] Specifically, one or more of the following processes are employed: grinding, chemical mechanical polishing, photolithography, dry etching, wet etching, and flash etching. The surface of the structure is comprehensively planarized, and the metal pillar material layer 210a and seed layer on the surface of the carrier plate 200 (including the first surface 201, the second surface 202, and the groove 203) are precisely removed. This ensures that the top surface of each metal pillar 210 is flat and at the same height as the corresponding area of ​​the carrier plate 200. The formed metal pillars 210 penetrate the carrier plate 200, creating a vertical electrical interconnection structure within the carrier plate, providing a physical channel for high-density three-dimensional electrical signal and power transmission.

[0077] The first metal pillar 211 penetrates the carrier plate 200, with one end located at the bottom of the groove 203 and the other end located at the second surface 202 of the carrier plate 200. In subsequent process flows, the end of the first metal pillar 211 located at the bottom of the groove 203 will be electrically connected to a second interconnect structure (such as a second wiring layer) formed within the groove 203. The first metal pillar 211 can establish a vertical electrical path from the second surface 202 of the carrier plate 200 to the optical chip within the groove 203, enabling direct, short-distance transmission of high-speed electrical signals, control signals, and power from the electronic integrated circuit to the photonic integrated circuit (PIC), thereby effectively reducing signal delay, crosstalk, and power consumption.

[0078] The second metal pillar 212 penetrates the carrier plate 200, with one end located in a non-grooved region (i.e., a flat region) of the first surface 201 of the carrier plate 200. In subsequent processes, the end located in the non-grooved region of the first surface 201 of the carrier plate 200 can be used to connect a third interconnect structure that may be formed in that region. The second metal pillar 212 can serve as an additional interconnect channel, and its functions may include, but are not limited to: providing additional power or ground paths for electrical chips, optical chips, or other devices located on the second surface 202 of the carrier plate, transmitting auxiliary signals, or serving as part of structural support and heat dissipation enhancement.

[0079] It should be noted that the distinction between the first metal pillar 211 and the second metal pillar 212 is based on their different functions. The first metal pillar 211 is mainly used for subsequent vertical interconnection between the optical chip and the electrical chip, while the second metal pillar 212 is mainly used for subsequent connection between the optical chip or electrical chip and the third interconnection structure. In actual intermediate structure design, the number, specific layout (e.g., array arrangement), cross-sectional shape (e.g., circular, rectangular), and dimensions (e.g., diameter, spacing) of the metal pillars 210 can be optimized and adjusted according to specific optoelectronic interconnection requirements, signal integrity requirements, power distribution network (PDN) design, and thermal management schemes. For example, metal pillars used for transmitting high-speed signals may require specific impedance control designs, while metal pillars used for power / grounding may require a larger cross-sectional area to reduce resistance.

[0080] The metal pillar 210 enables ultra-short-distance three-dimensional interconnection. By vertically connecting through the carrier board 200, the electrical path between the electrical chip and the optical chip located on both sides of the carrier board 200 is compressed to the shortest possible length, thereby avoiding the signal attenuation, increased latency, and increased power consumption problems caused by long-distance planar wiring in traditional solutions.

[0081] The metal pillars 210 improve signal integrity and bandwidth. Short, direct vertical paths significantly reduce parasitic inductance and capacitance in interconnects, helping to maintain the quality of high-speed signals and supporting higher data rates. The high-density array of metal pillars enables high-bandwidth-density interconnects.

[0082] The metal pillars 210 optimize power distribution and thermal management. The metal pillars 210 (especially high thermal conductivity copper pillars) not only provide electrical connections but also serve as effective vertical heat channels, helping to conduct and dissipate heat generated by optical or electrical chips more evenly. Properly planned power and grounding metal pillars contribute to the construction of low-impedance, low-noise power transmission networks.

[0083] The metal pillars 210 enhance structural integration and reliability. The combination of the metal pillars 210 and the carrier plate 200 provides reliable mechanical interconnection, helps alleviate stress caused by differences in the coefficients of thermal expansion of materials, and improves the mechanical stability and long-term reliability of the entire packaging structure.

[0084] See also Figure 6 and Figure 7 This forms the first layer of metal interconnects.

[0085] The first layer of metal wiring is a metal wiring layer located on the surface of the carrier plate 200 (including the first surface 201, the second surface 202 and the groove 203).

[0086] The first layer of metal interconnects includes a first wiring layer 221, a second wiring layer 231, and a third wiring layer 241.

[0087] The first layer of metal interconnects (first wiring layer 221, second wiring layer 231, and third wiring layer 241) forms the basis for the subsequent formation of multi-layer interconnect structures (such as the first interconnect structure, the second interconnect structure, and the third interconnect structure).

[0088] On the surface of the substrate 200 after planarization (i.e., in a flat state with the top of the metal pillars 210 exposed), a sacrificial dielectric layer, such as a polyimide (PI) layer, is formed by chemical vapor deposition (CVD) or spin coating, as an insulating layer for subsequent metal wiring and / or as a hard mask 205. Subsequently, a continuous conductive seed layer (not shown separately in the figure), such as a Ti / Cu composite layer or titanium nitride, tantalum nitride, etc., is formed on the sacrificial dielectric layer by physical vapor deposition (PVD).

[0089] Photoresist is coated onto the seed layer, and the pattern of the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241 is defined by photolithography (exposure and development). Then, an electroplating process, such as copper plating, is performed to selectively grow metal in the uncovered areas of the seed layer, forming a metal wiring pattern of a certain thickness. After electroplating, the photoresist is removed, and excess seed layer not covered by the electroplated metal is removed by etching (wet or dry etching), thereby obtaining the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241, which are isolated from each other and have a predetermined pattern. Finally, the sacrificial dielectric layer serving as a hard mask can optionally be removed, or it can be retained as part of the interlayer dielectric.

[0090] The first wiring layer 221 is formed above the second surface 202 of the carrier board 200. The first wiring layer 221 is electrically connected to the metal pillars 210 (particularly at their ends on the second surface 202) through its patterned traces. The first wiring layer 221 constitutes the bottom wiring network of the subsequent first interconnect structure, which can redistribute and transmit electrical signals from the metal pillars 210 in the plane, and prepare for connection to the upper solder ball array (such as the first ball grid array).

[0091] A second wiring layer 231 is formed above the bottom of the recess 203. The second wiring layer 231 is also electrically connected to the end of the first metal pillar 211 located at the bottom of the recess 203 via its patterned traces. The second wiring layer 231 constitutes the bottom wiring network of the subsequent second interconnect structure, allowing vertical electrical signals from the first metal pillar 211 to be routed within the plane of the recess 203 to match the pad layout of the optical chip to be subsequently mounted within the recess 203, and providing an interface for the solder ball array (such as a second ball grid array) connecting the optical chip.

[0092] The third wiring layer 241 is formed in a non-recessed (flat) region of the first surface 201 of the carrier board 200. The third wiring layer 241 is electrically connected to the end of the second metal pillar 212 located in this region. The third wiring layer 241 constitutes the bottom wiring portion of the third interconnect structure and can be used to provide additional power / ground planes, signal wiring, or connect other external circuits or devices located on the first surface 201 of the carrier board. The external circuit can be a separate "external circuit board" or "external carrier board." It can be a carrier and / or interconnect platform for the package in the next level of system integration, such as a printed circuit board, but the external circuit system is not limited to this and may also include ceramic carriers, flexible circuit boards, or other forms of interconnect carriers.

[0093] It should be noted that the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241 can be formed simultaneously in the same set of process steps. This helps to simplify the process, reduce costs, and ensure alignment accuracy between the wiring layers. The line width, line spacing, and thickness of the wiring layers can be optimized according to electrical performance (such as resistance, current carrying capacity, and impedance control) and process capabilities.

[0094] In some embodiments, the first wiring layer 221, the second wiring layer 231 and the third wiring layer 241 may be formed sequentially in different process steps to fulfill their respective different requirements.

[0095] In some embodiments, the metal pillar material layer 210a can be patterned to obtain the metal pillar 210, the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241. This approach simplifies the process flow, reduces manufacturing costs, and, by eliminating the heterogeneous interfaces between the metal pillar 210 and the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241, helps to reduce contact resistance and improve interconnect accuracy and electrical performance.

[0096] See also Figures 8 to 10 This forms metal bumps.

[0097] The metal bumps are located on the surfaces of the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241, and are electrically connected to each wiring layer.

[0098] The metal bumps include a first metal bump 222, a second metal bump 232, and a third metal bump 242.

[0099] The metal bumps are used for connection to subsequent interconnect layers or ball grid arrays.

[0100] Specifically, a sacrificial dielectric layer 206 (e.g., polyimide PI or silicon oxide) is deposited on the surfaces of the formed first wiring layer 221, second wiring layer 231, and third wiring layer 241. Contact holes are patterned in the sacrificial dielectric layer 206 using photolithography and etching processes to expose predetermined connection point regions on the underlying wiring layer. A conductive seed layer (e.g., Ti / Cu) is sputtered onto the surface of the dielectric layer and within the contact holes using physical vapor deposition (PVD). Subsequently, photoresist is applied, and the patterns of the first metal bump 222, second metal bump 232, and third metal bump 242 are defined using photolithography. Then, an electroplating process (e.g., copper plating) is performed to fill the patterned areas with metal, forming metal bumps with a certain thickness and raised structure. After electroplating, the photoresist is removed, and excess seed layer not covered by the electroplated metal is removed using etching. Finally, planarization can be selectively performed to control the height of the bumps or to retain their raised morphology.

[0101] The metal bumps serve as a transition structure between the bottom layer wiring and the upper layer interconnects, ensuring a low-resistance, high-mechanical-strength connection. Their thickness and shape can be designed to compensate for microscopic unevenness on the substrate surface or wiring layer, providing a good coplanarity basis for subsequent chip mounting or ball placement.

[0102] See Figure 11 This forms the first insulating dielectric layer 251.

[0103] The first insulating dielectric layer 251 covers part or all of the first surface 201 and the second surface 202 of the carrier plate 200.

[0104] The first insulating dielectric layer 251 is in contact with the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241. The first insulating dielectric layer 251 covers the sidewalls and part of the top of the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241.

[0105] The first insulating dielectric layer 251 is in contact with the first metal bump 222, the second metal bump 232, and the third metal bump 242. In other words, the first insulating dielectric layer 251 covers the sidewalls of the first metal bump 222, the second metal bump 232, and the third metal bump 242, and exposes the top surfaces of the first metal bump 222, the second metal bump 232, and the third metal bump 242.

[0106] The material of the first insulating dielectric layer 251 includes at least one of benzocyclobutene, epoxy resin, polyimide, or silicon dioxide. In this embodiment, the material of the first insulating dielectric layer 251 is silicon dioxide.

[0107] Specifically, a silicon dioxide thin film is conformally deposited on the first surface 201 and the second surface 202 of the carrier substrate 200, as well as on the structural surfaces covering the formed metal wiring layers (221, 231, 241) and metal bumps (222, 232, 242), using chemical vapor deposition processes such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). The deposition process is carried out under precisely controlled temperature, pressure, and reactive gas (such as silane and oxygen) ratios to ensure that the film has good uniformity, density, and good adhesion to the underlying materials (glass, metal). After the silicon dioxide layer is deposited, a planarization process is required to precisely control the dielectric layer thickness and expose the top surface of the metal bumps, providing a highly flat surface for subsequent photolithography, metal deposition, or ball-mounting processes.

[0108] Silica possesses extremely high resistivity and dielectric strength, providing excellent electrical isolation for high-density metal wiring and effectively preventing signal crosstalk and short circuits. Its chemical stability, good compatibility with glass substrates and metal materials, and low interface defects ensure long-term reliability.

[0109] See Figure 12 This forms a second layer of metal interconnects.

[0110] The second layer of metal interconnect is located on the first layer of metal interconnect, and the second layer of metal interconnect is located in a direction away from the carrier plate 200 of the first layer of metal interconnect.

[0111] The second layer of metal wiring is electrically connected to the first metal bump 222 and the second metal bump 232.

[0112] The second layer of metal interconnects includes: a first intermediate wiring layer 223 and a second intermediate wiring layer 233.

[0113] A first intermediate wiring layer is formed, which is located above the first wiring layer and connected to the first wiring layer.

[0114] A second intermediate wiring layer is formed, which is located above the second wiring layer and connected to the second wiring layer.

[0115] The specific formation processes of the first intermediate wiring layer 223 and the second intermediate wiring layer 233 can refer to the aforementioned preparation steps of the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241. The core processes also include sacrificial dielectric layer deposition and patterning, seed layer deposition, photoresist coating and patterning, electroplating to form metal wires, and subsequent etching and planarization. Those skilled in the art, based on the aforementioned disclosure, can directly and without doubt implement the preparation of the intermediate wiring layers; for the sake of brevity, the process details will not be repeated here.

[0116] The first intermediate wiring layer 223, based on the signal redistribution and power network refinement from the first wiring layer 221 to the upper-layer electrical or optical chip connection interface, has its top layer pattern specifically designed to precisely match the pad layout of the subsequent first ball grid array. It gathers and guides electrical signals and power / ground signals from the lower wiring layer to predetermined positions, providing process space for subsequent ball placement on the surface of the first intermediate wiring layer 223 to form the first ball grid array connecting the electrical or optical chips, or serving as a direct metallization pad.

[0117] The second intermediate wiring layer 233, while completing the fine-tuning of the interconnection path from the second wiring layer 231 to the optical chip or electrical chip (such as impedance tuning and channel isolation), also has its surface pattern configured to correspond to the pad layout of the subsequent second ball grid array. It accurately directs control signals, drive power, etc., to the predetermined pad positions, thereby preparing the interface for the formation of the second ball grid array connecting the optical chip or electrical chip on the second intermediate wiring layer 233 within the recess 203.

[0118] See also Figure 13 and Figure 16 A ball grid array is formed to obtain a first interconnect structure 220, a second interconnect structure 230, and a third interconnect structure 240.

[0119] The ball grid array includes: a first ball grid array 224, a second ball grid array 234, and a third ball grid array 243.

[0120] The first ball grid mesh array 224, the second ball grid mesh array 234, and the third ball grid mesh array 243 can be formed using the same process, such as ball placement or solder bumping followed by reflow. Alternatively, different processes or materials (such as solder alloys with different melting points, copper pillar bumps, etc.) can be used depending on the different connected objects (chip type, spacing, reliability requirements).

[0121] A first ball grid array 224 is formed above the first wiring layer 221. The first ball grid array 224 is coupled to the first wiring layer 221, and the first intermediate wiring layer 223 is electrically connected to the first ball grid array 224. The electrical chip can be connected to the first ball grid array 224.

[0122] In some embodiments, the optical chip may also be connected to the first ball grid array 224.

[0123] A second ball grid array 234 is formed above the second wiring layer 231. The second ball grid array 234 is coupled to the second wiring layer 231, and the second intermediate wiring layer 233 is electrically connected to the second ball grid array 234. The optical chip is connected to the second ball grid array 234.

[0124] In some embodiments, the electro-optic chip may also be connected to the second ball grid array 234.

[0125] The third ball grid array 243 is located above and coupled to the third wiring layer 241. The third ball grid array 243 is electrically connected to the third wiring layer 241 via the third metal bump 242. The third ball grid array 243 is used to connect external circuits, auxiliary devices, or provide expansion interfaces.

[0126] The first interconnect structure 220 includes: a first wiring layer 221, a first metal bump 222, a first intermediate wiring layer 223, and a first ball grid array 224. The first interconnect structure is located above the second surface 202 of the carrier board 200, with its first end connected to the corresponding metal pillar 210 through the first wiring layer 221, and its second end (i.e., the first ball grid array 224) used to connect the electrical chip.

[0127] The second interconnect structure 230 includes: a second wiring layer 231, a second metal bump 232, a second intermediate wiring layer 233, and a second ball grid array 234. The second interconnect structure is located within the groove 203, with its first end connected to a corresponding metal pillar 210 (such as the first metal pillar 211) via the second wiring layer 231, and its second end (i.e., the second ball grid array 234) used to connect to the optical chip.

[0128] The third interconnect structure 240 includes: the third wiring layer 241, the third metal bump 242, and the third ball grid array 243. The third interconnect structure is located in the non-recessed area of ​​the first surface 201 of the carrier board 200. Its first end is connected to the corresponding metal post 210 (such as the second metal post 212) through the third wiring layer 241, and its second end (i.e., the third ball grid array 243) can be used to connect external circuits to realize system-level expansion, auxiliary power supply, or testing functions.

[0129] The first interconnect structure 220 is located above the second surface 202 of the carrier 200 and connects to the electrical chip; the second interconnect structure 230 is located within the groove 203 and connects to the optical chip; the first interconnect structure 220 and the second interconnect structure 230 are connected by a metal pillar 210 penetrating the carrier 200. The groove 203 provides physical positioning and installation space for the optical chip, which is beneficial for increasing bandwidth density. This allows the second interconnect structure 230 to be directly and closely connected to the metal pillar 210 penetrating the carrier 200 in the vertical direction, thereby compressing the electrical signal transmission path between the optical chip and the electrical chip to the shortest possible length, significantly reducing the delay, parasitic effects, and energy loss of high-speed electrical signal transmission. The electrical chip is interconnected with the optical chip through the first interconnect structure 220 and the metal pillar 210, forming a vertical power supply and signal channel from the electrical chip to the optical chip, avoiding long-distance planar wiring. Moreover, the compact layout of "lateral coupling of optical signals and vertical transmission of electrical signals" can improve the integration of the optical chip and the electrical chip. Therefore, the aforementioned intermediary structure can improve the signal integrity of optoelectronic interconnects and enhance the quality and performance of optoelectronic interconnect structures.

[0130] See Figure 14 This forms a second insulating dielectric layer 252, resulting in an insulating dielectric layer 250.

[0131] The second insulating dielectric layer 252 covers the first insulating dielectric layer 251 located on the second surface 202 of the carrier plate 200, the first insulating dielectric layer 251 located in the groove 203 on the first surface 201 of the carrier plate 200, as well as the first intermediate wiring layer 223 and the second intermediate wiring layer 233.

[0132] The material of the second insulating dielectric layer 252 includes at least one of benzocyclobutene, epoxy resin, polyimide, or silicon dioxide. In this embodiment, the material of the second insulating dielectric layer 252 is polyimide. A silicon dioxide / PI composite laminate structure is formed to combine the high insulation and high thermal stability of silicon dioxide with the stress buffering and good coverage of polyimide.

[0133] The material of the second insulating dielectric layer 252 may be the same as or different from the material of the first insulating dielectric layer 251.

[0134] The second insulating dielectric layer 252 and the first insulating dielectric layer 251 together constitute the insulating dielectric layer 250 of the intermediate structure. The insulating dielectric layer 250 covers part or all of the first surface 201 and the second surface 202 of the carrier board 200, and is in close contact with the first interconnect structure (including the first wiring layer 221, the first intermediate wiring layer 223 and the surrounding area) and the second interconnect structure (including the second wiring layer 231, the second intermediate wiring layer 233 and the surrounding area), wrapping their sidewalls and playing the roles of heat dissipation, insulation, protection and mechanical buffering.

[0135] The second insulating dielectric layer 252 is windowed through precise patterning processes (such as photolithography and etching) to fully expose the first ball grid array 224 and the second ball grid array 234, ensuring the smooth mounting of the chip.

[0136] The insulating dielectric layer 250 has a multi-layer structure.

[0137] The insulating dielectric layer 250 covers part or all of the first surface 201 and the second surface 202 of the carrier plate 200, and is in contact with the first interconnect structure and the second interconnect structure, and exposes the first ball grid array 224 and the second ball grid array 234.

[0138] The top surface of the insulating dielectric layer 250 is flush with the surface of the first surface 201 of the carrier plate 200.

[0139] Specifically, by controlling the deposition thickness of the second insulating dielectric layer 252 and performing planarization treatment (e.g., chemical mechanical polishing), the top surface of the insulating dielectric layer 250 can be made flush with the non-groove area surface of the first surface 201 of the carrier 200. This provides a highly uniform planar reference for the entire intermediate structure, which not only facilitates subsequent processes such as chip bonding, multi-chip stacking, or heat sink mounting, but also significantly enhances the structural integrity and long-term reliability of the package.

[0140] In some embodiments, the top surface of the insulating dielectric layer 250 is lower than the non-recessed area surface of the first surface 201 of the carrier 200. This allows the back of the chip to be flush with the non-recessed area surface of the first surface 201 of the carrier 200 after the chip is mounted, facilitating the subsequent connection of external circuitry to the third interconnect structure 240.

[0141] See also Figure 15 and Figures 17 to 21 This forms an embedded waveguide.

[0142] It should be noted that, Figures 17 to 21 This is a cross-sectional schematic diagram of some steps in the manufacturing method of an embedded waveguide according to an embodiment of the present disclosure.

[0143] The embedded waveguide 261 can construct a low-loss optical channel for transmitting optical signals within the first surface 201 of the glass substrate 200, near the groove 203.

[0144] The embedded waveguide 261 is located within the first surface 201 of the carrier plate 200, maintaining a preset distance from its surface (first surface 201), and is located on one side of the groove 203 to facilitate subsequent optical coupling with the optical chip installed in the groove 203. One end of the embedded waveguide 261 protrudes from the side of the carrier plate 200.

[0145] Specifically, on the first surface 201 of the carrier 200, where most of the interconnect structure has been fabricated, and in a predetermined region near the groove 203, a mask material is deposited using a process such as magnetron sputtering, for example, forming an aluminum layer with a thickness of approximately 150 nm as a mask 207. Subsequently, the mask 207 is patterned using standard photolithography processes, including resist coating, exposure, development, and subsequent wet etching, to precisely form ion exchange channels 208 on the mask 207, which define the width and extension length of the subsequent waveguide.

[0146] The embedded waveguide 261 is formed through two thermionic exchange processes.

[0147] Specifically, the first of the two thermal ion exchange processes involves the exchange of potassium and sodium ions. The carrier plate 200, with a patterned mask 207, is placed in a crucible containing molten pure potassium nitrate, and thermal ion exchange is performed at a high temperature (e.g., 450°C) for approximately one hour. During this process, potassium ions in the molten salt exchange with sodium ions on the surface of the carrier plate 200 through ion exchange channels 208 at the mask opening, forming a thin layer rich in potassium ions, namely a potassium ion layer 260. The top surface of the potassium ion layer 260 eventually becomes approximately flush with the first surface 201 of the carrier plate 200.

[0148] The second step of the two-stage thermal ion exchange process involves the exchange of silver and sodium ions. The carrier plate 200, after the first-stage treatment, is transferred to a crucible containing molten silver nitrate (10 wt%). The second thermal ion exchange is then performed at a specific temperature (e.g., 350°C) for approximately 2 hours. Because silver ions have a smaller ionic radius than potassium ions, they exhibit a higher diffusion rate and probability. More importantly, after the first-stage potassium-sodium ion exchange, a large number of sodium ions in the bottom surface region of the ion exchange channel 208 have been replaced by potassium ions. Therefore, silver ions preferentially diffuse through the formed potassium ion layer 260 and continue to penetrate deeper into the carrier plate 200, exchanging with the sodium ions still present in the glass network below the potassium ion layer 260. The introduction of silver ions significantly increases the refractive index of this exchange region, thereby forming an embedded region with optical waveguide characteristics.

[0149] Finally, the carrier plate 200 is annealed in an air atmosphere (e.g., annealed at 200°C for 24 hours). The annealing process helps to eliminate stress generated during ion exchange, stabilize the refractive index distribution of the waveguide, and promote further homogenization and stabilization of silver ions in the glass network, thereby optimizing the optical performance of the waveguide.

[0150] This invention effectively solves the common problem of surface metallic silver deposition in traditional single silver ion exchange processes by employing a two-step ion exchange technology: "potassium ion to sodium ion exchange" and "silver ion to sodium ion exchange." The principle is as follows: the potassium ion layer 260 formed in the first step acts as a waveguide layer, consuming the surface sodium ions and altering the surface's chemical potential and physical structure. This ensures that subsequent silver ion exchange primarily occurs below this potassium ion layer, significantly reducing the likelihood of silver ions accumulating near the glass surface and being reduced to metallic silver. This significantly reduces light absorption loss caused by surface metallic silver deposition, laying a solid foundation for reducing insertion loss during subsequent coupling with optical fibers or optical chips.

[0151] The embedded waveguide 261 is a silver-containing ion-exchange waveguide.

[0152] The intermediate structure also includes the potassium ion layer 260 located above the embedded waveguide 261 and flush with the surface of the carrier plate 200.

[0153] The embedded waveguide 261 is formed by the diffusion of silver ions through the potassium ion layer 260 and the exchange of silver ions with sodium ions in the carrier plate below the potassium ion layer 260.

[0154] The preset spacing is the thickness of the potassium ion layer 260, which ensures that the core light-guiding area of ​​the waveguide is buried under the glass surface and is well protected.

[0155] In some embodiments, after the embedded waveguide 261 is formed, the potassium ion layer 260 is removed.

[0156] See also Figure 16 and Figure 22 A silicon nitride waveguide is formed, and a chip is then mounted on it.

[0157] Figure 22 This is a schematic diagram of a waveguide connection according to an embodiment of the present disclosure.

[0158] The first end (coupling end) of the silicon nitride waveguide 262 is formed and located on the top surface of the insulating dielectric layer 250. This surface is preferably flush with the surface of the area where the embedded waveguide 261 of the carrier 200 is located, providing a highly consistent reference surface for the mounting of the optical chip.

[0159] The second end (waveguide connection end) of the silicon nitride waveguide 262 extends and is precisely positioned directly above the embedded waveguide 261.

[0160] The projection of the silicon nitride waveguide 262 on the first surface 201 of the carrier plate 200 overlaps with the projection of the embedded waveguide 261 to ensure efficient optical mode coupling.

[0161] The silicon nitride waveguide 262 can be fabricated using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) processes. First, a silicon nitride thin film is deposited on the surface of the insulating dielectric layer 250. Then, it is patterned into waveguide stripes with specific width, thickness, and orientation using photolithography and dry etching techniques (e.g., using fluorine-based plasma). The end-face shape and position of the silicon nitride waveguide 262 need to be precisely designed to achieve optical field matching with the underlying embedded waveguide 261.

[0162] The optical chip 270, i.e., the photonic integrated circuit (PIC), is flip-mounted into the groove 203 through the second ball grid array 234 on its bottom and precisely aligned.

[0163] The optical chip 270 contains its own PIC waveguide 271.

[0164] The first end of the optical chip 270 (i.e. its optical input / output coupling area) covers and is precisely aligned with the first end of the silicon nitride waveguide 262. The two are optically coupled by means of end-face coupling or grating coupler through precise alignment, thereby efficiently introducing or extracting optical signals into or out of the optical chip 270.

[0165] The second end of the silicon nitride waveguide 262 is connected to the embedded waveguide 261 via vertical optical coupling. Since the silicon nitride waveguide 262 is located directly above the embedded waveguide 261, the coupling between the two can be achieved by designing a specific overlapping structure and mode field adaptation, such as through a tapered structure or grating coupler, to couple the optical signal upward from the embedded glass waveguide 261 to the silicon nitride waveguide 262, and then conduct it to the optical chip 270 via the silicon nitride waveguide 262.

[0166] The electrical chip 280, i.e., the electronic integrated circuit, is flip-mounted onto the first interconnect structure above the second surface 202 of the carrier board 200 via the first ball grid array 224 at its bottom, thereby achieving electrical connection and mechanical fixation.

[0167] This embodiment successfully constructs a high-efficiency, low-loss optical interconnect path from the embedded glass waveguide 261 to the optical chip 270. The silicon nitride waveguide 262, serving as an intermediate medium, not only provides fabrication convenience (it can be fabricated on the surface of a planarized dielectric layer), but more importantly, its refractive index is between that of glass and silicon-based optical chip waveguides, enabling a gradual transition of optical mode fields and effectively reducing coupling loss caused by mode mismatch. This design significantly improves the optical coupling efficiency between the glass interposer and the PIC chip, ensuring the integrity of optical signal transmission within the package.

[0168] The optical chip 270 and the embedded waveguide 261 are optically coupled through the silicon nitride waveguide 262, while the electrical chip 280 is electrically interconnected with the optical chip 270 through a three-dimensional electrical interconnection network composed of metal pillars 210, a first interconnection structure 220 and a second interconnection structure 230, thereby completing a highly integrated, optoelectronic co-packaged optical (CPO) core unit.

[0169] It should be noted that the positions of the optical chip 270 and the electrical chip 280 can be interchanged. However, the optical chip 270 needs to be placed in the groove 203 to facilitate the connection between the embedded waveguide and the optical chip 270.

[0170] Accordingly, this disclosure also provides an intermediary structure.

[0171] See Figure 16 , Figure 16 This is a schematic cross-sectional view of an intermediate structure according to an embodiment of the present disclosure.

[0172] The intermediary structure includes: carrier plate 200.

[0173] The carrier plate 200 has opposing first surfaces 201 and second surfaces 202, as shown in the figure as an upper and lower surface. Specifically, the lower surface is the first surface 201 of the carrier plate 200, which has a groove 203. The upper surface is the second surface 202 of the carrier plate 200.

[0174] The carrier plate 200 is made of glass.

[0175] Specifically, the carrier 200 is preferably made of borosilicate glass, whose coefficient of thermal expansion can be adjusted by adjusting the composition to match the silicon chip (including optical and electrical chips) within a range (e.g., 2.5-4.5 ppm / ℃). This effectively alleviates packaging warpage and interface stress problems caused by thermal mismatch when integrating heterogeneous chips, ensuring the long-term mechanical stability and thermal reliability of the intermediate structure. The glass carrier has extremely high transmittance (typically >90%) in the optical communication band (e.g., 1550 nm), providing an ideal transparent medium environment for low-loss transmission of optical signals through the subsequently formed embedded waveguide. In addition, the excellent electrical insulation, extremely low dielectric loss, and low crosstalk characteristics of the glass carrier create a high-purity electrical channel for the transmission of high-speed electrical signals in the metal pillars and interconnect structures, fundamentally supporting the high signal integrity, low power consumption, and high bandwidth potential of the final optoelectronic interconnect structure.

[0176] The carrier plate 200 contains sodium ions.

[0177] The carrier plate 200 needs to contain a certain amount of migratable sodium ions (e.g., in the form of sodium oxide, with a content of approximately 8.8 wt%), which is a necessary prerequisite for the subsequent formation of an embedded waveguide through a specific thermal ion exchange process. Sodium ions, as an exchange matrix, can selectively exchange with externally introduced potassium or silver ions in a high-temperature molten salt environment, thereby forming a waveguide region with a higher refractive index below the surface of the carrier plate 200 without significantly affecting the surface smoothness and chemical stability of the carrier plate 200. The content, distribution, and activity of sodium ions in the carrier plate 200 directly affect the depth and rate of ion exchange and the optical properties of the formed waveguide (such as mode field diameter and transmission loss). Those skilled in the art can adjust these parameters as needed, and this should not constitute a limitation of this disclosure.

[0178] The groove 203 structurally serves as a mounting cavity for the optical chip, providing precise physical positioning, mechanical support, and a thermal interface. This allows the active surface of the optical chip (the side with optical devices such as grating couplers and electrical pads) to be precisely aligned with the embedded waveguide and second interconnect structure on the substrate surface. The depth of the groove 203 is designed so that the top surface of the mounted optical chip is approximately coplanar with the surface of the non-groove area of ​​the substrate or at a predetermined relative height. This facilitates the planarization of the subsequent overall structure, dielectric layer filling, and the formation of other interconnect structures, ultimately optimizing the overall size of the package, thermal management performance, and signal transmission path.

[0179] The number of grooves 203 can be multiple.

[0180] In some embodiments, the lower surface is a first surface 201 of the carrier 200, and the first surface 201 has a groove 203. The upper surface is a second surface 202 of the carrier 200, and the second surface 202 also has a groove 203 (not shown). This allows the intermediary structure to freely select whether the second surface 202 of the carrier 200 is close to or far from the external circuit. In other words, the intermediary structure can freely select whether the optical chip on the second surface 202 of the carrier 200 is close to or far from the external circuit.

[0181] The intermediate structure includes: metal pillar 210.

[0182] The metal pillar 210 penetrates the carrier plate 200, with one end of the metal pillar 210 located on the first surface 201 of the carrier plate 200 and the other end of the metal pillar 210 located on the second surface 202 of the carrier plate 200.

[0183] The metal pillar 210 penetrates the carrier plate 200. One end of the metal pillar 210 is located at the bottom of the groove 203 on the first surface 201 of the carrier plate 200, and the other end of the metal pillar 210 is located on the second surface 202 of the carrier plate 200.

[0184] The metal material of the metal pillar 210 is preferably copper, due to its good electrical and thermal conductivity and mature process compatibility. Those skilled in the art may also select other conductive metals or alloys, such as one or more combinations of aluminum, gold, silver, nickel, tungsten, ruthenium, and cobalt, depending on the specific circumstances.

[0185] There are multiple metal pillars 210.

[0186] The metal pillar 210 includes: The first metal pillar 211 penetrates the carrier plate 200, with one end located at the bottom of the groove; The second metal pillar 212 penetrates the carrier plate, with one end located in the non-groove area of ​​the first surface of the carrier plate.

[0187] It should be noted that there can be multiple first metal pillars 211 and multiple second metal pillars 212.

[0188] The first metal pillar 211 penetrates the carrier plate 200, with one end located at the bottom of the groove 203 and the other end located at the second surface 202 of the carrier plate 200. In subsequent process flows, the end of the first metal pillar 211 located at the bottom of the groove 203 will be electrically connected to a second interconnect structure (such as a second wiring layer) formed within the groove 203. The first metal pillar 211 can establish a vertical electrical path from the second surface 202 of the carrier plate 200 to the optical chip within the groove 203, enabling direct, short-distance transmission of high-speed electrical signals, control signals, and power from the electronic integrated circuit to the photonic integrated circuit (PIC), thereby effectively reducing signal delay, crosstalk, and power consumption.

[0189] The second metal pillar 212 penetrates the carrier plate 200, with one end located in a non-grooved region (i.e., a flat region) of the first surface 201 of the carrier plate 200. In subsequent processes, the end located in the non-grooved region of the first surface 201 of the carrier plate 200 can be used to connect a third interconnect structure that may be formed in that region. The second metal pillar 212 can serve as an additional interconnect channel, and its functions may include, but are not limited to: providing additional power or ground paths for electrical chips, optical chips, or other devices located on the second surface 202 of the carrier plate, transmitting auxiliary signals, or serving as part of structural support and heat dissipation enhancement.

[0190] It should be noted that the distinction between the first metal pillar 211 and the second metal pillar 212 is based on their different functions. The first metal pillar 211 is mainly used for subsequent vertical interconnection between the optical chip and the electrical chip, while the second metal pillar 212 is mainly used for subsequent connection between the optical chip or electrical chip and the third interconnection structure. In actual intermediate structure design, the number, specific layout (e.g., array arrangement), cross-sectional shape (e.g., circular, rectangular), and dimensions (e.g., diameter, spacing) of the metal pillars 210 can be optimized and adjusted according to specific optoelectronic interconnection requirements, signal integrity requirements, power distribution network (PDN) design, and thermal management schemes. For example, metal pillars used for transmitting high-speed signals may require specific impedance control designs, while metal pillars used for power / grounding may require a larger cross-sectional area to reduce resistance.

[0191] The metal pillar 210 enables ultra-short-distance three-dimensional interconnection. By vertically connecting through the carrier board 200, the electrical path between the electrical chip and the optical chip located on both sides of the carrier board 200 is compressed to the shortest possible length, thereby avoiding the signal attenuation, increased latency, and increased power consumption problems caused by long-distance planar wiring in traditional solutions.

[0192] The metal pillars 210 improve signal integrity and bandwidth. Short, direct vertical paths significantly reduce parasitic inductance and capacitance in interconnects, helping to maintain the quality of high-speed signals and supporting higher data rates. The high-density array of metal pillars enables high-bandwidth-density interconnects.

[0193] The metal pillars 210 optimize power distribution and thermal management. The metal pillars 210 (especially high thermal conductivity copper pillars) not only provide electrical connections but also serve as effective vertical heat channels, helping to conduct and dissipate heat generated by optical or electrical chips more evenly. Properly planned power and grounding metal pillars contribute to the construction of low-impedance, low-noise power transmission networks.

[0194] The metal pillars 210 enhance structural integration and reliability. The combination of the metal pillars 210 and the carrier plate 200 provides reliable mechanical interconnection, helps alleviate stress caused by differences in the coefficients of thermal expansion of materials, and improves the mechanical stability and long-term reliability of the entire packaging structure.

[0195] The intermediary structure includes: a first interconnection structure 220 and a second interconnection structure 230.

[0196] The first interconnect structure 220 includes: a first wiring layer 221, a first metal bump 222, a first intermediate wiring layer 223, and a first ball grid array 224. The first interconnect structure is located above the second surface 202 of the carrier board 200, with its first end connected to the corresponding metal pillar 210 through the first wiring layer 221, and its second end (i.e., the first ball grid array 224) used to connect the electrical chip.

[0197] The second interconnect structure 230 includes: a second wiring layer 231, a second metal bump 232, a second intermediate wiring layer 233, and a second ball grid array 234. The second interconnect structure is located within the groove 203, with its first end connected to a corresponding metal pillar 210 (such as the first metal pillar 211) via the second wiring layer 231, and its second end (i.e., the second ball grid array 234) used to connect to the optical chip (PIC).

[0198] The first interconnect structure 220 is located above the second surface 202 of the carrier 200 and connects to the electrical chip; the second interconnect structure 230 is located within the groove 203 and connects to the optical chip; the first interconnect structure 220 and the second interconnect structure 230 are connected by a metal pillar 210 penetrating the carrier 200. The groove 203 provides physical positioning and installation space for the optical chip, which is beneficial for increasing bandwidth density. This allows the second interconnect structure 230 to be directly and closely connected to the metal pillar 210 penetrating the carrier 200 in the vertical direction, thereby compressing the electrical signal transmission path between the optical chip and the electrical chip to the shortest possible length, significantly reducing the delay, parasitic effects, and energy loss of high-speed electrical signal transmission. The electrical chip is interconnected with the optical chip through the first interconnect structure 220 and the metal pillar 210, forming a vertical power supply and signal channel from the electrical chip to the optical chip, avoiding long-distance planar wiring. Moreover, the compact layout of "lateral coupling of optical signals and vertical transmission of electrical signals" can improve the integration of the optical chip and the electrical chip. Therefore, the aforementioned intermediary structure can improve the signal integrity of optoelectronic interconnects and enhance the quality and performance of optoelectronic interconnect structures.

[0199] The intermediary structure also includes a third interconnection structure 240.

[0200] The third interconnect structure 240 includes: the third wiring layer 241, the third metal bump 242, and the third ball grid array 243. The third interconnect structure is located in the non-recessed area of ​​the first surface 201 of the carrier board 200. Its first end is connected to the corresponding metal post 210 (such as the second metal post 212) through the third wiring layer 241, and its second end (i.e., the third ball grid array 243) can be used to connect external circuits to realize system-level expansion, auxiliary power supply, or testing functions.

[0201] The first wiring layer 221, the second wiring layer 231, and the third wiring layer 241 are metal wiring layers located on the surface of the carrier board 200 (including the first surface 201, the second surface 202, and the groove 203).

[0202] The first wiring layer 221 is located above the second surface 202 of the carrier board 200. The first wiring layer 221 is electrically connected to the metal pillars 210 (particularly at their ends on the second surface 202) through its patterned traces. The first wiring layer 221 constitutes the bottom wiring network of the first interconnect structure, which can redistribute and transmit electrical signals from the metal pillars 210 in a plane, and prepare for connection to the upper solder ball array (such as the first ball grid array).

[0203] The second wiring layer 231 is located above the bottom of the groove 203. The second wiring layer 231 is electrically connected to the end of the first metal pillar 211 located at the bottom of the groove 203 through its patterned traces. The second wiring layer 231 constitutes the bottom wiring network of the second interconnect structure, which can route the vertical electrical signals from the first metal pillar 211 in the plane of the groove 203 to match the pad layout of the optical chip installed in the groove 203, and provide an interface for the solder ball array (such as the second ball grid array) connecting the optical chip.

[0204] The third wiring layer 241 is located in the non-recessed area of ​​the first surface 201 of the carrier board 200. The third wiring layer 241 is electrically connected to the end of the second metal pillar 212 located in this area. The third wiring layer 241 constitutes the bottom wiring portion of the third interconnect structure and can be used to provide additional power / ground planes, signal wiring, or connect other external circuits or devices located on the first surface 201 of the carrier board. The external circuit can be a separate "external circuit board" or "external carrier board". It can be a carrier and / or interconnect platform of the package in the next level of system integration, such as a printed circuit board, but the external circuit system is not limited to this and may also include ceramic carriers, flexible circuit boards, or other forms of interconnect carriers.

[0205] The first metal bump 222, the second metal bump 232, and the third metal bump 242 are located on the respective surfaces of the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241, and are electrically connected to each wiring layer. This is used for connection to interconnect layers or ball grid arrays.

[0206] The metal bumps can serve as a transition structure between the bottom layer wiring and the upper layer interconnect, ensuring a low-resistance, high-mechanical-strength connection. Their thickness and shape can be designed to compensate for microscopic unevenness on the substrate surface or wiring layer, providing a good coplanarity basis for chip mounting or ball placement.

[0207] The first intermediate wiring layer 223 is located above the first wiring layer and is connected to the first wiring layer.

[0208] The second intermediate wiring layer 233 is located above the second wiring layer and is connected to the second wiring layer.

[0209] The first intermediate wiring layer 223, based on the signal redistribution and power network refinement from the first wiring layer 221 to the upper-layer electrical or optical chip connection interface, has its top layer pattern specifically designed to precisely match the pad layout of the first ball grid array. It converges and guides electrical signals and power / ground signals from the lower wiring layer to predetermined positions, providing process space for ball bonding on the surface of the first intermediate wiring layer 223 to form the first ball grid array connecting the electrical or optical chips, or serving as direct metallization pads.

[0210] The second intermediate wiring layer 233, while completing the fine-tuning of the interconnection path from the second wiring layer 231 to the optical chip or electrical chip (such as impedance tuning and channel isolation), also has its surface pattern configured to correspond to the pad layout of the second ball grid array. It accurately directs control signals, drive power, etc., to the predetermined pad positions, thereby preparing the interface for the formation of the second ball grid array connecting the optical chip or electrical chip on the second intermediate wiring layer 233 within the recess 203.

[0211] A first ball grid array 224 is formed above the first wiring layer 221. The first ball grid array 224 is coupled to the first wiring layer 221, and the first intermediate wiring layer 223 is electrically connected to the first ball grid array 224. The electrical chip can be connected to the first ball grid array 224.

[0212] In some embodiments, the optical chip may also be connected to the first ball grid array 224.

[0213] A second ball grid array 234 is formed above the second wiring layer 231. The second ball grid array 234 is coupled to the second wiring layer 231, and the second intermediate wiring layer 233 is electrically connected to the second ball grid array 234. The optical chip is connected to the second ball grid array 234.

[0214] In some embodiments, the electro-optic chip may also be connected to the second ball grid array 234.

[0215] The third ball grid array 243 is located above and coupled to the third wiring layer 241. The third ball grid array 243 is electrically connected to the third wiring layer 241 via the third metal bump 242. The third ball grid array 243 is used to connect external circuits, auxiliary devices, or provide expansion interfaces.

[0216] The intermediate structure also includes an insulating dielectric layer 250.

[0217] The insulating dielectric layer 250 includes: a first insulating dielectric layer 251 and a second insulating dielectric layer 252.

[0218] The first insulating dielectric layer 251 covers part or all of the first surface 201 and the second surface 202 of the carrier plate 200.

[0219] The first insulating dielectric layer 251 is in contact with the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241. The first insulating dielectric layer 251 covers the sidewalls and part of the top of the first wiring layer 221, the second wiring layer 231, and the third wiring layer 241.

[0220] The first insulating dielectric layer 251 is in contact with the first metal bump 222, the second metal bump 232, and the third metal bump 242. In other words, the first insulating dielectric layer 251 covers the sidewalls of the first metal bump 222, the second metal bump 232, and the third metal bump 242, and exposes the top surfaces of the first metal bump 222, the second metal bump 232, and the third metal bump 242.

[0221] The material of the first insulating dielectric layer 251 includes at least one of benzocyclobutene, epoxy resin, polyimide, or silicon dioxide. In this embodiment, the material of the first insulating dielectric layer 251 is silicon dioxide.

[0222] Silicon dioxide possesses extremely high resistivity and dielectric strength, providing excellent electrical isolation for high-density metal wiring and effectively preventing signal crosstalk and short circuits. Its chemical stability and good compatibility with glass substrates and metal materials, along with few interface defects, ensure long-term reliability. This invention optimizes the heat dissipation capability of the structure by introducing silicon dioxide as the first insulating dielectric layer 251. Although the absolute thermal conductivity of silicon dioxide (approximately 1.4 W / (m·K)) is lower than that of metals, it is significantly higher than that of most polymer dielectrics (such as PI and BCB). As a continuous thin film covering the metal wiring layer and the substrate surface, the silicon dioxide layer can more effectively conduct and diffuse the Joule heat generated during metal interconnection laterally to a larger area of ​​the glass substrate. The glass substrate itself has low thermal conductivity, and the presence of the silicon dioxide interlayer helps reduce the thermal interface resistance from the metal lines to the glass substrate, thereby establishing a smoother heat flow path. This helps reduce the chip junction temperature and alleviate performance fluctuations or reliability issues caused by localized overheating, especially for high-power electrical chip interconnect areas.

[0223] The second insulating dielectric layer 252 covers the first insulating dielectric layer 251 located on the second surface 202 of the carrier plate 200, the first insulating dielectric layer 251 located in the groove 203 on the first surface 201 of the carrier plate 200, as well as the first intermediate wiring layer 223 and the second intermediate wiring layer 233.

[0224] The material of the second insulating dielectric layer 252 includes at least one of benzocyclobutene, epoxy resin, polyimide, or silicon dioxide. In this embodiment, the material of the second insulating dielectric layer 252 is polyimide. A silicon dioxide / PI composite laminate structure is formed to combine the high insulation and high thermal stability of silicon dioxide with the stress buffering and good coverage of polyimide.

[0225] The material of the second insulating dielectric layer 252 may be the same as or different from the material of the first insulating dielectric layer 251.

[0226] The insulating dielectric layer 250 covers part or all of the first surface 201 and the second surface 202 of the carrier plate 200, and is in close contact with the first interconnect structure (including the first wiring layer 221, the first intermediate wiring layer 223 and the surrounding area) and the second interconnect structure (including the second wiring layer 231, the second intermediate wiring layer 233 and the surrounding area), wrapping its sidewalls and playing the roles of heat dissipation, insulation, protection and mechanical buffering.

[0227] The second insulating dielectric layer 252 fully exposes the first ball grid array 224 and the second ball grid array 234, ensuring the smooth mounting of the chip.

[0228] The insulating dielectric layer 250 is a multilayer dielectric layer.

[0229] The insulating dielectric layer 250 covers part or all of the first surface 201 and the second surface 202 of the carrier plate 200, and is in contact with the first interconnect structure and the second interconnect structure, and exposes the first ball grid array 224 and the second ball grid array 234.

[0230] The top surface of the insulating dielectric layer 250 is flush with the surface of the first surface 201 of the carrier plate 200. This ensures that the top surface of the insulating dielectric layer 250 is flush with the non-recessed area surface of the first surface 201 of the carrier plate 200. This provides a highly uniform planar reference for the entire intermediate structure, which not only facilitates subsequent processes such as chip bonding, multi-chip stacking, or heat sink mounting, but also significantly enhances the overall structural integrity and long-term reliability of the package. The introduction of this composite insulating dielectric layer, through the synergistic effect of its multi-layer materials, optimizes the heat conduction path from the central metal interconnect to the glass carrier plate, effectively managing heat distribution during operation, thus providing crucial thermal management and mechanical protection for the stable and efficient operation of high-density optoelectronic co-packaging systems.

[0231] In some embodiments, the top surface of the insulating dielectric layer 250 is lower than the non-recessed area surface of the first surface 201 of the carrier 200. This allows the back of the chip to be flush with the non-recessed area surface of the first surface 201 of the carrier 200 after the chip is mounted, facilitating the subsequent connection of external circuitry to the third interconnect structure 240.

[0232] The intermediate structure includes: an embedded waveguide 261.

[0233] The embedded waveguide 261 is located on the first surface 201 of the carrier plate 200 (see...). Figure 2 It is located within the groove 203 and has a predetermined distance from the first surface 201 of the carrier plate, and is situated within the groove 203 (see...). Figure 2 ( ) on one side.

[0234] The embedded waveguide 261 can construct a low-loss optical channel for transmitting optical signals within the first surface 201 of the glass substrate 200, near the groove 203.

[0235] The embedded waveguide 261 is located within the first surface 201 of the carrier plate 200 and maintains a preset distance from its surface (first surface 201), and is located on one side of the groove 203, so as to facilitate subsequent optical coupling with the optical chip installed in the groove 203.

[0236] One end of the embedded waveguide 261 is exposed on the side of the intermediate structure.

[0237] The embedded waveguide 261 is formed through two thermionic exchange processes.

[0238] Specifically, the first step of the two-step thermal ion exchange process involves the exchange of potassium ions with sodium ions, and the second step involves the exchange of silver ions with sodium ions. This invention effectively solves the common problem of surface silver deposition in traditional single silver ion exchange processes by combining two-step ion exchange technologies: potassium ion exchange with sodium ion exchange and silver ion exchange with sodium ion exchange.

[0239] The embedded waveguide 261 is a silver-containing ion-exchange waveguide.

[0240] The intermediate structure also includes the potassium ion layer 260 located above the embedded waveguide 261 and flush with the surface of the carrier plate 200.

[0241] The embedded waveguide 261 is formed by the diffusion of silver ions through the potassium ion layer 260 and the exchange of silver ions with sodium ions in the carrier plate below the potassium ion layer 260.

[0242] The preset spacing is the thickness of the potassium ion layer 260, which ensures that the core light-guiding area of ​​the waveguide is buried under the glass surface and is well protected.

[0243] In some embodiments, the potassium ion layer 260 is not present.

[0244] The first end (coupling end) of the silicon nitride waveguide 262 is located on the top surface of the insulating dielectric layer 250. This surface is preferably flush with the surface of the area where the embedded waveguide 261 of the carrier 200 is located, providing a highly consistent reference surface for the mounting of the optical chip.

[0245] The second end (waveguide connection end) of the silicon nitride waveguide 262 extends and is precisely positioned directly above the embedded waveguide 261.

[0246] The projection of the silicon nitride waveguide 262 on the first surface 201 of the carrier plate 200 overlaps with the projection of the embedded waveguide 261 to ensure efficient optical mode coupling.

[0247] The optical chip 270, i.e., the photonic integrated circuit (PIC), is flip-mounted into the groove 203 through the second ball grid array 234 on its bottom and precisely aligned.

[0248] The optical chip 270 contains its own PIC waveguide 271.

[0249] The first end of the optical chip 270 (i.e. its optical input / output coupling area) covers and is precisely aligned with the first end of the silicon nitride waveguide 262. The two are optically coupled by means of end-face coupling or grating coupler through precise alignment, thereby efficiently introducing or extracting optical signals into or out of the optical chip 270.

[0250] The second end of the silicon nitride waveguide 262 is connected to the embedded waveguide 261 via vertical optical coupling. Since the silicon nitride waveguide 262 is located directly above the embedded waveguide 261, the coupling between the two can be achieved by designing a specific overlapping structure and mode field adaptation, such as through a tapered structure or grating coupler, to couple the optical signal upward from the embedded glass waveguide 261 to the silicon nitride waveguide 262, and then conduct it to the optical chip 270 via the silicon nitride waveguide 262.

[0251] The electrical chip 280, i.e., the electronic integrated circuit, is flip-mounted onto the first interconnect structure above the second surface 202 of the carrier board 200 via the first ball grid array 224 at its bottom, thereby achieving electrical connection and mechanical fixation.

[0252] This embodiment successfully constructs a high-efficiency, low-loss optical interconnect path from the embedded glass waveguide 261 to the optical chip 270. The silicon nitride waveguide 262, serving as an intermediate medium, not only provides fabrication convenience (it can be fabricated on the surface of a planarized dielectric layer), but more importantly, its refractive index is between that of glass and silicon-based optical chip waveguides, enabling a gradual transition of optical mode fields and effectively reducing coupling loss caused by mode mismatch. This design significantly improves the optical coupling efficiency between the glass interposer and the PIC chip, ensuring the integrity of optical signal transmission within the package.

[0253] The optical chip 270 and the embedded waveguide 261 are optically coupled through the silicon nitride waveguide 262, while the electrical chip 280 is electrically interconnected with the optical chip 270 through a three-dimensional electrical interconnection network composed of metal pillars 210, a first interconnection structure 220 and a second interconnection structure 230, thereby completing a highly integrated, optoelectronic co-packaged optical (CPO) core unit.

[0254] It should be noted that the positions of the optical chip 270 and the electrical chip 280 can be interchanged. However, the optical chip 270 needs to be placed in the groove 203 to facilitate the connection between the embedded waveguide and the optical chip 270.

[0255] Accordingly, this disclosure also provides a packaging structure.

[0256] The packaging structure includes the intermediate structure of any of the foregoing embodiments.

[0257] By mounting the optical chip and the electrical chip onto the corresponding interconnect structure of the intermediate structure respectively, and completing the necessary optical alignment and coupling, a fully functional optoelectronic co-packaged unit can be formed.

[0258] The core advantage of this packaging structure lies in its highly integrated three-dimensional architecture. The optical chip is precisely housed within a recess in the carrier substrate, achieving a tight electrical and optical connection through a short-pitch second interconnect structure and an embedded waveguide. The electrical chip is located on the other side of the carrier substrate, communicating with the optical chip at high speed via an ultra-short path formed by vertically penetrating metal pillars and multi-layer wiring. This layout not only minimizes the physical distance between optoelectronic interconnects, thereby significantly reducing signal transmission delay, power consumption, and parasitic effects, but also greatly optimizes the package size, improving bandwidth density and energy efficiency per unit area.

[0259] The composite insulating dielectric layer and optimized waveguide fabrication process in the encapsulation structure jointly ensure its thermal stability and low-loss characteristics in optical signal transmission during operation, thereby achieving high signal integrity and high reliability system-level performance. This encapsulation structure can serve as a core module and be further integrated with other packages, carriers, or heat dissipation components, finding wide application in data centers, high-performance computing, optical communication, and sensing, providing a key encapsulation solution for next-generation high-density optoelectronic integrated systems.

[0260] This disclosure also provides an electronic device, which includes the packaging structure of any of the foregoing embodiments.

[0261] The electronic device includes the packaging structure provided in the foregoing embodiments. The metal shielding layer of this packaging structure conformally covers the bottom and sidewalls of the chip housing cavity, exposing the top surface of the conductive pillars. This invention defines an independent chip housing cavity using a carrier plate and a surrounding dam for accommodating the chip. Based on this, a conformal covering process is used to form a complete metal shielding layer on the bottom and sidewalls of the cavity, constructing a quasi-Faraday cage shielding structure. Therefore, the packaging structure can ensure signal integrity in complex electromagnetic environments, improving the quality and performance of the packaging structure.

[0262] Electronic devices can include AI supercomputing and data center servers. Through the application of encapsulation structures, the data transmission and processing speeds of these servers can be significantly improved, enabling high-data throughput. Therefore, devices using encapsulation structures can integrate multiple functions such as electronic signal processing, optical signal transmission, and data storage, which helps improve the overall functional density and integration of the device, meeting the demands for high bandwidth, large-capacity storage, and rapid data processing, and ultimately enhancing device performance.

[0263] Electronic devices may also include augmented reality head-mounted displays or virtual reality head-mounted displays, thereby enabling ultra-low latency image transmission.

[0264] Electronic devices may also include endoscopic imaging modules. The combination of a CMOS image sensor and its packaging structure enhances the device's anti-interference capabilities, eliminates electromagnetic interference artifacts, improves imaging resolution, and reduces latency in practical applications.

[0265] It is understood that the above description of the packaging structure and its manufacturing method, as well as multiple embodiments of electronic devices, may combine and cross-reference the various optional methods described in each embodiment without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed and made public by this invention.

[0266] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0267] In the embodiments of this application, "multiple" refers to two or more.

[0268] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0269] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0270] While the embodiments disclosed above are provided, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An intermediary structure for interconnecting an optical chip and an electrical chip, characterized in that, include: A carrier plate having opposing first and second surfaces, wherein the first surface has a groove; Multiple metal pillars penetrate the carrier plate; An embedded waveguide is located within the first surface of the carrier plate and has a predetermined distance from the first surface of the carrier plate, and is located on one side of the groove; A first interconnect structure is located above the second surface of the carrier board, and a first end of the first interconnect structure is connected to the metal pillar, and a second end of the first interconnect structure is connected to the electrical chip. A second interconnect structure is located within the groove, with a first end of the second interconnect structure connected to the metal pillar and a second end of the second interconnect structure connected to the optical chip. The optical chip is optically coupled to the embedded waveguide.

2. The intermediary structure according to claim 1, characterized in that, The embedded waveguide is a silver-containing ion-exchange waveguide, and the carrier plate contains sodium ions; The intermediary structure also includes: A potassium ion layer is located above the embedded waveguide and flush with the carrier plate; The embedded waveguide is formed by the diffusion of silver ions through the potassium ion layer and their exchange with sodium ions below the potassium ion layer.

3. The intermediary structure according to claim 2, characterized in that, Meet one or more of the following: The carrier plate is made of borosilicate glass; The preset spacing is the thickness of the potassium ion layer.

4. The intermediary structure according to claim 1, characterized in that, The embedded waveguide is a silver-containing ion-exchange waveguide; The intermediary structure also includes: A silicon nitride waveguide is provided, wherein a first end of the silicon nitride waveguide is optically coupled to the optical chip, and the projection of the second end of the silicon nitride waveguide on the first surface of the carrier overlaps with the projection of the embedded waveguide on the first surface of the carrier, so as to achieve optical coupling with the embedded waveguide.

5. The intermediary structure according to claim 1, characterized in that, The first interconnect structure includes: The first wiring layer is located above the second surface of the carrier plate and is connected to the metal pillar; A first ball grid array is located above and coupled to the first wiring layer; The electrical chip is connected to the first ball grid array.

6. The intermediary structure according to claim 5, characterized in that, The first interconnect structure further includes: A first intermediate wiring layer is located above the first wiring layer and is connected to the first ball grid array and the first wiring layer.

7. The intermediary structure according to claim 1, characterized in that, The second interconnect structure includes: The second wiring layer is located above the bottom of the groove and is connected to the metal pillar; The second ball grid array is located above the second wiring layer and coupled to the second wiring layer; The optical chip is connected to the second ball grid array.

8. The intermediary structure according to claim 7, characterized in that, The second interconnect structure also includes: The second intermediate wiring layer is located above the second wiring layer and is connected to the second ball grid array and the second wiring layer.

9. The intermediary structure according to claim 1, characterized in that, Also includes: The third interconnection structure is located in the non-grooved area of ​​the first surface of the carrier plate and is connected to the metal pillar.

10. The intermediary structure according to claim 9, characterized in that, The third interconnect structure includes: The third wiring layer is located in the non-recessed area of ​​the first surface of the carrier plate and is connected to the metal pillar; The third ball grid array is located above the third wiring layer and is connected to the third wiring layer.

11. The intermediary structure according to claim 9, characterized in that, The metal column includes: A first metal pillar penetrates the carrier plate, with one end located at the bottom of the groove, connecting the first interconnect structure and the second interconnect structure; The second metal pillar penetrates the carrier plate, with one end located in the non-grooved area of ​​the first surface of the carrier plate, connecting the first interconnection structure and the third interconnection structure.

12. The intermediary structure according to claim 5, characterized in that, The second interconnect structure includes: The second wiring layer is located above the bottom of the groove and is connected to the metal pillar; The second ball grid array is located above the second wiring layer and coupled to the second wiring layer; The optical chip is connected to the second ball grid array; The intermediary structure also includes: An insulating dielectric layer covers part or all of the first and second surfaces of the carrier plate, and is in contact with the first interconnect structure and the second interconnect structure, and exposes the first ball grid array and the second ball grid array.

13. The intermediary structure according to claim 12, characterized in that, The embedded waveguide is a silver-containing ion-exchange waveguide; The intermediary structure also includes: A silicon nitride waveguide, wherein the first end of the silicon nitride waveguide is located on the top surface of the insulating dielectric layer; The first end of the optical chip covers the first end of the silicon nitride waveguide and is optically coupled to the silicon nitride waveguide.

14. The intermediary structure according to claim 12, characterized in that, The top surface of the insulating dielectric layer is flush with the surface of the first side of the carrier plate.

15. The intermediary structure according to claim 12, characterized in that, The insulating dielectric layer satisfies one or more of the following: The insulating dielectric layer is a multilayer dielectric layer; The material of the insulating dielectric layer includes at least one of benzocyclobutene, epoxy resin, polyimide, or silicon dioxide.

16. A method for manufacturing an intermediary structure for interconnecting an optical chip and an electrical chip, characterized in that, include: A carrier plate is provided, the carrier plate having opposing first and second surfaces, and the first surface having a groove; Multiple metal pillars are formed that penetrate the carrier plate; A first interconnect structure is formed, the first interconnect structure is located above the second surface of the carrier board, the first end of the first interconnect structure is connected to the metal pillar, and the second end of the first interconnect structure is connected to the electrical chip. A second interconnect structure is formed, the second interconnect structure is located in the groove, the first end of the second interconnect structure is connected to the metal pillar, and the second end of the second interconnect structure is connected to the optical chip; An embedded waveguide is formed, wherein the embedded waveguide is located within the first surface of the carrier plate and has a predetermined distance from the first surface of the carrier plate, and is located on one side of the groove; The optical chip is optically coupled to the embedded waveguide.

17. The method according to claim 16, characterized in that, The steps for forming the embedded waveguide include: A mask is formed on the first surface of the carrier plate, in the area near the groove; The mask is graphically represented to form ion exchange channels; A potassium ion layer is formed on the surface of the carrier plate at the ion exchange channel, and the top surface of the potassium ion layer is flush with the carrier plate. An embedded waveguide is formed beneath the potassium ion layer; The carrier plate contains sodium ions, and the embedded waveguide is formed by the diffusion of silver ions through the potassium ion layer and their exchange with sodium ions below the potassium ion layer.

18. The method according to claim 17, characterized in that, Meet one or more of the following: The mask is an aluminum mask; The carrier plate is made of borosilicate glass; The potassium ion layer is formed by thermal ion exchange. The preset spacing is the thickness of the potassium ion layer.

19. The method according to claim 16, characterized in that, The step of forming the first interconnect structure includes: A first wiring layer is formed above the second surface of the carrier plate, and the first wiring layer is connected to the metal pillar. A first ball grid array is formed above the first wiring layer, and the first ball grid array is coupled to the first wiring layer; The electrical chip is connected to the first ball grid array.

20. The method according to claim 19, characterized in that, The step of forming the first interconnect structure further includes: A first intermediate wiring layer is formed, which is located above the first wiring layer and connected to the first ball grid array and the first wiring layer.

21. The method according to claim 16, characterized in that, The step of forming the second interconnect structure includes: A second wiring layer is formed above the bottom of the groove, and the second wiring layer is connected to the metal pillar; A second ball grid array is formed above the second wiring layer, and the second ball grid array is coupled to the second wiring layer; The optical chip is connected to the second ball grid array.

22. The method according to claim 21, characterized in that, The step of forming the second interconnect structure further includes: A second intermediate wiring layer is formed, which is located above the second wiring layer and connected to the second ball grid array and the second wiring layer.

23. The method according to claim 21, characterized in that, A first wiring layer is formed above the second surface of the carrier plate, and the first wiring layer is connected to the metal pillar. The first wiring layer and the second wiring layer are formed in the same step.

24. The method according to claim 16, characterized in that, Also includes: A third interconnect structure is formed, which is located in the non-groove region of the first surface of the carrier plate and is connected to the metal pillar; The third interconnect structure includes: a third wiring layer located in the non-recessed area of ​​the first surface of the carrier board and connected to the metal pillar; and a third ball grid array located above the third wiring layer and connected to the third wiring layer.

25. The method according to claim 19 or 21, characterized in that, Also includes: An insulating dielectric layer is formed, which covers part or all of the first and second surfaces of the carrier plate and is in contact with the first interconnect structure and the second interconnect structure, and exposes the first ball grid array and the second ball grid array.

26. The method according to claim 25, characterized in that, Also includes: A silicon nitride waveguide is formed, wherein the first end of the silicon nitride waveguide is located on the top surface of the insulating dielectric layer, and the second end of the silicon nitride waveguide is located above the embedded waveguide; The first end of the optical chip covers the first end of the silicon nitride waveguide and is optically coupled to the silicon nitride waveguide. The top surface of the insulating dielectric layer is flush with the surface of the first side of the carrier plate.

27. A packaging structure, characterized in that, Including the intermediary structure as described in any one of claims 1 to 15.

28. An electronic device, characterized in that, Including the intermediary structure as described in any one of claims 1 to 15.

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