Half-bridge mosfet packaging method
By constructing a half-bridge MOSFET package using copper clip welding technology, the problems of large parasitic inductance and limited heat dissipation performance in traditional packages are solved, achieving low inductance, high-frequency applications and excellent heat dissipation, and adapting to various topologies and customized needs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU GOODARK ELECTRONICS CO LTD
- Filing Date
- 2026-04-27
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional half-bridge MOSFET packages suffer from problems such as large parasitic inductance, difficulty in controlling dead time and crosstalk, excessive EMI, large size, and limited heat dissipation performance, especially in high-frequency applications at the MHz level where switching losses increase dramatically.
The copper clip welding process is adopted, which forms a conductive connection path of half-bridge topology by the conductive pattern of the copper clip group and the lead frame, replacing the traditional wire bonding interconnection method. The copper clips are directly welded to the connection area between the top electrode of the chip and the lead frame.
It significantly reduces parasitic inductance and switching losses, improves current carrying capacity and heat dissipation performance, adapts to different topologies and customer customization requirements, reduces EMI emission levels, and supports MHz-level high-frequency applications.
Smart Images
Figure CN122497402A_ABST
Abstract
Description
Technical Field
[0001] This application relates to semiconductor packaging technology, specifically to a half-bridge MOSFET packaging method. Background Technology
[0002] Half-bridge topology is the core unit of DC-DC converters, PFC, motor drives, and inverters. Traditional solutions use two discrete MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) interconnected via a PCB. This approach suffers from drawbacks such as large parasitic inductance, difficulty in controlling dead time and crosstalk, excessive EMI (Electromagnetic Interference), and large size. In particular, switching losses increase dramatically in high-frequency applications at the MHz level.
[0003] While existing integrated solutions (such as PDFN and LFPAK dual N-MOS packages) have reduced size and parasitic inductance to some extent, they still generally use wire bonding technology, resulting in weak current carrying capacity, high parasitic inductance, limited heat dissipation performance, and a single chip mounting method, failing to fully leverage the advantages of copper clip bond and flip chip.
[0004] Therefore, there is an urgent need for a half-bridge MOSFET packaging method that can reduce parasitic inductance, improve current carrying capacity and heat dissipation performance. Summary of the Invention
[0005] To overcome the above-mentioned defects, this application provides a half-bridge MOSFET packaging method. The copper clip welding process used in this packaging method has a current carrying capacity that far exceeds that of the traditional wire bonding process, reaching several times that of wire bonding, thereby improving the overall current carrying capacity of the device.
[0006] The technical solution adopted by this application to solve its technical problem is:
[0007] A half-bridge MOSFET packaging method includes the following steps:
[0008] Provide a lead frame: the lead frame has a first chip mounting area, a second chip mounting area, a plurality of external pins, and a conductive pattern formed thereon;
[0009] First soldering: Apply solder paste to the first chip mounting area and / or the second chip mounting area;
[0010] Chip mounting: The first MOSFET chip is mounted in the first chip mounting area, and the second MOSFET chip is mounted in the second chip mounting area;
[0011] Second soldering: Apply solder paste to the top electrodes of the first MOSFET chip and / or the second MOSFET chip, as well as the connection area of the lead frame;
[0012] Placing the copper clip assembly: Place the copper clip assembly on top of the first MOSFET chip and / or the second MOSFET chip, and make the copper clip assembly contact the top electrode of the first MOSFET chip and / or the second MOSFET chip, as well as the connection area of the lead frame;
[0013] Forming a half-bridge topology connection: The copper clip group and the conductive pattern together form a conductive connection path, which enables the first MOSFET chip and the second MOSFET chip to form a half-bridge topology connection, and leads the drain, source, gate and intermediate node of the half-bridge topology to the external pins of the lead frame respectively.
[0014] Reflow soldering: The solder paste is melted to fix the copper clip assembly, the first MOSFET chip, the second MOSFET chip and the lead frame.
[0015] Post-processing: The semi-finished product after reflow soldering is post-processed to obtain a half-bridge MOSFET package structure. The post-processing includes flux cleaning, encapsulation, molding separation, testing, and packaging.
[0016] Optionally, the first MOSFET chip is an upper-side MOSFET chip, and the second MOSFET chip is a lower-side MOSFET chip.
[0017] Optionally, the copper clip assembly includes at least two copper clips, the copper clips in the copper clip assembly are fixed by the same reflow soldering process, and the copper clip assembly is mounted using a pick-and-place process.
[0018] Optionally, the first MOSFET chip is mounted upright in the first chip mounting area, and the second MOSFET chip is mounted flip-flop or upright in the second chip mounting area.
[0019] Optionally, the source of the first MOSFET chip and the drain of the second MOSFET chip are electrically connected through the copper clip group and are jointly connected to at least one external pin of the lead frame.
[0020] Optionally, the source of the first MOSFET chip and the drain of the second MOSFET chip are electrically connected through the conductive pattern of the lead frame and are jointly connected to at least one external pin of the lead frame.
[0021] Optionally, both the first MOSFET chip and the second MOSFET chip are mounted upright on the lead frame; the copper clip group includes a first copper clip, a second copper clip, a third copper clip, and a fourth copper clip, wherein:
[0022] The first copper clip electrically connects the source of the first MOSFET chip to the drain of the second MOSFET chip and connects to the external pin of the lead frame;
[0023] The second copper clip electrically connects the gate of the first MOSFET chip to the external pin of the lead frame;
[0024] The third copper clip electrically connects the gate of the second MOSFET chip to the external pin of the lead frame;
[0025] The fourth copper clip electrically connects the source of the second MOSFET chip to the external pin of the lead frame;
[0026] The drain of the first MOSFET chip is electrically connected to the external pin of the lead frame through the conductive pattern of the lead frame.
[0027] Optionally, the first MOSFET chip is mounted upright in the first chip mounting area, and the second MOSFET chip is mounted flip-chip in the second chip mounting area; the copper clip group includes a fifth copper clip and a sixth copper clip, wherein,
[0028] The fifth copper clip electrically connects the source of the first MOSFET chip to the drain of the second MOSFET chip, and is also electrically connected to the external pins of the lead frame.
[0029] The sixth copper clip electrically connects the gate of the first MOSFET chip to the external pin of the lead frame;
[0030] The drain of the first MOSFET chip, the source of the second MOSFET chip, and the gate of the second MOSFET chip are electrically connected to the external pins of the lead frame 100 through the conductive pattern of the lead frame.
[0031] Optionally, the source of the second MOSFET chip is provided with a flip-chip bump, which is connected to the lead frame by thermo-bonding. The bump includes a copper pillar bump or a gold bump, and the surface of the bump is provided with a solder layer. The area of the fifth copper clip is larger than the area of the sixth copper clip, and the fifth copper clip is configured to carry the main power current of the half-bridge switching node.
[0032] Optionally, both the first MOSFET chip and the second MOSFET chip are mounted upright on the lead frame; the copper clip group includes a seventh copper clip, an eighth copper clip, and a ninth copper clip, wherein:
[0033] The source of the first MOSFET chip and the drain of the second MOSFET chip are electrically connected through the conductive pattern of the lead frame, and the eighth copper clip leads the electrical connection point to the external pin of the lead frame.
[0034] The seventh copper clip electrically connects the gate of the first MOSFET chip to the external pin of the lead frame;
[0035] The ninth copper clip electrically connects the source of the second MOSFET chip to the external pin of the lead frame;
[0036] The drain of the first MOSFET chip is electrically connected to the external pin of the lead frame through the conductive pattern of the lead frame.
[0037] The gate of the second MOSFET chip is electrically connected to the external pin of the lead frame via a bonding lead.
[0038] The beneficial effects of this application are:
[0039] (1) This application constructs a complete conductive connection path for a half-bridge topology by combining the conductive patterns of the copper clip group and the lead frame. The copper clips are directly soldered between the connection area of the chip top electrode and the lead frame, replacing the traditional wire bonding interconnection method. The copper clips are large-area copper components with extremely short interconnection paths and large cross-sectional areas, which can reduce the parasitic inductance of the power loop to the sub-nH level. Compared with existing discrete device solutions, this application can effectively suppress voltage overshoot and ringing during the switching process, thereby significantly reducing switching losses and meeting the requirements of MHz-level high-frequency switching for applications such as fast charging and new energy vehicle OBC / DC-DC, i.e., significantly reducing parasitic inductance and supporting high-frequency applications.
[0040] (2) The copper clip welding process used in this application has a current carrying capacity far exceeding that of the traditional wire bonding process. The current carrying capacity can be several times that of wire bonding. At the same time, the copper clip and the chip electrode and lead frame are formed by solder paste reflow soldering to form a large area and low resistance solder joint, which can further reduce the contact resistance and thus improve the overall current carrying capacity of the device.
[0041] (3) In this application, copper clip welding process is used so that copper sheets are interconnected to the lead terminals on both the top and bottom of the chip. The copper PAD of the chip is directly welded to the PCB. Heat can be dissipated from the bottom to the PCB. Copper clips are used on the top, increasing the heat dissipation area and effectively reducing the temperature rise of the device. In addition, the epoxy of the encapsulation on the top of the copper clip is close to zero or directly exposed to the air, which further improves the heat dissipation effect. The temperature rise of the device is lower and the thermal resistance characteristics are better.
[0042] (4) This application does not limit whether the on-resistance of the two MOSFET chips is the same, nor does it limit that their mounting methods must be the same; the first MOSFET chip and the second MOSFET chip can be selected in upright or flip-chip mode according to actual application requirements, and different specifications of chips can be used. This flexibility enables this method to adapt to various topologies such as synchronous rectification Buck, totem pole bridgeless PFC, and the customized requirements of different customers for the asymmetric performance of the upper and lower transistors of the half-bridge. Attached Figure Description
[0043] Figure 1 This is a schematic diagram of the packaging structure in Embodiment 1 of this application;
[0044] Figure 2 This is a schematic diagram of the lead frame structure in Embodiment 1 of this application;
[0045] Figure 3 This is a simplified diagram of the first MOSFET chip in Embodiment 1 of this application;
[0046] Figure 4 This is a simplified diagram of the second MOSFET chip in Embodiment 1 of this application;
[0047] Figure 5 This is one of the simplified circuit diagrams of the packaging structure in Embodiment 1 of this application;
[0048] Figure 6 This is a second simplified circuit diagram of the packaging structure in Embodiment 1 of this application;
[0049] Figure 7 This is a schematic diagram of the packaging structure in Embodiment 2 of this application;
[0050] Figure 8 This is a simplified diagram of the first MOSFET chip in Embodiment 2 of this application;
[0051] Figure 9 This is a simplified diagram of the second MOSFET chip in Embodiment 2 of this application;
[0052] Figure 10 This is one of the simplified circuit diagrams of the packaging structure in Embodiment 2 of this application;
[0053] Figure 11This is a second simplified circuit diagram of the packaging structure in Embodiment 2 of this application;
[0054] Figure 12 This is an exploded view of the packaging structure in Embodiment 2 of this application;
[0055] Figure 13 This is a schematic diagram of the packaging structure in Embodiment 3 of this application;
[0056] Figure 14 This is a simplified diagram of the first MOSFET chip in Embodiment 3 of this application;
[0057] Figure 15 This is a simplified diagram of the second MOSFET chip in Embodiment 3 of this application;
[0058] Figure 16 This is one of the simplified circuit diagrams of the packaging structure in Embodiment 3 of this application;
[0059] Figure 17 This is a second simplified circuit diagram of the packaging structure in Embodiment 3 of this application;
[0060] Figure 18 This is a process flow diagram of the packaging structure in Embodiment 2 of this application;
[0061] Figure 19 This is a simplified diagram of the half-bridge structure in this application;
[0062] In the diagram: 100 - lead frame, 110 - first chip mounting area, 120 - second chip mounting area, 130 - external pin, 200 - first MOSFET chip, 300 - second MOSFET chip, 400 - copper clip group, 410 - first copper clip, 420 - second copper clip, 430 - third copper clip, 440 - fourth copper clip, 450 - fifth copper clip, 460 - sixth copper clip, 470 - seventh copper clip, 480 - eighth copper clip, 490 - ninth copper clip, 500 - bonding wire, 600 - plastic encapsulation shell, 610 - solder paste layer. Detailed Implementation
[0063] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the embodiments described in this application are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0064] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such uses of the terms can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0065] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.
[0066] like Figure 1-19 As shown, a half-bridge MOSFET packaging method includes the following steps:
[0067] A lead frame 100 is provided: the lead frame 100 has a first chip mounting area 110, a second chip mounting area 120, a plurality of external pins 130, and conductive patterns formed thereon;
[0068] First soldering: Apply solder paste to the first chip mounting area 110 and / or the second chip mounting area 120;
[0069] Chip mounting: The first MOSFET chip 200 is mounted in the first chip mounting area 110, and the second MOSFET chip 300 is mounted in the second chip mounting area 120;
[0070] Second soldering: Solder paste is applied to the top electrodes of the first MOSFET chip 200 and / or the second MOSFET chip 300, as well as the connection area of the lead frame 100; optionally, the connection area includes external pins, pads or other specific locations.
[0071] Placing the copper clip assembly 400: The copper clip assembly 400 is placed on top of the first MOSFET chip 200 and / or the second MOSFET chip 300, and the copper clip assembly 400 is in contact with the top electrode of the first MOSFET chip 200 and / or the second MOSFET chip 300, as well as the connection area of the lead frame 100.
[0072] Forming a half-bridge topology connection: The copper clip group 400 and the conductive pattern together form a conductive connection path, which enables the first MOSFET chip 200 and the second MOSFET chip 300 to form a half-bridge topology connection, and leads the drain, source, gate and intermediate node of the half-bridge topology to the external pin 130 of the lead frame respectively.
[0073] Reflow soldering: The solder paste is melted to fix the copper clip assembly 400, the first MOSFET chip 200, the second MOSFET chip 300, and the lead frame 100.
[0074] Post-processing: The semi-finished product after reflow soldering is post-processed to obtain a half-bridge MOSFET package structure. The post-processing includes flux cleaning, encapsulation, molding separation, testing, and packaging.
[0075] This application utilizes the conductive patterns of the copper clip group 400 and the lead frame 100 to form a complete conductive connection path for a half-bridge topology, as shown in the half-bridge structure. Figure 19 As shown, a copper clip bond is directly soldered between the top electrode of the chip and the connection area of the lead frame, replacing the traditional wire bonding interconnection method. The copper clip bond is a large-area copper component with an extremely short interconnection path and a large cross-sectional area, which can reduce the parasitic inductance of the power loop to the sub-nH level. Compared with existing discrete device solutions (where parasitic inductance is typically in the range of several nH to tens of nH), this application can effectively suppress voltage overshoot and ringing during the switching process, thereby significantly reducing switching losses and meeting the requirements of MHz-level high-frequency switching in applications such as fast charging and new energy vehicle OBC / DC-DC converters, i.e., significantly reducing parasitic inductance and supporting high-frequency applications.
[0076] The copper clip welding process used in this application has a current carrying capacity far exceeding that of the traditional wire bonding process, reaching several times that of wire bonding. At the same time, the copper clip forms a large-area, low-resistance solder joint with the chip electrode and lead frame through solder paste reflow soldering, which can further reduce contact resistance and thus improve the overall current carrying capacity of the device.
[0077] This application employs a copper clip welding process, which interconnects the chip's top and bottom with copper plates to the lead terminals. The chip's copper pads are directly soldered to the PCB, allowing heat to be dissipated from the bottom to the PCB. The use of copper clips on top increases the heat dissipation area, effectively reducing the device's temperature rise. Furthermore, the epoxy coating on the top of the copper clips is close to zero or directly exposed to the air, further improving the heat dissipation effect. This results in even lower device temperature rise and superior thermal resistance characteristics.
[0078] This application does not limit whether the on-resistance (RDS(on)) of the two MOSFET chips is the same, nor does it limit their mounting method to be the same. The first MOSFET chip and the second MOSFET chip can be selected in upright or flip-chip configurations according to actual application requirements, and different chip specifications can be used (e.g., the upper MOSFET focuses on fast switching, and the lower MOSFET focuses on low on-resistance). This flexibility allows this method to adapt to various topologies such as synchronous rectification Buck, totem pole bridgeless PFC, and the customized requirements of different customers for the asymmetric performance of the upper and lower MOSFETs in a half-bridge.
[0079] Because this application significantly reduces parasitic inductance and loop area, eliminating the physical basis for high-frequency oscillations, the switching waveform is smoother and the ringing amplitude is significantly reduced. Therefore, this method reduces the emission level of electromagnetic interference at the source, making the final product easier to pass EMC certification, reducing reliance on filtering components and external shielding measures, and helping to reduce system costs.
[0080] Optionally, the solder paste is applied using a dotting process or a screen printing process; the reflow soldering temperature profile is configured as follows: peak temperature 240℃~260℃, holding time above the liquidus line 40 seconds~90 seconds; the encapsulation uses epoxy resin molding compound for transfer molding and encapsulation; the molding separation includes lead removal and molding processes; the testing includes electrical testing, and the test items include at least on-resistance, leakage current, gate threshold voltage, and breakdown voltage.
[0081] Optionally, the first MOSFET chip 200 is the upper MOSFET chip, and the second MOSFET chip 300 is the lower MOSFET chip. The upper MOSFET chip DIE1 is abbreviated as E1, and the lower MOSFET chip DIE2 is abbreviated as E2. In the following text and the accompanying drawings, E1 and E2 respectively represent the upper MOSFET chip and the lower MOSFET chip.
[0082] In one specific embodiment, the source S1 of the first MOSFET chip 200 and the drain D2 of the second MOSFET chip 300 are electrically connected and are jointly connected to the switching node pin SW of the lead frame 100; the drain D1 of the first MOSFET chip 200 is connected to the power input pin Vin of the lead frame 100; the source S2 of the second MOSFET chip 300 is connected to the power ground pin PGND of the lead frame 100; the gate G1 of the first MOSFET chip 200 is connected to the high-side gate drive pin HG of the lead frame 100; and the gate G2 of the second MOSFET chip 300 is connected to the low-side gate drive pin LG of the lead frame 100.
[0083] In this embodiment, the half-bridge topology forms the power stage of the synchronous buck circuit. The Vin pin is used to connect to the input power supply, the PGND pin is used to connect to the power ground, the SW pin is used to connect to the output inductor, and the HG pin and LG pin are used to connect to the output terminals of the high-side driver and the low-side driver, respectively.
[0084] The half-bridge package structure of this application supports symmetrical or asymmetrical MOSFET chip designs for both the upper and lower MOSFETs. In practical applications, it can be flexibly configured according to the circuit operating characteristics: the upper MOSFET is suitable for high-voltage, high-frequency (tens of kHz to 100 kHz) fast switching scenarios; the lower MOSFET can use a chip with lower RDS(ON), utilizing its extremely low on-resistance to replace the traditional freewheeling diode. Compared to the forward voltage drop (VF) of a diode, the low RDS(ON) MOSFET has a significantly lower on-state voltage drop at the same current, thereby greatly reducing conduction losses and improving the overall efficiency of the power supply system.
[0085] The copper clip assembly 400 includes at least two copper clips. The copper clips in the copper clip assembly 400 are fixed by the same reflow soldering process, and the copper clip assembly 400 is mounted using a pick-and-place process. "Pick-and-place" refers to using the vacuum nozzle of an automatic pick-and-place machine to pick up the copper clips and precisely place them on the positions coated with solder paste, preparing for subsequent reflow soldering. This application integrates chip mounting, copper clip assembly setup, and reflow soldering into a single process, completing the melting of all solder paste and the formation of solder joints in one go, avoiding the process complexity and quality inconsistencies caused by multiple reflows or traditional wire bonding. Simultaneously, the pick-and-place method for the copper clips provides high positioning accuracy, and combined with flux cleaning and post-processing such as molding, it can effectively improve packaging yield and product consistency.
[0086] The first MOSFET chip 200 is mounted upright in the first chip mounting area 110, and the second MOSFET chip 300 is mounted either flip-chip or upright in the second chip mounting area 120. Upright mounting means the back side (drain) of the chip faces the lead frame and is attached to the base island using conductive adhesive or solder paste; the active side (source, gate) of the chip faces upwards, and is subsequently connected via wire bonding or copper clips. Its characteristics include: the drain is at the bottom, directly connected to the lead frame, while the source and gate are at the top, requiring additional connections.
[0087] Flip-chip design involves flipping the chip so that the active surfaces (source and gate) face down and directly connecting them to pads on the leadframe via bumps (such as copper pillars with solder or gold bumps). The back of the chip (drain) faces up and is subsequently connected via copper clips or other methods. Features: The source and gate are directly soldered to the bottom via bumps, eliminating the need for wire bonding; the drain is on top, facilitating large-area copper clip connections and improving heat dissipation; suitable for high-density, high-current, and low-parasitic-inductance applications.
[0088] This application allows for upright, flip-chip, or combinations thereof chip mounting methods, combined with large-area coverage of copper clips, achieving a double-sided heat dissipation path on both the top and bottom of the chip. The heat generated during chip operation can be conducted to the PCB not only through the bottom lead frame but also dissipated outwards through the top copper clips and the molding compound (or exposed to air), effectively reducing junction thermal resistance. Compared to traditional single-sided heat dissipation packaging, this invention significantly reduces device temperature rise, increases power density and long-term reliability, improves product heat dissipation characteristics, and reduces device thermal resistance.
[0089] In Embodiments 1 and 2, the source of the first MOSFET chip 200 and the drain of the second MOSFET chip 300 are electrically connected via the copper clip assembly and are jointly connected to at least one external pin 130 of the lead frame. Using copper clips to directly connect the intermediate nodes of the upper and lower MOSFET chips significantly reduces connection resistance and parasitic inductance compared to traditional wire bonding processes. The copper clips have a large cross-sectional area and good thermal conductivity, effectively carrying large currents and quickly conducting the heat generated by the chip to the outside of the package, reducing device temperature rise. Optionally, the intermediate node occupies only one external pin, saving pin resources and facilitating package miniaturization.
[0090] In Embodiment 3, the source of the first MOSFET chip 200 and the drain of the second MOSFET chip 300 are electrically connected through the conductive pattern of the lead frame 100, and are jointly connected to at least one external pin 130 of the lead frame through the copper clip group. The series connection of the upper and lower MOSFET chips is achieved using the conductive pattern of the lead frame itself, eliminating the need for additional copper clips and simplifying the design and assembly of the copper clip group. Optionally, the intermediate node is led out to two external pins through the copper clip group, which can be used in parallel to reduce contact resistance and parasitic inductance, or as two independent connection points, increasing the wiring flexibility of the application. This layout (left-right layout) allows both chips to be manufactured using traditional surface mount technology, reducing process complexity and equipment requirements.
[0091] Example 1: As Figure 1-6 As shown, both the first MOSFET chip 200 and the second MOSFET chip 300 are mounted upright on the lead frame 100; that is, the first MOSFET chip 200 is mounted upright in the first chip mounting area 110, and the second MOSFET chip 300 is mounted upright in the second chip mounting area 120, with the first chip mounting area 110 and the second chip mounting area 120 arranged vertically at intervals on the lead frame 100. The copper clip group 400 includes a first copper clip 410, a second copper clip 420, a third copper clip 430, and a fourth copper clip 440, wherein:
[0092] The first copper clip 410 electrically connects the source S1 of the first MOSFET chip 200 to the drain D2 of the second MOSFET chip 300, and connects to the external pin of the lead frame 100.
[0093] The second copper clip 420 electrically connects the gate G1 of the first MOSFET chip 200 to the external pin of the lead frame 100;
[0094] The third copper clip 430 electrically connects the gate G2 of the second MOSFET chip 300 to the external pin of the lead frame 100;
[0095] The fourth copper clip 440 electrically connects the source S2 of the second MOSFET chip 300 to the external pin of the lead frame 100.
[0096] The drain D1 of the first MOSFET chip 200 is electrically connected to the external pin of the lead frame 100 through the conductive pattern of the lead frame 100. The first copper clip 410, the second copper clip 420, the third copper clip 430, and the fourth copper clip 440 are soldered together in a single process.
[0097] The external pin connected to the drain of the first MOSFET chip 200 is the power input pin (Vin), the external pin connected to the first copper clip 410 is the switching node pin (SW), the external pin connected to the fourth copper clip 440 is the power ground pin (PGND), the external pin connected to the second copper clip 420 is the high-side gate drive pin (HG), and the external pin connected to the third copper clip 430 is the low-side gate drive pin (LG).
[0098] In this embodiment 1, both half-bridge MOSFET chips are soldered onto the lead frame 100, and the product structure is as follows. Figure 1 As shown, a partial circuit diagram is as follows: Figure 5-6 As shown in the figure, the external pins (1)-(10) are shown; the source S1 of E1 and the drain D2 of E2 are connected in series by welding the first copper clip 410, and D2S1 is connected to the external pin (2). The gate G1 of E1 is connected to the external pin (1) by the second copper clip 420. The gate G2 of E2 is connected to the external pin (8) by the third copper clip 430. The source S2 of E2 is connected to the external pins (5)-(7) by the fourth copper clip 440. The drain D1 of E1 is connected to the external pins (3), (4) and (9) by conductive pattern. The external pin (9) is located on the left and right sides of the frame, with one pin on each side. The drain D2 of E2 is connected to the external pin (10) by conductive pattern. The external pin (10) is located on the left and right sides of the frame, with two pins on each side. In this embodiment, there are a total of two chips and four copper clips, which are all welded in one welding process.
[0099] This solution employs dual upright mounting, eliminating the need for specialized equipment and customized chip design required for flip-chip processes. It can directly utilize standard packaging lines, reducing equipment investment and chip selection costs. The four copper clips have a regular shape, facilitating automated assembly and single-pass reflow soldering. The symmetrical layout ensures good thermal balance between the upper and lower transistors, making it suitable for symmetrical half-bridge designs. Direct soldering of the copper clips to the intermediate nodes results in low and consistent parasitic parameters. Therefore, this implementation, while ensuring low parasitic inductance, low on-resistance, and good heat dissipation, highlights the advantages of mature technology, controllable cost, and strong versatility, making it particularly suitable for mass production.
[0100] Example 2: Figure 7-12 As shown, the first MOSFET chip 200 is mounted upright in the first chip mounting area 110, and the second MOSFET chip 300 is mounted flip-chip in the second chip mounting area 120; the first chip mounting area 110 and the second chip mounting area 120 are arranged vertically on the lead frame 100; the copper clip group 400 includes a fifth copper clip 450 and a sixth copper clip 460, wherein,
[0101] The fifth copper clip 450 electrically connects the source S1 of the first MOSFET chip 200 to the drain D2 of the second MOSFET chip 300, and is also electrically connected to the external pin of the lead frame 100.
[0102] The sixth copper clip 460 electrically connects the gate G1 of the first MOSFET chip 200 to the external pin of the lead frame 100.
[0103] The drain D1 of the first MOSFET chip 200, the source S2 of the second MOSFET chip 300, and the gate G2 of the second MOSFET chip 300 are electrically connected to external pins of the lead frame 100 through the conductive pattern of the lead frame 100. Specifically: the external pin connected to the drain of the first MOSFET chip 200 is the power input pin (Vin); the external pin connected to the fifth copper clip 450 is the switching node pin (SW); the external pin connected to the sixth copper clip 460 is the high-side gate drive pin (HG); the external pin connected to the source of the second MOSFET chip 300 is the power ground pin (PGND); and the external pin connected to the gate of the second MOSFET chip 300 is the low-side gate drive pin (LG).
[0104] In this embodiment 2, the upper half-bridge MOSFET chip is soldered upright to the lead frame 100, and the lower half-bridge MOSFET chip is soldered flip-flop to the lead frame 100. The product structure is as follows: Figure 7 As shown, a partial circuit diagram is as follows: Figure 8-9 As shown in the figure, the external pins (1)-(10) are shown; the source S1 of E1 and the drain D2 of E2 are connected in series by welding through the fifth copper clip 450, and D2S1 is connected to the external pins (2), (5)-(7). The gate G1 of E1 is connected to the external pin (1) through the sixth copper clip 460. The gate G2 of E2 is connected to the external pin (8) through the conductive pattern. The source S2 of E2 is connected to the external pin (10) through the conductive pattern. The external pins (10) are located on the left and right sides of the frame, with two pins on each side. The drain D1 of E1 is connected to the external pins (3), (4) and (9) through the conductive pattern. The external pins (9) are located on the left and right sides of the frame, with one pin on each side. In this embodiment, there are a total of two chips and two copper clips, which are all welded in one welding process.
[0105] In this embodiment, the lower transistor chip DIE2 is flip-chip soldered onto a custom frame island, while the upper transistor chip DIE1 is soldered onto the frame. This ensures that the source of E1 and the drain of E2 are both on the top surface of the TOP module. A specially designed fifth copper clip 450 is used for direct soldering to achieve a short circuit. The intermediate node of the half-bridge can be redesigned and implemented on the pins on both sides of the package. The copper clip has high utilization, which helps with heat dissipation. Flip-chip technology is already mature in the industry. To maintain a consistent height of the fifth copper clip 450 at the drain of the lower transistor, a micro-bump matrix is used at the source. Copper bumps are bonded to the copper sheet using solder. The upper transistor is front-chip soldered, and a bump is designed to solder the short-circuit copper sheet to the source of the upper transistor. The fifth copper clip 450 can have a larger design area, effectively providing double-sided heat dissipation for the lower transistor, resulting in excellent heat dissipation performance. In conjunction with the filling of epoxy material for flip chips, the fifth copper clip 450 features an opening design and flow channel avoidance. Combined with epoxy resin that has good flowability, low coefficient of thermal expansion, and high Tg, it enables rapid filling of epoxy resin into the microbump gaps of flip chips, thereby improving the adhesion between the copper clip and the epoxy.
[0106] The source of the second MOSFET chip 300 has a flip-chip bump, which is connected to the lead frame 100 by thermoforming. The bump includes copper pillar bumps or gold bumps, and a solder layer is provided on the surface of the bump. The area of the fifth copper clip 450 is larger than that of the sixth copper clip 460, and the fifth copper clip 450 is configured to carry the main power current of the half-bridge switching node. The gap between the lower MOSFET chip and the lead frame is filled with epoxy resin, and the coefficient of thermal expansion of the epoxy resin matches that of the chip and the lead frame. The fifth copper clip and / or the sixth copper clip have openings or channels for the flow and filling of the epoxy resin.
[0107] In this embodiment, the top surface of the package structure at least partially exposes the fifth copper clip 450 and the sixth copper clip 460 to form a double-sided heat dissipation structure. Both the upper and lower MOSFET chips are vertical N-channel MOSFETs. The lead frame 100, the fifth copper clip 450, the sixth copper clip 460, and the upper and lower MOSFET chips are encapsulated in an epoxy molding compound 600, forming a PDFN shape. The fifth copper clip 450 simultaneously covers the entire source region of the upper MOSFET and the entire drain region of the lower MOSFET. The sixth copper clip 460 only covers the gate region of the upper MOSFET and does not contact the source of the upper MOSFET.
[0108] When the lower MOSFET is flip-chip mounted, its drain faces upwards, allowing for direct heat dissipation through a large copper clip. The upper MOSFET is mounted upright, with its drain dissipating heat through the frame. The top copper clip can be partially exposed or thinly encapsulated, forming a double-sided heat dissipation path, reducing junction thermal resistance and minimizing device temperature rise. Wire bonding completely eliminates the risks of bonding point fatigue and vibration breakage associated with wire bonding. Furthermore, the flip-chip bumps combined with epoxy resin filling at the bottom effectively buffer thermal expansion stress, improving resistance to temperature cycling and mechanical shock. The upper MOSFET's gate is connected using an independent small copper clip, avoiding coupling with the power current path, reducing parasitic inductance in the gate circuit, lowering crosstalk and false triggering risks, and improving EMI characteristics. Upper and lower MOSFETs with the same or different on-resistances can be selected according to application requirements without changing the packaging frame and clip mold, facilitating differentiated applications such as synchronous rectification and totem-pole PFC. All interconnections are completed in a single reflow soldering process (flip-chip bump soldering + copper clip soldering), eliminating the need for multiple wire bonding steps, shortening the process flow, reducing equipment investment, and making it suitable for mass production. In summary, this implementation method, while maintaining the basic functions of a half-bridge, highlights the unique advantages of double-sided heat dissipation, low parasitic parameters, fewer copper clips, and high reliability, making it particularly suitable for power modules with high frequency, high current, and stringent thermal management requirements.
[0109] Example 3: As Figure 13-17 As shown, both the first MOSFET chip 200 and the second MOSFET chip 300 are mounted upright on the lead frame; that is, the first MOSFET chip 200 is mounted upright in the first chip mounting area 110, and the second MOSFET chip 300 is mounted upright in the second chip mounting area 120, with the first chip mounting area 110 and the second chip mounting area 120 arranged at left-right intervals on the lead frame 100. The copper clip group 400 includes a seventh copper clip 470, an eighth copper clip 480, and a ninth copper clip 490, wherein:
[0110] The source S1 of the first MOSFET chip 200 and the drain D2 of the second MOSFET chip 300 are electrically connected through the conductive pattern of the lead frame 100, and the eighth copper clip 480 leads the electrical connection point to the external pin of the lead frame 100.
[0111] The seventh copper clip 470 electrically connects the gate G1 of the first MOSFET chip 200 to the external pin of the lead frame 100.
[0112] The ninth copper clip 490 electrically connects the source S2 of the second MOSFET chip 300 to the external pin of the lead frame 100.
[0113] The drain D1 of the first MOSFET chip 200 is electrically connected to the external pin of the lead frame 100 through the conductive pattern of the lead frame 100.
[0114] The gate G2 of the second MOSFET chip 300 is electrically connected to an external pin of the lead frame 100 via a bonding lead 500. The external pin connected to the drain of the first MOSFET chip 200 is the power input pin (Vin); the external pin connected to the eighth copper clip 480 is the switching node pin (SW); the external pin connected to the ninth copper clip 490 is the power ground pin (PGND); the external pin connected to the seventh copper clip 470 is the high-side gate drive pin (HG); and the external pin connected to the gate of the second MOSFET chip 300 via wire bonding is the low-side gate drive pin (LG).
[0115] In this embodiment 3, the upper half-bridge MOSFET chip is soldered to the lead frame 100, and the lower half-bridge MOSFET chip is soldered to the lead frame 100. The product structure is as follows: Figure 13 As shown, a partial circuit diagram is as follows: Figure 14-15 As shown in the figure, the external pins (1)-(10) are shown; the source S1 of E1 and the drain D2 of E2 are connected in series through a conductive pattern, and are connected to the external pins (2) and (3) through the eighth copper clip 480. The gate G1 of E1 is connected to the external pin (1) through the seventh copper clip 470. The gate G2 of E2 is connected to the external pin (8) through a conductive pattern. The source S2 of E2 is connected to the external pins (5) and (6) through the ninth copper clip 490. The drain D1 of E1 is connected to the external pins (7), (8) and (9) through a conductive pattern. The external pin (9) is located on the left side of the frame. The drain D2 of E2 is connected to the external pin (10) through a conductive pattern. The external pin (10) is located on the right side of the frame. In this embodiment, there are a total of two chips and three copper clips, which are all welded in one welding process.
[0116] In this embodiment, two PADs are provided on the left and right sides inside the lead frame 100. The upper and lower transistor chips are respectively placed on the two PADs, and both the upper and lower transistor chips are soldered to the lead frame 100. In this scheme, the connection of the middle node of the half bridge (the connection between the source of E1 and the drain of E2) is not directly connected through copper clips, but indirectly connected by copper plating on the bottom PAD.
[0117] This embodiment employs a dual upright mounting structure with a left-right layout. The first and second MOSFET chips are mounted in spaced-apart chip mounting areas, with the intermediate node electrically interconnected via the conductive pattern of the lead frame itself. Only an eighth copper clip is needed to lead this node to the switching pin, reducing material costs and assembly complexity. The lower MOSFET gate utilizes a mature wire bonding process, further simplifying the design of the copper clip group. This results in a neat lead frame structure that is easy to stamp and form, with high assembly alignment tolerance, making it particularly suitable for high-volume, low-cost production scenarios. Furthermore, both chips are upright mounted, eliminating the need for flip-chip equipment and underfill processes, allowing direct use of standard packaging lines. Although the heat dissipation performance of this solution is slightly inferior to solutions 1 and 2, its simple frame design, strong process compatibility, and stable production yield give it a significant competitive advantage in cost-sensitive applications with moderate heat dissipation requirements (such as consumer power supplies and motor drives).
[0118] In Embodiments 1 and 3 of this application, both chips of the half-bridge structure are soldered to the lead frame 100. The source of E1 and the drain of E2 are connected via copper clips, as are the corresponding high-voltage side drains and low-voltage side sources with their respective pin terminals. The gate windows of both chips are also connected to the control pins. From the perspective of the packaging company's assembly process, Embodiment 3 is actually the optimal solution, with a simple frame design and convenient assembly. However, from the perspective of market demand and heat dissipation, Embodiment 1 has lower thermal resistance, higher copper utilization on both the top and bottom surfaces of the chip, and is more conducive to heat dissipation at the application end.
[0119] In Example 2, the lower MOSFET chip uses flip-chip bonding. The source of the lower MOSFET chip employs a bump array, with bumps formed from copper pillars, solder, gold bumps, and other materials. High-precision equipment flips the chip with bumps, ensuring precise alignment between the bumps and the pads on the frame. Then, a thermocompression bonding (TCB) process is used, directly bonding the chips together under heat and pressure. After bonding, epoxy resin is used to fill and cure the gap between the chip and the frame. This process compensates for the difference in the coefficient of thermal expansion (CTE) between the chip and the frame, disperses stress, and prevents moisture intrusion, thereby improving the mechanical strength and reliability of the package. After flip-chip bonding, the upper and lower MOSFETs can be interconnected by copper clips, maximizing the copper area on the chip and reducing thermal resistance. If the epoxy thickness on the upper surface is very thin or nonexistent, directly exposing the air creates double-sided heat dissipation, further reducing thermal resistance and improving heat dissipation performance.
[0120] This application combines the design features of three schemes to provide an internal design method for symmetrical and asymmetrical MOS, all of which can be customized according to actual applications, especially for DFN or PDFN series package development. Regarding the two MOS in a half-bridge, the gate window size is generally coplanar with the source in vertical MOS. A larger gate window will result in a smaller source window. Sometimes, to facilitate copper clip bonding processes, the gate window is intentionally enlarged, which will cause the source window to become smaller. Example 3 provides a gate wirebonding process.
[0121] Taking the product in Example 2 as an example, such as Figure 18 As shown, its manufacturing method includes the following steps:
[0122] Step 1: Perform the first printing of solder paste in a predetermined area of the lead frame 100 to form a solder paste layer 610;
[0123] Step 2: Flip-mount the second MOSFET chip 300, i.e., the lower MOSFET chip, onto the second chip mounting area 120;
[0124] Step 3: Mount the first MOSFET chip 200 (i.e., the upper MOSFET chip) onto the first chip mounting area 110.
[0125] Step 4: Apply adhesive to the top of the upper and lower transistor chips;
[0126] Step 5: Place the fifth copper clip 450 into the preset position;
[0127] Step 6: Place the sixth copper clip 460° into the preset position;
[0128] Step 7: Use the plastic encapsulation shell 600 to encapsulate, cut, and test to obtain the half-bridge MOSFET package structure.
[0129] It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application shall be determined by the appended claims.
Claims
1. A method of packaging a half-bridge MOSFET, the method comprising: Includes the following steps: A lead frame (100) is provided: the lead frame (100) has a first chip mounting area (110), a second chip mounting area (120), a plurality of external pins (130), and a conductive pattern formed thereon; First soldering: Apply solder paste to the first chip mounting area (110) and / or the second chip mounting area (120); Chip mounting: The first MOSFET chip (200) is mounted in the first chip mounting area (110), and the second MOSFET chip (300) is mounted in the second chip mounting area (120). Second soldering: Apply solder paste to the top electrodes of the first MOSFET chip (200) and / or the second MOSFET chip (300), as well as the connection area of the lead frame (100); Placing the copper clip assembly (400): The copper clip assembly (400) is placed on top of the first MOSFET chip (200) and / or the second MOSFET chip (300), and the copper clip assembly (400) is in contact with the top electrode of the first MOSFET chip (200) and / or the second MOSFET chip (300), as well as the connection area of the lead frame (100); Forming a half-bridge topology connection: The copper clip group (400) and the conductive pattern together form a conductive connection path, which enables the first MOSFET chip (200) and the second MOSFET chip (300) to form a half-bridge topology connection, and the drain, source, gate and intermediate node of the half-bridge topology are respectively led out to the external pin (130) of the lead frame. Reflow soldering: The solder paste is melted to fix the copper clip assembly (400), the first MOSFET chip (200), the second MOSFET chip (300) to the lead frame (100); Post-processing: The semi-finished product after reflow soldering is post-processed to obtain a half-bridge MOSFET package structure. The post-processing includes flux cleaning, encapsulation, molding separation, testing, and packaging.
2. The half-bridge MOSFET packaging method of claim 1, wherein: The first MOSFET chip (200) is the upper MOSFET chip, and the second MOSFET chip (300) is the lower MOSFET chip.
3. The half-bridge MOSFET packaging method according to claim 1, characterized in that: The copper clip assembly (400) includes at least two copper clips. The copper clips in the copper clip assembly (400) are fixed by the same reflow soldering process. The copper clip assembly (400) is mounted using a pick-and-place process.
4. The half-bridge MOSFET packaging method according to claim 1, characterized in that: The first MOSFET chip (200) is mounted upright in the first chip mounting area (110), and the second MOSFET chip (300) is mounted flip-flop or upright in the second chip mounting area (120).
5. The half-bridge MOSFET packaging method according to claim 1, characterized in that: The source of the first MOSFET chip (200) and the drain of the second MOSFET chip (300) are electrically connected through the copper clip group and are connected together to at least one external pin (130) of the lead frame.
6. The half-bridge MOSFET packaging method of claim 1, wherein: The source of the first MOSFET chip (200) and the drain of the second MOSFET chip (300) are electrically connected through the conductive pattern of the lead frame (100) and are connected together to at least one external pin (130) of the lead frame.
7. The half-bridge MOSFET packaging method of claim 1, wherein: The first MOSFET chip (200) and the second MOSFET chip (300) are both mounted upright on the lead frame (100); the copper clip assembly (400) includes a first copper clip (410), a second copper clip (420), a third copper clip (430), and a fourth copper clip (440), wherein: The first copper clip (410) electrically connects the source of the first MOSFET chip (200) to the drain of the second MOSFET chip (300) and connects to the external pin of the lead frame (100); The second copper clip (420) electrically connects the gate of the first MOSFET chip (200) to the external pin of the lead frame (100); The third copper clip (430) electrically connects the gate of the second MOSFET chip (300) to the external pin of the lead frame (100); The fourth copper clip (440) electrically connects the source of the second MOSFET chip (300) to the external pin of the lead frame (100); The drain of the first MOSFET chip (200) is electrically connected to the external pin of the lead frame (100) through the conductive pattern of the lead frame (100).
8. The half-bridge MOSFET packaging method of claim 1, wherein: The first MOSFET chip (200) is mounted upright in the first chip mounting area (110), and the second MOSFET chip (300) is mounted flip-flop in the second chip mounting area (120); the copper clip group (400) includes a fifth copper clip (450) and a sixth copper clip (460), wherein, The fifth copper clip (450) electrically connects the source of the first MOSFET chip (200) to the drain of the second MOSFET chip (300), and is also electrically connected to the external pin of the lead frame (100). The sixth copper clip (460) electrically connects the gate of the first MOSFET chip (200) to the external pin of the lead frame (100); The drain of the first MOSFET chip (200), the source of the second MOSFET chip (300), and the gate of the second MOSFET chip (300) are electrically connected to the external pins of the lead frame (100) through the conductive pattern of the lead frame (100).
9. The half-bridge MOSFET packaging method of claim 8, wherein: The source of the second MOSFET chip (300) is provided with a flip-chip bump, which is connected to the lead frame (100) by thermo-bonding. The bump includes a copper pillar bump or a gold bump, and the surface of the bump is provided with a solder layer. The area of the fifth copper clip (450) is larger than the area of the sixth copper clip (460), and the fifth copper clip (450) is configured to carry the main power current of the half-bridge switching node.
10. The half-bridge MOSFET packaging method of claim 1, wherein: The first MOSFET chip (200) and the second MOSFET chip (300) are both mounted upright on the lead frame; the copper clip group (400) includes a seventh copper clip (470), an eighth copper clip (480), and a ninth copper clip (490), wherein: The source of the first MOSFET chip (200) and the drain of the second MOSFET chip (300) are electrically connected through the conductive pattern of the lead frame (100), and the electrical connection point is led out to the external pin of the lead frame (100) by the eighth copper clip (480). The seventh copper clip (470) electrically connects the gate of the first MOSFET chip (200) to the external pin of the lead frame (100); The ninth copper clip (490) electrically connects the source of the second MOSFET chip (300) to the external pin of the lead frame (100); The drain of the first MOSFET chip (200) is electrically connected to the external pin of the lead frame (100) through the conductive pattern of the lead frame (100); The gate of the second MOSFET chip (300) is electrically connected to the external pin of the lead frame (100) via a bonding lead (500).