Semiconductor package and method of manufacturing the same
By designing the structure of the substrate, memory chip, control chip, encapsulant, conductive pillars, and redistribution layer, the problem of difficult packaging in existing technologies has been solved, achieving low-cost and high-yield semiconductor packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ORIENT SEMICONDUCTOR ELECTRONICS LTD
- Filing Date
- 2025-01-24
- Publication Date
- 2026-07-31
AI Technical Summary
The packaging of storage and control chips in existing flash memory cards requires surface mount technology, which makes operation difficult and requires the use of three-dimensional steel plates, increasing costs and complexity.
The structure design employs a substrate, memory chip, control chip, encapsulant, conductive pillars, and redistribution layer, and forms conductive blocks, solder balls, and other electrical connections through the fabrication process, simplifying the packaging process.
This reduces the manufacturing cost of semiconductor packages and improves yield.
Smart Images
Figure CN122497408A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor package and its manufacturing method, and more particularly to a flash memory package and its manufacturing method. Background Technology
[0002] Currently, the storage and control chips in flash memory cards are packaged into a single package and then mounted onto the package of the system chip.
[0003] However, this design uses surface bonding technology, which is not only difficult to work with, but also requires the use of three-dimensional steel plates. Summary of the Invention
[0004] In view of this, the present invention provides a semiconductor package and a method for manufacturing the same, in order to solve the above problems.
[0005] To achieve the above objectives, the semiconductor package of the present invention includes: a substrate having opposing first and second surfaces; a memory chip disposed on the first surface of the substrate and electrically connected to the substrate; a control chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate and covering the control chip and the memory chip; a plurality of conductive pillars disposed on the first surface of the substrate and electrically connected to the substrate; a redistribution layer formed on the encapsulant and electrically connected to the control chip and the plurality of conductive pillars; and a processing chip disposed on the second surface of the substrate and electrically connected to the substrate.
[0006] The method for manufacturing a semiconductor package of the present invention includes: preparing a substrate having opposing first and second surfaces; disposing a memory chip on the first surface of the substrate and electrically connecting the memory chip to the substrate; forming a plurality of first conductive blocks on a control chip; disposing the control chip on the first surface of the substrate; disposing a plurality of conductive pillars on the first surface of the substrate and electrically connecting the plurality of conductive pillars to the substrate; forming an encapsulant on the first surface of the substrate to cover the control chip, the memory chip, and the plurality of first conductive blocks; grinding the encapsulant to expose the plurality of first conductive blocks and the plurality of conductive pillars; forming a redistribution layer on the encapsulant and electrically connecting the redistribution layer to the plurality of first conductive blocks and the plurality of conductive pillars; and disposing a processing chip on the second surface of the substrate and electrically connecting the processing chip to the substrate.
[0007] The semiconductor package according to the present invention has lower manufacturing costs and higher yield.
[0008] To make the above and other objects, features and advantages of the present invention more apparent, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0009] The nature of this disclosure is best understood by reading in conjunction with the accompanying drawings and the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of explanation.
[0010] Figure 1 This is a schematic diagram of the semiconductor package of the present invention.
[0011] Figures 2 to 10 show Figure 1 The method for manufacturing the semiconductor package shown.
[0012] Symbol explanation:
[0013] 110 substrate
[0014] 111 First Surface
[0015] 112 Second Surface
[0016] 113 Conductive circuit
[0017] 114 Conductive circuit
[0018] 115 Electroplated Through Hole
[0019] 120 control chip
[0020] 121 First Conductive Block
[0021] 130 memory chip
[0022] 132 wire bonding
[0023] 140 conductive pillar
[0024] 141 First Surface
[0025] 142 Second Surface
[0026] 150 sealing colloid
[0027] 151 First Surface
[0028] 152 Second Surface
[0029] 153 Third Surface
[0030] 160 Passive Components
[0031] 170 Rewiring Layer
[0032] 180 processing chip
[0033] 182 Second Conductive Block
[0034] 190 Tin Balls Detailed Implementation
[0035] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first member on or above a second member may include embodiments where the first member and the second member are formed in direct contact, and may also include embodiments where additional members may be formed between the first member and the second member such that the first member and the second member are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0036] In addition, for ease of description, spatial relative terms such as “under,” “below,” “lower,” “overlapping,” “upper,” and similar terms may be used herein to describe the relationship between one component or member and one or more components or members as illustrated in the figures. Besides the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.
[0037] Please refer to Figure 1 The semiconductor package of the present invention includes a substrate 110 having a first surface 111 and a second surface 112 opposite to each other, and the first surface 111 and the second surface 112 are located in different planes. Conductive lines 113 and 114 are formed on the first surface 111 and the second surface 112 of the substrate 110, respectively, and the conductive lines 113 and 114 are electrically connected by a plurality of conductive plated vias 115 penetrating the first surface 111 and the second surface 112 of the substrate 110.
[0038] In one embodiment, the substrate 110 may be a single-layer or multi-layer circuit board, a redistribution layer (RDL) substrate, or a glass substrate.
[0039] One or more memory dies, such as multiple memory dies, are disposed on the first surface 111 of the substrate 110. Each memory die 130 has an active side and a back side opposite to the active side. The multiple memory dies 130 can be stacked vertically or in a stepped manner on the substrate 110 and are adhered to the substrate 110 with adhesive or epoxy resin. When the multiple memory dies 130 are stacked in a stepped manner on the substrate 110, they can be electrically connected to the conductive lines 113 on the first surface 111 of the substrate 110 via multiple bonding wires 132.
[0040] A controller die 120 is also disposed on the first surface 111 of the substrate 110, which has an active side and a back side opposite to the active side. The back side of the controller die 120 is adhered to the first surface 111 of the substrate 110 with an adhesive or epoxy resin.
[0041] The control chip 120 has a plurality of first conductive blocks 121 on its active surface, which are electrically connected to the control chip 120. The plurality of first conductive blocks 121 can be metal bumps, formed on the control chip 120 using a bumping process. The plurality of first conductive blocks 121 can be composed of eutectic alloy, lead-free, high-lead materials, or copper pillars.
[0042] Passive components 160 may be disposed on the first surface 111 of the substrate 110 as needed.
[0043] An encapsulant 150 is formed on the first surface 111 of the substrate 110, which covers the control chip 120, the plurality of memory chips 130, the passive components 160, and the plurality of bonding wires 132. The encapsulant 150 does not completely cover the plurality of first conductive blocks 121, and each of the plurality of first conductive blocks 121 is partially exposed from the encapsulant 150.
[0044] The encapsulant 150 has a first surface 151, a second surface 152, and a plurality of third surfaces 153. The first surface 151 and the second surface 152 are located in different planes, and the plurality of third surfaces 153 connect the first surface 151 and the second surface 152. The second surface 152 of the encapsulant 150 is in contact with the first surface 111 of the substrate 110.
[0045] A plurality of conductive pillars 140 are disposed on the first surface 111 of the substrate 110, surrounding the encapsulant 150 and contacting the plurality of third surfaces 153 of the encapsulant 150. Each of the plurality of conductive pillars 140 has a first surface 141 and a second surface 142, which are located in different planes. The plurality of conductive pillars 140 are vertically fixed on the substrate 110 and electrically connected to the conductive lines 113 on the first surface 111. The second surfaces 142 of the plurality of conductive pillars 140 are in contact with the first surface 111 of the substrate 110. The first surfaces 141 of the plurality of conductive pillars 140 are not covered by the encapsulant 150.
[0046] A redistribution layer 170 is formed on the first surface 151 of the encapsulant 150, wherein conductive lines are arranged. The redistribution layer 170 is in contact with and electrically connected to the first surfaces 141 of the plurality of first conductive blocks 121 and the plurality of conductive pillars 140. The control chip 120 is electrically connected to the redistribution layer 170 through the plurality of first conductive blocks 121.
[0047] A processor die 180 is disposed on the second surface 112 of the substrate 110, having an active surface and a back surface opposite to the active surface. A plurality of second conductive blocks 182 are disposed on the active surface of the processor die 180, and are electrically connected to the processor die 180. The plurality of second conductive blocks 182 are sandwiched between the processor die 180 and the substrate 110. The processor die 180 is electrically connected to a plurality of conductive posts 140 through the plurality of second conductive blocks 182 and conductive lines 113 and 114 on the first surface 111 and the second surface 112 of the substrate 110.
[0048] The redistribution layer 170 has a plurality of solder balls 190 electrically connected to it. The plurality of memory chips 130 are electrically connected to the plurality of solder balls 190 via the plurality of bonding wires 132, the substrate 110, the plurality of conductive pillars 140, and the redistribution layer 170. The processing chip 180 is electrically connected to the plurality of solder balls 190 via the plurality of second conductive blocks 182, the substrate 110, the plurality of conductive pillars 140, and the redistribution layer 170. The control chip 120 is electrically connected to the plurality of solder balls 190 via the plurality of first conductive blocks 121 and the redistribution layer 170. In this manner, the plurality of memory chips 130, the control chip 120, and the processing chip 180 can be electrically connected to external circuits via the plurality of solder balls 190.
[0049] Please refer to Figures 2 to 10 Its display Figure 1 The method for manufacturing the semiconductor package shown is illustrated. Figure 2 As shown, a substrate 110 is prepared, having a first surface 111 and a second surface 112 opposite to each other, and the first surface 111 and the second surface 112 are located in different planes. Conductive lines 113 and 114 are respectively formed on the first surface 111 and the second surface 112 of the substrate 110, and the conductive lines 113 and 114 are electrically connected by a plurality of conductive plated through holes 115 penetrating the first surface 111 and the second surface 112 of the substrate 110.
[0050] In one embodiment, the substrate 110 may be a single-layer or multi-layer circuit board, a redistribution layer (RDL) substrate, or a glass substrate.
[0051] A plurality of conductive pillars 140 are disposed on the first surface 111 of the substrate 110. Each of the plurality of conductive pillars 140 has a first surface 141 and a second surface 142 facing each other, and the first surface 141 and the second surface 142 are located in different planes. The plurality of conductive pillars 140 are vertically fixed on the substrate 110 and electrically connected to the plurality of conductive lines 113 on the first surface 111. The second surfaces 142 of the plurality of conductive pillars 140 are in contact with the first surface 111 of the substrate 110.
[0052] Passive components 160 may be disposed on the first surface 111 of the substrate 110 as needed.
[0053] like Figure 3 As shown, a control chip 120 is then prepared, which has an active surface and a back surface opposite to the active surface. A plurality of first conductive blocks 121 are formed on the active surface of the control chip 120, and are electrically connected to the control chip 120. The plurality of first conductive blocks 121 can be metal bumps, formed on the control chip 120 using a bumping process. The plurality of first conductive blocks 121 can be composed of eutectic alloy, lead-free, high-lead materials, or copper pillars.
[0054] like Figure 4 As shown, the back side of the control chip 120 is then adhered to the first surface 111 of the substrate 110 using adhesive or epoxy resin.
[0055] like Figure 5 As shown, one or more, for example, a plurality of memory chips 130 are then stacked in a stepped manner on the first surface 111 of the substrate 110 and bonded to the substrate 110 with an adhesive or epoxy resin. Each of the plurality of memory chips 130 has an active side and a back side opposite to the active side. The plurality of memory chips 130 are electrically connected to conductive lines 113 on the first surface 111 of the substrate 110 via a plurality of bonding wires 132.
[0056] like Figure 6 As shown, an encapsulant 150 is then formed on the first surface 111 of the substrate 110 to cover the control chip 120, the plurality of memory chips 130, the passive components 160, the plurality of first conductive blocks 121 and the plurality of bonding wires 132.
[0057] like Figure 7 As shown, a portion of the encapsulant 150 is then removed by grinding to expose the first surfaces 141 of the plurality of first conductive blocks 121 and the plurality of conductive pillars 140.
[0058] After the sealant 150 is partially removed, it has a first surface 151, a second surface 152, and a plurality of third surfaces 153. The first surface 151 and the second surface 152 are located in different planes, and the plurality of third surfaces 153 connect the first surface 151 and the second surface 152.
[0059] The second surface 152 of the encapsulant 150 is in contact with the first surface 111 of the substrate 110, and the plurality of conductive pillars 140 surround the encapsulant 150 and are in contact with the plurality of third surfaces 153 of the encapsulant 150.
[0060] like Figure 8 As shown, a redistribution layer 170 is then formed on the first surface 151 of the encapsulant 150, wherein conductive lines are arranged. The redistribution layer 170 contacts and is electrically connected to the first surfaces 141 of the plurality of first conductive blocks 121 and the plurality of conductive pillars 140. The control chip 120 is electrically connected to the redistribution layer 170 through the plurality of first conductive blocks 121.
[0061] like Figure 9 As shown, a plurality of solder balls 190 are then formed on the redistribution layer 170, which are electrically connected to the redistribution layer 170.
[0062] like Figure 10 As shown, a processing chip 180 is then prepared, which has an active surface and a back surface opposite to the active surface. A plurality of second conductive blocks 182 are formed on the active surface of the processing chip 180, which are electrically connected to the processing chip 180.
[0063] Then invert Figure 9 The package shown attaches the processing chip 180 to the second surface 112 of the substrate 110 using flip-chip technology, with the plurality of second conductive blocks 182 sandwiched between the processing chip 180 and the substrate 110. The processing chip 180 is electrically connected to the plurality of conductive posts 140 through the plurality of second conductive blocks 182 and conductive lines 113 and 114 on the first surface 111 and the second surface 112 of the substrate 110.
[0064] In the semiconductor package of the present invention, the plurality of memory chips 130 are electrically connected to the plurality of solder balls 190 via the plurality of bonding wires 132, the substrate 110, the plurality of conductive pillars 140, and the redistribution layer 170; the processing chip 180 is electrically connected to the plurality of solder balls 190 via the plurality of second conductive blocks 182, the substrate 110, the plurality of conductive pillars 140, and the redistribution layer 170; and the control chip 120 is electrically connected to the plurality of solder balls 190 via the plurality of first conductive blocks 121 and the redistribution layer 170. In this manner, the plurality of memory chips 130, the control chip 120, and the processing chip 180 are electrically connected to an external circuit via the plurality of solder balls 190.
[0065] The semiconductor package according to the present invention has low manufacturing cost and high yield.
[0066] While the present invention has been disclosed through the foregoing embodiments, it is not intended to limit the invention. Anyone skilled in the art to which this invention pertains can make various modifications and alterations without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.
Claims
1. A semiconductor package, characterized in that, Include: A substrate having a first surface and a second surface opposite to each other; A memory chip is disposed on the first surface of the substrate and electrically connected to the substrate; A control chip is disposed on the first surface of the substrate; An encapsulant is formed on the first surface of the substrate and covers the control chip and the memory chip; A plurality of conductive pillars are disposed on the first surface of the substrate and electrically connected to the substrate; A redistribution layer is formed on the encapsulant and electrically connected to the control chip and the plurality of conductive pillars; as well as A processing chip is disposed on the second surface of the substrate and electrically connected to the substrate.
2. The semiconductor package as described in claim 1, characterized in that, Also includes: A plurality of first conductive blocks are sandwiched between the control chip and the redistribution layer, and are electrically connected to the control chip and the redistribution layer.
3. The semiconductor package as described in claim 1, characterized in that, Also includes: A plurality of second conductive blocks are sandwiched between the processing chip and the substrate, and are electrically connected to the processing chip and the substrate.
4. The semiconductor package as described in claim 1, characterized in that, The plurality of conductive pillars are arranged around the encapsulant.
5. The semiconductor package as described in claim 1, characterized in that, Also includes: Multiple bonding wires are disposed on the first surface of the substrate and electrically connected to the memory chip and the substrate.
6. The semiconductor package as described in claim 1, characterized in that, Also includes: A plurality of solder balls are formed on the redistribution layer.
7. A method for manufacturing a semiconductor package, characterized in that, Include: Prepare a substrate having opposing first and second surfaces; A memory chip is disposed on the first surface of the substrate and electrically connected to the substrate; A complex first conductive block is formed on the control chip; The control chip is disposed on the first surface of the substrate; A plurality of conductive pillars are disposed on the first surface of the substrate, and the plurality of conductive pillars are electrically connected to the substrate; An encapsulant is formed on the first surface of the substrate to cover the control chip, the memory chip, and the plurality of first conductive blocks; The encapsulant is ground to expose the plurality of first conductive blocks and the plurality of conductive pillars; A redistribution layer is formed on the encapsulant, and the redistribution layer is electrically connected to the plurality of first conductive blocks and the plurality of conductive pillars; as well as A processing chip is disposed on the second surface of the substrate and electrically connected to the substrate.
8. The method for manufacturing a semiconductor package as described in claim 7, characterized in that, Also includes: A plurality of second conductive blocks are disposed between the processing chip and the substrate.
9. The method for manufacturing a semiconductor package as described in claim 7, characterized in that, Also includes: Multiple bonding wires are disposed on the first surface of the substrate, and the multiple bonding wires are electrically connected to the memory chip and the substrate.
10. The method for manufacturing a semiconductor package as described in claim 7, characterized in that, Also includes: Multiple solder balls are formed on the redistribution layer.