Semiconductor structure and method of manufacturing the same, electronic device
By using different packaging layers to package different chips in a semiconductor structure, the problem of differences in the upper surface during packaging is solved, achieving differentiated chip packaging and good heat dissipation, and improving chip integration and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2025-01-26
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies struggle to package multiple chips due to surface variations, resulting in poor packaging and heat dissipation, which limits chip integration and performance improvement.
Different chips are packaged using different packaging layers. The first chip and the second chip are packaged by the first packaging layer and the second packaging layer, respectively, so that there is a difference in the upper surface of the chip. This exposes part of the chip surface to achieve a good heat dissipation effect, and the chip interconnection and support are achieved through the intermediary layer.
It enables differentiated packaging of multiple chips, improves chip design freedom, ensures good heat dissipation and packaging effects, and meets the requirements of high integration and high performance.
Smart Images
Figure CN122497409A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor structures and their fabrication methods, and electronic devices. Background Technology
[0002] As the demands for high performance, high integration, and low power consumption in electronic devices continue to increase, the requirements for chip integration and performance are also rising. 2.5D (2.5-dimensional) packaging technology and 3D (3-dimensional) packaging technology have become important technical routes for improving chip integration and performance.
[0003] Semiconductor structures typically contain multiple chips and encapsulating materials that surround them. To ensure good encapsulation and heat dissipation for all chips, their top surfaces are usually flush. Therefore, it is currently difficult to encapsulate multiple chips with different top surfaces. Summary of the Invention
[0004] Embodiments of this application provide a semiconductor structure and its fabrication method, as well as an electronic device, for packaging multiple chips with different upper surfaces.
[0005] In a first aspect, a semiconductor structure is provided. The semiconductor structure includes: a first interposer, a second interposer, a first chip, a second chip, a first encapsulation layer, and a second encapsulation layer. The second interposer is disposed on one side of the first interposer. The first chip is disposed on the side of the second interposer away from the first interposer, and the first chip and the first interposer are connected through the second interposer. The first encapsulation layer is disposed around the first chip and exposes at least a first surface of the first chip away from the first interposer; the first encapsulation layer can reduce damage to the first chip and inhibit oxidation of the first chip, etc. The second chip is disposed on one side of the first interposer and is connected to the first interposer; the first chip and the second chip can be interconnected. The second encapsulation layer is disposed around the second chip and exposes at least a second surface of the second chip away from the first interposer; the second encapsulation layer can reduce damage to the second chip and inhibit oxidation of the second chip, etc.
[0006] In the aforementioned semiconductor structure, a first encapsulation layer is disposed around a first chip, exposing at least a first surface of the first chip away from the first interposer, meaning at least a portion of the first chip is located within the first encapsulation layer. A second encapsulation layer is disposed around a second chip, exposing at least a second surface of the second chip away from the first interposer, meaning at least a portion of the second chip is located within the second encapsulation layer. By using different encapsulation layers to encapsulate different chips, it is possible to encapsulate multiple chips with different upper surfaces, and all upper surfaces of the multiple chips can be exposed, resulting in good heat dissipation for all chips. This increases the design freedom of chips in the semiconductor structure, facilitating the customization of multiple chips for different packaging needs.
[0007] In one possible implementation, the surface of the second encapsulation layer furthest from the first interposer is designated as the third surface, and the distance between the third surface and the first interposer is less than or equal to the distance between the first surface and the first interposer. In other words, the third surface of the second encapsulation layer is lower than or flush with the first surface of the first chip. This helps ensure that the second encapsulation layer does not cover the first surface of the first chip, thus providing the first chip with good heat dissipation.
[0008] In one possible implementation, the distance between the first surface and the first interposer is greater than the distance between the second surface and the first interposer. In other words, the first surface of the first chip can be higher than the second surface of the second chip.
[0009] In one possible implementation, the first chip is located within a first packaging layer with its first surface exposed; and the second chip is located within a second packaging layer with its second surface exposed.
[0010] With the first surface of the first chip higher than the second surface of the second chip, the first chip is located within the first encapsulation layer. This means the first encapsulation layer can encapsulate the entire area of the first chip, resulting in excellent encapsulation performance. Furthermore, the exposed first surface provides superior heat dissipation. Similarly, with the second chip located within the second encapsulation layer and its second surface exposed, the second chip exhibits both excellent encapsulation and heat dissipation performance.
[0011] In one possible implementation, the region of the first chip near the second interposer is in contact with the first encapsulation layer, and the region of the first chip away from the second interposer is in contact with the second encapsulation layer; wherein a portion of the first chip is located within the first and second encapsulation layers.
[0012] When the first surface of the first chip is higher than the second surface of the second chip, the first encapsulation layer can encapsulate the area of the first chip near the second interposer, and the second encapsulation layer can encapsulate the area of the first chip near the second interposer; that is, different encapsulation layers can be used to encapsulate the first chip. Furthermore, because the first surface of the first chip is higher than the second surface of the second chip, even if the second encapsulation layer completely encapsulates the second chip (i.e., the third surface of the second encapsulation layer is flush with the second surface of the second chip), only a portion of the first chip can be encapsulated by both the first and second encapsulation layers.
[0013] In one possible implementation, the distance between the first surface and the first interposer is less than the distance between the second surface and the first interposer. In other words, the first surface of the first chip can be lower than the second surface of the second chip.
[0014] In one possible implementation, the surface of the first encapsulation layer away from the first interposer is flush with the surface of the second encapsulation layer away from the first interposer.
[0015] When the first surface of the first chip is lower than the second surface of the second chip, when the first encapsulation layer encapsulates a portion of the first chip, the fourth surface of the first encapsulation layer can be flush with the third surface of the second encapsulation layer.
[0016] In one possible implementation, the region of the first chip near the second interposer contacts the first encapsulation layer, and the region of the first chip away from the second interposer contacts the second encapsulation layer; wherein the first chip is located within the first and second encapsulation layers, and the first surface is exposed.
[0017] When the first surface of the first chip is lower than the second surface of the second chip, the first encapsulation layer can encapsulate the area of the first chip near the second interposer, and the second encapsulation layer can encapsulate the area of the first chip near the second interposer; that is, different encapsulation layers can be used to encapsulate the first chip. Furthermore, since the first surface of the first chip is lower than the second surface of the second chip, when the second encapsulation layer encapsulates a portion of the second chip, it can achieve encapsulation of the entire area of the first chip, while exposing the first surface.
[0018] In one possible implementation, the second interposer is made of a conductive metal and is connected to both the first interposer and the first chip. In some examples, the second interposer may be made of copper or other metals with conductive properties.
[0019] The second interposer has superior rigidity, which can support the first packaging layer and the first chip. In addition, the second interposer has better conductivity, which can reduce the signal loss when passing through the second interposer.
[0020] In one possible implementation, the second interposer layer includes an organic material layer and conductive elements disposed within the organic material layer; the conductive elements are connected to the first interposer layer and the first chip, respectively. The conductive elements can be metal circuits and / or conductive pillars penetrating the organic material layer. This is a simple implementation.
[0021] In some examples, the semiconductor structure also includes a third chip, at least a portion of which is located within a second encapsulation layer. The second encapsulation layer can encapsulate part or all of the third chip, and can reduce damage to the third chip and inhibit oxidation of the third chip. The third chip and the second chip are connected through a first interposer layer, meaning that the first chip, the second chip, and the third chip can be interconnected. In other words, the second encapsulation layer can encapsulate multiple chips.
[0022] In some examples, the semiconductor structure also includes a fourth chip, at least a portion of which is located within a first encapsulation layer. The first encapsulation layer can encapsulate part or all of the fourth chip, and can reduce damage to the fourth chip and inhibit oxidation. The fourth chip and the first chip are connected through a second interposer layer, meaning that the first, second, and fourth chips can be interconnected. In other words, the first encapsulation layer can encapsulate multiple chips.
[0023] In one possible implementation, the semiconductor structure further includes a heat sink and a support pillar. The heat sink is disposed on the side of the first chip away from the first interposer layer. The heat sink can dissipate heat for the first chip and the second chip in the semiconductor structure. The support pillar extends along the thickness direction and supports the heat sink, which can alleviate the impact of the heat sink on the first chip and the second chip, thereby making the semiconductor structure have better reliability.
[0024] In some examples, a conductive element is provided in the first interposer layer, which may be a metal line and / or a conductive post that penetrates the first interposer layer.
[0025] In some examples, a first dielectric layer is disposed on the side of the first interposer layer away from the second encapsulation layer. This first dielectric layer can be a redistribution layer. By providing the first dielectric layer, the risk of warping of the second encapsulation layer can be mitigated.
[0026] In some examples, a second dielectric layer can be placed on the side of the second interposer layer away from the first encapsulation layer. This second dielectric layer can be a redistribution layer. By including a second dielectric layer, the risk of warping of the first encapsulation layer can be mitigated.
[0027] In a second aspect, a method for fabricating a semiconductor structure is provided. The method includes: attaching a first chip to a second interposer; encapsulating at least a portion of the first chip using a first encapsulation layer to obtain an encapsulation structure formed by the first chip, the first encapsulation layer, and the second interposer; attaching the encapsulation structure and the second chip to the first interposer; and encapsulating at least a portion of the second chip using the second encapsulation layer.
[0028] In the above method, a first encapsulation layer is first used to encapsulate a first chip on a second interposer layer to obtain an encapsulation structure. Then, the encapsulation structure and the second chip are connected to the first interposer layer. This allows for interconnection between the first and second chips and also provides support for the encapsulation of the second chip. Finally, a second encapsulation layer is used to encapsulate the second chip on the first interposer layer. Thus, by using different encapsulation layers to encapsulate different chips, it is possible to encapsulate multiple chips with different upper surfaces, and all the upper surfaces of these chips can be exposed, resulting in good heat dissipation for all chips. This increases the design freedom of chips in semiconductor structures and facilitates the customization of multiple chip packages.
[0029] In one possible implementation, at least a portion of encapsulating the first chip with a first encapsulation layer includes: encapsulating a region of the first chip near the second interposer with the first encapsulation layer; after connecting the semiconductor structure and the second chip to the first interposer, the method further includes: encapsulating a region of the first chip away from the second interposer with a second encapsulation layer.
[0030] The packaging of the first chip can be achieved by first using a first packaging layer to package the area of the first chip close to the second interposer layer, and then using a second packaging layer to package the area of the first chip far from the second interposer layer.
[0031] Thirdly, an electronic device is provided. The electronic device includes a circuit board and a semiconductor structure as described in any possible implementation of the first aspect, or a semiconductor structure prepared by the method described in any possible implementation of the second aspect; the semiconductor structure is disposed on the circuit board.
[0032] The technical effects brought about by the third aspect can be referred to the technical effects brought about by different implementations of the first or second aspect mentioned above, and will not be repeated here. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 Schematic diagrams of the structures of some electronic devices provided in the embodiments of this application;
[0035] Figure 2 This is a schematic diagram illustrating a semiconductor structure according to an embodiment of this application;
[0036] Figure 3 This is a schematic diagram illustrating the compression packaging of a chip, as shown in an embodiment of this application.
[0037] Figure 4 Schematic diagrams of some semiconductor structures provided in the embodiments of this application;
[0038] Figure 5 Schematic diagrams of other semiconductor structures provided in the embodiments of this application;
[0039] Figure 6 Schematic diagrams of some other semiconductor structures provided in the embodiments of this application;
[0040] Figure 7 Schematic diagrams of some semiconductor structures provided in the embodiments of this application;
[0041] Figure 8 Schematic diagrams of other semiconductor structures provided in the embodiments of this application;
[0042] Figure 9 Schematic diagrams of some other semiconductor structures provided in the embodiments of this application;
[0043] Figure 10 Schematic diagrams of some semiconductor structures provided in the embodiments of this application;
[0044] Figure 11 Schematic diagrams of other semiconductor structures provided in the embodiments of this application;
[0045] Figure 12 Schematic diagrams of some other semiconductor structures provided in the embodiments of this application;
[0046] Figure 13 This application provides schematic diagrams showing the positions of chips and circuit boards in some semiconductor structures.
[0047] Figure 14 Schematic diagrams of some semiconductor structures provided in the embodiments of this application;
[0048] Figure 15 Schematic diagrams of other semiconductor structures provided in the embodiments of this application;
[0049] Figure 16 This is a schematic diagram illustrating some semiconductor structures in the embodiments of this application;
[0050] Figure 17 Schematic diagrams of some other semiconductor structures provided in the embodiments of this application;
[0051] Figure 18 This application provides schematic diagrams illustrating the process of fabricating some semiconductor structures in its embodiments.
[0052] Figure 19 This application provides schematic diagrams illustrating the process for fabricating other semiconductor structures in its embodiments.
[0053] Figure 20 This application provides schematic diagrams illustrating the fabrication of some semiconductor structures.
[0054] Figure 21 This application provides schematic diagrams illustrating the fabrication of other semiconductor structures.
[0055] Figure 22 This is a schematic diagram illustrating the fabrication of some semiconductor structures provided in the embodiments of this application.
[0056] Figure label:
[0057] 10 - Semiconductor structure; 20 - Circuit board.
[0058] 100 - First interposer layer; 110 - First metal line; 120 - First conductive post.
[0059] 200 - Second interposer layer; 210 - Second conductive post; 220 - Second metal line.
[0060] 310 - First chip; 320 - Second chip; 330 - Third chip; 340 - Fourth chip.
[0061] 410 - First encapsulation layer; 420 - Second encapsulation layer.
[0062] 500 - First dielectric layer; 600 - Second dielectric layer; 700 - Support column; 800 - Heat dissipation cover. Detailed Implementation
[0063] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0064] In the following, the terms "first," "second," etc., are used only for descriptive purposes to distinguish identical or similar items that have substantially the same function and effect, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the embodiments of this application, the term "connection" should be interpreted broadly; unless otherwise explicitly specified and limited, "connection" can be a direct connection or an indirect connection through an intermediate medium.
[0065] This application provides an electronic device that can be a server, cloud computing electronic device, AI electronic device, optical communication device, mobile phone, tablet personal computer, laptop computer, personal digital assistant (PDA), camera, personal computer, laptop computer, in-vehicle device, wearable device, augmented reality (AR) glasses, AR headset, virtual reality (VR) glasses, or VR headset, or any other device that requires data processing / storage / transmission / reception. This application does not impose any special limitations on the specific form of the aforementioned electronic device.
[0066] Figure 1 Schematic diagrams of the structures of some electronic devices provided in the embodiments of this application; Figure 2 This is a schematic diagram of the semiconductor structure 10 illustrated in an embodiment of this application.
[0067] refer to Figure 1 The electronic device includes a semiconductor structure 10 and a circuit board 20. The semiconductor structure 10 is disposed on the circuit board 20, and the circuit board 20 and the semiconductor structure 10 are connected. The semiconductor structure 10 can transmit signals with chips or modules within the circuit board 20. The circuit board 20 can be a printed circuit board (PCB). In some examples, the circuit board 20 and the semiconductor structure 10 can be connected via, for example... Figure 2 The electrical connection structure C1 shown enables the connection. This electrical connection structure C1 may include a ball grid array (BGA) or multiple arrays of copper pillar bumps (CPBs). It is understood that... Figure 1 The examples shown are merely illustrative of some components included in the electronic device; the actual shape, size, location, and construction of these components are not subject to change. Figure 1 Restrictions.
[0068] As the demands for high performance, high integration, and low power consumption in electronic devices continue to increase, the requirements for chip integration and performance are also rising. With chip manufacturing processes gradually approaching the limits of physical size, 2.5D and 3D packaging technologies are becoming important technological routes for improving chip integration and performance.
[0069] refer to Figure 2 The semiconductor structure 10 may include an interposer, multiple chips, and a packaging material. The multiple chips can be disposed on the interposer, enabling interconnection between them. The interposer also features high integration, high-density connections, and low resistance. An electrical connection structure C1 can be disposed on the side of the interposer away from the multiple chips, allowing interconnection between the multiple chips and other electronic devices (such as a substrate). The packaging material encapsulates the entire area of the multiple chips. Of course, the semiconductor structure 10 may also include other components, which are not limited in this embodiment.
[0070] In current semiconductor structures, the upper surfaces of the packaging material layers surrounding multiple chips are usually flush, making it difficult for the packaging material layers to effectively encapsulate multiple chips with different upper surfaces.
[0071] Figure 3 This is a schematic diagram illustrating the compression packaging of a chip, as shown in an embodiment of this application.
[0072] The main processes for packaging chips include injection molding or compression packaging. (Reference) Figure 3 Taking compression packaging as an example, the compression packaging of chips includes: First, obtaining the upper and lower molds required for the packaging process. With the upper and lower molds engaged, their central areas form a cavity. Second, transferring multiple chips and the supporting structure beneath them into the cavity, and then supplying molten resin into the cavity. Finally, applying pressure to the upper and lower molds to ensure tight contact, causing the resin to deform and gradually harden, thus achieving chip encapsulation. In this way, the upper surface of the packaging material layer obtained through the compression packaging process is flush, and it is necessary to ensure that the upper surfaces of multiple chips are exposed to provide good heat dissipation.
[0073] Based on this, embodiments of this application propose a semiconductor structure and its fabrication method, as well as an electronic device, which can realize the packaging of multiple chips with different upper surfaces, which is beneficial to meet the differentiated packaging of multiple chips, and the upper surfaces of multiple chips can be exposed, which has a good heat dissipation effect.
[0074] This application provides a semiconductor structure 10. (See reference...) Figure 4The semiconductor structure 10 includes: a first interposer 100, a second interposer 200, a first chip 310, a second chip 320, a first packaging layer 410, and a second packaging layer 420.
[0075] The first interposer layer 100 serves to support the second interposer layer 200, the first chip 310, the second chip 320, the first packaging layer 410, and the second packaging layer 420. The first interposer layer 100 can also be used to interconnect the first chip 310 and the second chip 320, or to interconnect the first chip 310 and the second chip 320 with other electronic devices (such as a substrate).
[0076] The second interposer layer 200 is disposed on one side of the first interposer layer 100. The second interposer layer 200 can support the first chip 310 and the first package layer 410. The second interposer layer 200 can also be used to interconnect the first chip 310 and the second chip 320, or to interconnect the first chip 310 with other electronic devices (such as a substrate).
[0077] The first chip 310 is disposed on the side of the second interposer 200 away from the first interposer 100, and the first chip 310 is connected to the first interposer 100 through the second interposer 200.
[0078] A first encapsulation layer 410 is disposed around the first chip 310 and exposes at least a first surface of the first chip 310 away from the first interposer 100. The first encapsulation layer 410 can encapsulate part or all of the first chip 310, and can reduce damage to the first chip 310, inhibit oxidation of the first chip 310, etc. In some examples, the material of the first encapsulation layer 410 can be epoxy encapsulant or polyimide, etc.
[0079] The second chip 320 is disposed on one side of the first intermediary layer 100. The second chip 320 is connected to the first intermediary layer 100. That is, the first chip 310 is connected to the first intermediary layer 100 through the second intermediary layer 200, and the second chip 320 is connected to the first intermediary layer 100, so that the interconnection of the first chip 310 and the second chip 320 can be realized.
[0080] A second encapsulation layer 420 is disposed around the second chip 320 and exposes at least the second surface of the second chip 320 away from the first interposer 100. The second encapsulation layer 420 can encapsulate part or all of the second chip 320, and can reduce damage to the second chip 320, inhibit oxidation of the second chip 320, etc. In some examples, the material of the first encapsulation layer 410 can be epoxy encapsulant or polyimide, etc. The material of the first encapsulation layer 410 can be the same as or different from the material of the second encapsulation layer 420.
[0081] In the aforementioned semiconductor structure 10, at least a portion of the first chip 310 is located within the first packaging layer 410, and at least a portion of the second chip 320 is located within the second packaging layer 420. By using different packaging layers to package different chips, it is possible to package multiple chips with different upper surfaces, and the upper surfaces of multiple chips can all be exposed, resulting in good heat dissipation for all chips. This increases the design freedom of the chips in the semiconductor structure 10, which is beneficial for meeting the needs of differentiated packaging of multiple chips.
[0082] In the embodiments of this application, the surface of the first chip 310 away from the first interposer 100 is the first surface, which can also be referred to as the upper surface of the first chip 310; the surface of the second chip 320 away from the first interposer 100 is the second surface, which can also be referred to as the upper surface of the second chip 320; the surface of the second encapsulation layer 420 away from the first interposer 100 is the third surface, which can also be referred to as the upper surface of the second encapsulation layer 420; and the surface of the first encapsulation layer 410 facing away from the first interposer 100 is the fourth surface, which can also be referred to as the upper surface of the first encapsulation layer 410.
[0083] In the embodiments of this application, if the distance between surface A and the first interposer 100 is greater than the distance between surface B and the first interposer 100, it can be understood that surface A is higher than surface B; if the distance between surface A and the first interposer 100 is equal to the distance between surface B and the first interposer 100, it can be understood that surface A is flush with surface B; if the distance between surface A and the first interposer 100 is less than the distance between surface B and the first interposer 100, it can be understood that surface A is lower than surface B. For example, if the distance between the third surface and the first interposer 100 is less than or equal to the distance between the first surface and the first interposer 100, it can be understood that the third surface is lower than or flush with the first surface.
[0084] In the embodiments of this application, the distance between surface A and the first interposer 100 refers to the perpendicular distance between surface A and the first interposer 100. For example, the distance between the first surface and the first interposer 100 refers to the perpendicular distance between the first surface and the first interposer 100.
[0085] In some embodiments, reference Figure 4 The surface of the second encapsulation layer 420 furthest from the first interposer layer 100 is designated as the third surface, and the distance between the third surface and the first interposer layer 100 is less than or equal to the distance between the first surface and the first interposer layer 100. In other words, the third surface of the second encapsulation layer 420 is lower than or flush with the first surface of the first chip 310, meaning the upper surface of the second encapsulation layer 420 is lower than or flush with the upper surface of the first chip 310. This helps ensure that the second encapsulation layer 420 does not cover the first surface of the first chip 310, thus providing good heat dissipation for the first chip 310.
[0086] In some embodiments, reference Figures 4 to 6 The distance between the first surface and the first interposer 100 is greater than the distance between the second surface and the first interposer 100. In other words, the first surface of the first chip 310 can be higher than the second surface of the second chip 320, that is, the upper surface of the first chip 310 can be higher than the upper surface of the second chip 320.
[0087] The following example illustrates a scheme where the first surface of the first chip 310 is higher than the second surface of the second chip 320, but does not limit the specific parameters such as the thickness and position of the first chip 310, the second chip 320, the first packaging layer 410, and the second packaging layer 420.
[0088] In some examples, reference Figure 4 The first surface of the first chip 310 is higher than the second surface of the second chip 320, and a portion of the first chip 310 is located within the first encapsulation layer 410, while a portion of the second chip 320 is located within the second encapsulation layer 420.
[0089] On the one hand, the first encapsulation layer 410 can encapsulate a portion of the first chip 310, and the second encapsulation layer 420 can encapsulate a portion of the second chip 320. Since the first surface of the first chip 310 and the second surface of the second chip 320 are both exposed, the first chip 310 and the second chip 320 have good heat dissipation effects. On the other hand, it is no longer necessary to restrict the fourth surface of the first encapsulation layer 410 and the third surface of the second encapsulation layer 420 to be flush, which improves the degree of freedom in the encapsulation of multiple chips in the semiconductor structure.
[0090] In other examples, refer to Figure 5 The first surface of the first chip 310 is higher than the second surface of the second chip 320; the entire first chip 310 is located within the first encapsulation layer 410, and the first surface of the first chip 310 is exposed; the entire second chip 320 is located within the second encapsulation layer 420, and the second surface of the second chip 320 is exposed.
[0091] On the one hand, the first encapsulation layer 410 can encapsulate the entire area of the first chip 310, and the first encapsulation layer 410 has excellent encapsulation effect on the first chip 310. The second encapsulation layer 420 can encapsulate the entire area of the second chip 320, and the second encapsulation layer 420 has excellent encapsulation effect on the second chip 320. In addition, the first surface of the first chip 310 and the second surface of the second chip 320 are exposed, and the first chip 310 and the second chip 320 have good heat dissipation effect. On the other hand, it is no longer necessary to restrict the fourth surface of the first encapsulation layer 410 and the third surface of the second encapsulation layer 420 to be flush, which improves the degree of freedom of encapsulation of multiple chips in the semiconductor structure 10.
[0092] Alternatively, a portion of the first chip 310 can be located within the first packaging layer 410, and the entire area of the second chip 320 can be located within the second packaging layer 420. Or, the entire area of the first chip 310 can be located within the first packaging layer 410, and a portion of the second chip 320 can be located within the second packaging layer 420. For specific configuration options, please refer to [reference needed]. Figure 5 This will not be elaborated upon here.
[0093] In yet another example, refer to Figure 6 The first surface of the first chip 310 is higher than the second surface of the second chip 320. The area of the first chip 310 near the second interposer 200 is in contact with the first encapsulation layer 410, and the area of the first chip 310 away from the second interposer 200 is in contact with the second encapsulation layer 420. A portion of the first chip 310 is located within the first encapsulation layer 410 and the second encapsulation layer 420.
[0094] When the first surface of the first chip 310 is higher than the second surface of the second chip 320, the first encapsulation layer 410 can encapsulate the area of the first chip 310 near the second interposer 200, and the second encapsulation layer 420 can encapsulate the area of the first chip 310 near the second interposer 200. That is, different encapsulation layers can be used to encapsulate the first chip 310. Furthermore, since the first surface of the first chip 310 is higher than the second surface of the second chip 320, even if the second encapsulation layer 420 completely encapsulates the second chip 320, and the third surface of the second encapsulation layer 420 is flush with the second surface of the second chip 320, only a portion of the first chip 310 can be encapsulated.
[0095] Alternatively, a portion of the first chip 310 could be located within the first packaging layer 410, and a portion of the second chip 320 could be located within the second packaging layer 420. For specific configuration details, please refer to [reference needed]. Figure 6 This will not be elaborated upon here.
[0096] In other embodiments, reference is made to... Figures 7 to 9The distance between the first surface and the first interposer 100 is less than the distance between the second surface and the first interposer 100. In other words, the first surface of the first chip 310 can be lower than the second surface of the second chip 320, that is, the upper surface of the first chip 310 is lower than the upper surface of the second chip 320.
[0097] The following example illustrates a scheme in which the first surface of the first chip 310 can be lower than the second surface of the second chip 320, but does not limit the specific parameters such as the thickness and position of the first chip 310, the second chip 320, the first packaging layer 410, and the second packaging layer 420.
[0098] In some examples, reference Figure 7 The first surface of the first chip 310 may be lower than the second surface of the second chip 320, and a portion of the first chip 310 is located within the first packaging layer 410, while a portion of the second chip 320 is located within the second packaging layer 420.
[0099] In other examples, refer to Figure 8 The first surface of the first chip 310 may be lower than the second surface of the second chip 320, and the surface of the first encapsulation layer 410 away from the first interposer 100 is flush with the surface of the second encapsulation layer 420 away from the first interposer 100. In other words, the fourth surface of the first encapsulation layer 410 may be flush with the third surface of the second encapsulation layer 420, and the upper surface of the first encapsulation layer 410 may be flush with the upper surface of the second encapsulation layer 420.
[0100] Since the first surface of the first chip 310 can be lower than the second surface of the second chip 320, when the first encapsulation layer 410 encapsulates a portion of the first chip 310, the fourth surface of the first encapsulation layer 410 may be flush with the third surface of the second encapsulation layer 420, and the second surface of the second chip 320 is exposed, thus the second chip 320 has a good heat dissipation effect.
[0101] Alternatively, a portion of the first chip 310 can be located within the first packaging layer 410, and a portion of the second chip 320 can be located within the second packaging layer 420, with the fourth surface of the first packaging layer 410 and the third surface of the second packaging layer 420 flush. For specific configuration details, please refer to [reference needed]. Figure 8 This will not be elaborated upon here.
[0102] In yet another example, refer to Figure 9The first surface of the first chip 310 may be lower than the second surface of the second chip 320. The area of the first chip 310 near the second interposer 200 is in contact with the first encapsulation layer 410, and the area of the first chip 310 away from the second interposer 200 is in contact with the second encapsulation layer 420. The first chip 310 is located within the first encapsulation layer 410 and the second encapsulation layer 420, and the first surface is exposed.
[0103] Since the first surface of the first chip 310 can be lower than the second surface of the second chip 320, the first encapsulation layer 410 can encapsulate the area of the first chip 310 near the second interposer 200, and the second encapsulation layer 420 can encapsulate the area of the first chip 310 near the second interposer 200. That is, different encapsulation layers can be used to encapsulate the first chip 310. Furthermore, since the first surface of the first chip 310 is lower than the second surface of the second chip 320, when the second encapsulation layer 420 encapsulates a portion of the second chip 320, it can achieve encapsulation of the entire area of the first chip 310.
[0104] Alternatively, a portion of the first chip 310 could be located within the first packaging layer 410, and a portion of the second chip 320 could be located within the second packaging layer 420. For specific configuration details, please refer to [reference needed]. Figure 9 This will not be elaborated upon here.
[0105] The following example illustrates the structure of the first interposer 100, but does not limit the specific structure of the first interposer 100. The first interposer 100 can also be other structures with conductive and supporting effects.
[0106] In some embodiments, reference Figures 10 to 12 A first conductive element is disposed in the first interposer layer 100. One end of the first conductive element is connected to the second chip 320, and the other end of the first conductive element is connected to the second interposer layer 200. The first chip 310 is also connected to the first conductive element, thereby enabling the connection between the first chip 310 and the second chip 320. In some examples, the first interposer layer 100 further includes a first interposer material that encapsulates the first conductive element. The first interposer material can be epoxy molding compound (EMC), polyimide (PI), glass, silicone, or other organic materials.
[0107] Example, reference Figure 10The first conductive element is a first metal line 110. The first metal line 110 can be used to connect the second chip 320 and the second interposer 200. In addition, the first metal line 110 can also be used to connect the second chip 320 to other electronic devices (such as a substrate), and can also be used to connect the second interposer 200 to other electronic devices (such as a substrate).
[0108] For another example, see reference. Figure 11 The first conductive element is a first conductive post 120 that penetrates the first interposer layer 100. The first conductive post 120 can be used to interconnect the first chip 310 with other electronic devices (e.g., substrates) or to interconnect the second chip 320 with other electronic devices (e.g., substrates).
[0109] As another example, the first conductive element includes a first metal line 110 and a first conductive post 120 penetrating the first interposer layer 100. See also... Figure 10 and Figure 11 The relevant descriptions will not be repeated here.
[0110] In some embodiments, reference Figure 12 A first dielectric layer 500 is disposed on the side of the first interposer 100 away from the second encapsulation layer 420. By providing the first dielectric layer 500, the risk of warping of the second encapsulation layer 420 can be mitigated. In some examples, refer to... Figure 12 The first dielectric layer 500 can be a redistribution layer. Of course, the first dielectric layer 500 can also be placed between the first interposer layer 100 and the second encapsulation layer 420.
[0111] Furthermore, the first interposer 100 and other electronic devices (such as a substrate) can be connected via an electrical connection structure C2. The electrical connection structure C2 may include an array of solder balls or multiple arrays of bumps.
[0112] The following example explains the structure of the second interposer 200, but does not limit the specific structure of the second interposer 200. The second interposer 200 can also be other structures with conductive and supporting effects.
[0113] In some examples, reference Figure 11 The second interposer 200 is made of a conductive metal and is connected to the first interposer 100 and the first chip 310, respectively. In some examples, the material of the second interposer 200 may be copper or other metals with conductive properties.
[0114] The second interposer 200 has superior rigidity and can support the first chip 310 and the first package layer 410. In addition, the second interposer 200 has better conductivity and can reduce signal loss when passing through the second interposer 200.
[0115] In other examples, refer to Figure 12 The second interposer 200 includes a second interposer material and a second conductive element disposed within the second interposer material; the second conductive element is connected to the first interposer 100 and the first chip 310, respectively. The second interposer material includes epoxy molding compound, polyimide, glass, silicone, or other organic materials. The second conductive element can be a second metal line and / or a second conductive post 210 penetrating the organic material layer.
[0116] Furthermore, the second interposer layer 200 and the first interposer layer 100 can be connected via an electrical connection structure C3. The electrical connection structure C3 may include an array of solder balls or multiple arrays of bumps.
[0117] In some embodiments, reference Figure 12 A second dielectric layer 600 can be disposed on the side of the second interposer 200 away from the first encapsulation layer 410. By providing the second dielectric layer 600, the risk of warping of the first encapsulation layer 410 can be mitigated. In some examples, refer to... Figure 12 The second dielectric layer 600 can be a redistribution layer. Of course, a second dielectric layer 600 can also be provided between the first interposer layer 100 and the second encapsulation layer 420.
[0118] In some embodiments, reference Figure 10 The semiconductor structure 10 also includes a third chip 330, at least a portion of which is located within a second encapsulation layer 420. The second encapsulation layer 420 can encapsulate part or all of the third chip 330, and can reduce damage to the third chip 330 and inhibit oxidation of the third chip 330. The third chip 330 and the second chip 320 are connected through a first interposer layer 100, meaning that the first chip 310, the second chip 320, and the third chip 330 can be interconnected. In other words, the second encapsulation layer 420 can encapsulate multiple chips.
[0119] The arrangement of the third chip 330 in this embodiment is similar to that of the second chip 320. Of course, in the semiconductor structure 10 of this embodiment, more chips can be arranged in the second packaging layer 420; the number of chips is not limited, and the arrangement method is the same as described for the third chip 330, and will not be repeated here.
[0120] In embodiments of this application, the individual chips may present a lateral topology. For example, see reference... Figure 13In (1), the semiconductor structure 10 may include a first chip 310, a second chip 320, and a third chip 330, with the second chip 320 and the third chip 330 disposed on either side of the first chip 310. As another example, see [reference 1]. Figure 13 In (2), the semiconductor structure 10 may include a plurality of second chips 320, a first chip 310, and a plurality of third chips 330. The plurality of second chips 320 are disposed on one side of the first chip 310, and the plurality of third chips 330 are disposed on the other side of the first chip 310. The actual structure of the semiconductor structure 10 may be configured according to the needs of different scenarios, and the embodiments of this application do not impose any special limitations on it.
[0121] In some embodiments, reference Figure 14 The semiconductor structure 10 also includes a fourth chip 340, at least a portion of which is located within a first encapsulation layer 410. The first encapsulation layer 410 can encapsulate part or all of the fourth chip 340, and can reduce damage to the fourth chip 340 and inhibit oxidation of the fourth chip 340. The fourth chip 340 and the first chip 310 are connected through a second interposer layer 200, meaning that the first chip 310, the second chip 320, and the fourth chip 340 can be interconnected. In other words, the first encapsulation layer 410 can encapsulate multiple chips. Of course, if the semiconductor structure 10 includes such... Figure 14 The third chip 330 shown can be interconnected with the first chip 310, the second chip 320, the third chip 330, and the fourth chip 340.
[0122] The fourth chip 340 in this embodiment is configured similarly to the first chip 310. Of course, in the semiconductor structure 10 of this embodiment, more chips located in the first packaging layer 410 can be provided; the number of chips is not limited. The configuration of these chips is described in the description of the fourth chip 340 and will not be repeated here.
[0123] This application does not specifically limit the types of chips used in its embodiments. For example, refer to... Figure 15 The second chip 320 can be an input / output chip (I / O chip), and the third chip 330 can be high bandwidth memory (HBM).
[0124] refer to Figure 16A heat sink is typically located on the side of the chip furthest from the interposer. This heat sink dissipates heat from the chip within the semiconductor structure, improving its safety. The heat sink usually contains cavities, which can hold cooling gas or coolant depending on the cooling method. For example, in the case of a heat sink used for liquid cooling, the cavity contains coolant, which circulates to dissipate heat from the chip.
[0125] In embodiments of this application, there may be cases where the encapsulation layer only encapsulates a portion of the chip, for example... Figure 15 The second chip 320 and the third chip 330 shown are not fully encapsulated by the second packaging layer 420. If the heat sink is directly placed on... Figure 15 The heat sink above the second chip 320 and the third chip 330 shown may damage the second chip 320 and the third chip 330, resulting in a decrease in the reliability of the semiconductor structure 10.
[0126] Therefore, embodiments of this application provide a semiconductor structure 10, with reference to... Figure 17 The semiconductor structure 10 includes a support pillar 700 and a heat sink 800. The heat sink 800 is disposed on the side of the first chip 310 away from the interposer. The support pillar 700 extends along the thickness direction and supports the heat sink 800. Thus, by using the support pillar 700 to support the heat sink 800, the impact of the heat sink 800 on the chips (such as the second chip 320, the third chip 330, etc.) can be mitigated, and the semiconductor structure 10 exhibits superior reliability.
[0127] In the aforementioned semiconductor structure 10, when the differences in the upper surfaces of multiple chips are too large—for example, the second surface of the second chip 320 is significantly higher than the first surface of the first chip 310—a heat sink 800 containing cooling gas can be provided to dissipate heat from the multiple chips. The reason is that if the differences in the upper surfaces of the multiple chips are too large, using a heat sink 800 containing coolant to dissipate heat would result in a large distance between the coolant and the chip with the lower upper surface, leading to poor heat dissipation. Therefore, air cooling can be used to dissipate heat from the multiple chips to improve the heat dissipation effect.
[0128] In the semiconductor structure 10 described above, when the differences between the upper surfaces of multiple chips are small—for example, when the second surface of the second chip 320 is close to the first surface of the first chip 310—a heat sink 800 containing coolant can be provided to dissipate heat from the multiple chips. This is because, if the differences between the upper surfaces of the multiple chips are small, using a heat sink 800 containing coolant to dissipate heat from the multiple chips generally results in better heat dissipation than using cooling gas, thus improving the heat dissipation effect of the chips.
[0129] In some embodiments, reference Figure 17 The support column 700 can be disposed on the first intermediate layer 100. The support column 700 can also be disposed on other structures with a supporting effect, such as a substrate.
[0130] In some embodiments, reference Figure 17 A thermal interface material (TIM) can be disposed between the heat sink 800 and the first chip 310. The TIM can quickly and effectively transfer the heat generated by the first chip 310 to the heat sink 800, thereby achieving good heat dissipation of the first chip 310. The TIM includes thermal grease, thermal gel, thermal silicone pad, or other materials with heat dissipation effect, and this application does not constitute a limitation thereof.
[0131] Of course, for reference Figure 17 Thermal interface materials can be provided between the heat sink 800 and components such as the second chip 320, the third chip 330, and the fourth chip 340, and the resulting beneficial effects are similar to those described above.
[0132] In some embodiments, reference Figure 4 When the first surface of the first chip 310 is higher than the second surface of the second chip 320, the distance between the first surface and the first interposer 100 is L1, and the distance between the second surface and the first interposer 100 is L2. The ratio of L1 to L2 can be (1-10):(0.1-0.8), for example, 0.1:1, 0.5:1, 0.8:1, 0.1:5, 0.5:5, 0.8:5, 0.1:10, 0.5:10, 0.8:10, etc. In some examples, L1 can be from 1 mm to 10 mm, and L2 can be from 0.1 mm to 0.8 mm.
[0133] In other embodiments, reference is made to... Figure 7 When the first surface of the first chip 310 is lower than the second surface of the second chip 320, the distance between the first surface and the first interposer 100 is L3, and the distance between the second surface and the first interposer 100 is L4. The ratio of L3 to L4 can be (0.1-0.8):(1-10), for example, 0.1:1, 0.5:1, 0.8:1, 0.1:5, 0.5:5, 0.8:5, 0.1:10, 0.5:10, 0.8:10, etc. In some examples, L3 can be 0.1 mm to 0.8 mm, and L4 can be 1 mm to 10 mm.
[0134] Furthermore, the thickness of the third chip 330 can be referenced to that of the second chip 320, and the thickness of the fourth chip 340 can be referenced to that of the first chip 310, which will not be elaborated further here.
[0135] Figure 18 and Figure 19 These are schematic diagrams illustrating some processes for fabricating semiconductor structures, as provided in the embodiments of this application. Figures 20 to 22 These are some structural schematic diagrams for the fabrication of semiconductor structures provided in the embodiments of this application.
[0136] This application provides a method for preparing a semiconductor structure, referencing... Figure 18 The method may include the following steps:
[0137] S1: Connect the first chip to the second interposer layer.
[0138] In this step, refer to Figure 20 (1) and Figure 21 In step (1), the first chip 310 is connected to the second intermediary layer 200. The second intermediary layer 200 can provide support for the first chip 310 and the first packaging layer 410 in step S2. Therefore, the transfer of the first chip 310 and the first packaging layer 410 can be achieved by moving the second intermediary layer 200. In addition, the interconnection of the first chip 310 and the second intermediary layer 200 can be achieved by connecting the first chip 310 and the second intermediary layer 200.
[0139] When the material of the second interposer 200 includes a conductive metal, refer to Figure 20 In (1), the first chip 310 and the second interposer 200 can be connected to achieve interconnection between the first chip 310 and the second interposer 200; when the second interposer 200 includes a second interposer material and a second conductive element disposed in the second interposer material, refer to Figure 21 In step (1), the first chip 310 and the second conductive element are connected to achieve interconnection between the first chip 310 and the second interposer layer 200. The second conductive element in the second interposer layer 200 may include a second conductive post 210 and a second metal line 220.
[0140] S2: At least a portion of the first chip is packaged using a first packaging layer to obtain a package structure.
[0141] In this step, refer to Figure 20 In step (2), at least a portion of the first chip 310 is encapsulated using the first encapsulation layer 410 to obtain an encapsulation structure formed by the first chip 310, the first encapsulation layer 410, and the first interposer layer 100. Furthermore, after encapsulating the first chip 310 with the first encapsulation layer 410, the encapsulation material on the first chip 310 can be thinned to expose the first surface of the first chip 310.
[0142] In some embodiments, the method of encapsulating at least a portion of the first chip 310 with the first encapsulation layer 410 can be either compression encapsulation or dam and fill encapsulation.
[0143] S3: Connect the package structure and the second chip to the first interposer layer.
[0144] In this step, refer to Figure 20 (3) and Figure 21 In step (3), in the packaging structure obtained in step S2, the second interposer 200 can support the first chip 310 and the first packaging layer 410. Therefore, the first chip 310 and the first packaging layer 410 can be transferred to the first interposer 100 by moving the second interposer 200. The first chip 310 is connected to the first interposer 100, and the first interposer 100 can support the second chip 320, the second interposer 200, the first chip 310, and the second packaging layer 420 prepared in the subsequent step S4. The first chip 310 and the second chip 320 can also be interconnected.
[0145] In some embodiments, reference Figure 20 (3) and Figure 21 In step (3), step S3 may further include: connecting the third chip 330 to the first interposer layer 100. Of course, more chips may be connected to the first interposer layer 100, and the number of chips is not limited in this embodiment.
[0146] In some embodiments, the second chip 320 can be bonded to the first interposer 100. For example, the connection between the second chip 320 and the first interposer 100 can be achieved by thermocompression bonding, which can also be referred to as die to interposer.
[0147] In some embodiments, when the material of the second interposer 200 includes a conductive metal, the second interposer 200 and the first interposer 100 can be connected; when the second interposer 200 includes a second interposer material and a second conductive element disposed in the second interposer material, the second conductive element and the first interposer 100 are bonded to achieve connection.
[0148] S4: At least a portion of the second chip is packaged using a second packaging layer.
[0149] In this step, refer to Figure 20 In (4), a portion or all of the second chip 320 is packaged using a second packaging layer 420.
[0150] In some embodiments, the encapsulation method in step S4 can be dam and fill encapsulation. The steps of dam and fill encapsulation may include: firstly, using frame adhesive to form a barrier area around the second chip 320, and then using fill adhesive to fill the space within the barrier area.
[0151] In some embodiments, reference Figure 20 In (4), a portion of the third chip 330 is packaged using the second packaging layer 420.
[0152] In some embodiments, reference Figure 20 (5) and Figure 21 In (5), a first dielectric layer 500 may be provided on the side of the first interposer 100 away from the second chip 320. For example, the first dielectric layer 500 may be a redistribution layer. In addition, an electrical connection structure C2 may be provided on the side of the first dielectric layer 500 away from the first interposer 100.
[0153] In the above method, firstly, the first chip 310 on the second interposer layer 200 is encapsulated using a first encapsulation layer 410 to obtain an encapsulation structure; then, the encapsulation structure and the second chip 320 are connected to the first interposer layer 100, which allows for interconnection between the first chip 310 and the second chip 320, and also provides support for the encapsulation of the second chip 320; finally, the second chip 320 on the first interposer layer 100 is encapsulated using the second encapsulation layer 420. Thus, by using different encapsulation layers to encapsulate different chips, multiple chips with different upper surfaces can be encapsulated, and the upper surfaces of multiple chips can be exposed, resulting in good heat dissipation for all chips. This increases the design freedom of the chips in the semiconductor structure 10, which is beneficial for meeting the needs of differentiated encapsulation of multiple chips.
[0154] pass Figure 18 The preparation process shown can produce... Figure 4 , Figure 5 , Figure 7 , Figure 8 , Figure 10 , Figure 11 , Figure 12 The semiconductor structure 10 is shown.
[0155] This application provides another method for fabricating semiconductor structures, see embodiments thereof. Figure 19 The method may include the following steps:
[0156] S10: Connect the first chip to the second interposer layer.
[0157] The description of step S10 can be found in step S1, and will not be repeated here.
[0158] S20: The area of the first chip near the second interposer layer is packaged using the first encapsulation layer.
[0159] In some embodiments, reference Figure 21 In (2), the method of using the first encapsulation layer 410 to encapsulate the area of the first chip 310 near the second interposer layer 200 can be used for dam-filling encapsulation.
[0160] In some embodiments, a second dielectric layer 600 may be disposed on the side of the second interposer 200 away from the first chip 310. For example, the second dielectric layer 600 may be a redistribution layer.
[0161] S30: Connect the package structure and the second chip to the first interposer layer.
[0162] The description of step S30 can be found in step S3, and will not be repeated here.
[0163] S40: The area of the first chip away from the second interposer layer and at least a portion of the second chip are packaged using a second packaging layer.
[0164] In this step, refer to Figure 21 In (4), the first chip 310 is first encapsulated in the area close to the second interposer 200 by the first encapsulation layer 410, and then the area of the first chip 310 away from the second interposer 200 is encapsulated by the second encapsulation layer 420, which can realize the plastic encapsulation of the first chip 310; in addition, the second encapsulation layer can also encapsulate at least part of the second chip 320.
[0165] In some embodiments, the packaging method in step S40 can be compression packaging.
[0166] pass Figure 19 The preparation process shown can produce... Figure 6 , Figure 9 The semiconductor structure 10 is shown.
[0167] This application provides yet another method for fabricating a semiconductor structure, see embodiments thereof. Figure 22 (1) to Figure 22 In (5), the process of this method may include the following steps:
[0168] S100: Connect the first chip and the fourth chip to the second interposer layer.
[0169] S200: At least a portion of the first chip and the fourth chip are packaged using a first packaging layer to obtain a package structure.
[0170] In some embodiments, reference Figure 22 (1) and Figure 22In step (2), step S100 may include: mounting the first chip 310 and the fourth chip 340 onto a bottom wafer using hybrid bonding (HB), also known as chip-to-wafer (C2W). Step S200 may further include: after encapsulating at least a portion of the first chip 310 and the fourth chip 340 with the first encapsulation layer 410, thinning the encapsulation material on the upper surfaces of the first chip 310 and the fourth chip 340 to expose the upper surfaces of the first chip 310 and the fourth chip 340. The thinning method may be mechanical polishing.
[0171] In some embodiments, step S200 may further include: after thinning the encapsulation material on the upper surface of the first chip 310 and the upper surface of the fourth chip 340, performing a thinning process on the side of the wafer away from the second chip 320 until the first conductive element in the wafer is exposed. Taking the first conductive element as a conductive pillar as an example, the side of the wafer away from the second chip 320 is mechanically ground until the conductive pillar in the wafer is exposed. The thinned wafer can serve as the second interposer layer 200.
[0172] S300: Connect the package structure, the second chip 320, and the fourth chip 340 to the first interposer layer 100.
[0173] Among them, reference Figure 22 In step (3), the description of step S30 can be found in step S3, and will not be repeated here.
[0174] S400: At least a portion of the second chip 320 and at least a portion of the fourth chip 340 are packaged using a second packaging layer 420.
[0175] Among them, reference Figure 22 (4) and Figure 22 In step (5), the description of step S40 can be found in step S4, and will not be repeated here.
[0176] Embodiments of this application provide an electronic device comprising the semiconductor structure 10 and circuit board 20 described in the above embodiments, wherein the semiconductor structure 10 is disposed on the circuit board 20. The beneficial effects of the above electronic device can be understood by referring to the beneficial effects of the semiconductor structure 10.
[0177] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.
Claims
1. A semiconductor structure, characterized in that, include: First intermediary layer; The second intermediary layer is disposed on one side of the first intermediary layer; The first chip is disposed on the side of the second interposer layer away from the first interposer layer; The first chip is connected to the first intermediary layer through the second intermediary layer; A first encapsulation layer is disposed around the first chip and exposes at least a first surface of the first chip away from the first interposer layer; The second chip is disposed on one side of the first interposer layer and is connected to the first interposer layer. A second encapsulation layer is disposed around the second chip and exposes at least a second surface of the second chip away from the first interposer layer.
2. The semiconductor structure according to claim 1, characterized in that, The surface of the second encapsulation layer that is away from the first intermediary layer is a third surface, and the distance between the third surface and the first intermediary layer is less than or equal to the distance between the first surface and the first intermediary layer.
3. The semiconductor structure according to claim 1 or 2, characterized in that, The distance between the first surface and the first intermediary layer is greater than the distance between the second surface and the first intermediary layer.
4. The semiconductor structure according to claim 3, characterized in that, The first chip is located within the first encapsulation layer, with the first surface exposed; and the second chip is located within the second encapsulation layer, with the second surface exposed.
5. The semiconductor structure according to claim 3, characterized in that, The area of the first chip near the second interposer layer is in contact with the first encapsulation layer, and the area of the first chip away from the second interposer layer is in contact with the second encapsulation layer. The portion of the first chip is located within the first packaging layer and the second packaging layer.
6. The semiconductor structure according to claim 1 or 2, characterized in that, The distance between the first surface and the first intermediary layer is less than the distance between the second surface and the first intermediary layer.
7. The semiconductor structure according to claim 6, characterized in that, The surface of the first encapsulation layer away from the first interposer is flush with the surface of the second encapsulation layer away from the first interposer.
8. The semiconductor structure according to claim 6, characterized in that, The area of the first chip near the second interposer layer is in contact with the first encapsulation layer, and the area of the first chip away from the second interposer layer is in contact with the second encapsulation layer. The first chip is located within the first and second packaging layers, and the first surface is exposed.
9. The semiconductor structure according to any one of claims 1-8, characterized in that, The material of the second interposer includes a conductive metal, and the second interposer is connected to the first interposer and the first chip respectively.
10. The semiconductor structure according to any one of claims 1-8, characterized in that, The second interposer layer includes an organic material layer and a conductive element disposed in the organic material layer; the conductive element is connected to the first interposer layer and the first chip respectively.
11. The semiconductor structure according to any one of claims 1-10, characterized in that, The semiconductor structure also includes a heat sink and a support pillar. The heat sink is disposed on the side of the first chip away from the first interposer layer, and the support pillar extends along the thickness direction to support the heat sink.
12. A method for preparing a semiconductor structure, characterized in that, include: Connect the first chip to the second intermediary layer; At least a portion of the first chip is packaged using a first encapsulation layer to obtain a package structure formed by the first chip, the first encapsulation layer, and the second interposer layer; The packaging structure and the second chip are connected to the first interposer layer; At least a portion of the second chip is packaged using a second packaging layer.
13. The method according to claim 12, characterized in that, Encapsulating at least a portion of the first chip with the first encapsulation layer includes: encapsulating the region of the first chip adjacent to the second interposer layer with the first encapsulation layer; After connecting the semiconductor structure and the second chip to the first interposer, the method further includes: encapsulating the area of the first chip away from the second interposer using the second encapsulation layer.
14. An electronic device, characterized in that, It includes a circuit board, and a semiconductor structure as described in any one of claims 1-11 or a semiconductor structure prepared by the method of claim 12 or 13; the semiconductor structure is disposed on the circuit board.