Chip stack structure and method of manufacturing the same

Abstract

A chip stack structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulator, and a multilayer bonding film. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The insulating encapsulator is disposed on the first semiconductor die and laterally covers the second semiconductor die. The multilayer bonding film is disposed on the surface of the insulating encapsulator and the surface of the second semiconductor die. The multilayer bonding film includes a flat surface.

Description

Technical Field

[0001] Embodiments of the present invention relate to a chip stack structure and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements. Tens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. Individual chips are separated by dicing the integrated circuits along dicing lines. The individual chips are then packaged separately, either in multi-chip modules or other types of packages. In semiconductor manufacturing, the heat dissipation performance and reliability of semiconductor packages are of paramount concern. Summary of the Invention

[0003] According to some embodiments disclosed herein, a chip stack structure is provided including a first semiconductor die, a second semiconductor die, an insulating encapsulator, and a multilayer bonding film. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The insulating encapsulator is disposed on the first semiconductor die and laterally covers the second semiconductor die. The multilayer bonding film is disposed on the surface of the insulating encapsulator and on the surface of the second semiconductor die. The multilayer bonding film includes a flat surface.

[0004] According to some other embodiments disclosed herein, a chip stack structure is provided including a first semiconductor die, a second semiconductor die, an insulating encapsulator, and a multilayer bonding film. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The insulating encapsulator is disposed on the first semiconductor die and laterally covers the second semiconductor die, wherein the second semiconductor die and the insulating encapsulator provide a surface with unevenness. The multilayer bonding film is disposed on the surface with unevenness, wherein the multilayer bonding film includes a first dielectric layer and a second dielectric layer, the first dielectric layer being in contact with the surface with unevenness, and the second dielectric layer being disposed on and in contact with the first dielectric layer.

[0005] According to some other embodiments disclosed herein, a method for manufacturing a chip stack structure is provided. A semiconductor wafer including a first semiconductor die is provided. A second semiconductor die is bonded to the first semiconductor die of the semiconductor wafer. A gap-filling material is formed on the semiconductor wafer to laterally cover the second semiconductor die. The gap-filling material is thinned until the surface of the second semiconductor die is exposed to form an insulating encapsulation laterally covering the second semiconductor die, wherein the second semiconductor die and the insulating encapsulation provide a curved surface. A multilayer bonding film is formed on the curved surface, wherein the multilayer bonding film includes planar surfaces. Attached Figure Description

[0006] The various aspects of this disclosure are best understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for the purpose of discussing clarity.

[0007] Figures 1A to 1L This is a cross-sectional view illustrating the process flow for manufacturing a chip stack structure according to some embodiments of this disclosure.

[0008] Figures 2A to 2I This is a cross-sectional view illustrating the process flow for manufacturing a package-on-package (PoP) structure according to some embodiments of this disclosure.

[0009] Figures 3A to 3G This is a cross-sectional view illustrating the process flow for manufacturing a chip stack structure according to other embodiments of this disclosure.

[0010] Figures 4 to 7 This is a cross-sectional view illustrating various chip stack structures according to some alternative embodiments of this disclosure.

[0011] Figure 8 This is a schematic cross-sectional view illustrating the face-to-face bonding of a semiconductor wafer and a semiconductor die according to other embodiments of this disclosure.

[0012] Figure 9 This is a cross-sectional view illustrating a chip stack structure according to other embodiments of this disclosure.

[0013] Figure 10A and Figure 10B This is a schematic cross-sectional view illustrating the stepped portion between the sidewall of a second semiconductor die and the sidewall of an insulating encapsulation according to other embodiments of this disclosure.

[0014] Figure 11 and Figure 12 This is a cross-sectional view illustrating various chip-on-wafer-on-substrate (CoWoS) packages according to various alternative embodiments of this disclosure. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are provided to simplify this disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, or embodiments where other features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters are repeated in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or architectures discussed.

[0016] In addition, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used herein to describe the relationship between one component or feature and another, as shown in the figures. These spatial relative terms are intended to cover different orientations of the device in use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

[0017] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on redistribution layers or substrates, allowing testing of 3D packages or 3DICs using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with testing methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0018] A package and a method for forming the package are provided according to various exemplary embodiments. Intermediate stages in forming the package are described. Variations of the embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used to refer to the same components.

[0019] In some embodiments disclosed herein, a multilayer bonding film or interlayer film is formed to cover the semiconductor die and an insulating packaging material that laterally encapsulates the semiconductor die, providing surface flatness that facilitates subsequent bonding processes. The multilayer bonding film addresses the non-bonding issue between the semiconductor die and the substrate, thus improving reliability and bonding yield.

[0020] Figures 1A to 1L This is a cross-sectional view illustrating the process flow for manufacturing a chip stack structure according to some embodiments of this disclosure.

[0021] Reference Figure 1A The device provides a wafer 10 comprising semiconductor dies. The semiconductor dies in wafer 10 may be logic dies, system-on-chip (SoC) dies, or other suitable semiconductor dies. Wafer 10 is manufactured using, for example, N3, N5, or other suitable processes. Wafer 10 may include a semiconductor substrate 12 (e.g., a silicon substrate), through-substrate vias 14 embedded in the semiconductor substrate 12, interconnect structures 16 disposed on the semiconductor substrate 12, and a bonding dielectric layer 18a disposed on the interconnect structures 16, wherein the through-substrate vias 14 are electrically connected to the interconnect structures 16. The semiconductor substrate 12 of wafer 10 may include a crystalline silicon wafer. The semiconductor substrate 12 may include various doped regions (e.g., p-type or n-type substrates) depending on design requirements. In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; or n-type dopants, such as phosphorus or arsenic and / or combinations thereof. The doped regions can be configured for n-type fin field-effect transistors (FinFETs) and / or p-type fin field-effect transistors. In some alternative embodiments, the semiconductor substrate 12 is made of some other suitable elemental semiconductor, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide.

[0022] Through-substrate via 14 can be formed by forming a groove in the semiconductor substrate 12, for example, by etching, milling, laser technology, a combination thereof, or similar methods. A thin barrier layer can be conformally deposited on the front side of the semiconductor substrate 12 and in the opening, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, or similar methods. The barrier layer may include nitrides or oxynitrides, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, or similar materials. Conductive material is deposited on the thin barrier layer and in the opening. The conductive material can be formed by electrochemical plating processes, CVD, ALD, PVD, a combination thereof, or similar methods. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, or similar materials. Excess conductive material and the barrier layer can be removed from the front side of the semiconductor substrate 12 by, for example, chemical mechanical polishing. Therefore, in some embodiments, the through-substrate via 14 may include a conductive material and a thin barrier layer between the conductive material and the semiconductor substrate 12.

[0023] The interconnect structure 16 may include one or more dielectric layers (e.g., one or more inter-layer dielectric (ILD) layers, inter-metal dielectric (IMD) layers, or similar layers) and interconnect wiring embedded in the one or more dielectric layers, wherein the interconnect wiring is electrically connected to semiconductor devices (e.g., FinFETs) formed in the semiconductor substrate 12 and / or through-substrate vias 14. The material of the one or more dielectric layers may include silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric materials. Interconnect wiring may include metallic wiring. For example, interconnect wiring includes copper wiring, copper pads, aluminum pads, or combinations thereof. In some embodiments, through-substrate vias 14 pass through one or more layers of interconnect structure 16 and extend into semiconductor substrate 12.

[0024] The material for bonding dielectric layer 18a can be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric materials. The bonding dielectric layer 18a can be formed by depositing the dielectric material through a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD process or other suitable process).

[0025] Reference Figure 1A and Figure 1B The wafer 10 is picked up, flipped, and placed on and bonded to the carrier plate C1. The carrier plate C1 may be a semiconductor wafer, such as a silicon wafer having a dielectric layer (e.g., a silicon oxide layer) formed thereon. The carrier plate C1 may have a circular top-view shape and size of the silicon wafer. For example, the wafer 10 and the carrier plate C1 may have an 8-inch diameter, a 12-inch diameter, or similar dimensions. The wafer 10 is bonded to the carrier plate C1 via a wafer-to-wafer bonding process. A bonding process is performed to bond the bonding dielectric layer 18a (e.g., a silicon nitride layer) of the wafer 10 to the carrier plate C1. The bonding process may be a direct bonding process. After performing the above direct bonding process, a dielectric-to-dielectric bonding interface, such as silicon oxide to silicon nitride (SiO2), is formed. x -SiN x The bonding interface can be formed between the bonding dielectric layer 18a of the wafer 10 and the carrier C1.

[0026] Reference Figure 1B and Figure 1CA thinning process is performed to partially remove the semiconductor substrate 12 of the wafer 10 until the through-substrate via 14 is exposed from the back surface of the semiconductor substrate 12. The thinning process may be a chemical mechanical polishing (CMP) process and / or a mechanical polishing process. After the above thinning process is performed, the through-substrate via 14 can protrude from the back surface of the semiconductor substrate 12.

[0027] Reference Figure 1C and Figure 1D A planarization layer 24 is formed on the back surface of the semiconductor substrate 12 of the wafer 10, such that the exposed end of the through-substrate via 14 is substantially flush with the top surface of the planarization layer 24. A dielectric material may be formed on the back surface of the semiconductor substrate 12 to cover the exposed through-substrate via 14. The aforementioned dielectric material may be silicon oxide (SiO2) or may include silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric material. A planarization process, such as CMP and / or mechanical polishing, can be performed to partially remove the dielectric material, so that the planarization layer 24 is formed on the back surface of the semiconductor substrate 12 to laterally cover the end of the through-substrate via 14.

[0028] After the planarization layer 24 is formed, the bonding structure 26 (including the bonding dielectric layer 26a and the bonding conductor 26b embedded in the bonding dielectric layer 26a) is formed on the planarization layer 24 and the through-substrate via 14. The material of the bonding dielectric layer 26a may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y The bonding structure 26 can be formed by: depositing a dielectric material via a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes); patterning the dielectric material to form a bonding dielectric layer 26a including openings or through-holes; and filling the openings or through-holes defined in the bonding dielectric layer 26a with conductive material to form a bonding conductor 26b embedded in the bonding dielectric layer 26a. In some embodiments, the conductive material used to form the bonding conductor 26b can be formed via a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable processes), followed by a planarization process (e.g., CMP and / or mechanical polishing).

[0029] After the bonding structure 26 is formed, a semiconductor die 30 is provided on the bonding structure 26. The semiconductor die 30 can be a logic die, a system-on-a-chip (SoC) die, or other suitable semiconductor die. The semiconductor die 30 is manufactured using, for example, an N3 process, an N5 process, or other suitable processes. The semiconductor die in the wafer 10 and the semiconductor die 30 provided on the wafer 10 can perform the same or different functions. For example, both the semiconductor die in the wafer 10 and the semiconductor die 30 are system-on-a-chip (SoC) dies. Each semiconductor die 30 may include a semiconductor substrate 32 and an interconnect structure 34 disposed on the semiconductor substrate 32. Furthermore, a bonding structure 36 may be formed on the interconnect structure 34 of the semiconductor die 30. The bonding structure 36 includes a bonding dielectric layer 36a and a bonding conductor 36b embedded in the bonding dielectric layer 36a. The material of the bonding dielectric layer 36a may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y The bonding conductor 36b may be a conductive via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding structure 36 may be formed by: depositing a dielectric material via a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding dielectric layer 36a including openings or through-holes; and filling the openings or through-holes defined in the bonding dielectric layer 36a with conductive material to form a bonding conductor 36b embedded in the bonding dielectric layer 36a. In some embodiments, the conductive material used to form the bonding conductor 36b may be formed via a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process), followed by a planarization process (e.g., a CMP process and / or a mechanical polishing process).

[0030] A bonding process (e.g., a chip-to-wafer bonding process) is performed to bond the bonding structure 36 formed on the semiconductor die 30 to the bonding region of the bonding structure 26. The bonding process may include dielectric-to-dielectric bonding and metal-to-metal bonding. After performing the bonding process, a dielectric-to-dielectric bonding interface is formed between the bonding dielectric layer 26a and the bonding dielectric layer 36a, and a metal-to-metal bonding interface is formed between the bonding conductor 26b and the bonding conductor 36b. After performing the bonding process, the semiconductor die 30 is electrically connected to the semiconductor die of the wafer 10 through the bonding structure 36 and the bonding structure 26. In some other embodiments, the bonding process may include dielectric-to-dielectric bonding, metal-to-metal bonding, and dielectric-to-metal bonding. After performing the above bonding process, a dielectric-to-dielectric bonding interface is formed between the bonding dielectric layer 26a and the bonding dielectric layer 36a, a metal-to-metal bonding interface is formed between the bonding conductor 26b and the bonding conductor 36b, and a dielectric-to-metal bonding interface is formed between the bonding conductor 26b and the bonding dielectric layer 36a, and between the bonding conductor 36b and the bonding dielectric layer 26a. Furthermore, the bonding conductor 26b partially overlaps the bonding conductor 36b and partially overlaps the bonding dielectric layer 36a; while the bonding conductor 36b partially overlaps the bonding conductor 26b and partially overlaps the bonding dielectric layer 26a. Additionally, the bonding conductor 36b and the bonding conductor 26b may have different widths.

[0031] like Figure 1D As shown, semiconductor die 30 can be disposed above semiconductor die of wafer 10. The lateral dimensions (e.g., width and / or length) of semiconductor die of wafer 10 can be larger than the lateral dimensions (e.g., width and / or length) of semiconductor die 30. In other words, the area occupied by semiconductor die of wafer 10 can be larger than the area occupied by semiconductor die 30. Since bonding structure 36 only bonds to the bonding region of bonding structure 26, a portion of bonding dielectric layer 26a is not covered by bonding structure 36. In other words, these portions of bonding dielectric layer 26a not covered by bonding structure 36 are exposed at this stage.

[0032] Reference Figure 1E and Figure 1F A gap-filling material 38 is formed on the bonding structure 26 to cover the back surface of the semiconductor die 30, the sidewalls of the semiconductor die 30, the sidewalls of the bonding structure 36, and a portion of the bonding dielectric layer 26a not covered by the bonding structure 36. The gap-filling material 38 can be formed by a deposition process or other suitable process. The material of the gap-filling material 38 can be or include gap-filling oxides or other suitable dielectric materials. The gap-filling material 38 fills the gaps between adjacent semiconductor dies 30 and contacts a portion of the bonding dielectric layer 26a not covered by the bonding structure 36. After the gap-filling material 38 is formed, as... Figure 1FAs shown, the gap filler material 38 is partially removed until the semiconductor substrate 32 of the semiconductor die 30 is exposed, thereby forming an insulating encapsulation 40. In some embodiments, the gap filler material 38 may be partially removed by an etching process to remove a portion of the gap filler material 38, followed by a planarization process. The etching process for the gap filler material 38 may be a patterning process, and the planarization process for the gap filler material 38 may be a CMP process, a mechanical polishing process, or a combination thereof. After performing the gap filler material 38 removal process, the top surface of the insulating encapsulation 40 may be substantially flush with the back surface of the semiconductor die 30.

[0033] After forming the insulating encapsulation 40, a multilayer bonding film 41 is formed to cover the back surfaces of the insulating encapsulation 40 and the semiconductor die 30. The multilayer bonding film 41 includes a first dielectric layer 41a and a second dielectric layer 41b located above the first dielectric layer 41a. The first dielectric layer 41a is thicker than the second dielectric layer 41b. The second dielectric layer 41b includes a flat top surface for subsequent bonding processes. In some embodiments, the flat top surface of the second dielectric layer 41b can be defined as having a highest point and a lowest point on the surface topography of the second dielectric layer 41b when a 1 mm wide sample is taken, and the height difference between the highest point and the lowest point is less than 30 angstroms. In some embodiments, the height difference between the highest point and the lowest point ranges from about 0 angstroms to about 10 angstroms. In some other embodiments, the height difference between the highest point and the lowest point ranges from about 10 angstroms to about 20 angstroms. In some alternative embodiments, the height difference between the highest point and the lowest point ranges from about 20 angstroms to about 30 angstroms. The first dielectric layer 41a may be a dielectric layer with high thermal conductivity, while the second dielectric layer 41b may be a dielectric layer with relatively low thermal conductivity. In some embodiments, the first dielectric layer 41a of the multilayer bonding film 41 may be a crystalline film, such as an aluminum nitride (AlN) layer, a BN layer, a SiC layer, a BeO layer, a diamond layer, a graphene layer, a Cu layer, a SiGe layer, a TiO2 layer, a polycrystalline silicon layer, an Al2O3 layer, or a GaN layer, while the second dielectric layer 41b of the multilayer bonding film 41 may be a low dielectric constant dielectric layer, such as a silicon nitride (SiN) layer. x (where x>0) layer or silicon dioxide (SiO) xThe first dielectric layer 41a has a thickness ranging from about 500 angstroms to about 3000 angstroms, while the second dielectric layer 41b has a thickness ranging from about 200 angstroms to about 500 angstroms. In embodiments where the first dielectric layer 41a is an AlN layer and the second dielectric layer 41b is silicon oxide, the thickness ratio of the first dielectric layer 41a to the second dielectric layer 41b ranges from about 2.5 to about 15. The dielectric constant of the first dielectric layer 41a ranges from about 8.6 to about 9.0, while the dielectric constant of the second dielectric layer 41b ranges from about 6.5 to about 7.0. The thermal conductivity of the first dielectric layer 41a ranges from about 40 W / mK to about 321 W / mK, while the thermal conductivity of the second dielectric layer 41b ranges from about 2 W / mK to about 30 W / mK. In embodiments where the first dielectric layer 41a is an AlN layer and the second dielectric layer 41b is silicon oxide, the ratio of the thermal conductivity of the first dielectric layer 41a to the thermal conductivity of the second dielectric layer 41b ranges from about 10 to about 160. In alternative embodiments where the first dielectric layer 41a is an AlN layer and the second dielectric layer 41b is silicon oxide, the ratio of the thermal conductivity of the first dielectric layer 41a to the thermal conductivity of the second dielectric layer 41b is about 20.

[0034] The multilayer bonding film 41 may further include a third dielectric layer (i.e., a sacrificial layer) 41c formed to cover the second dielectric layer 41b. The third dielectric layer 41c may be an oxide layer, such as an oxide layer formed of tetraethoxysilane (TEOS). The third dielectric layer 41c may then be removed to expose the top surface of the underlying second dielectric layer 41b. In some embodiments, the third dielectric layer 41c is completely removed to expose the top surface of the second dielectric layer 41b. The removal of the third dielectric layer 41c may be by or include etching, CMP, mechanical polishing, or a combination thereof. The deposition and removal of the third dielectric layer 41c may enhance the flatness of the top surface of the second dielectric layer 41b. After the removal of the third dielectric layer 41c, the exposed top surface of the second dielectric layer 41b may have a roughness of less than 3 angstroms. In the embodiments disclosed herein, the first dielectric layer 41a of the multilayer bonding film 41 provides good thermal conductivity, while the second dielectric layer 41b of the multilayer bonding film 41 provides a flat top surface with a roughness of less than 3 angstroms, thereby improving the yield of subsequent processes.

[0035] Reference Figure 1GA carrier plate C2 is provided, comprising a bonding film 42 formed thereon. In some embodiments, the carrier plate C2 is a glass substrate, a ceramic carrier plate, or the like. The carrier plate C2 may have a circular top-view shape and the dimensions of the glass substrate. For example, the carrier plate C2 may have an 8-inch diameter, a 12-inch diameter, or similar dimensions. The bonding film 42 may be an oxide layer. In some embodiments, the bonding film 42 may be an oxide layer, such as an oxide bonding layer formed of tetraethoxysilane (TEOS), which may subsequently be removed along with the carrier plate C2. In some embodiments, the bonding film 42 is a dielectric film deposited on the carrier plate C2. The top surface of the bonding film 42 is substantially flat.

[0036] A bonding process is performed to bond the second dielectric layer 41b of the multilayer bonding film 41 to the bonding film 42 carried on the carrier substrate C2. This bonding process can be a wafer-to-wafer bonding process. After the multilayer bonding film 41 and the bonding film 42 carried on the carrier substrate C2 are bonded, the bonding film 42 and the multilayer bonding film 41 are located between the carrier substrate C2 and the semiconductor die 30. Furthermore, the gap filler material 38 and the semiconductor die 30 are separated from the bonding film 42 by the multilayer bonding film 41.

[0037] Reference Figure 1G and Figure 1H The structure formed on the carrier plate C1 (such as Figure 1F After the bonding film 42 carried on the carrier plate C2 is bonded to the bonding dielectric layer 18a, the carrier plate C1 debonded the bonding dielectric layer 18a, thus exposing the bonding dielectric layer 18a.

[0038] Reference Figure 1H and Figure 1I The bonding dielectric layer 18a is patterned to form openings, allowing the topmost interconnect wiring of the interconnect structure 16 to be exposed through the openings formed in the bonding dielectric layer 18a. Forming the openings in the bonding dielectric layer 18a can be performed using photolithography and subsequent etching or other suitable patterning processes. A passivation layer 44, containing the openings therein, can be formed to cover the bonding dielectric layer 18a, allowing the topmost interconnect wiring of the interconnect structure 16 to be exposed through the openings in the passivation layer 44. Forming the openings in the passivation layer 44 can be performed using photolithography and subsequent etching or other suitable patterning processes. The width of the openings defined in the passivation layer 44 can be smaller than the width of the openings defined in the bonding dielectric layer 18a. The passivation layer 44 can cover the top surface of the bonding dielectric layer 18a. The passivation layer 44 can further extend into the openings defined in the bonding dielectric layer 18a, such that the passivation layer 44 contacts the topmost interconnect wiring of the interconnect structure 16.

[0039] After the passivation layer 44 is formed, conductive terminals 46 are formed on the passivation layer 44. The conductive terminals 46 are electrically connected to the interconnect wiring of the interconnect structure 16 and protrude from the passivation layer 44. Each conductive terminal 46 may include a conductive post 46a and a solder cap 46b disposed on the conductive post 46a. The conductive post 46a fills an opening defined in the passivation layer 44 and protrudes from the passivation layer 44. The solder cap 46b covers the top surface of the conductive post 46a. After the conductive terminals 46 are formed, a chip probing process may be performed to improve yield. Forming the conductive terminals 46 may include forming a seed layer (not shown) on the passivation layer 44, forming a patterned mask (not shown) such as a mask layer on the seed layer, and then performing an electroplating process on the exposed seed layer. The patterned mask and the portion of the seed layer covered by the patterned mask are then removed, leaving the conductive terminals 46. A reflow process may be further performed to reshape the contour of the solder cap 46b. According to some embodiments, the seed layer includes a titanium layer and a copper layer situated on the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). Electroplating can be performed using, for example, chemical electroplating.

[0040] Reference Figure 1J and Figure 1K After the chip probing process, the solder cap 46b is removed, and a dielectric layer 48 is formed on the passivation layer 44 to cover the conductive pillar 46a. In other words, the conductive pillar 46a is protected by the dielectric layer 48, and the conductive pillar 46a is not exposed at this stage. In some embodiments, the dielectric layer 48 is formed of a polymer, which may be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In some other embodiments, the dielectric layer 48 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like.

[0041] Reference Figure 1J and Figure 1KA frame mount process is performed on conductive post 46a, so that the structure supported by carrier plate C2 is mounted on tape TP1 supported by the frame. After the frame mount process, dielectric layer 48 is attached to tape TP1, and then a debonding process is performed, so that carrier plate C2 is debonded from semiconductor die 30 and insulating encapsulation 40. After the debonding process, the back surfaces of semiconductor die 30 and insulating encapsulation 40 are exposed. During the debonding process, bonding film 42 is also debonded from semiconductor die 30 and insulating encapsulation 40. Debonding can be performed by irradiating bonding film 42 with light such as ultraviolet light or laser to decompose bonding film 42.

[0042] Reference Figure 1K and Figure 1L A tape TP2, carried by another frame, is provided, on which an adhesion film 50 is formed. The structure carried by the tape TP1 is transferred and bonded to the adhesion film 50. A dicing process is then performed along the dicing line SL to obtain a diced chip stack structure 100 (i.e., a SoIC structure). During the dicing process, the dielectric layer 48, passivation layer 44, bonding dielectric layer 18a, interconnect structure 16, planarization layer 24, semiconductor substrate 12, bonding structure 26, insulating encapsulator 40, and adhesion film 50 are diced along the dicing line SL. In some embodiments, after the dicing process, in each diced chip stack structure 100, the insulating encapsulator 40 laterally covers the semiconductor die 30, wherein the sidewalls of the insulating encapsulator 40 are substantially aligned with the sidewalls of the dielectric layer 48, passivation layer 44, bonding dielectric layer 18a, interconnect structure 16, planarization layer 24, semiconductor substrate 12, bonding structure 26, and adhesion film 50.

[0043] Figures 2A to 2I This is a cross-sectional view illustrating the process flow for manufacturing a package-on-package (PoP) structure according to some embodiments of this disclosure.

[0044] Reference Figure 2AThe system provides a carrier plate 60 having a bond remover layer 62 formed thereon. In some embodiments, the carrier plate 60 is a glass substrate, a ceramic carrier plate, or the like. The carrier plate 60 may have a circular top-view shape and size similar to a silicon wafer. For example, the carrier plate 60 may have an 8-inch diameter, a 12-inch diameter, or similar dimensions. The bond remover layer 62 may be formed of a polymer-based material (e.g., a light-to-heat-conversion (LTHC) material), which may then be removed along with the carrier plate 60 from an overlay structure to be formed in subsequent steps. In some embodiments, the bond remover layer 62 is formed of an epoxy-based heat-release material. In other embodiments, the bond remover layer 62 is formed of a UV adhesive. The bond remover layer 62 may be applied in a liquid state and subsequently cured. In an alternative embodiment, the bond remover layer 62 is a laminated film and is laminated onto the carrier plate 60. The top surface of the bond remover layer 62 is substantially flat.

[0045] Reference Figures 2A to 2C A redistribution structure 61, including a dielectric layer 64, redistribution conductors 66, and a dielectric layer 68, is formed on the debonding layer 62, such that the debonding layer 62 is located between the carrier board 60 and the dielectric layer 64 of the redistribution structure 61. Figure 2A As shown, dielectric layer 64 is formed on the bonding layer 62. In some embodiments, dielectric layer 64 is formed of a polymer, which may also be a photosensitive material such as PBO, polyimide, BCB, or the like, and can be patterned using photolithography followed by etching, or other suitable patterning processes. In some embodiments, dielectric layer 64 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. Figure 2B As shown, redistribution conductors 66 are formed on dielectric layer 64. The formation of redistribution conductors 66 may include forming a seed layer (not shown) on dielectric layer 64, forming a patterned mask (not shown) such as a mask layer on the seed layer, and then performing an electroplating process on the exposed seed layer. The patterned mask and the portion of the seed layer covered by the patterned mask are subsequently removed, leaving a layer such as... Figure 2B The redistribution wire 66 is shown. According to some embodiments, the seed layer includes a titanium layer and a copper layer situated on the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). Electroplating can be performed using, for example, chemical electroplating. Figure 2CAs shown, a dielectric layer 68 is formed on a dielectric layer 64 to cover the redistribution conductor 66. The bottom surface of the dielectric layer 68 contacts the redistribution conductor 66 and the top surface of the dielectric layer 64. According to some embodiments of this disclosure, the dielectric layer 68 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like. In some embodiments, the dielectric layer 68 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 68 is then patterned to form openings 70 therein. Thus, portions of the redistribution conductor 66 are exposed through the openings 70 in the dielectric layer 68. Figure 2C The following figures illustrate a single redistribution structure 61 with a single layer of redistribution conductors 66 for illustrative purposes only. In some embodiments, multiple layers of redistribution conductors 66 may be fabricated by repeating the process discussed above.

[0046] Reference Figure 2D After the redistribution structure 61 is formed on the bonding layer 62 on the carrier 60, a metal pillar 72 is formed on the redistribution structure 61 and electrically connected to the redistribution conductor 66 of the redistribution structure 61. Throughout the description, the metal pillar 72 is also referred to as a conductive via 72 because the metal pillar 72 penetrates the subsequently formed molding material (such as...). Figure 2G (As shown). In some embodiments, the conductive via 72 is formed by electroplating. The electroplating of the conductive via 72 may include forming a whole-sheet seed layer (not shown) on the dielectric layer 68 and extending into it. Figure 2C In the opening 70 shown, a mask (not shown) is formed and patterned, and a conductive via 72 is electroplated on the seed layer portion exposed through the opening in the mask. The mask and the portion of the seed layer covered by the mask are then removed. The material of the conductive via 72 may include copper, aluminum, or the like. The conductive via 72 may have a rod-like shape. The top view shape of the conductive via 72 may be circular, rectangular, square, hexagonal, or other similar shapes.

[0047] Reference Figure 2E After forming the conductive via 72, Figure 1L The chip stack structure 100 shown is placed on the rewiring structure 61. Figure 1L The chip stack structure 100 shown can be attached to the redistribution structure 61 through the attachment film 50. Figure 2E The image shows a single chip stack structure 100 and its surrounding conductive vias 72 for illustrative purposes only. The chip stack structure 100 is surrounded by conductive vias 72. Figure 2EAs shown, the lateral dimension of the attachment film 50 is slightly larger than the lateral dimension of the chip stack structure 100. In other words, the area occupied by the attachment film 50 is larger than the area occupied by the chip stack structure 100. Furthermore, after the chip stack structure 100 is attached to the redistribution structure 61, the edge of the attachment film 50 can extend upwards to cover the sidewalls of the chip stack structure 100. Figure 2E As shown, the edge of the attachment film 50 may extend upward to cover the sidewalls of the multilayer bonding film 41 and the lower portion of the sidewalls of the insulating encapsulant 40.

[0048] Reference Figure 2F An insulating encapsulating material 76 is formed on the redistribution structure 61 to cover the chip stack structure 100 and the conductive vias 72. The insulating encapsulating material 76 can be a molding compound (e.g., epoxy resin or other suitable resin) formed through a molding process. The insulating encapsulating material 76 fills not only the gaps between adjacent conductive vias 72, but also the gaps between the conductive vias 72 and the chip stack structure 100. At this stage, the insulating encapsulating material 76 covers the surface of the dielectric layer 48 of the chip stack structure 100.

[0049] Next, as Figure 2G As shown, planarization (such as CMP and / or mechanical polishing) is performed to partially remove the insulating encapsulation 76 and the dielectric layer 48 of the chip stack structure 100 until the conductive vias 72 and the conductive pillars 46a of the chip stack structure 100 are exposed. After the insulating encapsulation 76 is thinned, as... Figure 2G As shown, an insulating encapsulation 76' is formed to laterally cover the chip stack structure 100 and the conductive via 72. Due to planarization, the conductive via 72 penetrates the insulating encapsulation 76', and the tip of the conductive via 72 is substantially flush with or coplanar with the surface of the dielectric layer 48 and substantially flush with or coplanar with the surface of the insulating encapsulation 76' within the range of process variations. In the illustrated example embodiment, planarization is performed until the conductive via 72 and the conductive post 46a of the chip stack structure 100 are exposed.

[0050] Reference Figure 2H A rewiring structure 77, including a dielectric layer 78, a redistribution layer 80, a dielectric layer 82, a redistribution layer 86, and a dielectric layer 88, is formed on the chip stack structure 100 and the insulating encapsulation 76'. After forming the rewiring structure 77, a solder region including a ball bottom metal layer (UBMs) 92 and electrical connection terminals 94 disposed on the ball bottom metal layer 92 is formed on the rewiring structure 77.

[0051] A dielectric layer 78 is formed to cover the dielectric layer 48, the conductive pillar 46a, and the insulating encapsulation 76'. In some embodiments, the dielectric layer 78 is formed of a polymer such as PBO, polyimide, or the like. In other embodiments, the dielectric layer 78 is formed of silicon nitride, silicon oxide, or the like. Openings may be formed in the dielectric layer 78 to expose the conductive via 72 and the conductive pillar 46a. Forming openings in the dielectric layer 78 may be performed by a photolithography process followed by an etching process, or other suitable patterning processes.

[0052] Next, a redistribution line 80 is formed to connect the conductive post 46a and the conductive via 72. The redistribution line 80 may also interconnect the conductive post 46a and the conductive via 72. The redistribution line 80 may include metal traces (metal lines) on the dielectric layer 78 and metal vias extending into openings defined in the dielectric layer 78 to electrically connect the conductive via 72 and the conductive post 46a. In some embodiments, the redistribution line 80 is formed by an electroplating process, wherein each redistribution line 80 includes a seed layer (not shown) and an electroplated metal material on the seed layer. The seed layer and the electroplated metal material may be formed of the same material or different materials. The redistribution line 80 may include metals or metal alloys, including aluminum, copper, tungsten, and alloys thereof. The redistribution line 80 may be formed of a non-solder material. The via portions of the redistribution line 80 may be in physical contact with the surfaces of the conductive via 72 and the conductive post 46a.

[0053] Next, a dielectric layer 82 is formed on the redistribution line 80 and the dielectric layer 78. The dielectric layer 82 may be formed using a polymer selected from the same candidate materials as the dielectric layer 78. For example, the dielectric layer 82 may include PBO, polyimide, BCB, or the like. In some embodiments, the dielectric layer 82 may include an organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. Openings may also be formed in the dielectric layer 82 to expose the redistribution line 80. The formation of the openings defined in the dielectric layer 82 may be performed using a photolithography process followed by an etching process, or other suitable patterning processes. The redistribution line 86 may be formed using methods and materials similar to those used to form the redistribution line 80.

[0054] A dielectric layer 88, which may be a polymer layer, is formed to cover the redistribution layer 86 and the electrical layer 82. The dielectric layer 88 may be selected from the same candidate polymers used to form dielectric layers 78 and 82. Openings may be formed in the dielectric layer 88 to expose the metal pad portions of the redistribution layer 86. The formation of the openings defined in the dielectric layer 88 may be performed by a photolithography process followed by an etching process, or other suitable patterning processes.

[0055] The formation of the ball-bottom metal layer 92 may include a deposition process followed by a patterning process. The formation of the electrical connection terminal 94 may include placing solder on an exposed portion of the ball-bottom metal layer 92 and then reflowing the solder to form a solder ball. In some embodiments, the formation of the electrical connection terminal 94 includes performing an electroplating step to form a solder region on the redistribution 86, followed by reflowing the solder region. In other embodiments, the electrical connection terminal 94 includes metal pillars or metal pillars with solder caps, which may also be formed by electroplating. Throughout the description, the combined structure including the chip stack structure 100, conductive via 72, insulating encapsulation 76', redistribution structure 61, redistribution structure 77, ball-bottom metal layer 92, and electrical connection terminal 94 will be referred to as a wafer-level package, which may be a reconstructed wafer with a circular top-view shape.

[0056] Reference Figure 2H and Figure 2I Then, a debonding process is performed to debond the carrier 60 from the wafer-level package. After the debonding process, the dielectric layer 64 of the redistribution structure 61 is exposed. During the debonding process, the debonding layer 62 is also removed from the wafer-level package. Debonding can be performed by irradiating the debonding layer 62 with light such as ultraviolet light or a laser to break down the debonding layer 62. During the debonding process, tape (not shown) can be adhered to the dielectric layer 88 and the electrical connection terminals 94. In a subsequent step, the carrier 60 and the debonding layer 62 are removed from the wafer-level package. A dicing process is then performed to... Figure 2H The chip-level packaging described in the text is cut into Figure 2I The multiple individually integrated fan-out packages P1 are described in the text.

[0057] A patterning process is performed to form openings in dielectric layer 64 to expose redistribution 66. The formation of the openings defined in dielectric layer 64 can be performed via photolithography followed by etching, or other suitable patterning processes. A top package P2 is then provided and bonded to an integrated fan-out package P1 (i.e., a bottom package) to form a PoP structure. In some embodiments disclosed herein, the bonding between the top package P2 and the integrated fan-out package P1 is performed via electrical connection terminals (e.g., solder areas) 96 that connect the metal pad portions of the redistribution 66 to metal pads in the top package P2. An underfill 98 may be formed to fill the gap between the top package P2 and the integrated fan-out package P1, such that the electrical connection terminals 96 are laterally covered by the underfill 98, and the reliability of the electrical connection terminals 96 can be enhanced. In some embodiments, the top package P2 includes a semiconductor die 202, which may be a memory die, such as a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, or the like. In some example embodiments, the semiconductor die 202 may also be bonded to the packaging substrate 204.

[0058] In the above embodiments, the chip stack structure 100 (e.g., a SoIC structure) is applied in an integrated fan-out (InFO) package with a PoP structure for illustrative purposes. However, the chip stack structure 100 can be applied to other suitable types of packages, such as... Figure 11 and Figure 12 The chip-on-wafer-on-substrate (CoWoS) package described herein.

[0059] like Figure 2I As shown, the PoP structure may include an InFO package P1 and a package P2 stacked on the InFO package P1. The InFO package includes a chip stack structure 100 (e.g., a SoIC structure) having a multilayer bonding film 41 and an insulating encapsulation 76'. The chip stack structure 100 may include a first semiconductor die 20, a second semiconductor die 30, an insulating encapsulation 40, and a multilayer bonding film 41. The second semiconductor die 30 is disposed on and electrically connected to the first semiconductor die 20. The insulating encapsulation 40 is disposed on the first semiconductor die 20 and laterally covers the second semiconductor die 30. The multilayer bonding film 41 is disposed on the surface of the insulating encapsulation 40 and the surface of the second semiconductor die 30. The multilayer bonding film 41 includes a flat surface. The surface of the insulating encapsulation 40 may be substantially flush with the surface of the second semiconductor die 30. In some embodiments, the multilayer bonding film 41 includes a first dielectric layer 41a and a second dielectric layer 41b, wherein the first dielectric layer 41a is in contact with the surface of the insulating package 40 and the surface of the second semiconductor die 30, and the second dielectric layer 41b covers the first dielectric layer 41a and has a flat surface. In some embodiments, the chip stack structure 100 further includes an attachment film 50 covering the multilayer bonding film 41, wherein the attachment film 50 is in contact with the flat surface of the second dielectric layer 41b of the multilayer bonding film 41.

[0060] Figures 3A to 3G This is a cross-sectional view illustrating the process flow for manufacturing a chip stack structure according to some other embodiments of this disclosure.

[0061] Reference Figure 3A and Figure 1F , Figure 3A The process described in the text and Figure 1FSimilar to the description, except that the surface of the insulating encapsulation 40 includes a concave surface, the surface (e.g., the back surface) of the second semiconductor die 30 includes a convex surface, and the bottommost dielectric layer (i.e., the first dielectric layer 41a) in the multilayer bonding film 41 is conformally formed on the concave surface of the insulating encapsulation 40 and the convex surface of the second semiconductor die 30. The first dielectric layer 41a is thicker than the second dielectric layer 41b. In the chip stack structure 200, the second dielectric layer 41b in the multilayer bonding film 41 has a flat surface. The first dielectric layer 41a includes a first dielectric portion and a second dielectric portion, the maximum thickness of the second dielectric portion of the first dielectric layer 41a is greater than the maximum thickness of the first dielectric portion of the first dielectric layer 41a, and the second dielectric layer 41b includes a first dielectric portion and a second dielectric portion, the maximum thickness of the first dielectric portion of the second dielectric layer 41b is greater than the maximum thickness of the second dielectric portion of the second dielectric layer 41b. The first dielectric portion is located above and covers the second semiconductor die 30, while the second dielectric portion is located above and covers the insulating encapsulation 40. For example... Figure 3A As shown, the first dielectric layer 41a does not include a flat top surface, while the second dielectric layer 41b does include a flat top surface. Furthermore, the second dielectric layer 41b is in contact with and covered by the adhesion film 50 (e.g., Figure 3G (As shown). The first dielectric layer 41a provides good thermal conductivity, while the second dielectric layer 41b is thick enough to adequately cover the topography provided by the second semiconductor die 30 and the insulating encapsulator 40, such that the second dielectric layer 41b of the multilayer bonding film 41 provides suitable planarization functionality. For example, the thickness of the first dielectric layer 41a ranges from about 500 angstroms to about 3000 angstroms, while the thickness of the second dielectric layer 41b ranges from about 200 angstroms to about 500 angstroms. Furthermore, the maximum thickness of the second semiconductor die 30 is greater than the thickness of the insulating encapsulator 40. For example, the difference between the maximum thickness of the second semiconductor die 30 and the thickness of the insulating encapsulator 40 ranges from about 0.1 micrometers to about 0.5 micrometers. It should be noted that the insulating encapsulator 40 has sidewalls that contact the sidewalls of the second semiconductor die 30, and the sidewall heights of the second semiconductor die 30 and the insulating encapsulator 40 are substantially the same. In other words, there is no height difference between the sidewalls of the second semiconductor die 30 and the sidewalls of the insulating encapsulation 40. In some other embodiments, the sidewalls of the second semiconductor die 30 are higher or lower than the sidewalls of the insulating encapsulation 40, such as... Figure 10A and Figure 10B As shown. In other words, there is a height difference (e.g., about 0.1 micrometers to about 0.5 micrometers) between the sidewalls of the second semiconductor die 30 and the sidewalls of the insulating encapsulation 40. Figure 10A and Figure 10B In the embodiment shown, there is a stepped portion between the sidewall of the second semiconductor die 30 and the sidewall of the insulating encapsulation 40.

[0062] Reference Figures 3B to 3G as well as Figures 1G to 1L , Figures 3B to 3G The process flow described in the document is consistent with Figure 1G and Figure 1L Similar to the explanation in [the text]. Therefore, regarding... Figures 3B to 3G The details of the process flow described herein are omitted here.

[0063] Figures 4 to 7 These are schematic cross-sectional views illustrating various chip stack structures according to some alternative embodiments of this disclosure.

[0064] Reference Figure 4 and Figure 3G , Figure 4 The chip stack structure 300 described in the text is... Figure 3G Similar to the chip stack structure 200 described herein, the difference is that the multilayer bonding film 41 of the chip stack structure 300 further includes a third dielectric layer 41c covering the second dielectric layer 41b. In some embodiments, the second dielectric layer 41b and the third dielectric layer 41c are dielectric layers with uniform thickness. Furthermore, the third dielectric layer 41c is in contact with and covered by the adhesion film 50.

[0065] Reference Figure 5 and Figure 1F , Figure 5 The chip stack structure 400 described in the text is... Figure 1F Similar to the description, the difference lies in that the surface of the insulating encapsulation 40 includes a convex surface, the surface (e.g., the back surface) of the second semiconductor die 30 includes a concave surface, and the uppermost dielectric layer (i.e., the first dielectric layer 41a) in the multilayer bonding film 41 is conformally formed on the concave surface of the insulating encapsulation 40 and the convex surface of the second semiconductor die 30. The first dielectric layer 41a is thicker than the second dielectric layer 41b. In the chip stack structure 200, the second dielectric layer 41b in the multilayer bonding film 41 has a flat surface. The first dielectric layer 41a includes a first dielectric portion and a second dielectric portion, the maximum thickness of the first dielectric portion of the first dielectric layer 41a is greater than the maximum thickness of the second dielectric portion of the first dielectric layer 41a, and the second dielectric layer 41b includes a first dielectric portion and a second dielectric portion, the maximum thickness of the first dielectric portion of the second dielectric layer 41b is greater than the maximum thickness of the second dielectric portion of the second dielectric layer 41b. The first dielectric portion is located above and covers the second semiconductor die 30, while the second dielectric portion is located above and covers the insulating encapsulation 40. For example... Figure 5As shown, the first dielectric layer 41a does not include a planar top surface, while the second dielectric layer 41b does. The first dielectric layer 41a provides good thermal conductivity, and the second dielectric layer 41b is thick enough to adequately cover the terrain provided by the second semiconductor die 30 and the insulating encapsulator 40, such that the second dielectric layer 41b of the multilayer bonding film 41 provides suitable planarization functionality. For example, the thickness of the first dielectric layer 41a ranges from about 500 angstroms to about 3000 angstroms, and the thickness of the second dielectric layer 41b ranges from about 200 angstroms to about 500 angstroms. Furthermore, the maximum thickness of the insulating encapsulator 40 is greater than the thickness of the second semiconductor die 30. For example, the difference between the maximum thickness of the second semiconductor die 30 and the thickness of the insulating encapsulator 40 ranges from about 0.1 micrometers to about 0.5 micrometers. It should be noted that the sidewall of the insulating encapsulation 40 is in contact with the sidewall of the second semiconductor die 30, and the height of the sidewall of the second semiconductor die 30 is substantially the same as the height of the sidewall of the insulating encapsulation 40. In other words, there is no height difference between the sidewall of the second semiconductor die 30 and the sidewall of the insulating encapsulation 40.

[0066] Reference Figure 6 and Figure 4 , Figure 6 The chip stack structure 500 described in the document is... Figure 4 The chip stack structure 300 described herein is similar, except that both the first dielectric layer 41 and the second dielectric layer 41b conformally cover the uneven surface (or curved surface) provided by the second semiconductor die 30 and the insulating encapsulator 40. Furthermore, the third dielectric layer 41c of the multilayer bonding film 41 includes a first dielectric portion and a second dielectric portion. The maximum thickness of the first dielectric portion of the third dielectric layer 41c is greater than the maximum thickness of the second dielectric portion of the third dielectric layer 41c. The first dielectric portion covers the second semiconductor die 30, while the second dielectric portion covers the insulating encapsulator 40. Figure 6 As shown, the third dielectric layer 41c includes a dielectric pattern that covers a first portion of the second dielectric layer 41b. A second portion of the second dielectric layer 41b is not covered by the third dielectric layer 41c, and the top surface of the second portion of the second dielectric layer 41b is substantially flush with the top surface of the dielectric pattern of the third dielectric layer 41c. Furthermore, both the second dielectric layer 41b and the third dielectric layer 41c are in contact with and covered by the adhesion film 50.

[0067] Reference Figure 6 and Figure 7 , Figure 7 The chip stack structure 600 described in the text is... Figure 6The chip stack structure 500 described herein is similar, except that the second dielectric layer 41b is completely covered by the third dielectric layer 41c. The first dielectric layer 41a and the second dielectric layer 41b do not contact the adhesion film 50. Furthermore, the first dielectric layer 41a and the second dielectric layer 41b are separated from the adhesion film 50 through the third dielectric layer 41c.

[0068] It is important to note that Figures 5 to 7 The design of the multilayer bonding film 41 described herein can be applied to Figure 4 The structure is described in the diagram. Furthermore, the number of dielectric layers in the multilayer bonding film 41 is not limited to two or three layers. Multilayer bonding films 41 with more than three dielectric layers can also be applied to… Figure 3G as well as Figures 4 to 7 The structure described in the text.

[0069] Figure 8 This is a schematic cross-sectional view illustrating the face-to-face bonding of a semiconductor wafer 10' and a semiconductor die 30 according to some other embodiments of this disclosure.

[0070] Reference Figure 1D and Figure 8 The bonding between semiconductor wafer 10' and semiconductor die 30 is similar to the bonding between semiconductor wafer 10 and semiconductor die 30, except that the bonding between semiconductor wafer 10' and semiconductor die 30 is a face-to-face bonding. For example... Figure 8 As shown, wafer 10' may include a semiconductor substrate 12 (e.g., a silicon substrate), a through-substrate via 14 embedded in the semiconductor substrate 12, an interconnect structure 16 disposed on the semiconductor substrate 12, and a bonding structure 26 disposed on the interconnect structure 16, wherein the through-substrate via 14 is electrically connected to the interconnect structure 16. The semiconductor substrate 12 of wafer 10' may include a crystalline silicon wafer. The semiconductor substrate 12 may include various doped regions (e.g., a p-type substrate or an n-type substrate) depending on design requirements. In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured as n-type fin field-effect transistors (FinFETs) and / or p-type fin field-effect transistors. In some alternative embodiments, the semiconductor substrate 12 is made of other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. The semiconductor die 30 is bonded to the semiconductor wafer 10' via bonding structure 26 and bonding structure 36.

[0071] Figure 9 This is a schematic cross-sectional view illustrating a chip stack structure according to some other embodiments of this disclosure.

[0072] Reference Figure 1L and Figure 9 , Figure 9 The single-chip stack structure 100' described in the text is related to... Figure 1L The single-chip stack structure 100 (i.e., SoIC structure) described herein is similar, except that the single-chip stack structure 100' does not include the insulating encapsulation 40, because the insulating encapsulation 40 is in Figure 1L It was removed in the simplified process shown. For example... Figure 9 As shown, in the monolithic chip stack structure 100', the first semiconductor die 20 and the second semiconductor die 30 are substantially identical in lateral dimensions. In other words, in the monolithic chip stack structure 100', the sidewalls of the first semiconductor die 20 and the sidewalls of the second semiconductor die 30 are substantially aligned.

[0073] Figure 11 and Figure 12 These are schematic cross-sectional views illustrating various CoWoS package structures according to various alternative embodiments of this disclosure.

[0074] Reference Figure 11 A CoWoS package structure 700 is provided, comprising a package substrate 710 and a semiconductor device 720. The semiconductor device 720 is mounted on the surface of the package substrate 710. The semiconductor device 720 is electrically connected to the package substrate 710. The semiconductor device 720 may include at least one semiconductor die 721 and an insulating package 722 laterally covering at least one semiconductor die 721. The semiconductor device 720 may also include an intermediate wiring substrate 723, conductive terminals 724, a dielectric layer 725, conductive terminals 726, and a dielectric layer 727. Figure 11 As shown, the packaging substrate 710 may be a printed circuit board or other suitable type of wiring substrate. At least one semiconductor die 721 may be or include at least one first semiconductor die 721a and at least one second semiconductor die 721b. At least one first semiconductor die 721a and at least one second semiconductor die 721b are arranged side by side on the intermediate wiring substrate 723.

[0075] In some embodiments, the first semiconductor die 721a includes a system-on-a-chip (SoC) die, while the second semiconductor die 721b includes a high-bandwidth memory (HBM) cube, the HBM cube including stacked HBM memory dies and a controller die for controlling the operation of the stacked HBM memory dies. Figure 11 In the embodiment shown, Figure 1L The chip stack structure 100 shown is implemented as follows Figure 11The first semiconductor die 721a is shown. It should be noted that in other embodiments, other types of SoIC structures, such as chip stack structures 200 to 600, may be implemented as follows: Figure 11 The first semiconductor die 721a is shown. The first semiconductor die 721a and the second semiconductor die 721b are disposed on an interposer substrate 723 and electrically connected to the interposer substrate 723 via conductive terminals 724. The conductive terminals 724 are disposed between the semiconductor die 721a and the interposer substrate 723. The conductive terminals 724 may be or include microbumps for electrically connecting the semiconductor die 721a and the interposer substrate 723. A dielectric layer 725 is disposed on the interposer substrate 723. The dielectric layer 725 (e.g., an underfill) is disposed between the semiconductor die 721a and the interposer substrate 723 to laterally cover the conductive terminals 724. In some embodiments, the dielectric layer 725 includes an underfill material, a molding compound, a polymer, an oxide material, a nitride material, or a combination thereof. Therefore, the shear stress experienced by the conductive terminals 724 can be minimized through the dielectric layer 725, and the reliability of the conductive terminals 724 can be enhanced through the dielectric layer 725. The dielectric layer 725 may be made of epoxy resin or other suitable dielectric materials.

[0076] like Figure 11 As shown, an insulating encapsulation 722 is disposed on an interposer substrate 723 to laterally cover a semiconductor die 721 and a dielectric layer 725. The top surface (e.g., back surface) of the semiconductor die 721 is substantially flush with the top surface of the insulating encapsulation 722, and the sidewalls of the insulating encapsulation 722 are substantially aligned with the sidewalls of the interposer substrate 723. A conductive terminal 726 is disposed on the bottom surface of the interposer substrate 723, and the interposer substrate 723 is electrically connected to a package substrate 710 through the conductive terminal 726. The conductive terminal 726 may be or include controlled-dip chip connection bumps (C4 bumps) for electrically connecting the interposer substrate 723 and the package substrate 710. A dielectric layer 727 (e.g., underfill) is disposed on the package substrate 710. The dielectric layer 727 is disposed between the interposer substrate 723 and the package substrate 710 to laterally cover the conductive terminal 726. In some embodiments, dielectric layer 727 includes an underfill material, a molding compound, a polymer, an oxide material, a nitride material, or a combination thereof. Furthermore, dielectric layer 727 covers the sidewalls of the intermediate wiring substrate 723 and the lower portion of the sidewalls of the insulating encapsulation 722.

[0077] Semiconductor die 721 is electrically connected to package substrate 710 through interposer substrate 723, conductive terminal 724, and conductive terminal 726. Interposer substrate 723 may include a silicon interposer, an organic interposer, or other suitable interposer substrate. Interposer substrate 723 may include conductive wiring formed thereon. Furthermore, interposer substrate 723 may include conductive vias formed therein. Interposer substrate 723 may be a silicon interposer substrate with fine line pitch (e.g., submicron pitch), an organic interposer substrate with less fine line pitch (e.g., 4-micron pitch), or an interposer substrate with local silicon interconnect (LSI) dies. In embodiments where interposer substrate 723 is a silicon interposer substrate, CoWoS package structure 700 is referred to as a CoWoS-S package. In embodiments where interposer substrate 723 is an organic interposer substrate, CoWoS package structure 700 is referred to as a CoWoS-R package. In an embodiment where the interposer substrate 723 is an interposer substrate with local silicon interconnect (LSI) dies, the CoWoS package structure 700 is referred to as a CoWoS-L package.

[0078] In some embodiments, the semiconductor device 720 may further include a back-side metal layer 728 disposed on the top surface (e.g., the back surface) of the semiconductor die 721 and the top surface of the insulating encapsulation 722. The back-side metal layer 728 covers and contacts the top surface (e.g., the back surface) of the semiconductor die 721 and the top surface of the insulating encapsulation 722. The back-side metal layer 728 may be a single-layer metal structure or a multi-layer metal structure. The back-side metal layer 728 may be or include a copper layer or other metal layers with good thermal conductivity.

[0079] Reference Figure 11 and Figure 12 , Figure 12 The CoWoS package structure 700' described in the document is... Figure 11 The CoWoS package structure 700 is similar to that described in the previous section, except that the CoWoS package structure 700' further includes a photonic component 721c disposed on an intermediate wiring substrate 723. Furthermore, the CoWoS package structure 700' does not include... Figure 11The back-side metal layer 728 is described in the diagram. A first semiconductor die 721a, a second semiconductor die 721b, and a photonic component 721c are disposed on an intermediate wiring substrate 723 and electrically connected to the intermediate wiring substrate 723 via conductive terminals 724. The photonic component 721c may include a photonic integrated circuit (PIC) 730 and an electrical integrated circuit (EIC) 731 electrically connected to each other via metal-to-metal bonding and dielectric-to-dielectric bonding. The photonic component 721c may further include a support substrate 732, a lens substrate 733 having a lens portion (e.g., a Si / SiO2 lens portion) 733L formed thereon, and a protective film 734 covering the lens substrate 733, wherein the support substrate 732 is disposed on the photonic die 730, and the support substrate 732 and the electrical die 731 are arranged side-by-side. Lens substrate 733 and protective film 734 are disposed on and cover support substrate 732 and electrical die 731. In some embodiments, the bonding structure of photonic die 730 and electrical die 731 in photonic component 721c can be any of chip stack structures 200 to 600. Photonic component 721c can be or includes edge couplers or grating couplers, depending on the location of light input and output (e.g., an optical module with optical fibers). Furthermore, first semiconductor die 721a, second semiconductor die 721b, and photonic component die 721c are arranged side-by-side on intermediate wiring substrate 723.

[0080] In the above embodiments, the multilayer bonding film design in the chip stack structure (e.g., SoIC structure) provides good planarization, thereby enhancing reliability and bonding yield.

[0081] According to some embodiments disclosed herein, a chip stack structure is provided including a first semiconductor die, a second semiconductor die, an insulating encapsulator, and a multilayer bonding film. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The insulating encapsulator is disposed on the first semiconductor die and laterally covers the second semiconductor die. The multilayer bonding film is disposed on the surface of the insulating encapsulator and the surface of the second semiconductor die. The multilayer bonding film includes a flat surface. In some embodiments, the surface of the insulating encapsulator is substantially flush with the surface of the second semiconductor die. In some embodiments, the surface of the insulating encapsulator includes a concave surface, the surface of the second semiconductor die includes a convex surface, and the topmost dielectric layer of the multilayer bonding film includes the flat surface. In some embodiments, the maximum thickness of the second semiconductor die is greater than the thickness of the insulating encapsulator. In some embodiments, the surface of the insulating encapsulator includes a convex surface, the surface of the second semiconductor die includes a concave surface, and the topmost dielectric layer of the multilayer bonding film includes the flat surface. In some embodiments, the maximum thickness of the insulating encapsulator is greater than the thickness of the second semiconductor die. In some embodiments, the multilayer bonding film includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is in contact with the surface of an insulating encapsulation and the surface of a second semiconductor die, the second dielectric layer covers the first dielectric layer, and the second dielectric layer has the flat surface. In some embodiments, the multilayer bonding film includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the first dielectric layer is in contact with the surface of an insulating encapsulation and the surface of a second semiconductor die, the second dielectric layer covers the first dielectric layer, the third dielectric layer covers the second dielectric layer, and the third dielectric layer has the flat surface. In some embodiments, the multilayer bonding film includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the first dielectric layer is in contact with the surface of an insulating encapsulation and the surface of a second semiconductor die, the second dielectric layer covers the first dielectric layer, the third dielectric layer includes a dielectric pattern, the dielectric pattern covers a first portion of the second dielectric layer, a second portion of the second dielectric layer is not covered by the third dielectric layer, and the surface of the second portion of the second dielectric layer is substantially flush with the surface of the dielectric pattern. In some embodiments, the chip stack structure further includes an attachment film covering the multilayer bonding film.

[0082] According to some other embodiments disclosed herein, a chip stack structure is provided including a first semiconductor die, a second semiconductor die, an insulating encapsulator, and a multilayer bonding film. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The insulating encapsulator is disposed on the first semiconductor die and laterally covers the second semiconductor die, wherein the second semiconductor die and the insulating encapsulator provide a convex-concave surface. The multilayer bonding film is disposed on the convex-concave surface, wherein the multilayer bonding film includes a first dielectric layer and a second dielectric layer, the first dielectric layer contacting the convex-concave surface, and the second dielectric layer being disposed on and contacting the first dielectric layer. In some embodiments, the multilayer bonding film further includes a third dielectric layer covering the second dielectric layer. In some embodiments, the multilayer bonding film further includes a third dielectric layer comprising a dielectric pattern covering a first portion of the second dielectric layer, a second portion of the second dielectric layer not covered by the third dielectric layer, and wherein the surface of the second portion of the second dielectric layer is substantially flush with the surface of the dielectric pattern. In some embodiments, the insulating encapsulator includes a concave surface, and the second semiconductor die includes a convex surface. In some embodiments, the maximum thickness of the second semiconductor die is greater than the thickness of the insulating encapsulation. In some embodiments, the insulating encapsulation includes a convex surface, while the surface of the second semiconductor die includes a concave surface. In some embodiments, the maximum thickness of the insulating encapsulation is greater than the thickness of the second semiconductor die.

[0083] According to some other embodiments of this disclosure, a method for manufacturing a chip stack structure is provided. A semiconductor wafer including a first semiconductor die is provided. A second semiconductor die is bonded to the first semiconductor die of the semiconductor wafer. A gap-filling material is formed on the semiconductor wafer to laterally cover the second semiconductor die. The gap-filling material is thinned until the surface of the second semiconductor die is exposed to form an insulating encapsulation laterally covering the second semiconductor die, wherein the second semiconductor die and the insulating encapsulation provide a curved surface. A multilayer bonding film is formed on the curved surface, wherein the multilayer bonding film includes a plane. In some embodiments, after thinning the gap-filling material to the surface of the second semiconductor die, the second semiconductor die includes a concave surface, and the insulating encapsulation includes a convex surface. In some embodiments, after thinning the gap-filling material to the surface of the second semiconductor die, the second semiconductor die includes a convex surface, and the insulating encapsulation includes a concave surface.

[0084] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. A chip stack structure, characterized in that, include: The first semiconductor die includes a first contact pad and a first bonding dielectric layer; A second semiconductor die is disposed above and electrically connected to the first semiconductor die, wherein the second semiconductor die includes a second contact pad and a second bonding dielectric layer located on a first side, the first contact pad is bonded to the second contact pad, the first bonding dielectric layer is bonded to the second bonding dielectric layer, and the first contact pad partially overlaps the second contact pad and partially overlaps the second bonding dielectric layer. An insulating encapsulation is disposed above the first semiconductor die and laterally covers the second semiconductor die; as well as An interlayer film is disposed above a second side of the second semiconductor die, the second side being opposite to the first side, wherein the interlayer film includes a first dielectric layer located above the second semiconductor die, and the first dielectric layer has a density greater than [missing information]. The first thermal conductivity.

2. The chip stack structure as described in claim 1, characterized in that, The interlayer film further includes a second dielectric layer covering the first dielectric layer, and the first thermal conductivity is greater than the second thermal conductivity of the second dielectric layer.

3. The chip stack structure as described in claim 1, characterized in that, The surface of the insulating encapsulant includes a concave surface, and the surface of the second semiconductor die includes a convex surface; or the surface of the insulating encapsulant includes a convex surface, and the surface of the second semiconductor die includes a concave surface.

4. A chip stack structure, characterized in that, include: The first semiconductor die includes a first contact pad and a first bonding dielectric layer; A second semiconductor die is disposed on and electrically connected to the first semiconductor die, wherein the second semiconductor die includes a second contact pad and a second bonding dielectric layer, the first contact pad is bonded to the second contact pad, the first bonding dielectric layer is bonded to the second bonding dielectric layer, and the first contact pad partially overlaps the second contact pad and partially overlaps the second bonding dielectric layer. as well as An interlayer film is formed on the second semiconductor die, wherein the interlayer film includes a first region having a first thickness and a second region having a second thickness, and the first thickness and the second thickness are different. The surface topography of the interlayer membrane is defined as the height difference between the highest and lowest points within a 1 mm height, wherein the first surface has a first surface topography greater than 30 angstroms, and the second surface has a second surface topography less than 30 angstroms. The interlayer film includes a first dielectric layer and a second dielectric layer covering the first dielectric layer.

5. The chip stack structure as described in claim 4, characterized in that, The interlayer membrane further comprises: A third dielectric layer includes a dielectric pattern that covers a first portion of the second dielectric layer, a second portion of the second dielectric layer that is not covered by the third dielectric layer, wherein the surface of the second portion of the second dielectric layer is flush with the surface of the dielectric pattern.

6. The chip stack structure as described in claim 4, characterized in that, The device further includes an insulating encapsulation disposed on the first semiconductor die and laterally covering the second semiconductor die, wherein the insulating encapsulation includes a concave surface and the second semiconductor die includes a convex surface.

7. The chip stack structure as described in claim 5, characterized in that, The invention further includes an insulating encapsulation disposed on the first semiconductor die and laterally covering the second semiconductor die, wherein the insulating encapsulation includes a convex surface and the surface of the second semiconductor die includes a concave surface.

8. A method for manufacturing a chip stack structure, characterized in that, include: Provides a semiconductor wafer including a first semiconductor die; The second semiconductor die is bonded to the first semiconductor die of the semiconductor wafer; An interstitial filling material is formed on the semiconductor wafer to coat the second semiconductor grain; Thinning the gap-filling material to form an insulating encapsulation laterally covering the second semiconductor die, wherein the second semiconductor die and the insulating encapsulation provide curved surfaces; and A multilayer bonding film is formed on the curved surface, wherein the multilayer bonding film includes a planar surface.

9. The method as described in claim 8, characterized in that, After the gap-filling material is thinned until the surface of the second semiconductor die is exposed, the second semiconductor die includes a concave surface, and the insulating encapsulation includes a convex surface.

10. The method as described in claim 8, characterized in that, After the gap-filling material is thinned until the surface of the second semiconductor die is exposed, the second semiconductor die includes a convex surface, and the insulating encapsulation includes a concave surface.

Images