A heterogeneous stacked integrated structure and manufacturing method for ultra-large scale pad interconnect arrays
By forming a patterned channel structure on the chip, the problem of non-uniform reactant transport in ultra-large-scale pad interconnect arrays in three-dimensional heterogeneous integration is solved, achieving high-quality interconnection and improving production yield and process reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 上海曜感科技有限公司
- Filing Date
- 2026-04-20
- Publication Date
- 2026-07-31
AI Technical Summary
In existing three-dimensional heterogeneous integration technologies, ultra-large-scale pad (PAD) interconnect arrays suffer from slow PAD growth, uneven interconnection, and high defect rate in the central region due to differences in reactant transport paths during self-growing interconnect processes.
Patterned channel structures are formed on the first chip and distributed around the periphery and/or row and column gaps of the ultra-large scale pad interconnect array. This ensures that the distance between each pad and the nearest patterned channel structure is less than a preset threshold. Reactive materials are introduced into the interconnect cavities through these channel structures to achieve uniform growth of conductive interconnects.
It significantly improves the interconnect quality and production yield of ultra-large-scale PAD arrays, ensures that each PAD receives a uniform supply of reactants, enhances the uniformity and reliability of interconnects, and reduces the defect rate.
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Figure CN122497411A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a method for realizing a heterogeneous stacked integrated structure of ultra-large-scale pad arrays through a patterned channel structure. Background Technology
[0002] As Moore's Law approaches its physical limits, three-dimensional heterogeneous integration technology, which stacks chips vertically, has become a core direction for improving chip performance in the post-Moore's Law era. Among these technologies, the self-growing method for forming interconnects between chips has attracted widespread attention due to its advantages such as low-temperature processing and low cost.
[0003] However, when there is a very large-scale PAD (pad) interconnect array on the chip (e.g., thousands or even tens of thousands of PADs arranged in an array), the self-growth process faces serious challenges: the PADs located in the center of the array are far from the chip edge, the reactant transport path is long, and the gas or liquid exchange rate is significantly lower than that of the edge PADs, resulting in slow growth of the center PADs, uneven interconnection, or even defects, which seriously affect the overall interconnect quality and production yield.
[0004] Existing technologies, such as Chinese patent CN113539861B, disclose a method for forming interconnect structures by electroplating after bonding. However, this approach does not consider the uniformity of reactant transport in ultra-large-scale PAD arrays, making it difficult to meet the requirements of advanced packaging for high-density and high-uniformity interconnects.
[0005] Therefore, developing a heterogeneous stacking integration manufacturing method that can ensure a uniform supply of reactants for each PAD in an ultra-large-scale PAD array and achieve high-quality interconnection has become a technical problem that urgently needs to be solved in this field. Summary of the Invention
[0006] This invention aims to solve the problems of slow PAD growth, uneven interconnection, and high defect rate in the central region of ultra-large-scale pad (PAD) interconnect arrays in the self-growing interconnect process due to differences in reactant transport paths in existing three-dimensional heterogeneous integration technology. It provides a heterogeneous stacking integration manufacturing method and structure that can ensure that each PAD in the ultra-large-scale PAD array receives a uniform supply of reactants and achieves high-quality interconnection.
[0007] To achieve the above objectives, the present invention provides a heterogeneous stacked integration manufacturing method for ultra-large scale pad interconnect arrays, comprising the following steps: A first chip is provided, wherein the bonding surface of the first chip is provided with an array of very large-scale pad interconnects arranged in an array, the array of very large-scale pad interconnects comprising multiple pads; A patterned channel structure is formed on the first chip. The patterned channel structure is distributed around the periphery and / or row and column gaps of the ultra-large scale pad interconnect array, such that the distance between each pad in the ultra-large scale pad interconnect array and the nearest patterned channel structure is less than a preset threshold. The patterned channel structure provides a transport path for the reactive material. The first chip is aligned and bonded to a heterogeneous second chip or wafer to form an interconnect cavity. The interconnect cavity is connected to the patterned channel structure, and the pads of the first chip and the pads of the second chip or wafer are arranged opposite to each other in the interconnect cavity. By introducing reactive material into the interconnect cavity through the patterned channel structure, conductive interconnects are selectively grown on the oppositely arranged pads, thereby achieving electrical interconnection between the first chip and the second chip or wafer.
[0008] Optionally, the patterned channel structure includes a through-channel extending through the first chip, the through-channel extending from the unbonded surface of the first chip to the bonded surface, allowing reactive material to be introduced from the unbonded surface side of the first chip into the interconnect cavity.
[0009] Optionally, the patterned channel structure includes a groove formed on the bonding surface of the first chip, the groove not penetrating the first chip, the groove communicating with the interconnect cavity, for shortening the transport path of the reactive material to the pad surface.
[0010] Optionally, the layout of the graphical channel structure is designed in coordination with the arrangement of the ultra-large scale pad interconnect array, using a grid-like, radial, or ring-like structure, so that the spacing between each pad and the nearest graphical channel structure is equal or similar.
[0011] Optionally, the ultra-large scale pad interconnect array includes at least 1000 pads, the size of the pads is 1μm~8μm, and the minimum spacing between the pads is 3μm~10μm; the preset threshold is less than 50μm, and for low-density ultra-large scale pad interconnect arrays, the preset threshold can be relaxed to 50μm~100μm.
[0012] Optionally, the patterned channel structure is formed using one or more combined processes of dry etching, laser drilling, and wet etching; the width of the patterned channel structure is 2μm to 20μm, the depth of the through channel is 10μm to 100μm, and the depth of the groove is 0.5μm to 2μm and matches the height of the interconnect cavity.
[0013] Optionally, the reactive material is introduced into the interconnect cavity through a patterned channel structure by one or more of chemical vapor deposition, atomic layer deposition, electrochemical deposition, and electroless plating; the conductive interconnect is grown by one or more of electroplating, electroless deposition, and atomic layer deposition, and the growth temperature is room temperature to 200°C. The conductive interconnect grows from the pads and the pad surfaces towards each other and docks to form a complete electrical interconnect structure.
[0014] Optionally, the first chip and the second chip or wafer are aligned and bonded by a patterned bonding structure layer. The patterned bonding structure layer is set to avoid the ultra-large scale pad interconnect array and patterned channel structure region of the first chip. The material is selected from one or more of oxides, nitrides, polymers, and photoresists, and the thickness is 0.1μm to 10μm.
[0015] Optionally, it also includes a conductive interconnect defect repair step: if an open circuit or poor contact defect is detected in the conductive interconnect, reactive material is introduced into the interconnect cavity again through the patterned channel structure, and conductive material is selectively grown at the defect location to complete the repair of the interconnect structure.
[0016] A heterogeneous stacked integrated structure, comprising: The first chip has a bonding surface provided with an array of ultra-large scale pad interconnects, the ultra-large scale pad interconnects including multiple pads. A graphical channel structure is disposed on the first chip and distributed around the periphery and / or row and column gaps of the ultra-large scale pad interconnect array. The distance between each pad in the ultra-large scale pad interconnect array and the nearest graphical channel structure is less than a preset threshold. A second chip or wafer heterogeneous to the first chip, the first chip and the second chip or wafer are aligned and bonded, forming an interconnect cavity between them, the interconnect cavity is connected to the patterned channel structure, and the pads of the first chip and the pads of the second chip or wafer are arranged opposite to each other in the interconnect cavity; Conductive interconnects are formed within the interconnect cavity and selectively grown between oppositely arranged pads to achieve electrical interconnection between the first chip and the second chip or wafer.
[0017] Compared with existing technologies, this invention forms a patterned channel structure distributed around the periphery and between rows and columns of a large-scale PAD interconnect array on a first chip. This makes the distance between each PAD and the nearest channel less than a preset threshold, significantly shortening the reactant transport path of the PADs in the central region. This ensures that all PADs in the large-scale array receive a uniform supply of reactants, thereby solving the technical problems of slow growth of central PADs and uneven interconnection. This greatly improves interconnection quality and production yield. Furthermore, the channel structure can provide a path for subsequent interconnection defect repair, further enhancing process reliability and product economy. Attached Figure Description
[0018] Figure 1 This is a schematic flowchart of the heterogeneous stacking integration manufacturing method for ultra-large-scale pad interconnect arrays according to Embodiment 1 of the present invention. Figure 2 This is a schematic diagram illustrating the formation of a graphical channel structure in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the bonding and growth of conductive interconnects after forming a patterned channel structure in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the through-channel layout before bonding in Embodiment 2 of the present invention.
[0019] Figure 5 This is a schematic diagram of the through-channel layout after growing conductive interconnects according to Embodiment 2 of the present invention; Figure 6 This is a schematic diagram of the patterned channel structure of Embodiment 3 of the present invention, which uses an annular groove that does not penetrate the chip.
[0020] Explanation of reference numerals in the attached figures: 100 - First chip; 110 - First pad; 200 - Patterned channel structure; 210 - Through-channel structure; 220 - Groove channel structure; 230 - Annular groove channel structure; 300 - Second chip; 310 - Second pad; 400 - Interconnect cavity; 500 - Patterned bonding structure layer; 600 - Conductive interconnect. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.
[0022] In the description of this invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0023] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0024] Example 1
[0025] Please refer to Figure 1 This is a schematic flowchart of a heterogeneous stacking integration manufacturing method for ultra-large-scale pad interconnect arrays according to an embodiment of the present invention.
[0026] A heterogeneous stacked integration manufacturing method for ultra-large scale pad interconnect arrays includes the following steps: A first chip 100 is provided, wherein the bonding surface of the first chip 100 is provided with an array of ultra-large scale pad interconnects, the ultra-large scale pad interconnects including multiple pads; A patterned channel structure 200 is formed on the first chip 100. The patterned channel structure 200 is distributed around the periphery and / or row and column gaps of the ultra-large scale pad interconnect array, such that the distance between each pad in the ultra-large scale pad interconnect array and the nearest patterned channel structure 200 is less than a preset threshold. The patterned channel structure 200 provides a transport path for the reactive material. The first chip 100 is aligned and bonded with a heterogeneous second chip 300 or wafer to form an interconnect cavity 400. The interconnect cavity 400 is connected to the patterned channel structure 200, and the pads of the first chip 100 and the pads of the second chip 300 or wafer are arranged opposite to each other in the interconnect cavity 400. By introducing reactive material into the interconnect cavity 400 through the patterned channel structure 200, conductive interconnects 600 are selectively grown on the oppositely arranged pads, thereby achieving electrical interconnection between the first chip 100 and the second chip 300 or wafer.
[0027] refer to Figure 2 and Figure 3 As shown, a first chip 100 is provided, which in this embodiment is a silicon-based logic chip. On the bonding surface of the first chip 100, a very large-scale PAD interconnect array is formed using standard back-end interconnect processes in the art. The interconnect process includes: depositing a dielectric layer, photolithography to define the PAD pattern, PVD deposition of a metal seed layer, chemical plating of a filler metal, and CMP planarization, so that the PAD surface meets the flatness requirements of subsequent bonding processes.
[0028] In this embodiment, to meet the "ultra-large scale" requirement, the PAD interconnect array contains 10,000 PADs arranged in a 100×100 grid pattern. The size of each PAD is 3μm×3μm, the minimum spacing is 5μm, and the surface roughness after CMP planarization is better than 5nm (measured using atomic force microscopy).
[0029] A patterned channel structure 200 is formed on the first chip 100 to solve the problem of uneven mass transfer in the ultra-large-scale PAD array. According to the grid-like arrangement of the ultra-large-scale PAD interconnect array, a crisscrossing groove-like channel can be formed at the gaps between rows and columns of the PAD array using a dry etching process.
[0030] Specifically, a groove with a width of 5 μm and an initial depth of 1 μm is etched to keep the straight-line distance between each PAD and the nearest channel structure within 15 μm. This mesh-like channel structure covers the entire array, eliminating the difference in mass transfer paths between the center and edge PADs and providing a structural basis for the subsequent uniform growth of interconnects. After etching, the photoresist is removed and the residue is cleaned.
[0031] The first chip 100 is aligned and bonded to a heterogeneous second chip 300 (a memory chip in this embodiment) to form an interconnect cavity 400. Specifically, on the bonding surface of the first chip 100, SiO2 is deposited by PECVD and etched by photolithography to form a patterned bonding structure layer 500. It should be noted that the bonding structure layer strictly avoids the PAD array region and the patterned channel structure 200 region, retaining only the support region, with a thickness of 1μm. A low-temperature surface activation bonding process is used to align and bond the first chip 100 and the second chip 300 (alignment accuracy better than 0.5μm). After bonding, an interconnect cavity 400 (1μm high) is formed between the two chips, determined by the thickness of the bonding structure layer. The interconnect cavity 400 is seamlessly connected to the patterned channel structure 200, forming an integrated mass transfer space, and the PADs of the first chip 100 and the pads of the second chip 300 are arranged opposite each other within the cavity.
[0032] Subsequently, the back of the first chip 100 is mechanically ground and thinned until the bottom of the groove is exposed, forming a through channel from the back of the chip to the interconnect cavity.
[0033] Chemical plating solution or reactive material is introduced into the interconnect cavity 400 through the patterned channel structure 200 to selectively grow conductive interconnects 600. This embodiment uses chemical copper plating. The stacked structure is immersed in a conventional chemical copper plating solution. The plating solution uses a copper sulfate system with the following composition: CuSO4·5H2O 70g / L, H2SO4 180g / L, Cl... - 50 ppm of electrolyte and appropriate amounts of organic additives (such as polyethylene glycol and sodium mercaptopropane sulfonate) are supplied to the interconnect cavity 400 through a patterned channel structure 200. Since the distance between all PADs and channels is ≤15 μm, the electrolyte exchange rate is consistent. After approximately 30 minutes of deposition, copper atoms grow from the opposing PAD and pad surfaces, precisely mating in the center of the cavity after approximately 20 minutes to form a complete conductive interconnect. The cross-sectional morphology of the interconnect can be observed using a scanning electron microscope, or the interconnect resistance can be tested using a four-point probe method to verify the mating integrity. Finally, the interconnect is completed by rinsing with deionized water and annealing at 200°C for 30 minutes under a nitrogen atmosphere with a nitrogen flow rate of 5–10 L / min. The conductive interconnect 600 is made of one or more of copper, nickel, gold, silver, ruthenium, cobalt, palladium, platinum, tin, indium, bismuth, and antimony, or their alloys. In addition to copper, the conductive interconnect can also be made of nickel, gold, silver, ruthenium, cobalt or their alloys, which can be achieved by adjusting the composition of the chemical plating solution or the CVD / ALD precursor.
[0034] This embodiment forms a grid-like patterned channel structure 200 on the first chip 100, ensuring that the distance between each PAD and the nearest channel is ≤15μm. This effectively eliminates the problem of uneven growth caused by differences in reactant transport paths between center and edge PADs. Testing showed that the growth rate difference among 10,000 interconnect points was less than ±5%, the average contact resistance was 0.15Ω, and the yield was over 99.5%, significantly better than the control example without a channel structure (yield less than 60%). This method achieves highly uniform and reliable interconnection for ultra-large-scale PAD arrays.
[0035] Those skilled in the art will understand that the patterned channel structure 200 can also be implemented by through-channel (as in Example 2) or non-through groove through back thinning (as in Example 3); for low-density arrays, the preset threshold can be appropriately relaxed to 50~100μm; the channel formation method includes but is not limited to dry etching, laser drilling, etc.; in addition, the channel structure can also be used for subsequent interconnection defect repair (as in Example 5).
[0036] Example 2
[0037] The difference between this embodiment and Embodiment 1 is that the patterned channel structure 200 uses a through-channel that penetrates the first chip 100, rather than a bonding surface groove. This through-channel is fully connected before bonding, eliminating the need for a back-side thinning step.
[0038] like Figure 4 and Figure 5 As shown, specifically, after the fabrication of the ultra-large-scale PAD interconnect array on the first chip 100 is completed (same as in Example 1, 10,000 PADs, 100×100 grid arrangement, PAD size 3μm×3μm, spacing 5μm), laser drilling is used to drill holes from the non-bonded surface (back side) of the first chip 100 towards the bonded surface, forming through-channels that penetrate the chip. This embodiment adopts a radial layout, with a channel diameter of 8μm and a depth penetrating the chip (approximately 100μm). The design ensures that the distance between each PAD and the nearest channel is ≤30μm.
[0039] After bonding the first chip 100 and the second chip 300 (bonding process as in Example 1), the through-channel is naturally connected to the interconnect cavity 400. Subsequently, reactive material is introduced through the through-channel on the back of the chip. This embodiment uses chemical copper plating: the stacked structure is immersed in a chemical copper plating solution (composition: CuSO4·5H2O 15g / L, EDTA·2Na 40g / L, formaldehyde 10mL / L, pH 12.5), and deposited at 45°C for about 30 minutes. Copper grows and connects from the opposing PAD and pad surfaces, forming a complete conductive interconnect 600. Finally, it is rinsed three times with deionized water, dried with nitrogen, and annealed at 200°C for 30 minutes (nitrogen flow rate 5~10L / min).
[0040] This embodiment employs a through-channel structure 210 to introduce reactive materials from the back of the chip, making it suitable for scenarios where liquid cannot be directly supplied from the front of the first chip 100 (e.g., other devices or heat dissipation structures are integrated above the first chip 100). The radial layout of the through-channels ensures that the distance between each PAD in the array and the channel is ≤30μm, eliminating the difference in mass transfer paths between the center and edge PADs. Testing showed that the growth rate difference of interconnects formed by electroless copper plating was less than ±8%, the average contact resistance was 0.18Ω, and the yield was over 98%. Compared to a control example without a channel structure, this embodiment improves the interconnect yield in back-side liquid supply scenarios from less than 50% to over 98%, significantly expanding the process compatibility of the method of this invention.
[0041] Example 3
[0042] Compared to Embodiment 1, the main change in this embodiment is that the patterned channel structure 200 adopts an annular groove that does not penetrate the chip. The annular groove that does not penetrate the chip initially is made to be connected by thinning the back side after bonding, instead of a mesh-like groove.
[0043] like Figure 6As shown, specifically, after the fabrication of the ultra-large-scale PAD interconnect array on the first chip 100 is completed (same as in Example 1, but this example uses 5000 PADs arranged in a 50×100 rectangular array, with PAD dimensions of 5μm×5μm and a spacing of 8μm), an annular groove channel structure 230 is formed on the bonding surface of the first chip 100 using a dry etching process. The groove width is 6μm and the depth is 1.5μm, initially not penetrating the chip. The design ensures that each PAD is ≤45μm from the nearest groove.
[0044] After bonding the first chip 100 and the second chip 300 (using the same bonding process as in Example 1), the groove and the interconnect cavity 400 are naturally connected. Subsequently, mechanical grinding is performed on the back side of the first chip 100 to thin it until the bottom of the groove is exposed, forming a through channel from the back side of the chip to the interconnect cavity.
[0045] Then, ruthenium (Ru) was used as the interconnect material in atomic layer deposition (ALD). The reaction precursor (bis(ethylcyclopentadienyl)ruthenium and oxygen) entered the cavity through the groove channel and was selectively deposited at 200°C to finally form a ruthenium-based conductive interconnect. The growth thickness was measured by ellipsometry, and samples were taken at 9 uniformly distributed sites.
[0046] This embodiment employs a method of first forming non-through grooves, then bonding, followed by back-grinding to achieve through-hole processing. This eliminates the need for through-hole processing on the chip, preserving the mechanical strength of the first chip 100 and the back-side circuit layout, significantly reducing process complexity. The annular groove layout ensures that the distance between each PAD and the nearest channel in the array is ≤45μm, guaranteeing the uniformity of reactant supply. The ruthenium interconnects grown using the ALD process exhibit excellent step coverage and conductivity. Testing shows that the growth thickness consistency of 5000 interconnect points is better than ±3%, the average contact resistance is 0.12Ω, and the yield exceeds 99%. This embodiment is particularly suitable for applications with thinner chips (<50μm) or where sensitive devices are present on the back side.
[0047] Example 4
[0048] Unlike the grid layout of Embodiment 1, this embodiment demonstrates a variety of collaborative layout methods between the graphical channel structure 200 and the PAD array, enabling those skilled in the art to implement it flexibly according to the actual array configuration.
[0049] Method 1 (grid layout, suitable for regular arrays): As shown in Example 1, the channels are distributed in a grid pattern along the gaps between the rows and columns of PADs, so that each PAD is located at the center of the grid cell and is equidistant from the surrounding channels (10-15μm).
[0050] Method 2 (radial + ring layout, suitable for high-density arrays at the center): Radial channels are set with the array center as the origin (e.g., Figure 3As shown), and supplemented by concentric ring channels (such as... Figure 4 As shown in the figure, this ensures that the mass transfer distance between the center and the outer PADs is consistent. In this method, the PAD array is distributed in a circular high-density pattern (approximately 20,000 PADs, with the density in the central region being twice that of the edges). Radial channels extend outward from the center, and annular channels are set every 100 μm in the radial direction, so that the distance between each PAD and the nearest channel is ≤25 μm.
[0051] Method 3 (Variable Spacing Layout, Applicable to High-Density Arrays): Channels are densely distributed in areas with high PAD density and sparsely distributed in low-density areas, ensuring that the distance between all PADs and the nearest channel remains within a preset threshold (40μm in this embodiment). Specifically, for high-density areas with a PAD spacing of 3μm, the channel spacing is set to 50μm; for low-density areas with a PAD spacing of 8μm, the spacing between adjacent channels is set to 120μm.
[0052] This embodiment demonstrates various collaborative layout strategies for the patterned channel structure 200 and PAD arrays, enabling the method of this invention to adapt to ultra-large-scale PAD arrays of different shapes. A grid-like layout is suitable for regular rectangular arrays, simplifying fabrication; a radial + ring-shaped layout is suitable for high-density arrays in the center, eliminating the mass transfer "island" effect in the central region; a variable-pitch layout is suitable for arrays with uneven density distribution, reducing the number of channels (approximately 30% less than a uniform layout) while ensuring mass transfer uniformity, thus reducing the occupied effective chip area. All of the above layout methods can control the distance between each PAD and the nearest channel within a preset threshold. Actual measurements (three wafers were tested for each layout, each containing at least 10,000 interconnect points) showed that the difference in interconnect growth rate under the three layout methods was less than ±10%, and the yield reached over 97%.
[0053] Example 5
[0054] Based on Example 1, this example further adds a defect repair step, demonstrating the secondary utilization value of the graphical channel structure 200 after the initial interconnection is completed.
[0055] according to Figure 1 After completing the stack interconnection in steps S1-S4, add the following steps: Step S5: Defect Detection By using conventional semiconductor electrical testing (four-probe resistance testing method), interconnect points with open circuits or poor contact were identified. In this embodiment, 12 defect points were detected out of 10,000 interconnect points (8 open circuits and 4 high resistance).
[0056] Step S6: Defect Repair
[0057] The patterned channel structure 200 retained after the initial interconnection is used to reintroduce reactive materials. The specific process involves placing the stacked structure back into the electroless plating solution described in Example 1, lowering the deposition temperature to 35°C, and shortening the deposition time to 5 minutes. The repair principle is that the defect location has large voids and high local resistance; under constant-voltage electroless plating mode, the potential drop in this area is greater, attracting more Cu²⁺. + Deposition allows for selective repair. After repair, electrical testing shows all defects are eliminated. This channel structure can support 1-3 repair operations; exceeding 3 may result in channel blockage due to deposits. The repaired sample underwent 500 thermal cycles (-40°C to 125°C), with an interconnect resistance change of <5%.
[0058] This embodiment fully demonstrates the repairability advantage of the patterned channel structure 200. In traditional 3D interconnect processes, once an interconnect defect occurs after bonding, it is usually irreparable, requiring the entire stack structure to be discarded, resulting in significant losses. This invention, by retaining the patterned channel structure 200, provides a secondary transport path for the reactive material, enabling selective local repair of defect locations without disassembling the stack. Testing showed that this embodiment achieved a 100% repair success rate, increasing the overall yield from 98.5% after the initial interconnect to over 99.9%, significantly reducing the risk of overall scrap due to single-point interconnect defects. This has significant economic value for the large-scale production of high-value chips (such as AI processors and HBM stacks).
[0059] Example 6
[0060] This embodiment provides a heterogeneous stacked integrated structure prepared by the above method, comprising: A first chip 100 has a bonding surface provided with an array of ultra-large scale pad interconnects, the ultra-large scale pad interconnects including multiple pads. A graphical channel structure 200 is disposed on the first chip 100 and distributed around the periphery and / or row and column gaps of the ultra-large scale pad interconnect array. The distance between each pad in the ultra-large scale pad interconnect array and the nearest graphical channel structure 200 is less than a preset threshold. A second chip 300 or wafer, which is heterogeneous to the first chip 100, is aligned and bonded to the first chip 100 and the second chip 300 or wafer, forming an interconnect cavity 400 between them. The interconnect cavity 400 is connected to the patterned channel structure 200, and the pads of the first chip 100 and the pads of the second chip 300 or wafer are arranged opposite to each other in the interconnect cavity 400. Conductive interconnects are formed within the interconnect cavity 400 and selectively grown between opposing pads using one or more methods, such as electroless plating, chemical vapor deposition, or atomic layer deposition, to achieve electrical interconnection between the first chip 100 and the second chip 300 or a wafer. Specifically, a heterogeneous stacked integrated structure formed using the method of Embodiment 1 is adopted. This structure includes a first chip 100 with a large-scale PAD interconnect array (10,000 PADs, 3μm × 3μm, 5μm spacing) on the bonding surface. A patterned channel structure 200 is disposed on the first chip 100, which is a grid-like groove with a width of 5μm. After back-side thinning, the total depth is equivalent to the chip thickness, and the spacing between each PAD and the nearest channel is 15μm (less than 50μm). The second chip 300 is heterogeneous with the first chip 100 (a memory chip) and is aligned and bonded through a patterned bonding structure layer 500. Interconnect cavity 400: Formed between the two chips, supported by a bonding structure layer, 1 μm in height, and connected to the patterned channel structure 200. Conductive interconnect: Formed within the interconnect cavity 400, selectively grown between opposing PADs and pads, in a face-to-face growth and docking configuration, achieving electrical interconnection between the first chip 100 and the second chip 300. According to the methods of embodiments 2-5 above, the patterned channel structure 200 can also be a through-channel, a ring-shaped groove after back-thinning, or other cooperative layout forms, and the conductive interconnect can also be chemically plated copper or ALD ruthenium material. Interconnect yield was tested using a four-probe method on 10,000 interconnect points, with a resistance <0.3Ω as the criterion for acceptance, and a yield of over 99.5% was obtained.
[0061] The method provided by this invention solves the problem of low interconnect yield caused by uneven mass transfer in heterogeneous stacking of ultra-large-scale PAD interconnect arrays. Its process is highly compatible with existing CMOS production lines and can be widely applied in high-performance computing, artificial intelligence chips, high-bandwidth memory (HBM), and other fields, demonstrating significant industrial application value.
[0062] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.
Claims
1. A heterogeneous stacked integrated manufacturing method for very large scale pad interconnect arrays, comprising: Includes the following steps: A first chip is provided, wherein the bonding surface of the first chip is provided with an array of very large-scale pad interconnects arranged in an array, the array of very large-scale pad interconnects comprising multiple pads; A patterned channel structure is formed on the first chip. The patterned channel structure is distributed around the periphery and / or row and column gaps of the ultra-large scale pad interconnect array, such that the distance between each pad in the ultra-large scale pad interconnect array and the nearest patterned channel structure is less than a preset threshold. The patterned channel structure provides a transport path for the reactive material. The first chip is aligned and bonded to a heterogeneous second chip or wafer to form an interconnect cavity. The interconnect cavity is connected to the patterned channel structure, and the pads of the first chip and the pads of the second chip or wafer are arranged opposite to each other in the interconnect cavity. By introducing reactive material into the interconnect cavity through the patterned channel structure, conductive interconnects are selectively grown on the oppositely arranged pads, thereby achieving electrical interconnection between the first chip and the second chip or wafer.
2. The heterogeneous stack integration manufacturing method for very large scale pad interconnect array of claim 1, wherein, The patterned channel structure includes a through-channel that runs through the first chip, extending from the unbonded surface of the first chip to the bonded surface, allowing reactive material to be introduced from the unbonded surface side of the first chip into the interconnect cavity.
3. The heterogeneous stack integration manufacturing method for very large scale pad interconnect array of claim 1, wherein, The patterned channel structure includes a groove formed on the bonding surface of the first chip. The groove does not penetrate the first chip and is connected to the interconnect cavity to shorten the transport path of the reactive material to the pad surface.
4. The heterogeneous stack integration manufacturing method for very large scale pad interconnect array of claim 1, wherein, The layout of the patterned channel structure is designed in coordination with the arrangement of the ultra-large-scale pad interconnect array, using a grid-like, radial, or ring-like structure to ensure that the spacing between each pad and the nearest patterned channel structure is equal or similar.
5. The heterogeneous stack integration manufacturing method for very large scale pad interconnect array of claim 1, wherein, The ultra-large scale pad interconnect array contains at least 1000 pads, the size of which is 1μm to 8μm and the minimum spacing between the pads is 3μm to 10μm. The preset threshold is less than 50μm. For low-density ultra-large scale pad interconnect arrays, the preset threshold can be relaxed to 50μm to 100μm.
6. The heterogeneous stack integration fabrication method for very large scale pad interconnect array of claim 1, wherein, The patterned channel structure is formed using one or more combined processes of dry etching, laser drilling, and wet etching; the width of the patterned channel structure is 2μm to 20μm, the depth of the through channel is 10μm to 100μm, and the depth of the groove is 0.5μm to 2μm, which matches the height of the interconnect cavity.
7. The heterogeneous stacked integration manufacturing method for ultra-large-scale pad interconnect arrays according to claim 1, characterized in that, The reactive material is introduced into the interconnect cavity through a patterned channel structure by one or more of the following methods: chemical vapor deposition, atomic layer deposition, electrochemical deposition, and electroless plating; the conductive interconnect is grown by one or more of the following methods: electroplating, electroless deposition, and atomic layer deposition, and the growth temperature is room temperature to 200°C. The conductive interconnect grows from the pads and the pad surfaces towards each other and docks to form a complete electrical interconnect structure.
8. The heterogeneous stacked integration manufacturing method for ultra-large-scale pad interconnect arrays according to claim 1, characterized in that, The first chip and the second chip or wafer are aligned and bonded by a patterned bonding structure layer. The patterned bonding structure layer is set to avoid the ultra-large scale pad interconnect array and patterned channel structure region of the first chip. The material is selected from one or more of oxides, nitrides, polymers and photoresists, and the thickness is 0.1μm~10μm.
9. The heterogeneous stacked integration manufacturing method for ultra-large-scale pad interconnect arrays according to claim 1, characterized in that, It also includes a conductive interconnect defect repair step: if an open circuit or poor contact defect is detected in the conductive interconnect, reactive material is introduced into the interconnect cavity again through the patterned channel structure, and conductive material is selectively grown at the defect location to complete the repair of the interconnect structure.
10. A heterogeneous stacked integrated structure, characterized in that, include: The first chip has a bonding surface provided with an array of ultra-large scale pad interconnects, the ultra-large scale pad interconnects including multiple pads. A graphical channel structure is disposed on the first chip and distributed around the periphery and / or row and column gaps of the ultra-large scale pad interconnect array. The distance between each pad in the ultra-large scale pad interconnect array and the nearest graphical channel structure is less than a preset threshold. A second chip or wafer heterogeneous to the first chip, the first chip and the second chip or wafer are aligned and bonded, forming an interconnect cavity between them, the interconnect cavity is connected to the patterned channel structure, and the pads of the first chip and the pads of the second chip or wafer are arranged opposite to each other in the interconnect cavity; Conductive interconnects are formed within the interconnect cavity and selectively grown between oppositely arranged pads to achieve electrical interconnection between the first chip and the second chip or wafer.