A heterogeneous stacked integrated manufacturing method

Abstract

This invention relates to the field of semiconductor manufacturing technology, specifically disclosing a heterogeneous stacked integration manufacturing method in the field of semiconductor manufacturing technology, comprising: providing a mother wafer, forming a first interconnect pad array on the bonding surface of the mother wafer; providing at least one sub-die, forming a second interconnect pad array on the bonding surface of the sub-die; forming at least one through-hole within at least one of the mother wafer or the sub-die, the through-hole being located close to the first interconnect pad array or the second interconnect pad array, allowing the interconnect pads to communicate with the outside through the through-hole. This invention employs a bonding-before-interconnection process, avoiding pad oxidation contamination, supporting low-temperature processes from room temperature to 200°C, adapting to heat-sensitive devices, and providing a flexible channel for material introduction and defect repair through the through-hole, making it compatible with CMOS processes and enabling flexible three-dimensional stacked integration of multilayer heterogeneous dies.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a heterogeneous stacked integration manufacturing method, and more particularly to a three-dimensional integration method for achieving chip wafer electrical interconnection by introducing reactive materials through through-holes. Background Technology

[0002] As Moore's Law approaches its physical limits, traditional two-dimensional planar integration processes have encountered bottlenecks in improving chip integration density and signal transmission speed. Three-dimensional integration technology, by stacking chips / chips in the vertical direction, can integrate more functional devices in a unit area, effectively shortening interconnect length, improving signal transmission efficiency, and reducing power consumption, becoming the core direction of integrated circuit technology development in the post-Moore era.

[0003] Existing 3D integration technologies mainly include through-silicon via (TSV) technology, microbump bonding technology, and hybrid bonding technology. Among them, wafer-level bonding process is the mainstream 3D stacking manufacturing method. Its typical process is as follows: first, the target device wafer is thinned, and then the device wafer is bonded to the carrier through temporary bonding. After completing subsequent processes such as back-side thinning, back-side wiring, and pad fabrication, the device wafer is separated from the carrier through debonding process. Finally, the thinned multiple device wafers are permanently bonded multiple times to achieve 3D stacking.

[0004] However, the aforementioned existing technical solutions have many technical defects in practical industrial applications, which seriously affect interconnect reliability and production yield, specifically: First, solder pads are prone to oxidation and contamination. After the solder pads are fabricated, there is a certain time interval between the preparation of the clean microbump surface and wafer bonding. During this process, the solder pads are directly exposed to the external environment, making them highly susceptible to surface oxidation or contaminant adhesion. This leads to a decline in subsequent bonding quality and significantly reduces the reliability of electrical interconnects.

[0005] Second, the process temperature is limited, resulting in poor adaptability. Existing wafer-level bonding processes typically require high-temperature treatment. For heat-sensitive devices such as compound semiconductor devices, MEMS devices, and organic substrates, high temperatures can easily cause performance degradation or even structural damage, limiting the range of materials and devices that can be selected for heterogeneous integration.

[0006] Third, defects in the interconnect structure are difficult to repair. In traditional methods, the interconnect structure is formed in one step during the bonding process. If defects such as open circuits or poor contact are found after formation, they cannot be effectively repaired and the structure must be scrapped, resulting in a serious loss of yield.

[0007] Fourth, the introduction of conductive materials lacks flexibility. In existing processes, conductive materials are either pre-placed on the pads before bonding or filled in all at once after bonding. It is impossible to flexibly control the timing, amount, and deposition method of material introduction according to actual interconnection requirements, and it is also difficult to achieve precise control over the size and morphology of the interconnect structure.

[0008] Therefore, how to avoid oxidation contamination of pads before bonding, reduce process temperature to suit heat-sensitive devices, provide repairable paths for interconnect defects, achieve flexible introduction of conductive materials, and simplify the three-dimensional stacking process have become urgent technical problems to be solved in this field. Summary of the Invention

[0009] This invention constructs an innovative "bonding first, interconnect later" process path by setting through-holes on the mother wafer and / or sub-core near the interconnect pad array, using patterned bonding structure layers to achieve mechanical fixation and form interconnect cavities, and then introducing reactive materials into the cavities through the through-holes to selectively grow conductive interconnects between the relative pads to achieve electrical interconnection. This solves the problems of easy oxidation and contamination of pads, limited process temperature, difficulty in repairing interconnect defects, and lack of flexibility in material introduction methods in the prior art, and realizes low-temperature, high-reliability, and high-flexibility heterogeneous stacking integration.

[0010] A heterogeneous stacked integration manufacturing method includes the following steps: A master wafer is provided, and a first interconnect pad array is formed on the bonding surface of the master wafer; At least one sub-core is provided, and a second interconnect pad array is formed on the bonding surface of the sub-core; At least one through-hole is formed inside at least one of the mother wafer or the sub-core, the through-hole being located close to the first interconnect pad array or the second interconnect pad array, so that the interconnect pads communicate with the outside through the through-hole; A patterned bonding structure layer is formed on the bonding surface of the mother wafer and / or the sub-core. The bonding surface of the sub-core is aligned and in contact with the bonding surface of the mother wafer, so that the first interconnect pad array and the second interconnect pad array are arranged opposite each other at corresponding positions. At the same time, the two are mechanically fixed by the patterned bonding structure layer, forming an interconnect cavity between the opposite interconnect pads. Reactive material is introduced into the interconnect cavity through the through-hole, and conductive interconnects are selectively grown between the opposing first and second interconnect pads. The conductive interconnects connect the opposing first and second interconnect pads, thereby achieving electrical interconnection between the first interconnect pad array and the second interconnect pad array.

[0011] Preferably, one of the mother wafer and the sub-core is an interconnect adapter board, which is used to provide a redistribution path for signal transmission.

[0012] Preferably, the through-hole is formed in the edge region of the sub-core, allowing the second interconnect pad at the edge of the sub-core to communicate with the outside through a suspended narrow slit.

[0013] Preferably, the method for forming the through opening includes one or more combinations of dry etching, laser drilling, or wet etching.

[0014] Preferably, forming the through-hole specifically includes: etching to a predetermined depth by dry etching, and then thinning the back side of the chip to expose the through-hole; or first thinning the back side of the chip, and then forming the through-hole by dry etching.

[0015] Preferably, the patterned bonding structure layer is selected from permanent bonding materials or temporary bonding materials that can be ashing and removed; The permanent bonding material is selected from one or more of oxides, nitrides, and polymers, and has a thickness of 0.1-50 micrometers; The ashing-removable temporary bonding material is selected from one or more of hexamethyldisilazane, trimethylsilyldiethylamine, self-assembled monolayers formed by silane coupling agents, liquid-phase spin-coating temporary bonding adhesives, or hydrogenated amorphous carbon, with a thickness of 0.01-50 micrometers. The patterned bonding structure layer is patterned by one or more of the following methods: photolithography, laser etching, molding, mask deposition, or selective region self-assembly.

[0016] Preferably, the method for introducing reactive material into the interconnecting cavity through the through-hole includes one or more of chemical vapor deposition, atomic layer deposition, electrochemical deposition, or electroless plating.

[0017] Preferably, the selective growth method of the conductive interconnect is one or more of electroplating, electroless deposition, or chemical plating, and the selective growth is the opposite growth and docking of the interconnect pad surfaces, with a growth temperature of room temperature to 200°C.

[0018] Preferably, the method further includes a step of thinning and / or planarizing the back side of the mother wafer and / or the sub-core after forming the conductive interconnect.

[0019] Preferably, the method further includes, after forming the conductive interconnect, forming a redistribution layer and / or external connection terminals on the back side of the mother wafer and / or the sub-core, the redistribution layer being electrically connected to the conductive interconnect.

[0020] Beneficial effects: 1. This invention adopts an innovative process path of "bonding first, then interconnection". The pads are protected by a patterned bonding structure layer during the bonding process, which fundamentally avoids the oxidation and contamination problems during the pad preparation and bonding process, and improves the reliability of interconnection.

[0021] 2. This invention can complete the interconnect fabrication at low temperatures ranging from room temperature to 200°C, avoiding damage to heat-sensitive devices caused by high temperatures, broadening the range of materials and devices that can be adapted to heterogeneous integration, and is compatible with a variety of heat-sensitive devices such as compound semiconductors, MEMS, and organic substrates.

[0022] 3. By setting through-holes near the interconnect pads, the present invention provides a flexible material introduction channel and defect repair path for the interconnect structure, which can precisely control the size and morphology of the interconnect and adapt to the needs of high-density micro-pitch interconnects.

[0023] 4. This invention supports various methods of introducing reactive materials, such as electrochemical deposition, electroless plating, atomic layer deposition, and chemical vapor deposition. Materials (Cu, Ru, W, Au, etc.) and processes can be flexibly selected according to specific application requirements, and it has wide process adaptability.

[0024] 5. This invention is highly compatible with existing CMOS process lines, eliminating the need for redundant temporary bonding and debonding steps. The process is simple and highly controllable, effectively improving production yield and efficiency. It also enables flexible three-dimensional stacking integration of multilayer heterogeneous chips, providing an efficient and reliable technical solution for three-dimensional heterogeneous stacking integration in the post-Moore era. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the mother wafer after the first interconnect pad array is formed in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure after forming a conductive interconnect through the through-hole in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the structure in Embodiment 2 of the present invention in which the through-hole is formed in the core particle; Figure 4 This is a schematic diagram of the structure after the conductive interconnect is formed by the through-opening in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the back-side thinning and planarization process of the mother wafer in Embodiment 3 of the present invention, which forms a redistribution layer and external connection terminals; Figure 6 This is a schematic diagram of the stacked integrated structure of multilayer heterogeneous core particles in Embodiment 4 of the present invention.

[0026] Icon labels: 100, Mother wafer; 110, First interconnect pad array; 200, First sub-core; 210, Second interconnect pad array; 300, Through-hole opening; 400, Bonding structure layer; 500, Interconnect cavity; 600, Conductive interconnect; 700, Redistribution layer; 800, Solder ball array; 900, Suspended slot; 911, Second sub-core; 10, Third sub-core. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0028] In the description of this invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0029] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] This invention is applicable to the field of three-dimensional heterogeneous integration, and is particularly suitable for wafer-level stacking integration of different functional and process chips such as logic chips, memory chips, MEMS chips, and optoelectronic chips. The technical solution of this invention is described in detail below through several embodiments. Embodiment 1 is a basic embodiment, fully demonstrating the core process flow of this invention; Embodiments 2 to 4 are preferred embodiments, which optimize and expand upon Embodiment 1 in terms of the location of the through-hole, the method of introducing the reactive material, and the multilayer stacking structure, to demonstrate the wide applicability and technical superiority of this invention.

[0031] Example 1

[0032] A heterogeneous stacked integration manufacturing method includes the following steps: A mother wafer 100 is provided, and a first interconnect pad array 110 is formed on the bonding surface of the mother wafer 100; At least one sub-core is provided, and a second interconnect pad array 210 is formed on the bonding surface of the sub-core; At least one through-hole 300 is formed inside at least one of the mother wafer 100 or the sub-core, the through-hole 300 being disposed near the first interconnect pad array 110 or the second interconnect pad array 210, so that the interconnect pads communicate with the outside through the through-hole 300. A patterned bonding structure layer 400 is formed on the bonding surface of the mother wafer 100 and / or the sub-core; The bonding surface of the sub-core is aligned and contacted with the bonding surface of the mother wafer 100, so that the first interconnect pad array 110 and the second interconnect pad array 210 are arranged opposite each other at corresponding positions. At the same time, the patterned bonding structure layer 400 mechanically fixes the two together, forming an interconnect cavity 500 between the opposite interconnect pads. Reactive material is introduced into the interconnect cavity 500 through the through opening 300, and conductive interconnects 600 are selectively grown between the opposing first and second interconnect pads. The conductive interconnects 600 connect the opposing first and second interconnect pads, thereby realizing the electrical interconnection between the first interconnect pad array 110 and the second interconnect pad array 210.

[0033] This embodiment fully demonstrates the core process flow: preparation of the mother wafer 100 / sub-core pad array, formation of through-hole 300, preparation of patterned bonding structure layer 400, alignment and bonding to form interconnect cavity 500, introduction of through-hole 300 and selective growth of conductive interconnect 600.

[0034] like Figure 1 As shown, firstly, a mother wafer 100 is provided. The mother wafer 100 is a 12-inch (300mm) single-crystal silicon wafer with a thickness of 775μm, a standard wafer size in the semiconductor field, suitable for large-scale production. On the bonding surface of the mother wafer 100, a first interconnect pad array 110 is formed through electroplating. Planarization is then performed using chemical mechanical polishing (CMP) to achieve a surface flatness better than 5nm, ensuring the alignment accuracy of subsequent bonding. Unlike existing technologies where pads are directly exposed after fabrication, the pads in this invention are protected through subsequent processes to prevent oxidation.

[0035] Next, multiple sub-chips are provided. These sub-chips can be bare dies with different functions, such as logic chips, memory chips, MEMS (Micro-Electro-Mechanical Systems) chips, or optoelectronic chips, to meet the core requirements of heterogeneous integration. Unlike the single-wafer stacking method in existing technologies, this invention supports flexible integration of chips with different functions and processes. In this embodiment, the sub-chip is a high-performance computing chip manufactured using a 7nm process, with a size of 10mm × 12mm.

[0036] A second interconnect pad array 210 is formed on the bonding surface of the sub-core. Its material, size, and spacing are matched with the first interconnect pad array 110 of the mother wafer 100 to ensure the effectiveness of electrical interconnection after subsequent alignment and bonding. The pad surface is also subjected to CMP planarization treatment, and the surface flatness is better than 5nm.

[0037] like Figure 1 As shown, a through-hole 300 is then formed inside the mother wafer 100. The through-hole 300 is located close to the first interconnect pad array 110, so that the interconnect pads can communicate with the outside through the through-hole 300, providing a channel for the subsequent introduction of reactive materials and the repair of interconnect structures, thus solving the pain points of limited material introduction paths and the inability to repair interconnect defects in the prior art.

[0038] In this embodiment, the through-hole 300 is formed using a dry etching process. The specific process is as follows: First, photoresist is coated on the back side of the mother wafer 100. The opening position is defined using photolithography, aligning with the peripheral area of ​​the first interconnect pad array 110, approximately 2-5 μm from the pad edge. This distance is preferred, ensuring the shortest possible path for the reactive material while avoiding damage to the pads during etching. Then, a dry etching process is used, employing a sulfur hexafluoride / oxygen (SF6 / O2) mixed gas as the etchant to form a blind via with a depth of 50 μm and a diameter of 5 μm. The etching parameters are: SF6 flow rate 200 sccm, O2 flow rate 20 sccm, RF power 1500 W, and cavity pressure 50 mTorr. These are standard process parameters for dry etching in the semiconductor field, enabling precise etching. After etching, the photoresist is removed using an ashing process, and wet cleaning (using diluted HF solution) is performed to remove etching residues, ensuring the opening channel remains unobstructed.

[0039] It should be noted that in this embodiment, the through-hole 300 is formed using a "first etching, then thinning" method. The dry etching step described above forms a blind via with a depth of 50 μm, which does not completely penetrate the mother wafer 100. Subsequently, the back side of the mother wafer 100 is mechanically ground and thinned, reducing the wafer thickness from 775 μm to approximately 720 μm, exposing the bottom of the blind via and thus forming a through-hole 300, allowing the first interconnect pad array 110 to communicate with the outside world through this opening.

[0040] As an alternative, the through-hole opening 300 can also be formed by "thinning first, then etching": first, the back side of the mother wafer 100 is thinned to a predetermined thickness (e.g., 50 μm), and then a fully penetrating through-hole opening 300 is formed by dry etching. Those skilled in the art can choose the appropriate method according to the actual process conditions and equipment capabilities.

[0041] In addition, the through-hole 300 can also be formed inside the sub-core, or through-hole 300 can be formed in both the mother wafer 100 and the sub-core, depending on the design requirements; the number of through-hole 300 can be one or more, distributed in an array. In this embodiment, the through-hole 300 is formed by arranging the pads in an array, with 1 through-hole 300 corresponding to every 10 pads.

[0042] Next, a patterned bonding structure layer 400 is formed on the bonding surface of the mother wafer 100. The patterned bonding structure layer 400 serves to mechanically fix the mother wafer 100 and the sub-core, and is removed in the pad area to ensure that the pads are exposed and form the subsequent interconnect cavity 500. Unlike the full-surface bonding layer method in the prior art, the patterned design of this invention realizes the integrated molding of mechanical fixation and interconnect cavity 500.

[0043] In this embodiment, the patterned bonding structure layer 400 is made of SiO2 with a thickness of 0.5 μm, and the specific process is as follows: Deposition: SiO2 thin film was deposited on the 100 bonding surface of the mother wafer by plasma-enhanced chemical vapor deposition (PECVD). The deposition temperature was 300℃, the radio frequency power was 500W, and the SiH4 / N2O (silane / nitrous oxide) flow rates were 200sccm and 1000sccm, respectively, which are the conventional parameters for PECVD deposition of SiO2. Photolithography: A patterned mask is formed on a SiO2 thin film using photolithography. Positive photoresist is used, with a thickness of 1.2 μm, an exposure dose of 120 mJ / cm², and a development time of 60 seconds. This defines the exposed area of ​​the bonding pads and the bonding support area. Etching: Reactive ion etching (RIE) was used to etch SiO2 with a CF4 / CHF3 (carbon tetrafluoride / trifluoromethane) mixed gas at a etching rate of 50 nm / min. The etching endpoint was monitored by optical emission spectroscopy (OES). After etching, the patterned bonding structure layer 400 was completely removed in the pad area, exposing the first interconnect pad array 110. SiO2 was retained in the area between the pads to form a support structure. The pattern accuracy of the patterned bonding structure layer 400 was better than 0.1 μm. Cleaning: Residual photoresist is removed by oxygen plasma ashing, and then the surface is cleaned with diluted HF (hydrofluoric acid) solution (HF:H2O=1:100, time 30 seconds) to remove etching residues and ensure the bonding surface is clean.

[0044] The processed mother wafer 100 is then aligned and bonded with the prepared sub-core particles using advanced wafer bonding equipment with an alignment accuracy better than 0.5μm, ensuring the precise alignment of the first interconnect pad array 110 and the second interconnect pad array 210.

[0045] The bonding process employs low-temperature surface activation bonding, as follows: First, the bonding surface of the sub-core is placed opposite the bonding surface of the mother wafer 100. The first interconnect pad array 110 and the second interconnect pad array 210 are aligned one-to-one using an infrared optical alignment system. Then, Ar plasma is used to activate the two bonding surfaces for 60 seconds to improve the bonding force. Finally, pressure (0.5 MPa) and a low temperature of 180°C are applied to form a covalent bond between the patterned bonding structure layer 400 and the surface of the sub-core for 60 minutes.

[0046] After bonding is completed, the first interconnect pad array 110 and the second interconnect pad array 210 are precisely positioned opposite each other in the vertical direction, forming an interconnect cavity 500 with a height of 0.5 μm (determined by the thickness of the patterned bonding structure layer 400). At the same time, the patterned bonding structure layer 400 firmly and mechanically fixes the mother wafer 100 and the sub-core together, and the interconnect cavity 500 communicates with the outside through the through opening 300, providing a channel for the introduction of subsequent reaction materials.

[0047] like Figure 2 As shown, reactive material is introduced into the interconnect cavity 500 through the through opening 300, and conductive interconnect 600 is selectively grown between the opposing first interconnect pad array 110 and second interconnect pad array 210. This step realizes the innovative process path of "bonding first and then interconnecting", which fundamentally avoids pad oxidation, and the selective growth is a low-temperature process, which is suitable for the integration of heat-sensitive devices.

[0048] In this embodiment, the reactive material is introduced using electrochemical deposition (ECD). The conductive interconnect 600 is made of copper, and the selective growth method is electroplating. The specific process is as follows: Preparation before electroplating: Place the bonded stacked structure in the electroplating fixture with the back side of the mother wafer 100 (the side containing the through-hole 300) facing upwards. Immerse the entire structure in an electroplating solution containing copper ions. The electroplating solution composition is: CuSO4·5H2O (copper sulfate pentahydrate) 200g / L, H2SO4 (sulfuric acid) 50g / L, Cl... - (Chloride ions) 50ppm, and appropriate amounts of organic additives (accelerators, inhibitors, leveling agents), constitute the standard plating solution formula for electroplating copper, ensuring that the deposited copper layer is uniform and dense. Electroplating deposition: A cathode voltage is applied at the through-hole 300 on the back side of the mother wafer 100, with the current density controlled at 2A / dm², the electroplating solution temperature at 25℃ (room temperature), and the stirring speed at 200rpm to ensure uniform circulation of the plating solution. Copper ions enter the interconnect cavity 500 through the through-hole 300, and reduction deposition occurs simultaneously on the surfaces of the first interconnect pad array 110 and the second interconnect pad array 210. Since the two pads are vertically opposite each other with a very small spacing (0.5μm), metallic copper grows from the surfaces of the two pads and docks with each other. After about 15 minutes, they are precisely docked in the middle of the interconnect cavity 500 to form a complete conductive interconnect 600. The diameter of the conductive interconnect 600 matches the size of the pads, approximately 5μm. Post-treatment: After electroplating, rinse repeatedly with deionized water and dry with nitrogen to remove residual plating solution; then anneal at 200℃ for 30 minutes to improve the grain structure of copper interconnects, reduce contact resistance, and enhance interface characteristics.

[0049] In addition, it can also be chemical plating or other self-growing methods.

[0050] This embodiment fully demonstrates the core process flow of "bonding first, then interconnection." By forming through-holes 300 near the pads inside the mother wafer 100, and using a patterned bonding structure layer 400, mechanical fixation and interconnect cavities 500 are integrated. Reactive materials are then introduced through the through-holes 300, selectively growing conductive interconnects 600 between the pads. This fundamentally avoids oxidation and contamination problems during the pad fabrication and bonding process. The conductive interconnects 600 prepared in this embodiment have a resistance as low as 0.3Ω / solder joint, far superior to existing technologies, and the process temperature is controlled below 180℃, laying the foundation for the subsequent integration of heat-sensitive devices.

[0051] It should be noted that the thickness of the patterned bonding structure layer 400 can be flexibly selected within the range of 0.1-50μm (permanent bonding material) or 0.01-50μm (temporary bonding material) according to the actual interconnect cavity height requirements. This embodiment only uses 0.5μm as an example for illustration and is not a limitation on the protection range.

[0052] Example 2

[0053] The main difference between this embodiment and embodiment 1 is that the through opening 300 is formed in the edge region of the sub-core, so that the second interconnect pad at the edge of the sub-core is connected to the outside through the suspended narrow slit 900. The remaining steps are basically the same.

[0054] like Figure 3 and Figure 4As shown, specifically, the through-hole 300 is located inside the sub-core near the edge region, forming a 3-5 μm wide suspended slit 900 between the pads and the chip edge. The second interconnect pad array 210 communicates with the outside through this suspended slit 900. The through-hole 300 is formed using a laser drilling process with laser parameters of wavelength 355 nm, pulse energy 10 μJ, repetition frequency 50 kHz, drilling diameter 3 μm, and depth 80 μm, completely penetrating the sub-core. The reactive material is introduced using chemical plating rather than electrochemical deposition, with the plating solution composition being CuSO4 5 g / L, EDTA 30 g / L, and HCHO. At a concentration of 10 mL / L, pH 12.5, and a temperature of 60°C, the electroless plating time is 30 minutes. No external power supply is required. Copper ions enter the interconnect cavity 500 from the side through the suspended narrow slit 900. In addition, the sub-core in this embodiment is a memory chip (DDR5, size 8 mm × 10 mm), while the sub-core in Example 1 is a high-performance computing chip (7 nm process, size 10 mm × 12 mm).

[0055] Compared to Example 1, this embodiment places the through-hole 300 at the edge of the sub-core, and introduces the reactive material from the side through the suspended narrow slit 900. This eliminates the need for material introduction from the back side of the mother wafer 100, avoiding the back side thinning process and simplifying the process flow. This structure is particularly suitable for interconnecting intermediate layers in multilayer stacked structures, providing more flexible material introduction path selection for three-dimensional system-in-package.

[0056] Example 3

[0057] This embodiment, based on Embodiment 1, further demonstrates a complete system-in-package (SIP) process. Specifically, after forming the conductive interconnect 600, the mother wafer 100 undergoes backside thinning and planarization, and a redistribution layer 700 and external connection terminals are fabricated, ultimately completing the SIP structure as shown in the attached figure. Figure 5 As shown.

[0058] The specific steps are as follows: First, the core facet of the bonded stack structure is placed face down and bonded to the glass substrate using temporary bonding adhesive. A combination of coarse and fine grinding is used to thin the back side of the mother wafer 100 from 775 μm to 50 μm. After grinding, stress-relieving etching is performed using inductively coupled plasma reactive ion etching (ICP-RIE) to a depth of 2 μm to remove the grinding damage layer. Subsequently, chemical mechanical polishing (CMP) is performed to reduce the surface roughness (Ra) of the back side of the mother wafer 100 to less than 1 nm, with the total thickness deviation controlled within 2 μm. Finally, a laser debonding process is used to separate the glass substrate from the stacked structure.

[0059] Next, a redistribution layer 700 and external interconnect terminals are formed. A 0.5 μm thick SiO2 dielectric layer is deposited on the back side of the thinned mother wafer 100. Through photolithography and RIE etching processes, vias are created at positions corresponding to the through-hole 300 and the conductive interconnect 600 to expose the ends of the conductive interconnect 600. Subsequently, a Ti / Cu seed layer is deposited using physical vapor deposition (PVD), and a copper redistribution layer 700 with a thickness of 3 μm and a linewidth / spacing of 2 μm / 2 μm is deposited using electroplating. Afterward, a 0.3 μm thick SiN layer is deposited. x A passivation layer is applied, and vias are made at the pad locations of the redistribution layer 700 to expose the copper pads. A UBM layer (Ti / Ni / Ag) is electroplated at the vias, and finally, a ball-mounting process is used to form a ball array 800 as an external connection terminal for electrical connection with an external circuit board.

[0060] Through the above steps, a heterogeneous stacked integrated structure with a back-side redistribution layer 700 and external connection terminals is formed. This structure can be directly soldered to a printed circuit board (PCB) to achieve electrical connection between the chip and an external system.

[0061] Based on Example 1, this embodiment expands the core interconnect structure into a complete device that can be directly used in system-in-package by adding steps such as back-side thinning, planarization, redistribution layers, and solder ball arrays. This significantly reduces the stack thickness, provides a flexible external interconnect layout, enhances the industrial applicability of the process, and lays a flat and reliable foundation for multilayer heterogeneous integration.

[0062] Example 4

[0063] The difference between this embodiment and Embodiments 1 and 2 is that it realizes the stacked integration of three heterogeneous cores, and the mother wafer 100 acts as an interconnection board to provide a redistribution path for signal transmission between the sub-cores.

[0064] As attached Figure 6As shown, specifically, the first layer integrates the first sub-core 200 (logic computing chip) on the mother wafer 100 according to the steps of Example 1. The through-hole 300 is formed on the mother wafer 100, and the conductive interconnect 600 is made of copper. The second layer prepares a second patterned bonding structure layer 400 (material is polyimide, thickness is 2μm) on the back side of the first layer stacked structure. The second sub-core 911 (laser chip, InP-based compound semiconductor) is bonded by low-temperature surface activation bonding (pressure 0.4MPa, temperature 15℃). The first layer integrates a ruthenium (Ru) conductive interconnect 600 at 80°C. A through-hole 300 is formed at the edge of the second sub-core 911 (refer to Example 2, laser drilling diameter 3μm, suspended slit width 4μm). The second layer repeats the steps of the second layer, integrating a third sub-core 10 (photodetector chip, GaAs-based) on the back of the second sub-core 911. A gold (Au) conductive interconnect 600 is grown using atomic layer deposition (ALD) at 180°C. Different conductive interconnect materials can be selected for each layer according to transmission requirements (bottom layer copper, middle layer ruthenium, top layer gold). The entire process uses low-temperature technology, preventing performance degradation of heat-sensitive devices. The interconnect resistance of each layer is below 0.4Ω / solder joint, and the optoelectronic integration achieves an optical coupling efficiency of over 85%. The remaining steps are the same as in Examples 1 and 2.

[0065] This embodiment, based on Embodiments 1 and 2, successfully achieves the stacked integration of three heterogeneous chips. Each layer can select different conductive interconnect materials (copper for the bottom layer, ruthenium for the middle layer, and gold for the top layer) according to transmission requirements. The entire process utilizes low-temperature technology, preventing performance degradation of heat-sensitive devices. The interconnect resistance of each layer is below 0.4Ω / solder joint, and the optoelectronic integration achieves an optical coupling efficiency of over 85%. This embodiment demonstrates that the method of the present invention can achieve flexible stacked integration of multi-layer heterogeneous chips, resulting in high system-on-chip (SoC) architecture flexibility, meeting the development needs of three-dimensional system-in-package in the post-Moore's Law era.

[0066] Example 5

[0067] The difference between this embodiment and Embodiment 1 is that the patterned bonding structure layer 400 uses a temporary bonding material that can be removed by ashing, rather than a permanent bonding material.

[0068] Specifically, after forming the first interconnect pad array 110 on the mother wafer 100, HMDS vapor phase treatment is performed: dehydration baking at 120°C for 30 minutes, followed by HMDS vapor introduction into a 0.5 Torr vacuum chamber and reaction at 120°C for 10 minutes to form a hydrophobic monolayer, increasing the water contact angle from <10° to >65°. After forming the second interconnect pad array 210 on the bonding surface of the sub-core 200, a dielectric layer (silicon dioxide or silicon nitride, 5 μm thick) is deposited, and a raised bonding sheet 230 is formed by photolithography and dry etching, followed by CMP planarization. The surface of the sub-core 200 is not coated with HMDS. Subsequently, the sub-core 200 is flip-chip bonded onto the mother wafer 100, making the bonding sheet 230 contact the HMDS layer with an alignment accuracy of ≤±1μm. A pressure of 0.2N is applied, and temporary fixation is achieved using hydrophobic van der Waals forces. The height of the bonding sheet 230 is precisely controlled to control the gap (5μm) of the interconnect cavities 500. Next, an excimer laser (248nm) is used with an oblique incidence (30°-45°) to penetrate the gap from the edge of the sub-core, with an energy density of approximately 150mJ / cm², selectively removing HMDS from the surface of the first interconnect pad array 110: the pads (metal) absorb the laser and heat up to above 300°C, causing the HMDS to oxidize and decompose into gaseous products, restoring the pads' hydrophilicity (water contact angle <10°), while the dielectric region has low absorptivity, and the HMDS is retained. Then, a through-hole 300 is formed according to the method of Example 1, through which reactive material is introduced, and conductive interconnects 600 are selectively grown between the relative pads. After interconnection is completed, residual HMDS can be removed by oxygen plasma ashing (80°C, 10 minutes) to achieve separation or rework.

[0069] The bonding process employs a low-temperature thermo-press bonding technique, with the temperature controlled at 120°C and the pressure at 0.3 MPa to avoid affecting heat-sensitive devices. After the growth of the conductive interconnect 600 is completed, a removal step is added depending on the material type: for example, an oxygen plasma ashing process (approximately 180°C, 10 minutes) is used to completely ashing and remove the temporary bonding material (such as HMDS or hydrogenated amorphous carbon) serving as the bonding structure layer 400. This removal process leaves no residue and does not contaminate or damage the mother wafer 100 or the sub-core, thus achieving clean separation of the two and providing a feasible path for process rework or device reconstruction.

[0070] The remaining steps are the same as in Example 1.

[0071] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A heterogeneous stacked integrated manufacturing method, characterized in that, Includes the following steps: A master wafer is provided, and a first interconnect pad array is formed on the bonding surface of the master wafer; At least one sub-core is provided, and a second interconnect pad array is formed on the bonding surface of the sub-core; At least one through-hole is formed inside at least one of the mother wafer or the sub-core, the through-hole being located close to the first interconnect pad array or the second interconnect pad array, so that the interconnect pads communicate with the outside through the through-hole; A patterned bonding structure layer is formed on the bonding surface of the mother wafer and / or the sub-core. The bonding surface of the sub-core is aligned and in contact with the bonding surface of the mother wafer, so that the first interconnect pad array and the second interconnect pad array are arranged opposite each other at corresponding positions. At the same time, the two are mechanically fixed by the patterned bonding structure layer, forming an interconnect cavity between the opposite interconnect pads. Reactive material is introduced into the interconnect cavity through the through-hole, and conductive interconnects are selectively grown between the opposing first and second interconnect pads. The conductive interconnects connect the opposing first and second interconnect pads, thereby achieving electrical interconnection between the first interconnect pad array and the second interconnect pad array.

2. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that, One of the mother wafer and the sub-core is an interconnect adapter board, which is used to provide a redistribution path for signal transmission.

3. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that, The through-hole is formed in the edge region of the sub-core, allowing the second interconnect pad at the edge of the sub-core to communicate with the outside through a suspended narrow slit.

4. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that, The method for forming the through-hole includes one or more combinations of dry etching, laser drilling, or wet etching.

5. The heterogeneous stacked integrated manufacturing method according to claim 4, characterized in that, Forming the through-hole specifically includes: etching to a predetermined depth using dry etching, and then thinning the back side of the chip to expose the through-hole; or first thinning the back side of the chip, and then forming the through-hole by dry etching.

6. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that... The patterned bonding structure layer is selected from permanent bonding materials or temporary bonding materials that can be ashing and removed. The permanent bonding material is selected from one or more of oxides, nitrides, and polymers, and has a thickness of 0.1-50 micrometers; The ashing-removable temporary bonding material is selected from one or more of hexamethyldisilazane, trimethylsilyldiethylamine, self-assembled monolayers formed by silane coupling agents, liquid-phase spin-coating temporary bonding adhesives, or hydrogenated amorphous carbon, with a thickness of 0.01-50 micrometers. The patterned bonding structure layer is patterned by one or more of the following methods: photolithography, laser etching, molding, mask deposition, or selective region self-assembly.

7. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that, Methods for introducing reactive material into interconnected cavities through the perforated openings include one or more of chemical vapor deposition, atomic layer deposition, electrochemical deposition, or electroless plating.

8. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that, The selective growth method of the conductive interconnect is one or more of electroplating, electroless deposition or chemical plating. The selective growth is the growth and docking of opposite interconnect pad surfaces, and the growth temperature is room temperature to 200°C.

9. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that, It also includes the step of thinning and / or planarizing the back side of the mother wafer and / or the sub-core after forming the conductive interconnect.

10. The heterogeneous stacked integrated manufacturing method according to claim 1, characterized in that, It also includes the step of forming a redistribution layer and / or external connection terminals on the back side of the mother wafer and / or the sub-core after forming the conductive interconnect, the redistribution layer being electrically connected to the conductive interconnect.

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