Wafer-to-wafer hybrid bonding method, structure, and co-packaged optical device

Abstract

This invention provides a wafer-to-wafer hybrid bonding method, structure, and co-packaged optical device. The hybrid bonding method includes: providing a first wafer and a second wafer, both of which have a dielectric layer and metal interconnect pads embedded in the dielectric layer on their bonding surfaces; selectively forming an indium-modified layer on the surface of the metal interconnect pads using a peeling process, wherein the indium-modified layer covers 80% of the surface area of ​​the metal interconnect pads and has a thickness of 5 nanometers; aligning the bonding surfaces of the first wafer and the second wafer so that the indium-modified layers on the first wafer and the second wafer are in contact with each other; applying pressure at a bonding temperature of 200°C to perform thermo-press bonding, causing the contacting indium-modified layers to form a transient liquid phase, promoting atomic interdiffusion between the metal interconnect pads, and realizing metal-to-metal bonding and dielectric-to-dielectric layer bonding.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a wafer-to-wafer hybrid bonding method, structure, and co-packaged optical device. Background Technology

[0002] In hybrid bonding processes, lowering the annealing temperature (from the traditional 300~400℃ to 200℃ or even lower) is not only beneficial, but also a necessity in the current fields of 3D integration and CPO (co-packaged optics).

[0003] The following analysis examines the advantages and potential challenges of low-temperature annealing from three perspectives: 1. Reduce thermal stress and wafer warpage The chip is composed of silicon (Si), metal (Cu), and dielectric (SiO2), whose coefficients of thermal expansion differ significantly. Lower annealing temperatures result in less internal stress during cooling. This significantly reduces wafer warpage after bonding, thereby improving yields for subsequent thinning and dicing, and preventing interface delamination due to thermal mismatch.

[0004] 2. Protect heat-sensitive components (especially optoelectronic and storage components). Lasers and modulators are extremely sensitive to heat; high temperatures can cause wavelength drift or decreased photoelectric efficiency in quantum well structures. High temperatures accelerate the diffusion of dopant ions, leading to shifts in the threshold voltage (Vth) of DRAM transistors and even disrupting leakage control in ultra-low-power devices. Processes below 200°C ensure that these expensive active components maintain their "factory settings" in terms of physical and electrical properties.

[0005] 3. Kinetic obstacles caused by low-temperature annealing Copper atoms lack sufficient kinetic energy at low temperatures, making it difficult to cross the interface and form a metallurgical bond. A low-melting-point metal modification layer is used as a "low-temperature catalyst" or "intermediate solder" to compensate for the lack of thermal kinetic energy. Summary of the Invention

[0006] Therefore, the purpose of this invention is to address the shortcomings of existing low-temperature hybrid bonding processes, such as complexity, difficulty in mass production, easy damage to devices, or insufficient bonding strength, by providing a method for achieving high-strength and high-reliability hybrid bonding at 200°C or even lower temperatures, as well as the corresponding hybrid bonding structure and applications.

[0007] This invention provides a wafer-to-wafer hybrid bonding method, comprising the following steps: providing a first wafer and a second wafer, wherein the bonding surfaces of the first wafer and the second wafer both include a dielectric layer and metal interconnect pads embedded in the dielectric layer; selectively forming an indium-modified layer on the surface of the metal interconnect pads of the first wafer and the second wafer using a peeling process, wherein the indium-modified layer covers 80% of the surface area of ​​the metal interconnect pads and the thickness of the indium-modified layer is 5 nanometers; aligning the bonding surfaces of the first wafer and the second wafer such that the indium-modified layer on the first wafer and the indium-modified layer on the second wafer are in contact with each other; applying pressure at a bonding temperature of 200°C for thermo-press bonding, causing the contacting indium-modified layers to form a transient liquid phase, promoting atomic interdiffusion between the metal interconnect pads, and realizing metal-to-metal bonding and dielectric-to-dielectric layer bonding.

[0008] Furthermore, preferably, in the wafer-to-wafer hybrid bonding method of the present invention, the thickness of the indium modified layer is 2 to 10 nanometers, and the indium modified layer covers 70% to 90% of the surface of the metal interconnect pad.

[0009] Furthermore, preferably, in the wafer-to-wafer hybrid bonding method of the present invention, the stripping process includes: forming a photoresist pattern on the bonding surface of the wafer, the photoresist pattern exposing 80% of the area of ​​the metal interconnect pad; depositing an indium film; and removing the photoresist pattern to peel off the indium film on the photoresist pattern, thereby leaving the indium modified layer on the exposed area of ​​the metal interconnect pad.

[0010] Furthermore, preferably, in the wafer-to-wafer hybrid bonding method of the present invention, before forming the indium modified layer, the method further includes a step of chemically and mechanically polishing the wafer to form a recess on the surface of the metal interconnect pad; the indium modified layer is formed in the recess.

[0011] Furthermore, preferably, in the wafer-to-wafer hybrid bonding method of the present invention, before bonding, a step of activating the bonding surface using plasma is included.

[0012] Furthermore, preferably, in the wafer-to-wafer hybrid bonding method of the present invention, the bonding temperature is 150-250°C, the pressure is 1-5 MPa, and the bonding time is 0.5-2 hours.

[0013] Furthermore, preferably, in the wafer-to-wafer hybrid bonding method of the present invention, the material of the metal interconnect pad is copper, and the material of the dielectric layer is silicon dioxide or silicon carbonitride.

[0014] Furthermore, the present invention provides a wafer-to-wafer hybrid bonding structure, formed using any of the above-mentioned hybrid bonding methods.

[0015] Furthermore, preferably, in the wafer-to-wafer hybrid bonding structure of the present invention, a Cu-In solid solution bonding interface is formed between the metal interconnect pads of the first wafer and the second wafer, and the bonding interface is free from spillage from the indium modified layer that contaminates the dielectric layer.

[0016] Furthermore, the present invention provides a co-packaged optical device comprising any of the above-described wafer-to-wafer hybrid bonding structures.

[0017] The beneficial effects of this invention include at least the following: Significantly reduces annealing temperature and protects heat-sensitive devices: Utilizing the low melting point of indium (156.6℃), a transient liquid phase can be generated at 200℃ or even lower, promoting interdiffusion of metal atoms. This avoids the damage to heat-sensitive components such as lasers, modulators, and DRAMs caused by traditional 400℃ high-temperature annealing, ensuring the stability of the electrical and optical performance of the devices.

[0018] Reduced thermal stress and wafer warpage: As the bonding temperature drops from 300~400℃ to below 200℃, the internal stress caused by the mismatch of thermal expansion coefficients between silicon, metal and dielectric materials during the cooling process is greatly reduced, which significantly suppresses wafer warpage and interface delamination, and improves the yield of subsequent thinning and dicing, especially suitable for multi-layer stacking (multiple annealing) process scenarios.

[0019] Pure interface, free from ion contamination: An indium-modified layer is selectively formed only in 80% of the metal interconnect pads using a lift-off process, and the indium layer is hidden within the depressions formed by CMP. During bonding, the flow of transient liquid phase is confined within the metal pits and does not overflow to the dielectric layer surface, completely eliminating ion contamination of hydrophilic interfaces such as silica and ensuring the reliability of dielectric bonding.

[0020] Improved thermal conductivity of bonding interface: The indium-modified layer forms a Cu-In solid solution with copper. Compared with the traditional Cu-Cu interface, the alloyed interface has better thermal conductivity and can meet the heat dissipation requirements of high-frequency signals and power devices.

[0021] It has strong process compatibility and is suitable for mass production: the stripping process and the double-sided synchronous modification scheme are both based on existing semiconductor equipment (photolithography, electron beam evaporation, sputtering, etc.), without the need to introduce special conditions such as high-defect copper, formic acid vapor or extremely high pressure. The process flow is simple, the cost is controllable, the yield is high, and it is easy to achieve large-scale production.

[0022] Eliminating the fulcrum effect and optimizing stress buffering: By controlling the growth of a 5nm thick indium layer in 80% of the metal pad area and utilizing the excess expansion displacement (approximately 12nm) of the copper pillar during bonding, atomic-level interdiffusion is forcibly driven. At the same time, the reserved 20% blank area serves as a radial stress buffer zone, avoiding the fulcrum effect caused by the introduction of an additional passivation layer, thus ensuring the coplanarity and contact uniformity of the bonding surface. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating a hybrid bonding principle according to a preferred embodiment of the present invention, wherein (a) is the medium and metal to be bonded, and (b) is the medium and metal after bonding.

[0024] Figure 2 The specific process flow of the hybrid bonding method according to a preferred embodiment of the present invention is shown. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0026] Hybrid bonding is a key permanent bonding method in 3D silicon integration technology. It combines dielectric materials (such as silicon dioxide, silicon carbonitride, or polyimide) with embedded metals (such as copper, aluminum, or gold) to achieve mechanical support, electrical isolation, and vertical interconnection. Unlike traditional wire bonding and flip-chip packaging (minimum interconnect pitch of 20-50 μm), hybrid bonding technology directly connects via metal-to-metal and dielectric-to-dielectric bonding without the need for leads or microbumps, thus enabling ultra-high density electrical interconnection (interconnect pitch less than 5 μm).

[0027] Traditional copper-copper hybrid bonding typically employs thermocompression bonding. For example, at a pressure of 25 kN, a temperature of at least 400°C is required to achieve a good copper bonding interface; even bonding and annealing at 300°C for one hour necessitates prolonged high-temperature processing. However, high-temperature annealing introduces a series of serious problems: First, chips are composed of silicon, metal (copper), and dielectric (silicon dioxide), with vastly different coefficients of thermal expansion. The cooling process after high-temperature annealing generates significant internal stress, leading to wafer warping, interface delamination, and even chip failure. Second, for heat-sensitive components in co-packaged optics (CPO) and 3D integration (such as lasers, modulators, and DRAM memory cells), high temperatures can cause quantum well structure wavelength drift, decreased photoelectric efficiency, dopant ion diffusion, and threshold voltage shift, damaging the device's electrical performance. Therefore, reducing the annealing temperature of hybrid bonding to 200°C or even lower has become an urgent need in the current 3D integration and CPO fields.

[0028] To lower the bonding temperature, researchers have proposed various solutions. For example, increasing the copper diffusion rate by preparing high-density defect copper or nanocrystalline copper is an option, but these methods are complex, costly, and unsuitable for large-scale production. While pillar-concave bonding can achieve low-temperature bonding without chemical mechanical polishing (CMP), it requires a pillar-concave structure, increasing process complexity, relies on deformation to promote bonding, requires extremely high pressure, is difficult to control, and can easily damage devices. Formic acid vapor-assisted bonding requires extremely high gas flow rates (500-1000 L / min), easily generates static electricity and stress, and places stringent equipment requirements. Ultrasonic bonding requires extremely high wafer surface flatness and is complex to operate. Introducing passivation layers or self-assembled monolayers requires additional materials, resulting in high costs and low yields. Therefore, there is an urgent need for a low-temperature hybrid bonding scheme that can achieve reliable hybrid bonding below 200°C, is suitable for large-scale production, and does not damage heat-sensitive components.

[0029] The advantages of this solution are as follows.

[0030] 1. Compared with ordinary Cu-Cu hybrid bonding, it improves the thermal conductivity of the bonding interface; 2. Compared to ordinary Cu-Cu hybrid bonding, it lowers the annealing temperature, reduces damage to the chip, and is suitable for stacking more layers (tolerating more annealing cycles).

[0031] Hybrid bonding is a key method in 3D silicon integration technology. Hybrid bonding is a permanent bonding process that combines dielectric materials and embedded metals to form interconnects, as shown in Figure 1. The metals typically refer to copper, aluminum, or gold, while the dielectric materials are typically silicon dioxide, silicon carbonitride, or polyimide. Unlike traditional wire bonding and flip-chip packaging (minimum interconnect pitch 20-50 μm), hybrid bonding technology directly connects via metal-to-metal and dielectric-to-dielectric bonds, rather than introducing wires or microbumps. Dielectric-to-dielectric bonding provides mechanical support and electrical isolation for the entire integrated circuit, while metal-to-metal bonding enables vertical interconnects between chips. Therefore, hybrid bonding technology can achieve ultra-high density electrical interconnects (interconnect pitch less than 5 μm).

[0032] like Figure 1 As shown in the diagram, according to a preferred embodiment of the present invention, the hybrid bonding principle is illustrated. Specifically, (a) represents the medium and metal to be bonded, and (b) represents the medium and metal after bonding. The traditional copper-copper bonding method is thermo-press bonding, which involves applying external pressure at a certain temperature to promote the diffusion of copper atoms at the bonding interface, forming copper-copper metallic bonds. At a pressure of 25 kN, a temperature of at least 400°C is required to obtain a good copper bonding interface, with an interface adhesion energy of 4.93 J / m². Bonding at 300°C followed by annealing at 300°C for 1 hour in a nitrogen atmosphere can also effectively improve the bonding strength, with an interface bonding energy reaching 10 J / m². Prolonged high-temperature heating and annealing can easily generate thermal stress, leading to device deformation and breakage, and consequently, chip failure. Furthermore, high temperatures place higher demands on the equipment. To prevent excessive chip deformation or damage, low-temperature copper-copper bonding is necessary. Low-temperature bonding can significantly improve problems such as thermal migration, warpage, and misalignment caused by thermal stress, thereby greatly improving device reliability. However, low-temperature bonding reduces bonding energy, resulting in low bonding strength and low chip reliability. To achieve excellent bonding performance under low-temperature bonding conditions, researchers have proposed many optimization schemes for copper-copper bonding.

[0033] Many techniques can achieve low-temperature bonding in the laboratory, but these techniques are not suitable for large-scale production. Methods to improve copper diffusion rates by preparing high-density defect copper (HDC) or nanocrystalline copper are not practical for actual production, as they not only complicate the process and increase costs but also hinder large-scale mass production. Pillar-concave bonding can achieve low-temperature bonding rapidly without chemical mechanical polishing (CMP). However, it requires a pillar-concave structure, which increases process complexity. Furthermore, its principle involves bonding promoted by deformation, thus requiring extremely high pressures. This is difficult to control in actual production and can easily damage devices. Injecting formic acid vapor can rapidly achieve low-temperature bonding in a short time, but it faces many difficulties in actual production. On the one hand, the extremely high gas flow rates (500-1000 L / min) are difficult to achieve, and high flow rates easily generate static electricity and stress; on the other hand, introducing formic acid vapor places high demands on the equipment. Methods involving the introduction of passivation layers, self-assembled monolayers, and indirect bonding require the introduction of other materials and involve complex processes, resulting in high costs, low yields, and difficulty in achieving large-scale mass production. Ultrasonic bonding can achieve low-temperature bonding in a short time, but it requires a high degree of surface flatness on the wafer. The process and equipment requirements are also more stringent. Furthermore, the hardness and oxidation rate of copper further complicate bonding.

[0034] To ensure the consistency and thermodynamic symmetry of the interfacial metallurgy, a double-sided simultaneous modification scheme is adopted. The double-sided 2nm indium layer ensures that both metal surfaces are protected during the pre-bonding stage, avoiding the oxidation risk of the pure copper surface in a single-sided scheme. Wetting kinetics counterbalancing: The transient liquid phase generated at 156.6℃ in the in-to-In contact enables bidirectional penetration, reducing alloying time by approximately 40% compared to single-sided diffusion and significantly improving bonding strength at a low temperature of 200℃. The symmetrical thin film structure effectively balances the bimetallic effect during annealing, minimizing wafer-level residual stress and ensuring the long-term reliability of sensitive devices.

[0035] A 5 nm thick In layer was grown in the 80% region of the mixed-bonded metal using a lift-off process. This process counteracts thermal expansion through spatial redundancy. The 80% effective region defined at the center of the curved surface by the lift-off process essentially provides a radial stress buffer for the transient liquid phase at 156.6°C. The 20% blank area at the edge ensures that any trace liquid phase flow is confined within the metal pit during intense pressing at 200°C, preventing ionic contamination of the SiO2 hydrophilic interface. The 2 nm In layer is hidden within a 4 nm Dishing depth, resulting in a total retreat height of over 2 nm at room temperature, completely avoiding the fulcrum effect introduced by the passivation layer. The 12 nm excess expansion displacement of the Cu pillar forces atomic-level interdiffusion at the interface, and the resulting Cu-In solid solution phase meets the stringent requirements for high-frequency signals in terms of both conductivity and thermal fatigue resistance.

[0036] 1. The incoming wafers from the front-end wafer fab undergo a 5-minute ultrasonic cleaning process, using acetone and ethanol to remove organic contaminants from the substrate. Subsequently, the silicon substrate is dried with nitrogen and quickly transferred to the coating chamber to minimize air pollution.

[0037] 2. The CMP process for hybrid bonding is usually divided into three stages (Platen 1, 2, 3), and its core logic is to shift from "high-speed grinding" to "fine morphology modification".

[0038] 2.1 Phase One: Bulk Copper Polishing (Main Copper Removal) Remove the extra-thick copper layer after electroplating until the barrier layer (such as Ta / TaN) is exposed.

[0039] Using a high-rate polishing slurry, the process is precisely stopped on the barrier layer surface using an endpoint detection (EPD) system.

[0040] Phase 2.2: Barrier Removal Remove the remaining barrier layer to expose the underlying dielectric layer (SiO2 / SiCN).

[0041] This step involves fine-tuning. The pressure and polishing slurry selection ratio need to be adjusted to ensure that the removal rate of copper and dielectric material reaches a "controlled imbalance," thereby initiating the initial induction of copper depressions.

[0042] 2.3 Stage Three: Buff Polishing / Finshing (Fine Polishing and Shape Refinement) Achieve the final surface roughness requirements and precisely refine the depth of the copper recesses.

[0043] Polishing fluid made with colloidal silica with extremely fine particles.

[0044] Selective ratio adjustment: By using chemical additives, the wear rate of the dielectric layer is slightly higher than that of metallic copper, thus precisely "digging" out a depth difference of several nanometers. pH value is controlled to prevent oxidation or corrosion of the copper surface.

[0045] After CMP, an extremely rigorous cleaning process must be performed immediately. PVA brushing and high-pressure deionized water are used to thoroughly remove the nano-abrasives from the polishing solution. Surface activation is typically achieved using plasma (N2 or Ar) treatment, which creates a high density of hydroxyl groups (-OH) on the dielectric layer surface, preparing it for subsequent van der Waals bonding.

[0046] 3 Lift off 3.1 Lithography: Photoresist is coated onto a substrate (such as a silicon wafer), and the desired pattern window (i.e., the location where the future metal will be) is created on the photoresist through exposure and development.

[0047] 3.2 Thin Film Deposition: A target thin film (indium) is deposited over the entire surface using physical vapor deposition techniques such as electron beam evaporation or sputtering. At this point, the film simultaneously covers both the photoresist surface and the exposed window of the substrate.

[0048] 3.3 Lift-off: The sample is immersed in an organic solvent (such as acetone). The solvent penetrates and dissolves the photoresist. As the photoresist disappears, the excess metal covering the photoresist "drifts" away from the substrate, while the metal deposited directly within the substrate window remains.

[0049] 3.4 Cleaning: Prior to the bonding process, the surface is treated with argon plasma to enhance surface activity, ensure surface cleanliness, and facilitate subsequent bonding steps. Because indium possesses inherent passivation properties, wet chemical processes are unnecessary for removing surface oxides.

[0050] Finally, wafer-level bonding was completed by maintaining a high temperature of 200°C and a pressure of 2 MPa for 1 hour.

[0051] 1. To ensure the consistency of interfacial metallurgy and thermodynamic symmetry, a two-sided synchronous modification scheme is adopted.

[0052] 2. Using a lift-off process, a 5-nanometer-thick In layer is grown in 80% of the middle region of the mixed-bonded metal.

[0053] Example 1 This embodiment provides a method for wafer-level hybrid bonding at 200°C, specifically including the following steps.

[0054] Step 1: Pre-cleaning The first and second wafers (with bonding surfaces already containing copper interconnect pads and silicon dioxide dielectric layers) from the upstream wafer fab are placed in an ultrasonic cleaner and cleaned for 5 minutes each with acetone and ethanol to remove organic contaminants from the substrate. Subsequently, they are dried with high-purity nitrogen and quickly transferred to the coating chamber to minimize air pollution.

[0055] Step 2: Chemical Mechanical Polishing (CMP) to create metal depressions A three-step CMP process is performed on the wafer surface to form a pre-defined dishing on the surface of the copper interconnect pads.

[0056] Phase 1 (Bulk Copper Polishing): The ultra-thick copper layer after electroplating is removed using a high-rate polishing slurry, and the process is precisely stopped on the surface of the barrier layer (Ta / TaN) by the endpoint detection system (EPD).

[0057] Phase Two (Barrier Removal): Replace the polishing slurry to remove the remaining barrier layer, exposing the underlying silicon dioxide dielectric layer. Adjust the pressure and polishing slurry selectivity to create a controlled imbalance in the removal rates of copper and dielectric materials, initially inducing copper depressions.

[0058] Phase Three (Buff Polishing / Finishing): Using an extremely fine-particle colloidal silica polishing slurry, chemical additives are used to achieve a dielectric layer removal rate slightly higher than that of metallic copper, precisely controlling the copper recess depth to 4nm. Simultaneously, the pH value is controlled to prevent oxidation or corrosion of the copper surface.

[0059] After CMP is completed, PVA brushing and high-pressure deionized water are used to thoroughly remove the nano-abrasives from the polishing solution.

[0060] Step 3: Surface activation Argon plasma is used to treat the wafer bonding surface, forming a high density of hydroxyl groups (-OH) on the silicon dioxide dielectric layer surface, preparing it for subsequent van der Waals bonding. Since the subsequent indium layer has inherent passivation properties, no wet chemical process is required to remove the oxide after this step.

[0061] Step 4: Selectively form the indium-modified layer using a stripping process. An indium-modified layer is selectively formed on the surface of the copper interconnect pads of the first and second wafers using a stripping process, as detailed below: Photolithography: Photoresist is coated onto the wafer surface. Through exposure and development, a patterned window covering 80% of the copper interconnect pad surface is created on the photoresist. The window is located in the center of the copper pad, with the edge 20% covered by photoresist.

[0062] Thin film deposition: An electron beam evaporation device was used to deposit a 5 nm thick indium film on the entire surface. The indium film was simultaneously deposited on the photoresist surface and the copper pad surface exposed within the window (the copper pad has a 4 nm recess, and the 5 nm indium layer is completely embedded in the recess, with the surface slightly lower than the dielectric layer).

[0063] Stripping: The sample is immersed in acetone, an organic solvent. The solvent penetrates and dissolves the photoresist, and the indium film covering the photoresist is stripped off, while the indium-modified layer deposited directly in the copper pad window is retained.

[0064] Cleaning: Rinse with isopropanol and dry.

[0065] Indium-modified layers were formed on the copper interconnect pads of both the first and second wafers using the exact same method (double-sided synchronous modification).

[0066] Step 5: Alignment and Pre-bonding The bonding surfaces of the first and second wafers are aligned so that the indium-modified layers on the two wafers come into contact. Pre-bonding is performed at room temperature, utilizing the van der Waals forces between the surface hydroxyl groups to achieve initial fixation.

[0067] Step Six: Low-Temperature Hot Press Bonding The pre-bonded wafer pairs were placed in a bonding machine and hot-pressed at 200°C and 2 MPa for 1 hour. During this process, the indium layer melted at 156.6°C, forming a transient liquid phase. This liquid indium wetted the copper surface and counteracted each other. Simultaneously, the copper pillars underwent an excess expansion displacement of approximately 12 nm due to thermal expansion, driving interdiffusion between copper and indium atoms to form a Cu-In solid solution phase. Because the indium layer only covered 80% of the copper pad, the 20% blank area at the edge, and the 4 nm recess depth ensured that the flow of liquid indium was confined within the metal pit and did not overflow onto the silicon dioxide dielectric layer surface. Ultimately, simultaneous metal-to-metal bonding and dielectric-to-dielectric bonding were achieved.

[0068] result After bonding, tests showed that the interface bonding energy was higher than 8 J / m², the thermal conductivity was improved by about 15% compared to traditional Cu-Cu bonding, and the wafer warpage was less than 50 μm (the warpage of traditional 400℃ processes is usually greater than 150 μm). Scanning electron microscopy observation of the bonding interface showed no indium overflow into the dielectric layer region, and electrical tests showed stable interconnect resistance.

[0069] Example 2 This embodiment is essentially the same as Embodiment 1, except that the thickness of the indium-modified layer is 2 nanometers, covering 70% of the surface area of ​​the copper interconnect pad. The bonding temperature is 180°C, the pressure is 1.5 MPa, and the bonding time is 2 hours. The results show that good low-temperature bonding is also achieved, and thermal stress is further reduced, making it particularly suitable for sensitive devices containing ultrathin gate dielectrics.

[0070] Example 3 This embodiment is essentially the same as Embodiment 1, except that the indium-modified layer is 10 nm thick, covering 90% of the surface area of ​​the copper interconnect pad. The bonding temperature is 220 °C, the pressure is 4 MPa, and the bonding time is 0.5 hours. The results show that a thicker Cu-In intermetallic compound layer is formed at the interface, resulting in higher bonding strength, making it suitable for stacking applications that withstand greater mechanical stress.

[0071] Comparative Example A traditional Cu-Cu hybrid bonding method was used without adding any indium modification layer. Bonding and annealing were performed at 300℃ and 2MPa for 1 hour. Results showed that unbonded areas existed at the bonding interface; wafer warpage was significantly increased; and when bonding wafers containing laser chips, the laser wavelength drift exceeded 1.5nm, leading to device failure. However, using the method of Example 1 of this invention, bonding at 200℃ resulted in a laser wavelength drift of less than 0.2nm, and the device performance remained intact.

[0072] The hybrid bonding structure, formed using the above method, includes a first wafer and a second wafer. The first wafer has a first dielectric layer 1 and a first metal interconnect pad 2 embedded therein; the second wafer has a second dielectric layer 3 and a second metal interconnect pad 4 embedded therein. The first metal interconnect pad 2 and the second metal interconnect pad 4 are interconnected by a Cu-In solid solution bonding layer, which is derived from an indium-modified layer 5 that is disposed on both sides, covers 80% of the metal pad area, and has a thickness of 5 nm. The blank area (20% area) at the edge of the metal pad without the indium-modified layer serves as a stress buffer zone, and there is no indium residue contamination at the bonding interface of dielectric layers 1 and 3.

[0073] The low-temperature hybrid bonding method and structure provided by this invention are particularly suitable for fields such as three-dimensional integrated circuits, co-packaged optical devices, and high-bandwidth memory stacks. This method can achieve high-density, high-reliability interconnects while protecting heat-sensitive components, and the process flow is compatible with existing semiconductor manufacturing lines, showing promising prospects for industrial applications.

[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0075] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. The above descriptions are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A wafer-to-wafer hybrid bonding method, characterized in that, Includes the following steps: A first wafer and a second wafer are provided, wherein the bonding surfaces of the first wafer and the second wafer both include a dielectric layer and metal interconnect pads embedded in the dielectric layer; An indium-modified layer is selectively formed on the surface of the metal interconnect pads of the first wafer and the second wafer using a stripping process. The indium-modified layer covers 80% of the surface area of ​​the metal interconnect pads and has a thickness of 5 nanometers. Align the bonding surfaces of the first wafer and the second wafer so that the indium-modified layer on the first wafer and the indium-modified layer on the second wafer come into contact with each other. At a bonding temperature of 200°C, pressure is applied for thermo-press bonding, causing the indium-modified layers in contact to form a transient liquid phase, promoting atomic interdiffusion between the metal interconnect pads, and realizing metal-metal bonding and dielectric layer-dielectric layer bonding.

2. The wafer-to-wafer hybrid bonding method according to claim 1, characterized in that, The thickness of the indium-modified layer is 2 to 10 nanometers, and the indium-modified layer covers 70% to 90% of the surface of the metal interconnect pad.

3. The wafer-to-wafer hybrid bonding method according to claim 1, characterized in that, The stripping process includes: A photoresist pattern is formed on the bonding surface of the wafer, the photoresist pattern exposing the 80% area of ​​the metal interconnect pad; Depositing indium thin films; Remove the photoresist pattern to peel off the indium film on the photoresist pattern, thereby leaving the indium-modified layer on the exposed area of ​​the metal interconnect pad.

4. The wafer-to-wafer hybrid bonding method according to claim 1, characterized in that, Prior to forming the indium-modified layer, the wafer is further subjected to chemical mechanical polishing to form a recess on the surface of the metal interconnect pad; the indium-modified layer is formed within the recess.

5. The wafer-to-wafer hybrid bonding method according to claim 1, characterized in that, Prior to bonding, the bonding surface is activated using plasma.

6. The wafer-to-wafer hybrid bonding method according to claim 1, characterized in that, The bonding temperature is 150–250°C, the pressure is 1–5 MPa, and the bonding time is 0.5–2 hours.

7. The wafer-to-wafer hybrid bonding method according to claim 1, characterized in that, The metal interconnect pads are made of copper, and the dielectric layer is made of silicon dioxide or silicon carbonitride.

8. A wafer-to-wafer hybrid bonding structure, characterized in that, Formed using the hybrid bonding method according to any one of claims 1 to 7.

9. The wafer-to-wafer hybrid bonding structure according to claim 8, characterized in that, A Cu-In solid solution bonding interface is formed between the metal interconnect pads of the first wafer and the second wafer, and there is no spillage from the indium-modified layer contaminating the dielectric layer in the bonding interface.

10. A co-packaged optical device, characterized in that, Includes the wafer-to-wafer hybrid bonding structure as described in claim 8 or 9.

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