A packaged chip and a packaging method

Abstract

This disclosure provides a packaged chip and a packaging method. The packaged chip includes: a carrier substrate; a system-on-a-chip (SoC) die fixed to the carrier substrate by an underfill adhesive; and a filler die fixed to the carrier substrate by an underfill adhesive. The filler die is disposed on the outer region of the SoC die and is correspondingly disposed along one or more of the four edge lines of the SoC die. The distance between the filler die and the SoC die is such that the filler die provides support for the SoC die. This disclosure effectively reduces the stress risk of the packaged chip, improves the yield of the packaging process, improves the reliability of the chip, and increases the lifespan of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a packaged chip and a packaging method. Background Technology

[0002] Flip Chip Ball Grid Array (FCBGA) packaging technology has become the mainstream choice for large-scale integrated circuits due to its high density, high reliability, and excellent thermal management performance. With the explosive growth in computing power demands, chip performance is improved through process miniaturization and increased die size, leading to a significant increase in the number of back-end of line (BEOL) traces. However, the use of extremely brittle low-k dielectric materials between layers significantly increases the risk of cracking due to the thicker dielectric layers. Simultaneously, the difference in the coefficient of thermal expansion (CTE) between the ultra-large die and the substrate generates enormous internal stress, significantly increasing the risk of die cracking under thermal shock. Summary of the Invention

[0003] In view of this, the present disclosure provides a packaged chip and a packaging method to at least solve or alleviate the above problems.

[0004] According to a first aspect of the present disclosure, a packaged chip is provided, comprising: a carrier substrate; a system-on-a-chip (SoC) die fixed to the carrier substrate by an underfill adhesive; a filler die fixed to the carrier substrate by an underfill adhesive; the filler die is disposed in an outer region of the SoC die and is correspondingly disposed along one or more of the four edge lines of the SoC die; the distance between the filler die and the SoC die allows the filler die to provide support for the SoC die.

[0005] According to a second aspect of the present disclosure, a chip packaging method is provided, the method comprising: soldering a system-on-a-chip (SoC) die and a filler die to a carrier substrate; the filler die being disposed in an outer region of the SoC die and correspondingly disposed along one or more of the four edge lines of the SoC die; the distance between the filler die and the SoC die being such that the filler die provides support for the SoC die; fixing the SoC die and the filler die with bottom filler adhesive; and providing one of a reinforcing ring, a cover plate packaging structure, or a cap packaging structure around the SoC die and the filler die.

[0006] According to the chip packaging solution provided in this disclosure, a filler die is disposed on the outer region of the system-on-chip (SoC) die, and correspondingly disposed along one or more of the four edge lines of the SoC die. The distance between the filler die and the SoC die allows the filler die to provide support for the SoC die. This disclosure effectively reduces the stress risk of the packaged chip, improves the yield of the packaging process, enhances chip reliability, and increases chip lifespan. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0008] Figure 1a and Figure 1b This is a schematic diagram of the thermal expansion and cooling contraction of a carrier substrate according to an embodiment of the present disclosure; Figure 2a and Figure 2b This is a schematic diagram of the internal stress and cracking risk points of the silicon chip grain after thermal expansion and cooling contraction according to another embodiment of this disclosure; Figure 3 This is a schematic diagram of the thermal expansion of a silicon chip according to another embodiment of the present disclosure; Figure 4 This is a schematic diagram of a silicon chip undergoing cooling and shrinkage according to another embodiment of the present disclosure; Figure 5a and Figure 5b This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 6 This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 7 This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 8 This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 9 This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 10 This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 11 This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 12 This is a schematic diagram of a system-on-chip die in a packaged chip according to another embodiment of the present disclosure; Figure 13This is a schematic diagram of a packaged chip according to another embodiment of the present disclosure; Figure 14 This is a flowchart of a chip packaging method according to an embodiment of the present disclosure; Figure 15 This is a flowchart of a chip packaging method according to another embodiment of the present disclosure. Detailed Implementation

[0009] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0010] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0011] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0012] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0013] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0014] First, some of the nouns or terms that appear in the description of the embodiments of this disclosure are to be interpreted as follows.

[0015] Flip Chip Ball Grid Array (FCBGA): A high-density chip packaging technology. The die faces down (flip-chip) and is directly connected to the carrier substrate via metal bumps, rather than via wire bonding.

[0016] Die: A single, independent chip unit with complete circuit functionality, cut from a semiconductor wafer. It is a general term for the exposed silicon wafer state before packaging.

[0017] Back-end process (BEOL): The latter half of the semiconductor manufacturing process. At this stage, the manufacturer builds multiple layers of metal interconnects and dielectric layers on the wafers that already contain transistors and other devices, connecting hundreds of millions of individual devices into complete circuit systems.

[0018] Coefficient of Thermal Expansion (CTE): A physical quantity that measures the degree of volume or length expansion of a material when heated. In packaging, the coefficients of thermal expansion of silicon chips (low CTE) and organic substrates (high CTE) differ greatly. Temperature changes generate thermal stress, which is a major cause of chip warping or cracking.

[0019] Die crack: refers to a physical fracture or microcrack that occurs within the die itself. For example, internal stress caused by a mismatch in the coefficient of thermal expansion (CTE) can lead to chip malfunction.

[0020] Bumps: Tiny metal balls (usually solder or copper pillars) grown on the surface electrodes of a die. In flip-chip packaging, they act as "bridges," transmitting electrical signals and power, as well as providing mechanical support and heat dissipation paths.

[0021] Underfill: A liquid epoxy resin adhesive injected into the tiny gaps between the die and the encapsulation substrate. After curing, it encapsulates the bumps, disperses thermal stress caused by the mismatch in coefficients of thermal expansion, prevents bump breakage, and improves encapsulation reliability.

[0022] The following describes in detail the packaging chip solution provided in the embodiments of this disclosure with reference to the accompanying drawings.

[0023] To meet the ever-increasing demands for chip performance, transistor density has risen exponentially, directly driving the complexity of back-end processes. To connect the billions of individual electronic components manufactured in the front-end processes into complete circuits via multi-layered metal interconnects, the number of interconnect layers in the back-end processes has changed significantly, surging from less than 10 layers in the past to 14, 16, or even more layers today. This high-layer metal interconnect architecture not only solves the wiring congestion problem of high-density transistors but also becomes a key physical foundation supporting high-speed signal transmission in modern high-performance chips.

[0024] However, this radical evolution of the physical architecture brings serious reliability risks. First, to reduce signal delay, porous silicon dioxide and other low-dielectric-constant materials are widely used as dielectric layers between trace layers. Although these materials have excellent electrical properties, they are extremely brittle and have low mechanical strength. As the number of layers increases, leading to an increase in the overall thickness of the dielectric layer, the risk of internal cracking under stress increases significantly. Second, as the size of a single die continues to increase, its contact area with the substrate expands accordingly. Due to the huge difference in thermal expansion coefficients between the silicon chip and the substrate, both will generate extremely high internal stress (thermomechanical stress) during thermal cycling, which will greatly increase the probability of die cracking in the chip body.

[0025] Figure 1a This is a schematic diagram of the thermal expansion of the substrate 11. Figure 1b This is a schematic diagram of the carrier substrate 11 shrinking under cooling. Bumps 13 are grown on the surface of the grains 12 and are fixed to the carrier substrate 11 by underfill adhesive 14. (See also...) Figure 1a When the support substrate 11 expands due to heat, both sides of the support substrate 11 bend upwards; see [link / reference]. Figure 1b When the carrier substrate 11 is cooled and shrinks, both sides of the carrier substrate 11 bend downward.

[0026] Figure 2a This diagram illustrates the internal forces and cracking risk points of a silicon chip grain after thermal expansion. Figure 2b This diagram illustrates the internal stress on the silicon chip grains and the potential cracking points after cooling and shrinkage. (See also...) Figure 2a and Figure 2bWhen the substrate 11 expands due to heat and contracts due to cold, the force exerted by the deformation of the substrate 11 is transmitted to the die 12 through the bump 13. The surface of the die 12 that contacts the bump 13 has a back-end process trace 121, which has low mechanical strength, thus causing a die cracking risk point to form at the edge where the bump 13 contacts the back-end process trace 121 of the die 12.

[0027] Figure 3 Top view of a flip-chip ball grid array package; Figure 4 This is a schematic diagram of the cross-sectional structure of a flip-chip ball grid array package.

[0028] See Figure 3 and Figure 4 The evolution of semiconductor process nodes and the continuous increase in die size have led to a surge in internal stress in flip-chip ball grid array packaging technology, which in turn causes a high risk of die cracking and seriously reduces the reliability of the packaging.

[0029] This disclosure proposes a chip packaging technology solution that effectively dissipates and reduces the mechanical stress inside the chip, thereby solving the aforementioned technical defects.

[0030] Figure 5a This is a schematic cross-sectional view of the flip-chip ball grid array package according to an embodiment of this disclosure.

[0031] See Figure 5a This disclosure provides a packaged chip, comprising: The system on-chip (SoC) die 52 and the filler die 53 are attached to the SoC 51 by an underfill adhesive 54.

[0032] The filler die 53 is disposed in the outer region of the system-on-chip die 52, and is disposed along one or more of the four edge lines of the system-on-chip die 52. The distance between the filler die 53 and the system-on-chip die 52 allows the filler die 53 to provide support for the system-on-chip die 52.

[0033] Figures 5b to 8 This is a top view of a flip-chip ball grid array package according to some embodiments of this disclosure.

[0034] Figure 5b The filler die 53 is disposed in the outer region of the on-chip system die 52 and along the four edge lines of the on-chip system die 52.

[0035] Figure 6 The filler die 53 is disposed in the outer region of the system-on-chip die 52 and along one of the four edge lines of the system-on-chip die 52. It is worth noting that the filler die 53 can be disposed along any one of the four edge lines of the system-on-chip die 52.

[0036] Figure 7 The filler die 53 is disposed in the outer region of the on-chip system die 52, and is disposed along two of the four edge lines of the on-chip system die 52. It is worth noting that the filler die 53 can be disposed along any two of the four edge lines of the on-chip system die 52.

[0037] Figure 8 The filler die 53 is disposed in the outer region of the system-on-chip die 52, and is disposed along three of the four edge lines of the system-on-chip die 52. It is worth noting that the filler die 53 can be disposed along any three of the four edge lines of the system-on-chip die 52.

[0038] In this embodiment, the die is disposed in the outer region of the system-on-chip (SoC) die 52, and can be disposed along one or more of the four edge lines of the SoC die 52. Alternatively, it can be disposed in... Figures 5b to 8 Other methods of setting up besides these will not be described in this disclosure.

[0039] This embodiment of the disclosure provides mechanical support and stress buffering for the system-on-chip (SoC) die 52 by placing filler dies 53 on the outer side (along one or more edges) of the SoC die 52. This structure effectively distributes the concentrated stress generated at the edges of the SoC die 52 due to thermal expansion coefficient mismatch, suppressing package warpage and significantly reducing the risk of die cracking caused by a low-dielectric-constant layer inside the SoC die 52. Simultaneously, the flexible arrangement of the filler dies 53 (Figures 5 to 10) allows for… Figure 8 It allows for on-demand settings based on actual stress distribution, balancing improved reliability with flexible packaging design.

[0040] Furthermore, considering the strict limitations of package size in practical applications, there may not be enough wiring space or physical space to completely surround the on-chip system die 52 with filler dies 53. In this case, the embodiments of this disclosure (as shown in Figures 5 to 5) Figure 7 The present invention provides a flexible solution. Based on the specific location of the system-on-chip die 52 on the carrier substrate 51 and the stress simulation results, the present invention can select to set the filler die 53 only on one side, two sides or three sides.

[0041] Specifically, the filler die 53 is disposed in the outer region of one or more of the four edge lines corresponding to the interconnect center region of the on-chip system die 52.

[0042] The embodiments disclosed herein reduce localized stress in a specific direction, thereby providing focused protection for vulnerable locations in the interconnect center region of the system-on-chip die 52 that are prone to cracking, thus avoiding the problem of insufficient space preventing the implementation of protection.

[0043] In some specific implementations of the embodiments of this disclosure, the filling grain 53 includes a silicon substrate.

[0044] Since both the filler die 53 and the system-on-chip die 52 are made of silicon-based materials, their coefficients of thermal expansion are basically the same. During temperature cycles such as reflow soldering or operation heating, the filler die 53 and the system-on-chip die 52 will expand or contract synchronously, avoiding the introduction of additional thermomechanical stress due to differences in material properties and ensuring the uniformity of stress distribution.

[0045] In some specific implementations of the embodiments of this disclosure, the filling die 53 is a mechanical support structure without a device layer and back-end engineering.

[0046] Because the filler die 53 does not contain a fragile low-k dielectric layer or complex back-end metallization (BEOL), its overall structure is dense and its mechanical strength is much higher than that of the functional chip. This makes the filler die 53 less prone to delamination or cracking when subjected to external pressure from the carrier substrate 51 or the heat dissipation structure, providing an extremely robust physical barrier.

[0047] In some specific implementations of the embodiments of this disclosure, the distance between the filler die 53 and the on-chip system die 52 is greater than or equal to 50 μm and less than or equal to 150 μm.

[0048] If the distance between the filler die 53 and the system-on-chip die 52 is too small (<50µm), the mounting accuracy requirement will be too high. If the distance between the filler die 53 and the system-on-chip die 52 is too large (>150µm), the stress distribution and absorption effect of the filler die 53 will be weakened, and it will not be able to effectively protect the edge of the system-on-chip die 52. The distance between the filler die 53 and the system-on-chip die 52 is greater than or equal to 50µm and less than or equal to 150µm, which ensures both mounting accuracy and the formation of a strong stress coupling structure between the filler die 53 and the system-on-chip die 52.

[0049] In some specific implementations of the embodiments of this disclosure, the gap between the filler die 53 and the on-chip system die 52 is filled with bottom filler adhesive 54.

[0050] After the bottom filler 54 cures, it bonds the filler grains 53 and the on-chip system grains 52 into a mechanically integrated whole. This allows the stress that was originally concentrated at the edge of the on-chip system grains 52 to be smoothly transferred and dispersed to the filler grains 53 through the colloid. The filler fills the gaps, eliminating the physical interface that is directly exposed at the edge of the on-chip system grains 52, and inhibiting the propagation of microcracks from the edge.

[0051] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 9In this embodiment of the present disclosure, a reinforcing ring 55 is provided on the substrate 51, and the reinforcing ring 55 is disposed around the on-chip system die 52 and the filler die 53.

[0052] The reinforcing ring 55 is primarily responsible for suppressing overall substrate warping, preventing the substrate from bending like a potato chip; while the filler die 53 is responsible for addressing localized micro-stress in the chip. Together, they comprehensively reduce the risk of chip cracking and bump breakage, from overall flatness to localized edge protection.

[0053] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 10 A cover-type packaging structure 56 is provided on the substrate 51, and the cover-type packaging structure 56 covers the system-on-chip die 52 and the filler die 53 around it.

[0054] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 11 A cap-type packaging structure 57 is provided on the substrate 51, and the cap-type packaging structure 57 covers the system-on-chip die 52 and the filler die 53 around it.

[0055] The cover-type package structure 56 or the cap-type package structure 57 is placed around the system-on-chip die 52 and the filler die 53, providing physical protection and heat dissipation. The combination of the cover-type package structure 56 or the cap-type package structure 57 and the filler die 53 comprehensively reduces the risk of chip cracking and bump breakage.

[0056] In addition, the cover-type package structure 56 or the cap-type package structure 57 covers the periphery of the system-on-chip die 52 and the filler die 53. Compared with the cover-type package structure 56 or the cap-type package structure 57, which only covers the system-on-chip die 52, the heat dissipation surface covered by the cover-type package structure 56 or the cap-type package structure 57 is increased, which further improves the heat dissipation effect.

[0057] 2.5D wafer-level multi-chip packaging technology places multiple chips side-by-side on a silicon interposer substrate to achieve better interconnect density and performance. However, in 2.5D wafer-level multi-chip packaging, the system-on-chip die 52 located in a corner may experience poor reliability due to an unbalanced overall layout.

[0058] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 12 The system-on-chip die 52 adopts 2.5D wafer-level multi-chip packaging technology. The system-on-chip die 52 includes: System-on-a-chip substrate 521.

[0059] At least one central logic chip 522 is fixed to the system-on-a-chip substrate 521.

[0060] Multiple peripheral functional chips 523 are fixed to the system-on-a-chip substrate 521 and are located in the vicinity of at least one central logic chip 522.

[0061] At least one virtual chip 524 is fixed to a system-on-a-chip substrate 521. At least one virtual chip 524, at least one central logic chip 522 and multiple peripheral functional chips 523 form a rectangular arrangement. At least one virtual chip 524 is located at a corner of the rectangular arrangement.

[0062] Specifically, the virtual chip 524 can be a chip without any electrical function; the virtual chip 524 can be a silicon chip; the virtual chip 524 can be a chip with a thickness similar to that of the central logic chip 522 and the peripheral function chip 523.

[0063] The virtual chip 524 can be set in one or more of the four corner positions of the arrangement. Figure 12 Only three corners are used as examples.

[0064] This embodiment of the disclosure introduces a virtual chip 524 into a rectangular arrangement formed by multiple peripheral functional chips 523 and at least one central logic chip 522. This completes the arrangement, which may originally be irregular in shape (such as L-shaped or concave), into a regular and complete rectangular arrangement, thereby achieving a balanced overall layout of the system-on-chip (SoC) die 52. With the virtual chip 524 at the corner positions, the in-plane stiffness distribution of the entire SoC die 52 array is more symmetrical, reducing the risk of SoC die 52 breakage and avoiding the poor reliability caused by corner failure in 2.5D packaging.

[0065] Specifically, at least one virtual chip 524 is fixed to the system-on-a-chip substrate 521 by an underfill adhesive 54. In this embodiment of the present disclosure, the use of a virtual chip 524 at a corner position reduces the risk of the underfill adhesive 54 at the corner position being peeled off by heat.

[0066] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 13 A heat dissipation structure 58 is provided on the surface of the system-on-chip die 52 and the filler die 53 away from the carrier substrate 51.

[0067] A heat dissipation structure 58 is directly disposed above the system-on-chip die 52 and the filler die 53, such as... Figure 13 As shown by the middle arrow, the area covered by the heat dissipation structure 58 is increased, which increases the heat dissipation area of ​​the heat dissipation structure 58 and enables it to dissipate the high heat generated by the grain during operation more quickly.

[0068] For the corresponding chip package, see [link / reference]. Figure 14 This disclosure also provides a chip packaging method, the method comprising: Step S1: Solder the system-on-chip die and filler die to the carrier substrate.

[0069] The filler die is located in the outer region of the system-on-chip die and is correspondingly located along one or more of the four edge lines of the system-on-chip die; the distance between the filler die and the system-on-chip die allows the filler die to provide support for the system-on-chip die.

[0070] Step S2: Use bottom filler adhesive to fix the system chips and filler chips on the wafer.

[0071] The embodiments disclosed herein effectively reduce the stress risk of packaged chips, improve the yield of packaging processes, enhance chip reliability, and increase chip lifespan.

[0072] In some specific implementations of the embodiments disclosed herein, see [link to relevant documentation]. Figure 15 The method also includes: Step S3: Set one of the following: reinforcement ring, cover plate packaging structure, or cap packaging structure around the system-on-chip die and filler die.

[0073] The reinforced ring, cover plate, and cap-type packaging structures comprehensively reduce the risk of chip cracking and bump breakage.

[0074] The cover-type or cap-type package structure covers the area around the system-on-chip die and filler die. Compared with the cover-type package structure 56 or the cap-type package structure which only covers the system-on-chip die, the heat dissipation surface covered by the cover-type or cap-type package structure is increased, which further improves the heat dissipation effect.

[0075] In some specific implementations of the embodiments of this disclosure, the system-on-chip die and the filler die are simultaneously soldered to the carrier substrate.

[0076] In this embodiment, the system-on-chip die and filler die are simultaneously soldered to the carrier substrate, which further simplifies the chip packaging process and further ensures the stress consistency of the system die and filler die as a whole.

[0077] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0078] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0079] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0080] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A packaged chip, comprising: substrate; The system-on-chip die is fixed to the carrier substrate by an underfill adhesive; Filler grains are fixed to the carrier substrate using the bottom filler adhesive; The filler grains are disposed in the outer region of the on-chip system grains and are disposed along one or more of the four edge lines of the on-chip system grains. The distance between the filler die and the system-on-chip die allows the filler die to provide support for the system-on-chip die.

2. The packaged chip of claim 1, wherein, The filling grains comprise a silicon substrate.

3. The packaged chip according to claim 2, wherein, The filling die is a mechanical support structure without a device layer or back-end process.

4. The packaged chip according to any one of claims 1-3, wherein, The filling grains are disposed in the outer regions of one or more of the four edge lines corresponding to the interconnection center region of the on-chip system grains.

5. The packaged chip according to claim 4, wherein, The distance between the filler die and the on-chip system die is greater than or equal to 50 μm and less than or equal to 150 μm.

6. The packaged chip according to claim 1, wherein the gap between the filler die and the system-on-chip die is filled with the underfill adhesive.

7. The packaged chip according to claim 1, wherein, A reinforcing ring is provided on the carrier substrate, and the reinforcing ring is disposed around the on-chip system grains and the filler grains.

8. The packaged chip according to claim 1, wherein, The substrate is provided with a cover-type packaging structure or a cap-type packaging structure, which covers the system-on-chip die and the filler die around it.

9. The packaged chip according to claim 1, wherein, The system-on-chip (SoC) die employs 2.5D wafer-level multi-chip packaging technology, and the SoC die includes: System-on-a-chip substrate, At least one central logic chip is fixed to the system-on-a-chip substrate; Multiple peripheral functional chips are fixed to the system-on-a-chip substrate and located in the vicinity of the at least one central logic chip; At least one virtual chip is fixed to the system-on-a-chip substrate. The at least one virtual chip, the at least one central logic chip, and the plurality of peripheral functional chips form a rectangular arrangement. The at least one virtual chip is located at a corner of the rectangular arrangement.

10. The packaged chip according to claim 1, wherein a heat dissipation structure is provided on the surface of the system-on-chip die and the filler die away from the carrier substrate.

11. A chip packaging method, the method comprising: The system-on-chip die and filler die are soldered to the carrier substrate; The filler grains are disposed in the outer region of the on-chip system grains and are disposed along one or more of the four edge lines of the on-chip system grains. The distance between the filler die and the system-on-chip die allows the filler die to provide support for the system-on-chip die; The on-chip system die and the filler die are fixed together using bottom filler adhesive.

12. The chip packaging method according to claim 11, wherein, The method further includes: A reinforcing ring, a cover-type packaging structure, or a cap-type packaging structure is provided around the on-chip system die and the filler die.

13. The chip packaging method according to claim 11 or 12, wherein, The system-on-chip die and the filler die are simultaneously soldered to the carrier substrate.

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