Semiconductor package structure and manufacturing method

Abstract

This invention provides a semiconductor packaging structure and method. The structure includes: a substrate, which serves as a support structure for carrying chips and providing electrical connections; multiple chips stacked sequentially in a horizontal direction, with each chip tilted relative to the substrate, such that each chip has an exposed portion at its edge facing the substrate; and multiple conductive bumps disposed on the side of each chip facing the substrate, achieving electrical connection between the chip and the substrate through the exposed portions. In this technical solution, all chips are stacked in a staggered manner, and each chip is tilted relative to the substrate, allowing the conductive bumps of each chip to be directly electrically connected to the substrate through their corresponding exposed portions. This eliminates the need for TSV vias and conductive bumps of varying heights, resulting in a simple overall structure with low processing difficulty. It also enables high-density integration of multiple chips, adapting to the packaging needs of multi-chips with different functional layers.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and more particularly to a semiconductor packaging structure and manufacturing method. Background Technology

[0002] In the field of semiconductor chip packaging, common chip interconnection methods include wire bonding, which uses wire bonding to interconnect chips and chips with substrates. Another common chip interconnection method is flip-chip bonding, which uses metals such as copper, tin, and silver to connect chips and substrates.

[0003] For wire bonding technology, the length of the bonding wires is typically in the millimeter or sub-millimeter range. As chip speeds increase, the resistance and inductance of these wires gradually limit chip performance. High resistance leads to high power consumption, while high inductance limits bandwidth. As chips become more complex, the number of pads on the bare chip surface increases, requiring further reduction in pad size and spacing. Limited by the diameter of the wires and the physical dimensions of the bonding equipment, the pads need to maintain a certain size, such as two to three times the diameter of the gold wire, which cannot meet the needs of complex chips requiring more input / output pads. A common approach to address these shortcomings is to use flip-chip technology.

[0004] In flip-chip technology, solder joints are located on the top surface of the chip. Solder balls, copper pillars, etc., are mass-produced and then flip-chip mounted onto a substrate. Flip-chip technology can shorten the distance between the chip and the substrate and increase the number of chip input / output ports, making it one of the main choices for advanced chip packaging technologies.

[0005] Since the bumps on flip chips are of the same height and distributed on the surface of the chip, they will cover the bumps when stacked. Flip chips cannot achieve chip stacking by using a single-chip flip chip.

[0006] To achieve multi-chip stacking, TSV technology can be used. This involves creating through-holes on the chips, followed by insulation and copper plating to connect the front and back sides. Then, flip-chip or hybrid bonding methods are used to interconnect the chips. TSV technology is complex, costly, and has limited production capacity, and is primarily used in servers and other applications.

[0007] If flip-chip bonding is used instead of TSV, one approach is to use fan-out packaging, where the pads are fanned out of the die and vertical interconnects are achieved on the top and bottom surfaces before flip-chip stacking. Compared to TSV, this method simplifies the fan-out packaging process, but requires multiple reflows. Each stack increases the signal transmission path length by the chip thickness.

[0008] Another approach uses vertical wire bonding and wafer-level packaging to stack and flip-chip the chips together. This involves two packaging methods, which are complex and require time to verify before combining them, resulting in high costs.

[0009] If flip-chip bonding is used instead of TSV (Through-Switch Vessel), one approach is to fabricate bumps of varying heights. However, since chips have a certain thickness (typically 50µm for stacked chips), the height of solder balls or copper pillars gradually increases with each additional layer. Generally, the height of copper pillars and other bumps is 100µm or less. In this approach, excessively high chip plating heights increase plating time, complicate process control, and significantly increase production costs, making it unsuitable for further increasing solder ball size or copper pillar height. Furthermore, fabricating bumps of varying heights increases the variety of materials used in production, requiring more stacking equipment and extending production time, making it unsuitable for mass production. Summary of the Invention

[0010] To address the aforementioned problems, the present invention provides a semiconductor packaging structure, comprising: a substrate, the substrate being a support structure for supporting chips and providing electrical connections; a plurality of chips, stacked sequentially in a horizontal direction, with each chip tilted relative to the substrate, such that each chip edge has an exposed portion facing the substrate; and a plurality of conductive bumps disposed on the side of each chip facing the substrate, thereby achieving electrical connections between the chips and the substrate through the exposed portions.

[0011] Optionally, the multiple chips have the same tilt angle, so that the height of the conductive bumps on each chip is consistent.

[0012] Optionally, a molding compound is also included, covering the plurality of chips, the plurality of conductive bumps, and a portion of the surface of the substrate.

[0013] Optionally, at least one dummy chip may be disposed at the bottom or top of the stacked structure of the plurality of chips to provide mechanical support.

[0014] To address the aforementioned problems, the present invention provides a method for manufacturing a semiconductor package structure, comprising the following steps: providing a substrate; forming conductive bumps on one side of a plurality of chips; stacking the plurality of chips sequentially and layer by layer with staggered spacing, forming exposed portions on the side where the bumps are formed to expose the bumps; flip-chipping the stacked plurality of chips onto the substrate, wherein the flip-chipping is performed with each chip tilted relative to the substrate and the conductive bumps facing the substrate, so that the conductive bumps are electrically connected to the substrate.

[0015] Optionally, a molding compound is formed to cover the plurality of chips, the conductive bumps, and a portion of the surface of the substrate.

[0016] Optionally, prior to the stacking step, a wafer adhesive film may be applied to the back of the chip.

[0017] Optionally, the stacking step further includes placing at least one dummy chip at the bottom or top of the stacked structure of the plurality of chips to provide mechanical support.

[0018] Optionally, the conductive bump can be a copper pillar formed by electroplating, a solder bump, an implanted solder ball, a metal pillar, or a pinned bump formed by wire bonding.

[0019] To address the aforementioned problems, the present invention provides a method for manufacturing a semiconductor package structure, comprising the following steps: providing a substrate and a plurality of chips; sequentially and layer by layer forming exposed portions of the plurality of chips to expose the electrical pins of the chips; forming conductive bumps at predetermined positions on the surface of the substrate; and flip-chipping the stacked plurality of chips onto the substrate, wherein the flip-chipping is performed by tilting each chip relative to the substrate and ensuring that the electrical pins of the chips are correspondingly attached to the conductive bumps, so that the conductive bumps are electrically connected to the substrate.

[0020] In the above technical solution, all chips are stacked in a staggered manner, with each chip tilted relative to the substrate. This allows the conductive bumps of each chip to be directly electrically connected to the substrate through their corresponding exposed portions. This eliminates the need for TSV vias and conductive bumps of varying heights, resulting in a simple overall structure with low fabrication difficulty. It also enables high-density integration of multiple chips, adapting to the packaging needs of multi-chip packages with different functions and layer counts. The conductive bumps can be set to the same height, further simplifying the fabrication process and reducing processing costs. In this structure, all chip pins are located on a single side of the chip, consistent with the design requirements of conventional multi-layer vertical stacked packages. No additional adjustments to existing chip designs are required, resulting in strong process adaptability.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] AppendixFigure 1 The diagram shows the implementation steps of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0024] Appendix Figure 2A To be continued Figure 2E The diagram shown is a process flow chart of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0025] Appendix Figure 3 The diagram shows the implementation steps of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0026] Appendix Figure 4A To be continued Figure 4D The diagram shown is a process flow chart of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0027] Appendix Figure 5 The diagram shows the implementation steps of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0028] Appendix Figure 6A To be continued Figure 6B The diagram shown is a process flow chart of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0029] Appendix Figure 7 The diagram shows the implementation steps of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0030] Appendix Figure 8A To be continued Figure 8B The diagram shown is a process flow chart of a method for manufacturing a semiconductor packaging structure according to a specific embodiment of the present invention.

[0031] Appendix Figure 9A To be continued Figure 9D The diagram shown is a schematic diagram of a semiconductor packaging structure according to a specific embodiment of the present invention. Detailed Implementation

[0032] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Appendix Figure 1The diagram illustrates the implementation steps of a semiconductor packaging structure manufacturing method according to a specific embodiment of the present invention, including the following steps: Step S10, providing a substrate; Step S11, forming conductive bumps on one side of a plurality of chips; Step S12, stacking the plurality of chips sequentially and layer by layer with staggered spacing, forming exposed portions on the side where the bumps are formed to expose the bumps; Step S13, flip-chipping the stacked plurality of chips onto the substrate, wherein each chip is tilted relative to the substrate with the conductive bumps facing the substrate, so that the conductive bumps are electrically connected to the substrate; Step S14, forming a molding compound layer to cover the plurality of chips, the conductive bumps, and a portion of the surface of the substrate.

[0034] Appendix Figure 2A As shown, referring to step S10, a substrate 21 is provided. The substrate 21 is a support structure used to support the chip and provide electrical connections. It can be a silicon wafer, a metal plate, or an organic substrate, and can be adapted to different materials according to actual packaging requirements, adapting to different process scenarios such as batch wafer-level packaging or single-chip packaging. The substrate 21 can also be a redistribution layer (RDL) on a functional wafer or a wiring layer on the chip surface, such as wafer-level packaging pads on a computing chip, where the stacked structure is directly flip-chip mounted on the wafer.

[0035] Appendix Figure 2B As shown, referring to step S11, conductive bumps 23 are formed on one side of the plurality of chips 22. The plurality of chips 22 can be of the same type or different types; for example, memory chips, control chips, or computing chips can be stacked together to meet different functional packaging requirements. Furthermore, the thickness of the plurality of chips can be the same or different depending on design requirements, adapting to diverse stacking designs. In this specific embodiment, four chips 22 are used as an example. Typical memory chips have four or multiples of four layers, such as the common 4 / 8 / 16 layers. In other specific embodiments, more or fewer chips can be used depending on actual needs.

[0036] In one specific implementation, in this step, conductive bumps 23 can be formed on one side of each chip 22 on a wafer to be connected. Then, dicing is performed to cut the wafer into individual bare chips. Alternatively, dicing can be performed first, followed by forming the conductive bumps. The number of conductive bumps 23 matches the number of pins to be brought out from the chip 22, and they are arranged in a direction perpendicular to the drawing. The conductive bumps 23 can be selected according to the process, using electroplated copper pillars, solder bumps, implanted solder balls, metal pillars, or wire-bonded stud bumps, adapting to different process line configurations. In the specific implementation of this packaging process, the chip 22 is designed to have all pins on a single side of the chip to facilitate the implementation of this technical solution. Compared to the interconnect structure of multiple chips stacked vertically, in order to form interconnects between chips, vias need to be formed through all chips at the edges, thus requiring pins to be designed on a single side of the chip. This structure is necessary for multi-layer stacked packaging; therefore, this technical solution does not require changes to the chip design compared to the vertical stacking interconnect scheme of multi-layer chips. Instead of simply creating solder joints, conductive bumps 23 can be distributed in areas outside the surface pads using a redistribution process.

[0037] In specific implementations, in addition to conventional packaging and connection processes, a die attach film (DAF film) can be attached to the back of the chip before dicing. The main purpose is to provide auxiliary fixing and bonding functions for subsequent multi-chip stacking and assembly processes, thereby ensuring the stability and relative position accuracy of the stacked structure during processing, and facilitating more reliable integration and connection.

[0038] Appendix Figure 2C As shown, referring to step S12, the multiple chips 22 are stacked layer by layer with staggered spacing, and exposed portions 24 are formed on the side where the bumps 23 are formed, thus exposing the bumps. During the stacking process, the positions of the exposed portions 24 on the side where the conductive bumps 23 are formed are staggered layer by layer, so that the conductive bump 23 area of ​​each chip forms a corresponding exposed portion 24. The width of the exposed portions 24 of each chip 22 can be set to be consistent, facilitating subsequent unified mating with the substrate 21. A temporary bonding method can be used for stacking. After stacking, the temporary bonding carrier wafer is removed, and then the stacked structure is further divided into independent stacked structures.

[0039] Appendix Figure 2DAs shown, referring to step S13, the stacked chips 22 are flip-chipped onto the substrate 21. The flip-chipping involves tilting each chip 21 relative to the substrate 21 with its conductive bumps 23 facing the substrate 21, so that the conductive bumps 23 are electrically connected to the substrate 21. The stacked chips 22 are flip-chipped onto the substrate 21 as a whole. During flip-chipping, the side of each chip 22 with the conductive bumps 23 faces the substrate 21, and each chip 22 is tilted relative to the substrate 21, ensuring that the conductive bumps 23 of each chip 22 are aligned with the corresponding connection points on the substrate 21 through their exposed portions, thus achieving electrical connection between the chip and the substrate 21. In this embodiment, the multiple chips 22 can be set to the same tilt angle, allowing the conductive bumps on different chips to maintain the same height, eliminating the need to manufacture bumps of different heights and simplifying the manufacturing process. A dedicated flip-chip fixture can also be used to fix the stacked structure during the flip-chipping process, ensuring the stability of the stacked structure and improving alignment accuracy.

[0040] Appendix Figure 2E As shown, referring to step S14, a molding compound 25 is formed, covering the plurality of chips 22, the conductive bumps 23, and a portion of the surface of the substrate 21. After flip-chip alignment is completed, the step of forming the molding compound 25 may be further included. This step covers the plurality of chips, all conductive bumps, and a portion of the surface of the substrate, sealing and protecting the entire structure and improving the reliability of the packaging structure.

[0041] Finally, if a batch processing technology such as fan-out wafer-level or board-level packaging is used, after the molding process is completed, steps such as ball mounting and dicing can be performed to cut the overall molded structure into multiple independent packaging units, thus completing the manufacturing of the entire semiconductor package.

[0042] Appendix Figure 3 The diagram illustrates the implementation steps of a semiconductor packaging structure manufacturing method according to a specific embodiment of the present invention, including the following steps: Step S20, providing a substrate and a plurality of chips; Step S21, sequentially and layer by layer forming exposed portions of the plurality of chips to expose the electrical pins of the chips; Step S22, forming conductive bumps at predetermined positions on the surface of the substrate; Step S23, flip-chipping the stacked plurality of chips onto the substrate, wherein each chip is tilted relative to the substrate and the electrical pins of the chip are correspondingly attached to the conductive bumps, so that the conductive bumps are electrically connected to the substrate.

[0043] Appendix Figure 4AAs shown, referring to step S20, a substrate 41 and multiple chips 42 are provided. In this step, the substrate 41 can also be selected as a silicon wafer, metal plate, or organic substrate according to requirements. The multiple chips 42 can be selected as chips of the same type or different functional types as needed, and the thickness can also be adjusted according to the design to adapt to diverse packaging requirements. In this embodiment, conductive bumps are prepared on one side of the substrate 41, eliminating the need to pre-fabricate conductive bumps on each chip 42, further simplifying the chip 42 preprocessing process and adapting to different supply chain process configurations.

[0044] Appendix Figure 4B As shown, referring to step S21, the plurality of chips 42 are sequentially staggered layer by layer to form exposed portions 44, thereby exposing the electrical pins of the chips 42. The plurality of chips 42 are stacked sequentially layer by layer, with each layer of chips 42 extending outwards from the side where the electrical pins are located, staggered relative to the layer below. This allows the electrical pins of each layer of chips 42 to form independent exposed portions, preventing them from being blocked by the upper layer of chips 42, thus providing conditions for subsequent alignment and bonding with the conductive bumps on the substrate 41.

[0045] Appendix Figure 4C As shown, referring to step S22, conductive bumps 43 are formed at predetermined positions on the surface of the substrate 41. The conductive bumps 43 are pre-arranged to correspond to the positions of the electrical pins exposed by each layer of chip 42. Similarly, depending on the existing process conditions, electroplated copper pillars, solder bumps, implanted solder balls, metal pillars, or wire bonding formed pin bumps can be selected to adapt to the processing capabilities of different production lines, and processing can be completed without additional modifications to the production line.

[0046] Appendix Figure 4D As shown, referring to step S23, the stacked chips 42 are flip-chip mounted onto the substrate 41. The flip-chip mounting involves tilting each chip 42 relative to the substrate 41, with the electrical pins of the chip 42 corresponding to and abutting the conductive bumps 43, thus electrically connecting the conductive bumps 43 to the substrate 41. The stacked chips 42 are then flip-chip mounted onto the substrate 41 as a whole. During flip-chip mounting, each chip 42 remains tilted, ensuring that the exposed electrical pins of each layer of chips 42 correspond one-to-one with the pre-set conductive bumps 43 on the substrate 41. This guarantees reliable electrical connections and eliminates the need to fabricate conductive bumps 43 of different heights for different layers; all conductive bumps 43 can be set to the same height, significantly simplifying the fabrication process and reducing processing costs.

[0047] After the alignment and bonding are completed, a molding layer can be further formed to cover the entire stacked chip 42, conductive bumps 43 and part of the substrate 41 surface, to protect the packaging structure and improve structural reliability. If it is wafer-level batch processing, it can be cut into independent packaging units at the end.

[0048] Unlike the previous embodiment, this embodiment pre-fabricates conductive bumps on the substrate instead of on each chip. This adjustment adapts to different chip supply processes. For scenarios where the chip foundry has already completed wafer fabrication and only outputs bump-free finished chips, no additional chip-side preprocessing steps are required. Bump fabrication can be directly completed using existing substrate processing lines, further reducing process integration costs. Simultaneously, this embodiment retains the core design of staggered stacking and flip-chip tilting, eliminating the need for bumps of different heights or additional TSV vias. It also achieves multi-chip stacking and flip-chip bonding while simplifying the process and reducing costs, meeting the demands of high-density advanced packaging. In this embodiment, the position of the conductive bumps on the substrate can be adjusted according to the chip pin arrangement, allowing for flexible adaptation to both stacking chips with the same function and integrating heterogeneous chips, thus accommodating different packaging application scenarios.

[0049] Appendix Figure 5 The diagram illustrates the implementation steps of a semiconductor packaging structure manufacturing method according to a specific embodiment of the present invention, including the following steps: Step S30, providing a substrate and a plurality of chips; Step S31, forming conductive bumps on one side of each chip; Step S32, sequentially staggering the plurality of chips layer by layer, staggering the sides where the bumps are formed to form exposed portions to expose the bumps, and placing a dummy die on top of the stacked structure of the plurality of chips; Step S33, flip-chipping the stacked plurality of chips onto the substrate, wherein each chip is tilted relative to the substrate and the conductive bumps face the substrate, so that the conductive bumps are electrically connected to the substrate; Step S34, forming a molding compound layer to cover the plurality of chips, the conductive bumps, the dummy die, and a portion of the surface of the substrate.

[0050] The specific implementation methods described above refer to the implementation process of the foregoing specific implementation methods. The difference lies in the appendix... Figure 6A As shown, in step S32, the multiple chips are staggered layer by layer, and an exposed portion is formed on one side where a bump is formed to expose the bump. A dummy die 61 is then placed on top of the stacked chip structure. Correspondingly, refer to the attached diagram. Figure 6BAs shown, in the package formed after step S34, the dummy chip 61 is flipped to the bottom, forming a support between the chip stack structure and the substrate. This supports the tilted chip and prevents collapse during the molding process and subsequent use. When there are many stacked chips and the overall stack height is high, the dummy chip can balance the stress on the entire stack structure, further improving the structural stability during flip-chip alignment and ensuring better packaging yield. The dummy chip can be made of an insulating material with a coefficient of thermal expansion similar to that of the chip, avoiding the introduction of additional thermal stress mismatch issues. It also does not occupy additional functional pin layout space and does not affect the electrical performance of the package structure.

[0051] Appendix Figure 7 The diagram illustrates the implementation steps of a semiconductor packaging structure manufacturing method according to a specific embodiment of the present invention, including the following steps: Step S40, providing a substrate and a plurality of chips; Step S41, forming conductive bumps on one side of each chip; Step S42, sequentially staggering the plurality of chips layer by layer, forming exposed portions on the side where the bumps are formed to expose the bumps, and placing a dummy die at the bottom of the stacked chip structure; Step S43, flip-chipping the stacked plurality of chips onto the substrate, wherein each chip is tilted relative to the substrate with the conductive bumps facing the substrate, so that the conductive bumps are electrically connected to the substrate; Step S44, forming a molding compound layer to cover the plurality of chips, the conductive bumps, the dummy die, and a portion of the surface of the substrate.

[0052] The specific implementation methods described above refer to the implementation process of the foregoing specific implementation methods. The difference lies in the appendix... Figure 8A As shown, in step S42, the multiple chips are staggered layer by layer, and an exposed portion is formed on one side where a bump is formed to expose the bump. A dummy die 81 is then placed at the bottom of the multiple chip stack structure. Correspondingly, refer to the attached diagram. Figure 8BAs shown, in the package formed after step S34, the dummy die 81 is flipped to the top, forming a protective layer for the chip. Subsequent grinding and polishing create a complete protective structure, preventing damage caused by direct exposure of the chip top and improving the overall structural strength and reliability of the package. Furthermore, by designing the dummy die as a high thermal conductivity material, the overall heat dissipation rate of the package structure can be improved. This structure eliminates the need for a dedicated flip-chip fixture to fix the stacked structure during the flip-chip process, as the dummy die ensures the stability of the stacked structure. When there are many stacked chip layers and the overall structure is tall, this setting provides additional protection for the top chip and can also adjust the resin flow during molding, reducing the formation of voids and further improving the packaging yield. The dummy die is also made of an insulating material with a coefficient of thermal expansion matching that of the chip, ensuring no negative impact on the electrical performance and reliability of the package.

[0053] The dummy chips in the two positions mentioned above can be used simultaneously to balance the structural stability during flip-chip bonding and the structural protection performance after molding. This also solves the problems of stress support and top protection when the stacking height is high, further adapting to high-density packaging scenarios with large-layer multi-chip stacking. Without adding extra complex processes or changing the core chip design, it effectively improves the reliability and processing yield of the packaging structure, meeting the needs of multi-chip packaging with higher integration.

[0054] After completing the above steps, a semiconductor packaging structure is obtained. (See attached image) Figure 9A The diagram illustrates a semiconductor packaging structure according to a specific embodiment of the present invention, comprising: a substrate 91; a plurality of chips 92, stacked sequentially in a horizontal direction, with each chip 92 tilted relative to the substrate 91, such that each chip 92 has an exposed edge facing the substrate 91; a plurality of conductive bumps 94 disposed on the side of each chip 92 facing the substrate 91, and the exposed portions 93 enabling electrical connection between the chip 92 and the substrate 91. A molding compound 95 covers the plurality of chips 92, the plurality of conductive bumps 94, and a portion of the surface of the substrate 91.

[0055] In the above structure, all chips are stacked in a staggered manner, with each chip tilted relative to the substrate. This allows the conductive bumps of each chip to be directly electrically connected to the substrate through their corresponding exposed portions. This eliminates the need for TSV vias and conductive bumps of varying heights, resulting in a simple overall structure with low fabrication difficulty. It also enables high-density integration of multiple chips, adapting to the packaging needs of multi-chip packages with different functions and layer counts. The conductive bumps can be set to the same height, further simplifying the fabrication process and reducing processing costs. In this structure, all chip pins are located on a single side of the chip, consistent with the design requirements of conventional multi-layer vertical stacked packages. No additional adjustments to existing chip designs are required, resulting in strong process adaptability.

[0056] Furthermore, as a preferred embodiment, the appendix... Figure 9B The diagram illustrates a semiconductor packaging structure according to another specific embodiment of the present invention, comprising: a substrate 91; a plurality of chips 92, stacked sequentially along a horizontal direction, with each chip 92 tilted relative to the substrate 91, thereby exposing an edge of each chip 92 facing the substrate 91; a plurality of conductive bumps 94 disposed on the side of each chip 92 facing the substrate 91, achieving electrical connection between the chip 92 and the substrate 91 through the exposed portion; and dummy wafers 961 and 962, wherein the dummy wafer 961 forms a support between the chip stack structure and the substrate, and the dummy wafer 962 is disposed on top of the packaging structure, forming a protective layer for the chip 92. Compared with the above structure, the structure using dummy wafer support or top protection can further improve structural reliability for high-layer stacking scenarios without changing the core stacking flip-chip design, while not increasing additional process costs. The addition of dummy wafers and their placement can be flexibly selected according to actual stacking requirements.

[0057] Furthermore, as a preferred embodiment, the appendix... Figure 9C The diagram shown is a schematic representation of a semiconductor packaging structure according to another specific embodiment of the present invention, including: a substrate 91, a plurality of chips 92 in an inclined state, and a plurality of conductive bumps 94. This specific embodiment also includes a dummy die 963, which forms additional support between the chip stack structure.

[0058] Furthermore, as a preferred embodiment, the appendix... Figure 9DThe diagram illustrates a semiconductor packaging structure according to another specific embodiment of the present invention, including: a substrate 91, multiple chips 92 in an inclined state, and multiple conductive bumps 94. This embodiment also includes dummy wafers 964, formed in the exposed portion of the chip stack structure, without increasing the stack height or horizontal dimensions. These dummy wafers serve a supporting function. Such dummy wafers are suitable for situations where the conductive bumps 94 are unevenly distributed due to design considerations. Adding additional dummy wafers in areas with sparse conductive bump distribution can balance stress distribution and improve support strength, preventing localized collapse.

[0059] The above methods for setting up fake chips can be combined in one or more ways to achieve different packaging forms, depending on the actual situation.

[0060] In the above technical solution, the flip-chip and substrate are not parallel. The chips are stacked first and then flipped, with a certain tilt angle between the flip-chip and the substrate. This tilting achieves consistent bump heights in the stacked chips, saving the cost of long electroplating times during bump fabrication and avoiding the process complexity caused by excessively high bumps in subsequent packaging processes. This angle is a predetermined angle generated in the packaging structure design to ensure that the bump ends have different heights when the stacked structure is placed horizontally, thus achieving flip-chip bonding. This angle is not caused by process deviations during manufacturing. For ease of understanding, the dimensions and angles in the figure may not be proportional to the actual dimensions and angles. As the number of stacks increases, the thickness of the packaging structure does not change, but the horizontal area increases, which is particularly suitable for mobile terminal applications with strict thickness requirements. Compared with wire bonding solutions, this solution reduces the connection size and the requirements for pad size, solving the problem of reducing chip pad size and spacing to the equivalent size or below of bonding wires, such as 10µm pads and 15µm spacing. The thickness of the stacked chips can be the same or different to meet the needs of mechanical support or heat dissipation, and both are considered to be within the scope of protection of this patent.

[0061] In the above technical solution, multiple chips are stacked horizontally and then flip-chip mounted on a substrate at an angle. Utilizing the positional difference after the chips are tilted, the conductive bumps of each chip are exposed on the side facing the substrate. This eliminates the need to fabricate conductive bumps of varying heights or TSV vias, significantly simplifying the multi-chip flip-chip stacking process and reducing manufacturing costs. Multiple chips can be fabricated using the same process to create conductive bumps of uniform height. Maintaining a consistent tilt angle ensures that the bottom ends of all conductive bumps are flush, aligning with the corresponding conductive pads on the substrate. This allows for one-time soldering interconnection, eliminating the need for multiple reflow soldering steps, shortening the signal transmission path, and improving mass production efficiency. Furthermore, the exposed positions after tilting are precisely where TSV vias would normally be fabricated. Therefore, compared to TSV via packaging technologies, this solution can be implemented without altering the chip pin positions.

[0062] In the above technical solutions, multiple chips can be selected from the same or different types according to packaging requirements. For example, multiple memory chips of the same specification can be stacked, or memory chips, control chips, and computing chips can be mixed and stacked to adapt to different functional requirements. The thickness of the chips can also be adjusted according to the actual design without affecting the interconnection process. Conductive bumps can be selected from electroplated copper pillars, solder bumps, implanted solder balls, metal pillars, or wire bonding-formed pin bumps according to process conditions, with strong compatibility and adaptability to different existing packaging production line processes. When the number of stacked chips is large, dummy chips can be set at the bottom or top of the stacked structure to provide mechanical support, improve the stability of the stacked structure, and facilitate subsequent flip-chip and molding operations. The substrate can also be selected from silicon wafers, metal plates, or organic substrates according to packaging requirements, adapting to different packaging forms such as wafer-level packaging and board-level packaging.

[0063] After flip-chip interconnection is completed, a molding compound is formed to cover multiple chips, conductive bumps, and part of the substrate surface, protecting and insulating the entire stacked structure. Then, a dicing process is used to cut the molded structure into individual packaging units, yielding the finished semiconductor package structure. The entire manufacturing process does not require combining multiple different packaging processes, the process steps are simple, verification costs are low, it is suitable for mass production, and it can achieve multi-chip flip-chip stacking without using TSVs, balancing performance and cost.

[0064] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0065] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0066] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: A substrate, which is a support structure used to support the chip and provide electrical connections; Multiple chips are stacked sequentially in a horizontal direction, and each chip is tilted relative to the substrate, so that each chip edge has an exposed portion facing the substrate; Multiple conductive bumps are disposed on the side of each chip facing the substrate, and the exposed portion enables electrical connection between the chip and the substrate.

2. The semiconductor packaging structure according to claim 1, characterized in that, The multiple chips are tilted at the same angle, so that the height of the conductive bumps on each chip is consistent.

3. The semiconductor packaging structure according to claim 1, characterized in that, It also includes a molding compound that covers the plurality of chips, the plurality of conductive bumps, and a portion of the surface of the substrate.

4. The semiconductor packaging structure according to claim 1, characterized in that, It also includes at least one dummy chip, disposed at at least one or a combination of the bottom, middle or top of the stacked structure of the plurality of chips, for providing mechanical support.

5. A method for manufacturing a semiconductor package structure, characterized in that, Includes the following steps: Provide a substrate; Conductive bumps are formed on one side of the plurality of chips; The multiple chips are stacked in a staggered manner, and an exposed portion is formed on one side of the bump to expose the bump; The stacked chips are flip-chipped onto the substrate, wherein each chip is tilted relative to the substrate with the conductive bumps facing the substrate, so that the conductive bumps are electrically connected to the substrate.

6. The manufacturing method according to claim 5, characterized in that, Also includes: A molding layer is formed to cover the plurality of chips, the conductive bumps, and a portion of the surface of the substrate.

7. The manufacturing method according to claim 5, characterized in that, Prior to the stacking step, a wafer adhesive film is also attached to the back of the chip.

8. The manufacturing method according to claim 5, characterized in that, The stacking step also includes placing at least one dummy chip or a combination of multiple locations at the bottom, middle or top of the stacked structure of the multiple chips to provide mechanical support.

9. The manufacturing method according to claim 5, characterized in that, The conductive bumps are electroplated copper pillars, solder bumps, implanted tin balls, metal pillars, or studded bumps formed by wire bonding.

10. A method for manufacturing a semiconductor package structure, characterized in that, Includes the following steps: Provides a substrate and multiple chips; The multiple chips are staggered layer by layer to form exposed portions, thereby exposing the electrical pins of the chips; Conductive bumps are formed at predetermined positions on the surface of the substrate; The stacked chips are flip-chipped onto the substrate. The flip-chipping involves tilting each chip relative to the substrate and aligning the electrical pins of the chip with the conductive bumps, so that the conductive bumps are electrically connected to the substrate.

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