Performing thermal management based on temperature evolution model in processor device

Abstract

This document discloses performing thermal management based on a temperature evolution model in a processor device. In some aspects, a processor device provides cluster thermal management circuitry configured to determine power consumption measurements of corresponding functional units of processor cores among multiple processor cores in a core cluster. The cluster thermal management circuitry also determines temperature measurements taken by corresponding digital thermal sensors (thermal sensors) outside a point of interest (POI) within the processor core. The cluster thermal management circuitry generates a predicted temperature at the POI based on a temperature evolution model that correlates the power consumption measurements and temperature measurements with the predicted temperature at the POI. When the cluster thermal management circuitry determines that the predicted temperature at the POI exceeds a thermal mitigation threshold, the cluster thermal management circuitry performs thermal management operations.

Description

Priority application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 407,690, filed January 9, 2024, entitled “Performing Thermal Management Based on Temperature Evolution Models in Processor Devices,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The technology disclosed herein relates generally to thermal management in multi-core processor devices, and particularly to thermal management of clusters of processor cores in a processor device. Background Technology

[0003] Conventional processor devices can be implemented as multiple processing units or "processor cores" organized into core clusters, each processor core configured to fetch, decode, and execute computer instructions to manipulate and store data. Because multi-core processor devices can execute instructions simultaneously on multiple processor cores, the performance of software supporting parallel computing techniques such as multithreading can be improved. Each core cluster of a multi-core processor device can be "synchronous" because all processor cores in the core cluster are timed using a single clock source such as a phase-locked loop (PLL). Because all processor cores share the same clock source, frequency changes in a synchronous core cluster affect all active processor cores within the core cluster. The processor cores in a core cluster can also be implemented using a shared Level 2 (L2) microarchitecture, in which the processor cores are connected to and share a single L2 cache.

[0004] Many conventional processor cores include functional units (e.g., by way of non-limiting example, Integer Execution Unit (IXU), Vector Execution Unit (VXU), and Arithmetic Logic Unit (ALU)) that consume a larger proportion of power relative to other components of the processor device, and therefore tend to exhibit higher power density relative to those other components. Depending on the type of workload performed by the processor core, the processor core's power consumption at a given time may be concentrated within specific functional units of the processor core. These points of higher power consumption create localized "hot spots," where temperatures are higher than other areas within the processor core. For example, when the processor core performs a workload consisting primarily of integer operations, the processor core's IXU consumes more power than other areas within the processor core, and therefore generates more heat. Similarly, a workload heavy with vector instructions may cause the processor core's VXU to consume more power and generate more localized heat.

[0005] To mitigate the effects of high temperatures, each processor core incorporates multiple thermal sensors (such as digital thermal sensors (DTS) as a non-limiting example) to monitor temperatures at different locations within the processor. However, minimizing the number of thermal sensors within a processor core is desirable, as each additional sensor increases the area occupied by the processor core. Furthermore, the placement of each thermal sensor within the processor core may not be optimal for monitoring the temperature at a specific point of interest (POI) (such as one of the hotspots described above). This can lead to a significant discrepancy between the temperature measurement at the thermal sensor location and the temperature at the POI. Finally, the latency of obtaining temperature measurements from the thermal sensors can pose a challenge to the thermal management architecture compared to the potential rate of temperature increase. Summary of the Invention

[0006] The aspects disclosed in the specific embodiments include performing thermal management based on a temperature evolution model in a processor device. Related apparatus, methods, and computer-readable media are also disclosed. In this regard, a processor device provides a core cluster including a plurality of processor cores and cluster thermal management circuitry. The cluster thermal management circuitry is configured to receive one or more power consumption measurements for one or more corresponding functional units of the processor cores among the plurality of processor cores. The cluster thermal management circuitry is further configured to receive one or more temperature measurements taken by one or more corresponding thermal sensors outside a point of interest (POI) (such as a hot spot) within the processor core. The cluster thermal management circuitry then generates a predicted temperature at the POI based on a temperature evolution model that correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The cluster thermal management circuitry determines whether the predicted temperature at the POI exceeds a thermal mitigation threshold. If so, the cluster thermal management circuitry performs thermal management operations. Thus, the cluster thermal management circuitry is able to control the temperature at multiple POIs within a processor core without requiring physical thermal sensors at each POI. Furthermore, cluster thermal management circuitry can (e.g., through a combination of clock throttling and dynamic voltage and frequency scaling (DVFS)) control the rapid evolution of temperature within the processor core based on the core's temperature evolution characteristics, and can achieve active temperature control.

[0007] In some aspects, the temperature evolution model includes a transfer function model comprising: multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and multiple outputs, each representing a pre-silicon temperature measurement performed by a thermal sensor among the one or more thermal sensors. The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit. In this aspect, the temperature evolution model also includes a gradient model configured to model the temperature change between each thermal sensor and the POI. The temperature evolution model, according to some aspects, can be integrated into the firmware of the cluster thermal management circuitry.

[0008] In some aspects, generating the predicted temperature at the POI may include using a temperature evolution model to generate a first model representing the temperature at the thermal sensor among the one or more thermal sensors. In such aspects, the cluster thermal management circuitry also uses the temperature evolution model and the first model to generate a second model representing the temperature at the POI. Furthermore, the cluster thermal management circuitry uses the temperature evolution model to generate a third model representing the boundary conditions.

[0009] Several aspects are available: Performing thermal management operations includes the cluster thermal management circuitry employing clock throttling circuitry to perform thermal management. In this regard, the cluster thermal management circuitry uses a temperature evolution model to calculate a power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. The cluster thermal management circuitry then determines whether the current power consumption of the processor core exceeds the power threshold. If so, the cluster thermal management circuitry identifies a target clock throttling level lower than the current clock throttling level of the core cluster and sends the target clock throttling level to the clock throttling circuitry.

[0010] According to some aspects, performing thermal management operations may include the cluster thermal management circuit employing a DVFS circuit to perform thermal management. Accordingly, in such aspects, the cluster thermal management circuit may use the temperature evolution model to calculate one or more operating points for the core cluster. Some such aspects may provide that calculating the one or more operating points may include the cluster thermal management circuit calculating a cost function, which may include predicting future temperature evolution based on a future temperature evolution filter. The cluster thermal management circuit may then use the cost function to generate a frequency change strategy. If the cluster thermal management circuit subsequently determines that the predicted temperature at the POI exceeds the thermal mitigation threshold, the cluster thermal management circuit performs the thermal management operation by selecting a target operating point from the one or more operating points, wherein the target operating point is lower than the current operating point for the core cluster. In some aspects, the selection of the target operating point may be based on the frequency change strategy. The cluster thermal management circuit then sends the target operating point to the DVFS circuit.

[0011] In another aspect, a processor device is provided. The processor device includes a core cluster comprising a plurality of processor cores, and further includes cluster thermal management circuitry. The cluster thermal management circuitry is configured to receive one or more power consumption measurements for one or more corresponding functional units of the processor cores. The cluster thermal management circuitry is further configured to receive one or more temperature measurements performed by one or more corresponding thermal sensors outside a Point of Interest (POI) within the processor core. The cluster thermal management circuitry is also configured to generate a predicted temperature at the POI based on a temperature evolution model that correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The cluster thermal management circuitry is additionally configured to determine whether the predicted temperature at the POI exceeds a thermal mitigation threshold. The cluster thermal management circuitry is further configured to perform thermal management operations in response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold.

[0012] In another aspect, a processor device is provided. The processor device includes components for receiving one or more power consumption measurements of one or more corresponding functional units of a processor core among a plurality of processor cores in a core cluster of the processor device. The processor device also includes components for receiving one or more temperature measurements performed by one or more corresponding thermal sensors outside a POI within the processor core. The processor device further includes components for generating a predicted temperature at the POI based on a temperature evolution model that correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The processor device additionally includes components for determining whether the predicted temperature at the POI exceeds a thermal mitigation threshold. The processor device also includes components for performing thermal management operations in response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold.

[0013] On the other hand, a method for performing thermal management based on a temperature evolution model is provided. The method includes determining, by cluster thermal management circuitry of a core cluster of a processor device, one or more power consumption measurements for one or more functional units corresponding to a processor core among a plurality of processor cores in the core cluster. The method also includes determining, by the cluster thermal management circuitry, one or more temperature measurements taken by one or more corresponding thermal sensors outside a POI within the processor core. The method further includes generating a predicted temperature at the POI by the cluster thermal management circuitry based on a temperature evolution model that correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The method additionally includes determining, by the cluster thermal management circuitry, that the predicted temperature at the POI exceeds a thermal mitigation threshold. The method also includes performing thermal management operations by the cluster thermal management circuitry in response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold.

[0014] In another aspect, a non-transitory computer-readable medium is disclosed. This non-transitory computer-readable medium stores computer-executable instructions that, when executed, cause a processor device of a processor-based device to receive one or more power consumption measurements of one or more corresponding functional units of a processor core among a plurality of processor cores in a core cluster of the processor device. The computer-executable instructions further cause the processor device to receive one or more temperature measurements performed by one or more corresponding thermal sensors outside a Point of Interest (POI) within the processor core. The computer-executable instructions further cause the processor device to generate a predicted temperature at the POI based on a temperature evolution model that correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The computer-executable instructions additionally cause the processor device to determine whether the predicted temperature at the POI exceeds a thermal mitigation threshold. The computer-executable instructions further cause the processor device to perform thermal management operations in response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold. Attached Figure Description

[0015] Figure 1 It is a block diagram of an exemplary processor-based device including a core cluster that includes cluster thermal management circuitry configured to perform thermal management based on a temperature evolution model.

[0016] Figure 2 This illustrates some aspects used for implementing thermal management. Figure 1 A block diagram showing exemplary components of a cluster thermal management circuit and the information flow to and from the cluster thermal management circuit.

[0017] Figures 3A to 3D Examples are provided based on some aspects. Figure 1 The flowchart illustrates the exemplary operations performed by the processor device to perform thermal management based on a temperature evolution model.

[0018] Figure 4 Yes, it can include Figure 1 A block diagram of an exemplary processor-based device. Detailed Implementation

[0019] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects. The terms “first,” “second,” etc., are used herein to distinguish similarly named elements and should not be construed as indicating an ordinal relationship between such elements unless so explicitly described herein.

[0020] The aspects disclosed in the specific embodiments include performing thermal management based on a temperature evolution model in a processor device. Related apparatus, methods, and computer-readable media are also disclosed. In this regard, a processor device provides a core cluster including a plurality of processor cores and cluster thermal management circuitry. The cluster thermal management circuitry is configured to receive one or more power consumption measurements for one or more corresponding functional units of the processor cores among the plurality of processor cores. The cluster thermal management circuitry is further configured to receive one or more temperature measurements taken by one or more corresponding thermal sensors outside a point of interest (POI) (such as a hot spot) within the processor core. The cluster thermal management circuitry then generates a predicted temperature at the POI based on a temperature evolution model that correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The cluster thermal management circuitry determines whether the predicted temperature at the POI exceeds a thermal mitigation threshold. If so, the cluster thermal management circuitry performs thermal management operations. Thus, the cluster thermal management circuitry is able to control the temperature at multiple POIs within a processor core without requiring physical thermal sensors at each POI. Furthermore, cluster thermal management circuitry can (e.g., through a combination of clock throttling and dynamic voltage and frequency scaling (DVFS)) control the rapid evolution of temperature within the processor core based on the core's temperature evolution characteristics, and can achieve active temperature control.

[0021] In some aspects, the temperature evolution model includes a transfer function model comprising: multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and multiple outputs, each representing a pre-silicon temperature measurement performed by a thermal sensor among the one or more thermal sensors. The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit. In this aspect, the temperature evolution model also includes a gradient model configured to model the temperature change between each thermal sensor and the POI. The temperature evolution model, according to some aspects, can be integrated into the firmware of the cluster thermal management circuitry.

[0022] In some aspects, generating the predicted temperature at the POI may include using a temperature evolution model to generate a first model representing the temperature at the thermal sensor among the one or more thermal sensors. In such aspects, the cluster thermal management circuitry also uses the temperature evolution model and the first model to generate a second model representing the temperature at the POI. Furthermore, the cluster thermal management circuitry uses the temperature evolution model to generate a third model representing the boundary conditions.

[0023] Several aspects are available: Performing thermal management operations includes the cluster thermal management circuitry employing clock throttling circuitry to perform thermal management. In this regard, the cluster thermal management circuitry uses a temperature evolution model to calculate a power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. The cluster thermal management circuitry then determines whether the current power consumption of the processor core exceeds the power threshold. If so, the cluster thermal management circuitry identifies a target clock throttling level lower than the current clock throttling level of the core cluster and sends the target clock throttling level to the clock throttling circuitry.

[0024] According to some aspects, performing thermal management operations may include the cluster thermal management circuit employing a DVFS circuit to perform thermal management. Accordingly, in such aspects, the cluster thermal management circuit may use the temperature evolution model to calculate one or more operating points for the core cluster. Some such aspects may provide that calculating the one or more operating points may include the cluster thermal management circuit calculating a cost function, which may include predicting future temperature evolution based on a future temperature evolution filter. The cluster thermal management circuit may then use the cost function to generate a frequency change strategy. If the cluster thermal management circuit subsequently determines that the predicted temperature at the POI exceeds the thermal mitigation threshold, the cluster thermal management circuit performs the thermal management operation by selecting a target operating point from the one or more operating points, wherein the target operating point is lower than the current operating point for the core cluster. In some aspects, the selection of the target operating point may be based on the frequency change strategy. The cluster thermal management circuit then sends the target operating point to the DVFS circuit.

[0025] In this respect, Figure 1 This is a block diagram of an exemplary processor device 100 (also referred to as a “processor” or “CPU”). The processor device 100 may include ordered or unordered processors (OoP), and / or may be one of a plurality of processor devices 100. Examples of processor devices 100 may include, but are not limited to, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits.

[0026] like Figure 1 As seen, the processor device 100 includes multiple core clusters 102(0)-102(X), each of which includes multiple processor cores, such as processor cores 104(0)-104(C) of core cluster 102(0). Figure 1The processor device 100 in the example also includes a graphics processing unit (GPU) 106 for performing graphics operations. As a non-limiting example, GPU 106 may include a dedicated hardware unit having fixed functionality and programmable components for rendering graphics and executing GPU applications. GPU 106 may also include a DSP, a general-purpose microprocessor, an ASIC, an FPGA, or other equivalent integrated or discrete logic circuitry; for clarity, these are referred to as such in... Figure 1 Not shown in the image.

[0027] Figure 1 The processor device 100 in the example also includes additional exemplary components, including an artificial intelligence (AI) engine 108, mobile device management (MDM) circuitry 110, power management circuitry 112, on-chip network (NoC) 114, and memory device 116. As a non-limiting example, the AI ​​engine 108 of the processor device 100 includes circuitry and logic for providing AI-based functionality such as search, speech recognition, text and / or image generation. The MDM circuitry 110 provides functionality for provisioning, configuring, updating, and / or protecting mobile devices to which the processor device 100 is integrated. The power management circuitry 112 provides advanced performance and power management functionality for the processor device 100 as a whole, while the NoC 114 is configured to manage communication between different devices including the processor device 100. Finally, the memory device 116 provides storage and access to data used by the processor device 100, and in some aspects, as a non-limiting example, may include a double data rate (DDR) synchronous dynamic random access memory (SDRAM) device.

[0028] Figure 1 Exemplary elements of core cluster 102(0) are illustrated in more detail. The processor cores 104(0)-104(C) of core cluster 102(0) are communicatively coupled to a last-level cache (LLC) 118 that stores frequently accessed data for faster access, and are communicatively coupled to a phase-locked loop (PLL) 120 that provides clock signals to the processor cores 104(0)-104(C) and LLC 118. The frequency and voltage at which the processor cores 104(0)-104(C) of core cluster 102(0) operate are controlled by a DVFS circuit 122 configured to select the operating point (i.e., the combination of voltage and clock frequency) at which core cluster 102(0) will operate. The core cluster 102(0) also includes a clock throttling circuit 124 configured to control the clock frequency of core cluster 102(0) operation by, for example, throttling the core cluster 102(0), such that core cluster 102(0) operates at a clock frequency lower than the maximum clock frequency supported by the voltage at which core cluster 102(0) operates. It should be understood that, although Figure 1Only exemplary elements of core cluster 102(0) are shown, but each core cluster in core clusters 102(0)-102(X) includes elements corresponding to the illustrated elements of core cluster 102(0).

[0029] Figure 1 Exemplary elements of the processor core 104(0) are illustrated in more detail. For example... Figure 1 As seen, the processor core 104(0) includes a plurality of functional units 126(0)-126(F), each of which includes circuitry for performing a specific subset of operations or functions for the processor core 104(0) in response to instructions (not shown) executed by the processor core 104(0). As a non-limiting example, functional units 126(0)-126(F) may include an integer execution unit (IXU) configured to perform integer operations, a vector execution unit (VXU) configured to perform vector operations, an arithmetic logic unit (ALU) configured to perform logical operations, and so on.

[0030] Figure 1 The processor device 100 may encompass any of the known digital logic elements, semiconductor circuits, processing cores, and / or memory structures, as well as other elements or combinations thereof. The aspects described herein are not limited to any particular arrangement of elements, and the disclosed techniques can be readily extended to various structures and layouts on semiconductor dies or packages. It should be understood that some aspects of the processor device 100, core cluster 102(0), and / or processor cores 104(0)-104(C) may include, in addition to… Figure 1 Components other than those exemplified, or substitutes Figure 1 The elements exemplified, and / or may include elements that are more than... Figure 1 The illustrated components may be more or fewer. For example, processor device 100 may also include cache, controller, communication bus and / or persistent storage devices, which, for clarity, are described in... Figure 1 The middle part is omitted.

[0031] As noted above, functional units 126(0)-126(F) tend to exhibit higher power density relative to other components of processor core 104(0). Depending on the type of workload performed by processor core 104(0), the power consumption of processor core 104(0) at a given time may be concentrated within specific units of functional units 126(0)-126(F). These points of higher power consumption create local “hot spots” (referred to herein as POIs, such as POI 128 within functional unit 126(0)) where the temperature is higher than other areas within processor core 104(0). Processor core 104(0) provides thermal sensors (in... Figure 1Thermal sensors 130(0)-130(1), labeled “TS”, are used to monitor the temperature at different locations within processor core 104(0). Temperature measurements provided by thermal sensors 130(0)-130(1) can be used by processor core 104(0) to mitigate the effects of high temperatures. However, the number and placement of thermal sensors 130(0)-130(1) within processor core 104(0) may not be optimal for monitoring temperatures at, for example, POI 128, potentially leading to significant discrepancies between temperature measurements at thermal sensors 130(0)-130(1) and the temperature at POI 128. Furthermore, the latency in obtaining temperature measurements from thermal sensors 130(0)-130(1) may pose challenges to the thermal management architecture compared to the potential rate of temperature increase.

[0032] In this regard, core cluster 102(0) provides cluster thermal management circuitry 132, which is configured to perform thermal management based on temperature evolution model 134. As discussed in more detail below, temperature evolution model 134 enables cluster thermal management circuitry 132 to inferentially determine the predicted temperature at POI 128 using temperature measurements from thermal sensors 130(0)-130(1) and power consumption measurements for processor core 104(0), and to perform appropriate thermal management operations (e.g., using clock throttling circuitry 124 and / or DVFS circuitry 122) if the predicted temperature exceeds a thermal mitigation threshold. Thus, cluster thermal management circuitry 132 is able to monitor and control the temperature at multiple locations within processor core 104(0) without requiring physical thermal sensors at each location, and can use thermal management operations to control the rapid evolution of temperature within the processor core. Specifically, the cluster thermal management circuit 132 can use the clock throttling circuit 124 to control the rapid increase in temperature, and can further use the DVFS circuit 122 for slower but more efficient temperature management.

[0033] To illustrate the use of temperature evolution model 134 for performing thermal management Figure 1 Exemplary elements of the cluster thermal management circuit 132 and the information flow to and from the cluster thermal management circuit provide Figure 2 .like Figure 2 As seen, in some aspects, the temperature evolution model 134 may include a multiple-input multiple-output (MIMO) model, which includes a transfer function model (in... Figure 2 The transfer function model 200 is labeled as "transfer function model" 200 and gradient model 202. In this respect, the transfer function model 200 may include: multiple inputs (not shown), each of which represents a functional unit (such as...). Figure 1The functional units 126(0)-126(F) measure the silicon front power consumption; and multiple outputs (not shown), each of which represents the power consumption measured by a thermal sensor (such as...). Figure 1 The temperature measurements were performed at the silicon front by thermal sensors 130(0)-130(1). A transfer function model 200 was configured to model the temperature evolution at each of the thermal sensors 130(0)-130(1) based on the power consumed by each of the functional units 126(0)-126(F). A gradient model 202 was then configured to model the temperature change between each of the thermal sensors 130(0)-130(1) and POI 128.

[0034] Tables 1 and 2 below illustrate exemplary transfer function model 200 and exemplary gradient model 202, respectively, which together constitute temperature evolution model 134. In the example of Table 1, each transfer function includes a three (3)-input two (2)-output model, which represents the temperature (T) evolution at the location of a thermal sensor associated with each of the two (2) functional units of the processor core (IXU and VXU in this example). The temperature evolution is modeled based on the power (P) injected into the IXU and VXU and the power injected into the rest of the processor core. Each transfer function in the example of Table 1 may have three (3) poles and six (6) zeros.

[0035] The gradient model 202 in the example in Table 2 also includes a three (3) input two (2) output model, which represents the temperature gradient from each thermal sensor associated with the IXU and DXU and the hot spot (HS) within each of the TXU and VXU, thus taking into account the power distribution in the IXU, VXU and the rest of the processor core.

[0036] The models illustrated in Tables 1 and 2 can be constructed using pre-silicon thermal simulation data and are not expected to vary in actual processor cores, as the models will only focus on the small time constant evolution of temperature (e.g., approximately five (5) milliseconds to 10 milliseconds). In some respects, the temperature evolution model 134, including the transfer function model 200 and the gradient model 202, can be integrated into the firmware 204 of the cluster thermal management circuitry 132 of the core cluster 102 (0).

[0037] Continue to refer to Figure 2 In the exemplary operation, the cluster thermal management circuit 132 receives data for... Figure 1 One or more power consumption measurements of one or more of the corresponding functional units 126(0)-126(F) (in Figure 2 The power rating is labeled as 206(0)-206(F). The cluster thermal management circuit 132 also receives power from... Figure 1 One or more temperature measurements performed by one or more of the corresponding thermal sensors 130(0)-130(1) (in Figure 2 The thermal sensors, labeled “temperature”, are located outside POI 128 (0)-208 (1). The cluster thermal management circuit 132 then generates a predicted temperature at POI 128 based on the temperature evolution model 134. Figure 2 The temperature evolution model, labeled "predicted temperature" 210, correlates one or more power consumption measurements 206(0)-206(F) (collectively referred to as "power consumption measurement 206") and one or more temperature measurements 208(0)-208(1) with the predicted temperature 210 at POI 128. The cluster thermal management circuit 132 determines that the predicted temperature 210 at POI 128 exceeds the thermal mitigation threshold 212. In response to determining that the predicted temperature 210 at POI 128 exceeds the thermal mitigation threshold 212, the cluster thermal management circuit 132 performs thermal management operations.

[0038] In some aspects, generating the predicted temperature 210 at POI 128 may include cluster thermal management circuitry 132 using temperature evolution model 134 to generate a first model 214 representing the temperature at the thermal sensors among one or more thermal sensors 130(0)-130(1). Cluster thermal management circuitry 132 also uses temperature evolution model 134 and the first model 214 to generate a second model 216 representing the temperature at POI 128. The first model 214 and the second model 216 may each depend on power dissipation within functional units 126(0)-126(F) of processor core 104(0) and on propagation impedance from across the cluster, which may introduce errors into the model. Furthermore, cluster thermal management circuitry 132 uses temperature evolution model 134 to generate a third model 218 representing boundary conditions.

[0039] Table 3 below illustrates an exemplary first model 214 according to some aspects, and the items used in the first model 214 are defined in Table 4 below:

[0040] Note that in Table 3, part of the first equation before the second addition sign (+) describes the power dissipated within the core cluster, while the remainder represents the error due to cross-cluster propagation and inaccuracies in power estimation. The second equation in Table 3 uses only the information available to the core cluster to estimate the temperature of sensor s at time k.

[0041] Table 5 below illustrates an exemplary second model 216 according to some aspects, and the items used in the second model 216 are defined in Table 6 below:

[0042] Continue to refer to Figure 2 In some aspects, performing thermal management operations may include cluster thermal management circuitry 132 employing clock throttling circuitry 124 to perform thermal management. In these aspects, clock throttling circuitry 124 is able to control rapid temperature rises more quickly than DVFS circuitry 122 (but the linear power reduction caused by using clock throttling circuitry 124 is less efficient than the power reduction caused by using DVFS circuitry 122). Such aspects may provide that cluster thermal management circuitry 132 performs thermal management operations by first calculating a power threshold 220 for processor core 104(0) using temperature evolution model 134. Power threshold 220 represents the maximum power that processor core 104(0) can consume without exceeding thermal mitigation threshold 212. Then, cluster thermal management circuitry 132 determines whether the current power consumption 222 of processor core 104(0) exceeds power threshold 220. If so, the cluster thermal management circuit 132 identifies a target clock throttling level 224 that is lower than the current clock throttling level 226 of the core cluster 102(0) and sends the target clock throttling level 224 to the clock throttling circuit 124. The clock throttling circuit 124 then performs clock throttling in a normal manner, which has the effect of reducing the temperature of the processor core 104(0) at POI 128.

[0043] In some of these respects, the power threshold 220 may use a thermal mitigation threshold 212 (hereinafter referred to as...) The thermal model was calculated. Because the thermal model is based on the unit power within the cluster, and the power threshold 220 is cluster-based, it is assumed that... ,in It is determined based on previous measurements of the total core power of processor core c and the unit power of unit i.

[0044] Then, the thermal model includes the optimization problem of P_budget(k, core c = 1,2,3,4), as shown in Table 7 below:

[0045] Still referencing Figure 2In some respects, performing thermal management operations may include cluster thermal management circuitry 132 employing DVFS circuitry 122 to perform thermal management. As noted above, DVFS circuitry 122 provides slower but more efficient thermal management compared to clock throttling circuitry 124. Therefore, in some respects, cluster thermal management circuitry 132 may use temperature evolution model 134 to calculate one or more operating points 228 for core cluster 102(0). Calculating one or more operating points 228 may involve calculating cost function 230, which may employ a future temperature evolution filter (in... Figure 2 The filter 232 (labeled as "future temperature evolution filter") is used to predict future temperature evolution. Then, the cluster thermal management circuit 132 uses a cost function 230 to generate a frequency changing strategy 234.

[0046] Subsequently, the cluster thermal management circuit 132 can perform thermal management operations by selecting a target operating point 236 from one or more operating points 228 (e.g., based on frequency change strategy 234), where the target operating point 236 is lower than the current operating point 238 for the core cluster 102(0). The cluster thermal management circuit 132 then sends the target operating point 236 to the DVFS circuit 122, which sets the voltage and frequency for the core cluster 102(0) in a conventional manner based on the target operating point 236.

[0047] One challenge of using the DVFS circuit 122 in this way is that temperature measurements 208(0)-208(1) from thermal sensors 130(0)-130(1) may not be simultaneously available for the cluster thermal management circuit 132. Because the DVFS delay is variable and greater than the thermal sensor update delay, the history-based cost function is purely reactive and may lead to inefficiency due to the large delays in the application. Therefore, in some respects, the cost function 230 may include the functions illustrated below in Table 8, with related terms defined in Table 9. The goal of this approach is to utilize faster power telemetry (e.g., ...) when optimizing costs. Figure 2 The power consumption is measured by 206(0)-206(F) instead of the slower temperature sensor telemetry (e.g., temperature measurement 208(0)-208(1)).

[0048] It should be noted that the cost function in Table 8 can have both causal and look-ahead contributions. A look-ahead contribution can be achieved by assuming f>=1. This look-ahead requires a dynamic cost (CDYN) forecasting model, which will be discussed in more detail below. It should also be noted that the look-ahead range is based on the expected DVFS delay of DVFS circuit 122.

[0049] Some aspects may be provided: the operation performed by the cluster thermal management circuit 132 to select the target operating point 236 may include using the equations in Table 10 below to select the frequency for the core cluster 102(0).

[0050] Using the equations in Table 10, the cost function is minimized on a per-core basis and used to determine the core cluster frequency that optimizes the cost of this processor core. The minimum of the frequencies generated above is selected to generate the target cluster frequency, and thus the target operating point 236. Assume P i,c (k) represents the power consumed by the i-th unit of processor core c in the k-th instance (i.e., within the window [(k-1)T, kT] when running at voltage V and effective frequency F_eff). The equations in Table 11 below calculate the workload characteristics Cdyn of the i-th unit of the m-th core in the core cluster within the interval [k-1, k]. i,c (k). Plkg i,c (V, T) represents the leakage power of the i-th unit of the c-th processor core in the core cluster at V and T.

[0051] Cost(k, c) can be restructured into the equations in Table 12 below based on the optimization variable F (representing the DVFS frequency):

[0052] Here, voltage V = g(F), which represents the voltage / frequency curve of the core cluster, and the term... This represents the power contribution outside the optimization window. Note that the cost function is only a function of the processor core frequency, and further, the frequency optimization space is a finite number of points. The optimal solution can be selected by calculating the cost function for all operating points.

[0053] As noted above, active temperature management requires predicting future temperature evolution. However, future temperature evolution depends on the power dissipated in the core cluster and its adjacent core clusters in the future. Because this information is not known at a given time t, some aspects provide a future temperature evolution filter 232 to predict CDYN at future times based on past information. In this regard, some aspects can provide a future temperature evolution filter 232 that operates to predict CDYN and thus predict the corresponding temperature evolution. In such aspects, the future temperature evolution filter 232 can use a recursive least squares (RLS) formula. Knowing P(k) (the power consumed in the time interval [k-1, k]) and using the equations in Table 11 above to calculate CDYN, the predicted CDYN in the first look-ahead interval starting from time instance k can be calculated using the equations in Table 13 below:

[0054] Filters in Table 13 This represents the filter at time instance k. It is achieved by using a forgetting factor. The filter coefficients are derived by minimizing the quadratic error to reduce the contribution of past samples. In some respects, The values ​​are 0.9 and -(1), which improves stability but slows down adaptation.

[0055] The parameter update equations are provided in Table 14 below:

[0056] In the parameter update equation, This represents the adaptive gain, multiplied by the prior error.

[0057] To illustrate, based on some aspects, Figure 1 The processor device 100 performs exemplary operations for performing thermal management based on a temperature evolution model. Figures 3A to 3D A flowchart illustrating exemplary operation 300 is provided. For clarity, in the description... Figures 3A to 3D Referenced at the time Figure 1 and Figure 2 The components. It should be understood that, in some respects, some exemplary operations in exemplary operation 300 may be performed differently from the order illustrated herein and / or may be omitted.

[0058] Example operation 300 in Figure 3A The cluster thermal management circuitry, which begins in the core cluster of the processor device (e.g., Figure 1 The cluster thermal management circuit 132 of the core cluster 102(0) of the processor device 100 receives one or more functional units corresponding to the processor cores of the multiple processor cores of the core cluster 102(0). Figure 1 One or more power consumption measurements (such as those of functional units 126(0)-126(F) of processor core 104(0) in multiple processor cores 104(0)-104(C)) of processor core 104(0) Figure 2 Power consumption measurement 206 (box 302). Cluster thermal management circuit 132 also receives POIs (such as those from processor core 104(0) within the processor core 104(0)). Figure 1 One or more corresponding thermal sensors (e.g., POI 128) outside the POI 128 Figure 1 One or more temperature measurements (such as those performed by one or more thermal sensors 130(0)-130(1)) Figure 2 One or more temperature measurements 208(0)-208(1) (box 304).

[0059] Then, the cluster thermal management circuit 132 is based on a temperature evolution model (such as...) Figure 1 The temperature evolution model 134) is used to generate the predicted temperature at POI 128 (e.g., Figure 2 The temperature evolution model correlates one or more power consumption measurements 206 and one or more temperature measurements 208(0)-208(1) with the predicted temperature 210 at POI 128 (box 306). In some aspects, the operation of box 306 for generating the predicted temperature 210 at POI 128 may include cluster thermal management circuitry 132 using temperature evolution model 134 to generate a first model (such as...) representing the temperature at the thermal sensors among one or more thermal sensors 130(0)-130(1). Figure 2 The first model 214 (box 308). The cluster thermal management circuit 132 also uses the temperature evolution model 134 and the first model 214 to generate a second model representing the temperature at POI 128 (e.g., Figure 2 The second model 216 (box 310). Additionally, the cluster thermal management circuit 132 uses the temperature evolution model 134 to generate a third model representing the boundary conditions (such as...). Figure 2 The third model 218 (box 312). In some aspects, exemplary operation 300 may be available in Figure 3B Continue at frame 314.

[0060] Now for reference Figure 3B According to some exemplary aspects, operation 300 can continue, wherein cluster thermal management circuitry 132 uses temperature evolution model 134 to calculate one or more operating points (such as...) for core cluster 102(0). Figure 2 Operation point 228 (box 314). Some such aspects may be provided: the operations of box 314 for calculating one or more operation points 228 may include cluster thermal management circuitry 132 calculating a cost function (e.g., Figure 2The cost function 230 (box 316). In some aspects, the operations of box 316 for calculating the cost function 230 may include cluster thermal management circuitry 132 based on a future temperature evolution filter (such as... Figure 2 The future temperature evolution filter 232 is used to predict future temperature evolution (box 318). Then, the cluster thermal management circuit 132 can use the cost function 230 to generate a frequency changing strategy (e.g., Figure 2 The frequency change strategy 234 (box 320). The cluster thermal management circuit 132 determines that the predicted temperature 210 at POI 128 exceeds the thermal mitigation threshold (such as...). Figure 2 The thermal mitigation threshold 212 (box 322). Exemplary operation 300 then... Figure 3C Continue at frame 324.

[0061] Turn now Figure 3C Exemplary operation 300 continues, wherein cluster thermal management circuitry 132 performs thermal management operations (block 324) in response to determining that the predicted temperature 210 at POI 128 exceeds the thermal mitigation threshold 212. In some aspects, the operations of block 324 for performing the thermal management operations may include cluster thermal management circuitry 132 employing a clock throttling circuit (such as...) Figure 1 The clock throttling circuit 124) performs thermal management. In this respect, the cluster thermal management circuit 132 uses the temperature evolution model 134 to calculate the power threshold for the processor core 104(0) (e.g., Figure 2 The power threshold 220 represents the maximum power that the processor core 104(0) can consume without exceeding the thermal mitigation threshold 212 (box 326). Then, the cluster thermal management circuit 132 determines the current power consumption of the processor core 104(0) (such as the power threshold 220), where the power threshold 220 represents the maximum power that the processor core 104(0) can consume without exceeding the thermal mitigation threshold 212. Figure 2 Does the current power consumption (222) exceed the power threshold (box 328)?

[0062] If the cluster thermal management circuit 132 determines that the current power consumption 222 of the processor core 104(0) exceeds the power threshold 220, a series of operations are performed (box 330). The cluster thermal management circuit 132 identifies a current clock throttling level below the core cluster 102(0) (e.g., Figure 2 The target clock throttling level (e.g., the current clock throttling level 226) Figure 2 The target clock throttling level 224 (box 332) is then sent to the clock throttling circuit 124. The cluster thermal management circuit 132 then sends the target clock throttling level 224 (box 334). Exemplary operation 300 can be performed according to some aspects. Figure 3D Continue at frame 336.

[0063] Continue to refer to Figure 3D Some aspects may be provided: the operation of block 324 for performing thermal management operations may include cluster thermal management circuitry 132 employing DVFS circuitry (such as... Figure 1 The DVFS circuit 122 is used to perform thermal management. Accordingly, in this respect, the cluster thermal management circuit 132 can select a target operating point from one or more operating points 228 (e.g., Figure 2 The target operation point 236), where the target operation point 236 is lower than the current operation point for core cluster 102(0) (such as Figure 2 The current operating point 238 (box 336). In some aspects, the operation of selecting the target operating point 236 in box 336 may be based on a frequency-changing strategy 234 (box 338). Then, the cluster thermal management circuit 132 sends the target operating point 236 to the DVFS circuit 122 (box 340).

[0064] Based on the information disclosed in this article and referenced Figure 1 The processor devices discussed in these aspects can be located in or integrated into any processor-based device. Examples, without limitation, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0065] In this respect, Figure 4 Examples are given regarding Figure 1 An example of a processor-based device 400 illustrated and described. In this example, the processor-based device 400 includes a processor device 402, which functionally corresponds to Figure 1The processor device 100 includes one or more processor cores 404 coupled to cache memory 406. The processor cores 404 are also coupled to a system bus 408 and can interactively couple to devices included in the processor-based device 400. As is well known, the processor cores 404 communicate with these other devices by exchanging address, control, and data information on the system bus 408. For example, the processor cores 404 can communicate bus transaction requests to the memory controller 410. Although in Figure 4 Not illustrated, but multiple system buses 408 may be provided, each of which constitutes a different structure.

[0066] Other devices can be connected to system bus 408. For example... Figure 4 As illustrated, these devices may include a memory system 412, one or more input devices 414, one or more output devices 416, one or more network interface devices 418, and one or more display controllers 420. Input devices 414 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 416 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 418 may be any device configured to allow data exchange to and from network 422. Network 422 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. Network interface device 418 can be configured to support any type of communication protocol desired. Memory system 412 may include a memory controller 410 coupled to one or more memory arrays 424. Display controller may include, for example... Figure 1 GPU 106.

[0067] The processor core 404 can also be configured to access the display controller 420 via the system bus 408 to control the transmission of information to one or more displays 430. The display controller 420 transmits information to be displayed to the displays 430 via one or more video processors 432, which process the information to be displayed into a format suitable for the displays 430. The displays 430 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0068] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0069] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0070] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0071] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0072] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0073] Specific implementation examples are described in the following numbered clauses.

[0074] 1. A processor device, the processor device comprising: The core cluster includes: Multiple processor cores; and Cluster thermal management circuit; The cluster thermal management circuit is configured as follows: Receive one or more power consumption measurements for one or more functional units corresponding to a processor core among the plurality of processor cores; Receive one or more temperature measurements from one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; The predicted temperature at the POI is generated based on a temperature evolution model, which correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. Determine whether the predicted temperature at the POI exceeds the thermal mitigation threshold; and In response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold, a thermal management operation is performed.

[0075] 2. The processor device according to Clause 1, wherein the temperature evolution model comprises: The transfer function model includes: Multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and Multiple outputs, each of which represents a silicon front temperature measurement performed by one or more of the thermal sensors; The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit; and A gradient model is configured to model the temperature change between each thermal sensor and the POI.

[0076] 3. The processor device according to any one of Clauses 1 to 2, wherein the cluster thermal management circuitry includes firmware in which the temperature evolution model is integrated.

[0077] 4. The processor device according to any one of clauses 1 to 3, wherein the cluster thermal management circuitry is configured to generate the predicted temperature at the POI by being configured to: The temperature evolution model is used to generate a first model representing the temperature at the thermal sensor in one or more thermal sensors; The temperature evolution model and the first model are used to generate a second model representing the temperature at the POI; and The temperature evolution model is used to generate a third model representing the boundary conditions.

[0078] 5. The processor device according to any one of clauses 1 to 4, wherein: The core cluster also includes a clock throttling circuit; and The cluster thermal management circuit is configured to perform the thermal management operation by being configured to do the following: The temperature evolution model is used to calculate the power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. Determine whether the current power consumption of the processor core exceeds the power threshold; and In response to determining that the current power consumption of the processor core exceeds the power threshold: Identify the target clock throttling level, which is lower than the current clock throttling level of the core cluster; and The target clock throttling level is sent to the clock throttling circuit.

[0079] 6. The processor device according to any one of clauses 1 to 5, wherein: The core cluster also includes Dynamic Voltage and Frequency Scaling (DVFS) circuitry; and The cluster thermal management circuit is configured as follows: The temperature evolution model is used to calculate one or more operating points for the core cluster; and The thermal management operation is performed by being configured to do the following: Select a target operation point from the one or more operation points, wherein the target operation point is lower than the current operation point for the core cluster; and The target operation point is sent to the DVFS circuit.

[0080] 7. The processor device according to Clause 6, wherein: The cluster thermal management circuit is configured to calculate one or more operating points for the core cluster by performing the following: Calculate the cost function; and The cost function is used to generate a frequency-changing strategy; and The cluster thermal management circuit is configured to select the target operating point from the one or more operating points based on the frequency changing strategy.

[0081] 8. The processor device according to Clause 7, wherein the cluster thermal management circuitry is configured to calculate the cost function by being configured to predict future temperature evolution based on a future temperature evolution filter.

[0082] 9. The processor device according to any one of Clauses 1 to 8, wherein the processor device is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0083] 10. A processor device, the processor device comprising: A component for receiving one or more power consumption measurements of one or more functional units corresponding to a processor core in a core cluster of the processor device. A component for receiving one or more temperature measurements taken by one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; Components for generating a predicted temperature at the POI based on a temperature evolution model, the temperature evolution model relating the one or more power consumption measurements and the one or more temperature measurements to the predicted temperature at the POI; Components for determining whether the predicted temperature at the POI exceeds the thermal mitigation threshold; and A component for performing thermal management operations in response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold.

[0084] 11. A method for performing thermal management based on a temperature evolution model in a processor device, the method comprising: One or more power consumption measurements are determined by the cluster thermal management circuitry of the core cluster of the processor device for one or more functional units corresponding to a processor core among the multiple processor cores of the core cluster. The cluster thermal management circuit determines one or more temperature measurements taken by one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; The cluster thermal management circuit generates a predicted temperature at the POI based on a temperature evolution model, which correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The cluster thermal management circuit determines that the predicted temperature at the POI exceeds the thermal mitigation threshold; and In response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold, the cluster thermal management circuitry performs a thermal management operation.

[0085] 12. The method according to Clause 11, wherein the temperature evolution model comprises: The transfer function model includes: Multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and Multiple outputs, each of which represents a silicon front temperature measurement performed by one or more of the thermal sensors; The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit; and A gradient model is configured to model the temperature change between each thermal sensor and the POI.

[0086] 13. The method according to any one of clauses 11 to 12, wherein the cluster thermal management circuit includes firmware in which the temperature evolution model is integrated.

[0087] 14. The method according to any one of clauses 11 to 13, wherein generating the predicted temperature at the POI comprises: The temperature evolution model is used to generate a first model representing the temperature at the thermal sensor in one or more thermal sensors; The temperature evolution model and the first model are used to generate a second model representing the temperature at the POI; and The temperature evolution model is used to generate a third model representing the boundary conditions.

[0088] 15. The method according to any one of clauses 11 to 14, wherein: The core cluster includes a clock throttling circuit; and Performing the thermal management operation includes: The temperature evolution model is used to calculate the power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. Determining that the current power consumption of the processor core exceeds the power threshold; and In response to determining that the current power consumption of the processor core exceeds the power threshold: Identify the target clock throttling level, which is lower than the current clock throttling level of the core cluster; and The target clock throttling level is sent to the clock throttling circuit.

[0089] 16. The method according to any one of clauses 11 to 15, wherein: The core cluster includes dynamic voltage and frequency scaling (DVFS) circuitry; The method further includes using the temperature evolution model to calculate one or more operating points for the core cluster; and Performing the thermal management operation includes: Select a target operation point from the one or more operation points, wherein the target operation point is lower than the current operation point for the core cluster; and The target operation point is sent to the DVFS circuit.

[0090] 17. The method according to Clause 16, wherein: Calculating the one or more operation points for the core cluster includes: Calculate the cost function; and The cost function is used to generate a frequency-changing strategy; and Select the target operation point from the one or more operation points and change the strategy based on the frequency.

[0091] 18. The method according to Clause 17, wherein calculating the cost function includes predicting future temperature evolution based on a future temperature evolution filter.

[0092] 19. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed, cause a processor device of a processor-based device to: Receive one or more power consumption measurements for one or more functional units corresponding to a processor core in a plurality of processor cores of the core cluster of the processor device; Receive one or more temperature measurements from one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; The predicted temperature at the POI is generated based on a temperature evolution model, which correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. Determine whether the predicted temperature at the POI exceeds the thermal mitigation threshold; and In response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold, a thermal management operation is performed.

[0093] 20. The non-transitory computer-readable medium according to Clause 19, wherein the temperature evolution model comprises: The transfer function model includes: Multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and Multiple outputs, each of which represents a silicon front temperature measurement performed by one or more of the thermal sensors; The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit; and A gradient model is configured to model the temperature change between each thermal sensor and the POI.

[0094] 21. A non-transitory computer-readable medium according to any one of clauses 19 to 20, wherein the computer-executable instructions cause the processor device to generate the predicted temperature at the POI by causing the processor device to perform the following: The temperature evolution model is used to generate a first model representing the temperature at the thermal sensor in one or more thermal sensors; The temperature evolution model and the first model are used to generate a second model representing the temperature at the POI; and The temperature evolution model is used to generate a third model representing the boundary conditions.

[0095] 22. A non-transitory computer-readable medium according to any one of clauses 19 to 21, wherein: The core cluster includes a clock throttling circuit; and The computer-executable instructions cause the processor device to perform the thermal management operation by causing the processor device to do the following: The temperature evolution model is used to calculate the power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. Determine whether the current power consumption of the processor core exceeds the power threshold; and In response to determining that the current power consumption of the processor core exceeds the power threshold: Identify the target clock throttling level, which is lower than the current clock throttling level of the core cluster; and The target clock throttling level is sent to the clock throttling circuit.

[0096] 23. A non-transitory computer-readable medium according to any one of clauses 19 to 22, wherein: The core cluster includes dynamic voltage and frequency scaling (DVFS) circuitry; The computer-executable instructions further cause the processor device to use the temperature evolution model to calculate one or more operating points for the core cluster; and The computer-executable instructions cause the processor device to perform the thermal management operation by causing the processor device to do the following: Select a target operation point from the one or more operation points, wherein the target operation point is lower than the current operation point for the core cluster; and The target operation point is sent to the DVFS circuit.

[0097] 24. The non-transitory computer-readable medium as described in Clause 23, wherein: The computer-executable instructions cause the processor device to compute the one or more operation points for the core cluster by causing the processor device to perform the following: Calculate the cost function; and The cost function is used to generate a frequency-changing strategy; and The computer-executable instructions cause the processor device to select the target operating point from the one or more operating points based on the frequency changing strategy.

[0098] 25. The non-transitory computer-readable medium according to Clause 24, wherein the computer-executable instructions cause the processor device to compute the cost function by causing the processor device to predict future temperature evolution based on a future temperature evolution filter.

Claims

1. A processor device, the processor device comprising: The core cluster includes: Multiple processor cores; and Cluster thermal management circuit; The cluster thermal management circuit is configured as follows: Receive one or more power consumption measurements for one or more functional units corresponding to a processor core among the plurality of processor cores; Receive one or more temperature measurements from one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; The predicted temperature at the POI is generated based on a temperature evolution model, which correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. Determine whether the predicted temperature at the POI exceeds the thermal mitigation threshold; and In response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold, a thermal management operation is performed.

2. The processor device according to claim 1, wherein the temperature evolution model comprises: The transfer function model includes: Multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and Multiple outputs, each of which represents a silicon front temperature measurement performed by one or more of the thermal sensors; The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit; and A gradient model is configured to model the temperature change between each thermal sensor and the POI.

3. The processor device of claim 1, wherein the cluster thermal management circuitry includes firmware in which the temperature evolution model is integrated.

4. The processor device of claim 1, wherein the cluster thermal management circuitry is configured to generate the predicted temperature at the POI by being configured to perform the following: The temperature evolution model is used to generate a first model representing the temperature at the thermal sensor in one or more thermal sensors; The temperature evolution model and the first model are used to generate a second model representing the temperature at the POI; and The temperature evolution model is used to generate a third model representing the boundary conditions.

5. The processor device according to claim 1, wherein: The core cluster also includes a clock throttling circuit; and The cluster thermal management circuit is configured to perform the thermal management operation by being configured to do the following: The temperature evolution model is used to calculate the power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. Determine whether the current power consumption of the processor core exceeds the power threshold; as well as In response to determining that the current power consumption of the processor core exceeds the power threshold: Identify the target clock throttling level, which is lower than the current clock throttling level of the core cluster; and The target clock throttling level is sent to the clock throttling circuit.

6. The processor device according to claim 1, wherein: The core cluster also includes Dynamic Voltage and Frequency Scaling (DVFS) circuitry; and The cluster thermal management circuit is configured as follows: The temperature evolution model is used to calculate one or more operation points for the core cluster; as well as The thermal management operation is performed by being configured to do the following: Select a target operation point from the one or more operation points, wherein the target operation point is lower than the current operation point for the core cluster; as well as The target operation point is sent to the DVFS circuit.

7. The processor device according to claim 6, wherein: The cluster thermal management circuit is configured to calculate one or more operating points for the core cluster by performing the following: Calculate the cost function; as well as Use the aforementioned cost function to generate a frequency-changing strategy; and The cluster thermal management circuit is configured to select the target operating point from the one or more operating points based on the frequency changing strategy.

8. The processor device of claim 7, wherein the cluster thermal management circuitry is configured to calculate the cost function by being configured to predict future temperature evolution based on a future temperature evolution filter.

9. The processor device of claim 1, wherein the processor device is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

10. A processor device, the processor device comprising: A component for receiving one or more power consumption measurements of one or more functional units corresponding to a processor core in a core cluster of the processor device. A component for receiving one or more temperature measurements taken by one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; Components for generating a predicted temperature at the POI based on a temperature evolution model, the temperature evolution model relating the one or more power consumption measurements and the one or more temperature measurements to the predicted temperature at the POI; Components used to determine whether the predicted temperature at the POI exceeds the thermal mitigation threshold; as well as A component for performing thermal management operations in response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold.

11. A method for performing thermal management based on a temperature evolution model in a processor device, the method comprising: One or more power consumption measurements are determined by the cluster thermal management circuitry of the core cluster of the processor device for one or more functional units corresponding to the processor cores among the multiple processor cores of the core cluster. The cluster thermal management circuit determines one or more temperature measurements taken by one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; The cluster thermal management circuit generates a predicted temperature at the POI based on a temperature evolution model, which correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. The cluster thermal management circuit determines that the predicted temperature at the POI exceeds the thermal mitigation threshold; as well as In response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold, the cluster thermal management circuitry performs a thermal management operation.

12. The method of claim 11, wherein the temperature evolution model comprises: The transfer function model includes: Multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and Multiple outputs, each of which represents a silicon front temperature measurement performed by one or more of the thermal sensors; The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit; and A gradient model is configured to model the temperature change between each thermal sensor and the POI.

13. The method of claim 11, wherein the cluster thermal management circuit includes firmware in which the temperature evolution model is integrated.

14. The method of claim 11, wherein generating the predicted temperature at the POI comprises: The temperature evolution model is used to generate a first model representing the temperature at the thermal sensor in one or more thermal sensors; The temperature evolution model and the first model are used to generate a second model representing the temperature at the POI; as well as The temperature evolution model is used to generate a third model representing the boundary conditions.

15. The method of claim 11, wherein: The core cluster includes a clock throttling circuit; and Performing the thermal management operation includes: The temperature evolution model is used to calculate the power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. Determining that the current power consumption of the processor core exceeds the power threshold; and In response to determining that the current power consumption of the processor core exceeds the power threshold: Identify the target clock throttling level, which is lower than the current clock throttling level of the core cluster; and The target clock throttling level is sent to the clock throttling circuit.

16. The method of claim 11, wherein: The core cluster includes dynamic voltage and frequency scaling (DVFS) circuitry; The method also includes using the temperature evolution model to calculate one or more operating points for the core cluster; and Performing the thermal management operation includes: Select a target operation point from the one or more operation points, wherein the target operation point is lower than the current operation point for the core cluster; as well as The target operation point is sent to the DVFS circuit.

17. The method of claim 16, wherein: Calculating the one or more operation points for the core cluster includes: Calculate the cost function; and The cost function is used to generate a frequency-changing strategy; and Select the target operation point from the one or more operation points and change the strategy based on the frequency.

18. The method of claim 17, wherein calculating the cost function includes predicting future temperature evolution based on a future temperature evolution filter.

19. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed, cause a processor device of a processor-based device to: Receive one or more power consumption measurements for one or more functional units corresponding to a processor core in a plurality of processor cores of the core cluster of the processor device; Receive one or more temperature measurements from one or more corresponding thermal sensors outside the point of interest (POI) within the processor core; The predicted temperature at the POI is generated based on a temperature evolution model, which correlates the one or more power consumption measurements and the one or more temperature measurements with the predicted temperature at the POI. Determine whether the predicted temperature at the POI exceeds the thermal mitigation threshold; as well as In response to determining that the predicted temperature at the POI exceeds the thermal mitigation threshold, a thermal management operation is performed.

20. The non-transitory computer-readable medium of claim 19, wherein the temperature evolution model comprises: The transfer function model includes: Multiple inputs, each representing a pre-silicon power consumption measurement of a functional unit among the one or more functional units; and Multiple outputs, each of which represents a silicon front temperature measurement performed by one or more of the thermal sensors; The transfer function model is configured to model the temperature evolution at each thermal sensor based on the power consumed by each functional unit; and A gradient model is configured to model the temperature change between each thermal sensor and the POI.

21. The non-transitory computer-readable medium of claim 19, wherein the computer-executable instructions cause the processor device to generate the predicted temperature at the POI by causing the processor device to perform the following: The temperature evolution model is used to generate a first model representing the temperature at the thermal sensor in one or more thermal sensors; The temperature evolution model and the first model are used to generate a second model representing the temperature at the POI; and The temperature evolution model is used to generate a third model representing the boundary conditions.

22. The non-transitory computer-readable medium according to claim 19, wherein: The core cluster includes a clock throttling circuit; and The computer-executable instructions cause the processor device to perform the thermal management operation by causing the processor device to do the following: The temperature evolution model is used to calculate the power threshold for the processor core, where the power threshold represents the maximum power that the processor core can consume without exceeding the thermal mitigation threshold. Determine whether the current power consumption of the processor core exceeds the power threshold; as well as In response to determining that the current power consumption of the processor core exceeds the power threshold: Identify the target clock throttling level, which is lower than the current clock throttling level of the core cluster; and The target clock throttling level is sent to the clock throttling circuit.

23. The non-transitory computer-readable medium according to claim 19, wherein: The core cluster includes dynamic voltage and frequency scaling (DVFS) circuitry; The computer-executable instructions further cause the processor device to use the temperature evolution model to calculate one or more operating points for the core cluster; and The computer-executable instructions cause the processor device to perform the thermal management operation by causing the processor device to do the following: Select a target operation point from the one or more operation points, wherein the target operation point is lower than the current operation point for the core cluster; as well as The target operation point is sent to the DVFS circuit.

24. The non-transitory computer-readable medium according to claim 23, wherein: The computer-executable instructions cause the processor device to compute the one or more operation points for the core cluster by causing the processor device to perform the following: Calculate the cost function; as well as Use the aforementioned cost function to generate a frequency-changing strategy; and The computer-executable instructions cause the processor device to select the target operating point from the one or more operating points based on the frequency changing strategy.

25. The non-transitory computer-readable medium of claim 24, wherein the computer-executable instructions cause the processor device to compute the cost function by causing the processor device to predict future temperature evolution based on a future temperature evolution filter.

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