Configurable pmic device with micro-integrated array of voltage regulation cells and shared programmable reference

Abstract

This application relates to providing rail voltage for an electronic system. The electronic system includes an array of voltage regulator units and multiple reference circuits. The voltage regulator unit array is configured to provide multiple sets of voltage regulators, each set of voltage regulators being configured to output a corresponding rail voltage to a corresponding power rail among a plurality of power rails. The multiple reference circuits are coupled to the voltage regulator unit array. Each reference circuit is shared by one or more corresponding voltage regulator units of a corresponding set of voltage regulators and is configured to provide a corresponding reference voltage to the one or more corresponding voltage regulator units. The corresponding set of voltage regulators is configured to generate the corresponding rail voltage based on the corresponding reference voltage.

Description

[0001] Related applications This application is a continuation of and claims priority to U.S. Patent Application No. 18 / 919,345, filed October 17, 2024, entitled “Apparatus of Configurable PMIC with Array of MicroIntegrated Voltage Regulation Cells and Shared Programmable References,” which claims the benefit of U.S. Provisional Patent Application No. 63 / 592,109, filed October 20, 2023, entitled “Apparatus of Configurable PMIC with Array of MicroIntegrated Voltage Regulation Cells and Shared Programmable References,” which is incorporated herein by reference in its entirety. Technical Field

[0002] This application generally relates to power management of electronic systems, including but not limited to methods, systems, apparatus, and integrated circuits for providing rail voltage to drive the power rails of electronic systems. Background Technology

[0003] A System-on-a-Chip (SoC) integrates multiple computer components, such as processors, memory, input / output interfaces, and various peripherals, onto a substrate. SoCs are widely used in modern electronic devices, including smartphones, tablets, and embedded systems, where space, power efficiency, and performance are critical. To manage the complex power requirements of these components, power management integrated circuits (PMICs) are employed. The PMIC is responsible for regulating, distributing, and controlling the power delivered to the various subsystems of the SoC. It effectively manages multiple voltage levels, enabling features such as dynamic voltage scaling to conserve energy and ensure the SoC operates within its optimal power and thermal limits. Together, the SoC and PMIC form a highly efficient system capable of handling a variety of tasks with minimal power consumption, making it essential in today's compact, high-performance devices. However, PMICs used with SoCs can face challenges in consistency between different power rails and stability within individual power rails. Consistency issues arise when different power rails fail to deliver uniform voltage levels or are not correctly sequenced, leading to performance variations or even failures within the SoC. This can be caused by mismatched regulation circuitry, varying load demands, or poor coordination between multiple power rails. On the other hand, stability issues can affect individual power rails, where voltage fluctuations, oscillations, or noise occur within a single rail. These issues can cause intermittent faults, timing errors, or performance degradation in the SoC. Summary of the Invention

[0004] Based on at least some embodiments disclosed herein, it is recognized that a System-on-a-Chip (SoC) requires consistent and reliable power delivery across its power rails. Each power rail delivers its rail voltage consistently, and different power rails providing the same rail voltage may need to be consistent with each other. Various embodiments of this application relate to methods, systems, apparatus, and integrated circuits for generating one or more rail voltages to power multiple power rails using a configurable power management integrated circuit (PMIC) with one or more integrated reference circuits. The configurable PMIC includes an array of micro-integrated voltage regulator cells. A subset of the voltage regulator cells may be selected and grouped to act as power sources driving the power rails. The selected voltage regulator cells are driven by the same reference circuit. In some embodiments, the voltage regulator cells of the PMIC are grouped to form multiple power sources, for example, each of which outputs a programmable rail voltage, and a subset of the voltage regulator cells corresponding to each respective power source is driven by a corresponding common reference circuit.

[0005] In one aspect, an electronic system includes: an array of voltage regulator units; and a plurality of reference circuits coupled to the voltage regulator unit array. The voltage regulator unit array is configured to provide a plurality of voltage regulator sets. Each voltage regulator set is configured to output a corresponding rail voltage and provide the corresponding rail voltage to a corresponding power rail among a plurality of power rails. Each of the plurality of reference circuits is shared by one or more corresponding voltage regulator units of the corresponding voltage regulator set and is configured to provide a corresponding reference voltage to the one or more corresponding voltage regulator units, and the corresponding voltage regulator set is configured to generate the corresponding rail voltage based on the corresponding reference voltage.

[0006] In another aspect, an apparatus includes: a plurality of power rails configured to provide one or more rail voltages; an array of voltage regulator units coupled to the plurality of power rails; and a plurality of reference circuits coupled to the array of voltage regulator units. The array of voltage regulator units is configured to provide a plurality of voltage regulator sets, each voltage regulator set being configured to output a corresponding rail voltage to a corresponding power rail. Each of the plurality of reference circuits is shared by one or more corresponding voltage regulator units of a corresponding voltage regulator set and is configured to provide a corresponding reference voltage to the one or more corresponding voltage regulator units, and the corresponding voltage regulator set is configured to generate the corresponding rail voltage based on the corresponding reference voltage.

[0007] In another aspect, a method is implemented for providing rail voltage to an electronic system (e.g., driving a processor or memory module). The method includes grouping voltage regulator units in an array of voltage regulator units to provide a plurality of voltage regulator sets. The method further includes: for each of the plurality of voltage regulator sets, generating a corresponding reference voltage by a corresponding entity in a plurality of reference circuits, wherein the corresponding entity in the plurality of reference circuits is shared by one or more corresponding voltage regulator units of the corresponding voltage regulator set. The method further includes: for each voltage regulator set, generating a corresponding rail voltage based on the corresponding reference voltage and providing the corresponding rail voltage to drive a corresponding entity in a plurality of power rails.

[0008] These illustrative embodiments are mentioned not to limit or restrict the scope of this disclosure, but to provide examples to aid in understanding it. Additional embodiments are discussed in the embodiments and are further described herein. Attached Figure Description

[0009] To better understand the various described implementation schemes, the following diagrams should be used in conjunction with the implementation methods, where the diagrams are consistent with each other and similar reference numerals indicate the corresponding parts.

[0010] Figure 1 Here is a block diagram of an example electronic system based on some implementation schemes.

[0011] Figure 2A and Figure 2B These are top and bottom perspective views of an example electronic system including a SoC, according to some implementation schemes.

[0012] Figure 3A and Figure 3B These are, respectively, top and bottom perspective views of another example electronic system according to some implementation schemes.

[0013] Figure 4A This is a high-order block diagram of an example PMIC module based on some implementation schemes, and Figure 4B This is a detailed block diagram of an example PMIC module based on some implementation schemes.

[0014] Figure 5 This is a schematic diagram of an example voltage regulator unit based on some implementation schemes.

[0015] Figure 6 To illustrate the method for providing rail voltage V according to some implementation schemes RAIL Two example voltage regulator units (also shown in) Figure 4B (Concept diagram of the Chinese version)

[0016] Figure 7AA perspective view of an example PMIC chip including multiple inductors coupled to multiple voltage regulator units according to some implementation schemes.

[0017] Figure 7B and Figure 7C According to some implementation plans Figure 7A The image shows two cross-sectional views of a portion of a PMIC chip, including two inductors and two voltage regulator units.

[0018] Figure 8 This is a flowchart of an example method for providing rail voltage to an electronic system according to some implementation schemes.

[0019] Several views are shown throughout the diagram, and similar labels indicate the corresponding parts. Detailed Implementation

[0020] Specific embodiments will now be described in detail with reference to the accompanying drawings. Numerous non-limiting specific details are set forth in the following detailed description to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternatives may be used without departing from the scope of the claims, and that the subject matter may be practiced without these specific details. For example, it will be apparent to those skilled in the art that the subject matter presented herein can be implemented in many types of electronic devices with storage capabilities.

[0021] Based on at least some embodiments disclosed herein, it is recognized that a System-on-a-Chip (SoC) requires consistent and reliable power delivery across its power rails. Each power rail delivers its rail voltage consistently, and different power rails providing the same rail voltage may need to be consistent with each other. Various embodiments of this application relate to methods, systems, apparatus, and integrated circuits for generating one or more rail voltages to power multiple power rails using a configurable power management integrated circuit (PMIC) with one or more integrated reference circuits. The configurable PMIC includes an array of micro-integrated voltage regulator cells. A subset of the voltage regulator cells may be selected and grouped to act as power sources driving the power rails. The selected voltage regulator cells are driven by the same reference circuit. In some embodiments, the voltage regulator cells of the PMIC are grouped to form multiple power sources, for example, each of which outputs a programmable rail voltage, and a subset of the voltage regulator cells corresponding to each respective power source is driven by a corresponding common reference circuit.

[0022] Based on at least some of the embodiments disclosed herein, it is recognized that the challenge of grouping a set of voltage regulator units, when each voltage regulator unit has a corresponding regulation control loop, lies in the load current balancing (or sharing) among the voltage regulator units. In other words, two voltage regulator units providing different output voltages and experiencing load current imbalances can potentially cause the power rails coupled to these two voltage regulator units to fail and permanently damage the electronic components powered by the power rails.

[0023] To overcome this problem, a reference circuit is shared among a group of voltage regulator units coupled to the same power rail. The output voltage of each voltage regulator unit tracks a corresponding reference voltage provided by the shared reference circuit. In some embodiments, a digital-to-analog converter (DAC) provides the reference voltage, which may be offset based on various factors (e.g., location, manufacturing conditions), even when the DAC is programmed with fixed digital input data. When the DAC is applied within a reference voltage source driving multiple voltage regulator units coupled to the same power rail, the reference voltage is jointly offset for the voltage regulator units coupled to the same power rail, thereby ensuring that these voltage regulator units perform uniformly and remain balanced with each other. In some embodiments, the DAC array is coupled to a reference voltage distribution bus and a switch array and configured to provide a common voltage reference to a group of voltage regulator units that output the same rail voltage. Each voltage regulator unit does not have its own independent DAC, thus eliminating the current imbalance problem caused by differences between independent DACs.

[0024] Figure 1 This is a block diagram of an example electronic system 100 according to some embodiments. Electronic system 100 includes at least one processor module 102, a memory module 104, an input / output (I / O) interface 106, one or more communication interfaces such as a network interface 108, and one or more communication buses 110 for interconnecting these components. In some embodiments, the I / O interface 106 allows the processor module 102 to communicate with I / O devices (e.g., a keyboard, mouse, or touchpad). The I / O interface 106 may conform to data communication bus standards, including but not limited to Universal Serial Bus (USB) and Peripheral Component Interconnect High Speed ​​(PCIe). In some embodiments, one or more communication buses 110 include circuitry (sometimes referred to as chipsets) that interconnects and controls communication between the various system components included in electronic system 100. In some embodiments, electronic system 100 further includes other dedicated hardware (e.g., radio, graphics card, sound card, sensors).

[0025] In some embodiments, electronic system 100 further includes a PMIC module 112 configured to receive an input supply voltage 114. PMIC module 112 is configured to modulate the received input supply voltage 114 to a desired DC voltage level, such as 5V, 3.3V, or 1.8V, as needed by various components or circuits within electronic system 100 (e.g., processor module 102). For example, PMIC module 112 is configured to generate DC voltage levels at a plurality of power rails 116 for supplying power to other components in electronic system 100 (e.g., components 102 to 110). Examples of the plurality of power rails 116 include, but are not limited to: one or more GPU power rails 116A, one or more CPU power rails 116B, one or more network connection power rails 116C, one or more memory interface power rails 116D, and one or more memory module power rails 116E. In some implementations, the PMIC module 112 further includes a layer within a printed circuit board (PCB) or integrated circuit (IC), and said layer is used as an input power plane for distributing the input supply voltage 114.

[0026] In some implementations, electronic system 100 corresponds to SoC 120. Different components of electronic system 100 may be formed on two or more integrated circuits distributed on two or more chips, which are further mounted on a single substrate of SoC 120 (e.g., Figure 2A On substrate 202). Alternatively, in some embodiments, different components of the electronic system 100 are included in integrated circuits formed on a single substrate of the SoC 120. In examples, the SoC 120 includes one of a silicon substrate, a polymer substrate, a glass substrate, or a printed circuit board (PCB). Examples of polymer substrates include, but are not limited to, polyimide (PI), polyethylene terephthalate (PET), and polydimethylsiloxane (PDMS).

[0027] In some embodiments, SoC 120 further includes SoC control medium 118, which refers to operating mechanisms or modules within SoC 120. SoC control medium 118 is configured to manage the operation of different components integrated on SoC 120 (e.g., components 102 to 110). More specifically, in some embodiments, SoC control medium 118 is configured to perform one or more of the following: resource management, inter-component communication, power management, task scheduling, security management, and thermal management. For example, SoC control medium 118 may allocate resources such as power, processing time, and memory bandwidth to different components of SoC 120; manage communication between various components, such as coordinating data transfers between processor module 102 and peripheral devices; disconnect or place certain components in a low-power state to conserve energy when they are not in use; manage the scheduling of different tasks or operations across processing units of processor module 102 within SoC 120; implement security features (e.g., using hardware security modules, encryption, and access control); or monitor temperature sensors and adjust operation (e.g., reduce clock speed) to prevent overheating. In this example, the SoC control medium 118 includes one or more of the following: a power controller, a bus controller, and a clock controller. In some implementations, the SoC control medium 118 is implemented at the firmware level, for example, dynamically adjusting system parameters based on workload or external conditions.

[0028] In some embodiments, processor module 102 includes multiple processing units. In some embodiments, processor module 102 includes two or more different types of processing units, which include a subset of: one or more central processing units (CPUs) 102C, one or more graphics processing units (GPUs) 102G, digital signal processors (DSPs), neural processing units (NPUs) (also known as artificial intelligence (AI) accelerators), image signal processors (ISPs), video processing units (VPUs), audio processing units (APUs), security microcontrollers, and field-programmable gate arrays (FPGAs). CPU 102C is configured to execute instructions from software (e.g., operating systems, applications). Examples of CPU architectures include, but are not limited to, Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CIS). GPU 102G is configured to render graphics and handle tasks requiring parallel processing, such as image processing, video encoding / decoding, and machine learning.

[0029] In some implementations, network interface 108 is configured to enable communication between SoC 120 and external networks, such as a local area network (LAN) or the Internet, and includes both hardware and software components for handling data transmission, reception, and protocol management. Network interface 108 may include one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each interface allowing electronic system 100 to exchange data with external sources and participate in network connectivity applications such as IoT (Internet of Things), mobile communications, or cloud computing.

[0030] In some embodiments, memory module 104 includes high-speed random access memory, such as static random access memory (SRAM), dual data rate (DDR) dynamic random access memory (DRAM), or other random access solid-state memory devices. In some embodiments, memory module 104 includes non-volatile memory, such as one or more disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state memory devices. In some embodiments, memory module 104 (or alternatively, one or more non-volatile memory devices within memory module 104) includes a non-transitory computer-readable storage medium. In an example, memory module 104 includes high-bandwidth memory (HBM) configured to provide data bandwidth greater than a bandwidth threshold to support GPU 102G. HBM includes a plurality of memory dies stacked vertically on top of each other. In some embodiments, electronic system 100 further includes a memory controller 122 coupled to manage memory access requests to memory module 104.

[0031] Figure 2A and Figure 2B These are top and bottom perspective views of an example electronic system 100 according to some embodiments. The electronic system 100 includes an SoC 120 having a substrate 202. The substrate 202 includes a first surface 202A and a second surface 202B opposite to the first surface 202A. The substrate 202 may be one of a silicon substrate, a polymer substrate, a glass substrate, or a PCB. Examples of polymer substrates include, but are not limited to, PI, PET, and PDMS. In some embodiments, each electronic component of the electronic system 100 corresponds to a region of the substrate 202 and includes a portion of an integrated circuit of the SoC 120. Alternatively, in some embodiments, each electronic component of the electronic system 100 includes one or more chips mounted to the substrate 202, for example, with or without an intermediate support structure 210. In an example, the substrate 202 is made of a polymer material, and the intermediate support structure 210 is made of silicon and applied to mechanically support multiple components (e.g., including an I / O chip 206, a memory chip 208, and a processor chip 212).

[0032] In some embodiments not shown, all electronic components included in electronic system 100 are disposed on a first surface 202A of substrate 202. Alternatively, in some embodiments, a first subset of the electronic components of electronic system 100 is disposed on the first substrate 202A of substrate 202, and a second subset of the electronic components of electronic system 100 is disposed on a second substrate 202B of substrate 202. In one example, one or more chips corresponding to subsets of electronic components 102 to 108, 118, and 122 are disposed on the second surface 202B. In another example, one or more chips corresponding to PMIC module 112 are disposed on the second surface 202B.

[0033] In some embodiments, PMIC module 112 includes a plurality of dissimilar PMIC chips 204, which further include a first set of PMIC chips 204A and a second set of PMIC chips 204B. The first set of PMIC chips 204A is disposed on a first surface 202A of substrate 202, for example, in conjunction with all or a subset of the remaining components of SoC 120 that are different from PMIC module 112. The second set of PMIC chips 204B is disposed on a second surface 202B of substrate 202. Rail voltages output from the first set of PMIC chips 204A are routed on or below the first surface 202A to access, for example, the power rails 116 of the remaining components of SoC 120 via a configurable power plane. In some embodiments, rail voltages are output from the second set of PMIC chips 204B and routed vertically across substrate 202 from the second surface 202B to the first surface 202A to access, for example, the associated power rails 116 located on or below the first surface 202A via a configurable power plane.

[0034] In some implementations, PMIC module 112 includes multiple voltage regulator units (e.g., Figure 4B The voltage regulator unit 406 in the example. In this example, the first PMIC chip 204-1 includes one or more corresponding voltage regulator units (e.g., voltage regulator unit 406 in the example). Figure 4BA subset of the units 406 in the first PMIC chip 204-1 is disposed adjacent to the I / O chip 206 including the I / O interface 106, thereby allowing the I / O interface 106 to access the rail voltage provided by a subset of the voltage regulator units of the first PMIC chip 204-1. Alternatively, in some cases, two or more first PMIC chips 204-1 are disposed adjacent to the I / O chip 206 to jointly provide the rail voltage to the I / O chip 206. In another example, a memory chip 208 including one of the memory modules 104 is disposed at a location on a first surface 202A, and a second PMIC chip 204-2 is disposed at a location on a second surface 202B aligned (e.g., opposite) to the location of the first surface 202A. The second PMIC chip 204-2 includes one or more corresponding voltage regulator units (e.g., ... Figure 4B A subset of cells 406 in the memory module 104 is allowed, and vertical access to the rail voltage provided by the respective voltage regulator cell is permitted in one of the memory modules 104. In this way, components of the SoC 120 can access one or more of their associated voltage regulator cells located on the respective PMIC chip 204, which is positioned close to the component without introducing an extended length to access the power rail 116. This helps to reduce the resistance and capacitance parasitics of the power rail 116 and enhance the performance of the SoC 120.

[0035] Figure 3A and Figure 3B These are top and bottom perspective views of an electronic system 100 according to some embodiments. In some embodiments, a first surface 202A of substrate 202 includes a device region 302 on which a plurality of component chips (e.g., processor chip 212, I / O chip 206, memory chip 208) are disposed. One or more first PMIC regions 304A (e.g., two PMIC regions) are positioned adjacent to the device region 302, and a first set of PMIC chips 204A is disposed on one or more PMIC regions 304A of the first surface 202A of substrate 202. For example, two rows of PMIC chips 204A are disposed adjacent to two opposite sides of device region 302. In another embodiment not shown, four rows of PMIC chips 204A are disposed adjacent to four opposite sides of device region 302.

[0036] In some embodiments not shown, the second surface 202B of substrate 202 includes an alternative device region on which one or more component chips (e.g., processor chip 212, I / O chip 206, memory chip 208) are disposed, and one or more PMIC regions on which a second set of PMIC chips 204B is disposed, independent of the chip configuration of the first surface 202A. Alternatively, in some embodiments ( Figure 3BThe second surface 202B of the substrate 202 includes a second PMIC region 304B. (Reference) Figure 3A The perspective view of the integrated electronic system 100 is depicted from a top angle with a perspective effect (e.g., with a view of the substrate 202). In some embodiments, the second PMIC region 304B at least partially overlaps with the device region 302, thereby allowing component chips mounted on the device region 302 to access the output of the second PMIC region 304B using vias (e.g., through-silicon vias (TSVs)).

[0037] In some embodiments, the centers of the second PMIC region 304B and the device region 302 are aligned with each other; that is, the center of the second PMIC region 304A and the center of the device region 302 are directly opposite each other on the two opposing surfaces 202A and 202B of the substrate 202. Furthermore, in some embodiments, the second PMIC region 304A and the device region 302 are of equal size. Alternatively, in some embodiments, the second PMIC region 304A and the device region 302 are of different sizes. Alternatively, in some embodiments, the size and / or position of the second PMIC region 304A and the device region 302 are independent of each other.

[0038] In other words, the PMIC module 112 includes a plurality of voltage regulator units distributed across a subset of a plurality of PMIC chips 204. Each PMIC chip 204 is located at a corresponding position on a first surface 202A or a second surface 202B of the substrate 202. In some embodiments, the plurality of voltage regulator units are grouped based on their positions to provide a plurality of rail voltages to a plurality of power rails 116 coupled to different components of the SoC 120. More specifically, in some embodiments, each power rail 116 coupled to a component (e.g., a CPU chip, a GPU chip, a memory chip, an I / O chip) is coupled to a group of voltage regulator units selected based on their position relative to the component. For example, the group of voltage regulator units is closest in distance to the corresponding component compared to the rest of the voltage regulator units, thereby controlling associated resistance and capacitance parasitics. In another example, the group of voltage regulator units coupled to the corresponding component provides the lowest parasitic level. Among two voltage regulator units equidistant from the corresponding component, the voltage regulator unit located on the first surface 202A is preferentially selected over the voltage regulator unit located on the second surface 202B. In some embodiments, the voltage regulator unit located on the first surface 202A and at a greater distance from the corresponding component is preferentially selected over the voltage regulator unit located on the second surface 202B and at a smaller distance from the corresponding component.

[0039] In some implementations, the PMIC module 112 further includes multiple reference circuits (e.g., Figure 4A and Figure 4B (Circuit 408 in the PMIC). Multiple reference circuits may be formed on the same PMIC chip 204 or distributed across two or more PMIC chips 204. For example, each PMIC region 304A or 304B includes at least one PMIC chip 204 (e.g., chips 204-3, 204-4, and 204-5) dedicated to providing one or more reference circuits. In another example, all the multiple reference circuits used within the voltage regulator unit of PMIC module 112 are combined on a single PMIC chip (e.g., chip 204-5).

[0040] Alternatively, in some implementations, multiple reference circuits used with the voltage regulator unit of PMIC module 112 are provided by a single chip 306, or distributed among multiple chips (e.g., chips 306 and 308) mounted on or integrated into device region 302.

[0041] Figure 4A Here is a high-order block diagram of an example PMIC module 112 based on some implementation schemes, and Figure 4B This is a detailed block diagram of an example PMIC module 112 according to some implementation schemes. The PMIC module 112 includes or is coupled to a plurality of power rails 116, the plurality of power rails being configured to provide one or more rail voltages V. RAIL The PMIC module 112 further includes an array 404 of voltage regulator units 406 and a plurality of reference circuits 408. The plurality of reference circuits 408 are coupled to (but are different from) the array 404 of voltage regulator units 406. The array 404 of voltage regulator units 406 is coupled to a plurality of power rails 116 and configured to provide a plurality of voltage regulator sets 410. Each voltage regulator set 410 is configured to apply a corresponding rail voltage V RAIL The output is sent to the corresponding power rail 116. Each of the plurality of reference circuits 408 is shared by one or more corresponding voltage regulator units 406 of the corresponding voltage regulator set 410 and configured to output the corresponding reference voltage V. REF Provided to the one or more corresponding voltage regulator units. The corresponding voltage regulator set 410 is configured based on the corresponding reference voltage V. REF This generates the corresponding rail voltage V. RAIL .

[0042] In other words, some embodiments of this application include a PMIC module 112 having an array 404 of voltage regulator units 406, a selectable and programmable plurality of voltage references 408, and selectable distributed circuitry and buses. Different numbers of voltage regulator units 406 can be grouped together to form an output rail voltage V. RAIL A set of voltage regulators 410 (also referred to as the power supply voltage). An array 404 of voltage regulator units 406 can be grouped to form a single voltage regulator set 410 or multiple voltage regulator sets 410, thereby providing a single rail voltage V. RAIL or multiple rail voltages V RAIL In some implementations, the PMIC module 112 provides multiple rail voltages V corresponding to multiple sets of dissimilar voltage regulators 410. RAIL Each voltage regulator assembly 410 includes a corresponding number of voltage regulator units 406, independent of other voltage regulator assemblies 410. For each voltage regulator assembly 410, the outputs of the corresponding voltage regulator units 406 are electrically coupled (e.g., short-circuited) to each other and further electrically coupled to a corresponding power rail 116. In some embodiments, the voltage regulator assembly 410 is configured to output a variable rail voltage V. RAIL For example, to track the corresponding reference voltage V REF .

[0043] In some implementations, the PMIC module 112 includes or is coupled to a single substrate (e.g., Figure 2A and Figure 2B The substrate 202 is located in the substrate 202. An array 404 of voltage regulator units 406 and a plurality of reference circuits 408 are disposed on the substrate 202, spaced apart from each other. In some embodiments, the array 404 of voltage regulator units 406 and the plurality of reference circuits 408 correspond to PMIC regions 304A and 304B disposed on the substrate 202. Figure 3A and Figure 3B Different groups of PMIC chips 204 on the substrate 202. Alternatively, in some embodiments, the array 404 of voltage regulator units 406 is distributed in the PMIC chips 204 disposed on PMIC regions 304A and 304B of the substrate 202, and a plurality of reference circuits 408 correspond to the device regions 302 disposed on the substrate 202. Figure 3A On the chip (e.g., Figure 3A (Chip 306 or 308 in the chip).

[0044] refer to Figure 4B In some implementations, the plurality of power rails 116 include a first number M A power rail 116, and a plurality of reference circuits 408 including a second number NOne reference circuit 408. Second number. N Equal to or less than the first number M Furthermore, in some embodiments, each reference circuit 408 is uniquely associated with a corresponding power rail 116, and the corresponding reference circuit 408 is configured to apply a corresponding reference voltage V. REF Provided to the rail voltage V distributed to generate the power rail 116 RAIL The corresponding voltage regulator unit set 410. The number of voltage regulator units 406 in the corresponding voltage regulator unit set 410 can vary.

[0045] In some implementations, the rail voltage V of the two power rails 116-1 and 116-2 RAIL The voltages are equal to each other, and each power rail 116 maintains a constant voltage. It is required that the voltage regulator units 406 contributing to each corresponding power rail 116-1 or 116-2 be driven by the same corresponding reference circuit 408. Furthermore, in some embodiments, two sets of voltage regulators 410-1 and 410-2 corresponding to the two power rails 116-1 and 116-2 are coupled to two dissimilar reference circuits 408-1 and 408-2. Alternatively, in some embodiments, two sets of voltage regulators 410-1 and 410-2 corresponding to the two power rails 116-1 and 116-2 are coupled to the same reference circuit 408 (e.g., 408-1). Therefore, the second number of reference circuits 408... N The first number is equal to or less than the number of power rails 116. M .

[0046] In some implementations, the plurality of power rails 116 include a first number M A power rail 116, and a plurality of reference circuits 408 including a second number N A reference circuit 408. An array 404 of voltage regulator units 406 includes a third number of reference circuits 408. K One voltage regulator unit 406. Second number N Equal to or less than (≤) the third number K And the first number M Equal to or less than (≤) the third number K .

[0047] In some implementations, the PMIC module 112 includes a first switch array 412 (e.g., having a second number of switches). N Individual rows and third number K One column, or the second number N Individual columns and the third number K (rows). For example, rows of the first switch array 412 are electrically coupled to the second number of rows. NA reference circuit 408, and the columns of the first switch array 412 are electrically coupled to a third number of arrays 404. K Each voltage regulator unit 406. Each row-column cross section of the first switch array 412 includes a switching assembly configured to control the coupling of a corresponding reference circuit 408 with a corresponding voltage regulator unit 406. For each voltage regulator set 410 (e.g., Figure 4B In the first switch array 412 (set 410-1), corresponding group switch components are enabled to couple a corresponding reference circuit 408 (e.g., circuit 408-1) to one or more corresponding voltage regulator units 406 (e.g., units 406-1 and 406-2). It should be noted that in some embodiments, the lines directly connecting reference circuits 408-1 and 408-2 to voltage regulator units 406 in voltage regulator sets 410-1 and 410-2 may not correspond to interconnects, and are only used for illustrative purposes. Figure 4B Draw in the middle.

[0048] Return to reference Figure 4A In some embodiments, the PMIC module 112 further includes a mapping module 414 coupled to the first switch array 412. The mapping module 414 is configured to control the switching components of the first switch array 412 to group the voltage regulator units 406 to form a plurality of voltage regulator sets 410. More specifically, the mapping module 414 is configured to determine whether to enable or disable each of the switching components of the first switch array 412.

[0049] In some embodiments, the PMIC module 112 further includes a plurality of configurable power planes 416 embedded in a module substrate of the PMIC module 112 or a substrate 202 on which the PMIC module 112 is mounted. Each of the plurality of power rails 116 is electrically coupled to a corresponding power plane 416 and extends to one or more electrical components (e.g., modules 102 to 108) to provide a corresponding rail voltage V to these components. RAIL Each output of the voltage regulator unit 406 of the corresponding voltage regulator assembly 410 is also electrically coupled to the corresponding power plane 416, thereby adjusting the supply voltage V. RAIL Provided to the corresponding power plane 416.

[0050] In addition, refer to Figure 4B In some implementations, the PMIC module 112 includes a second switch array 418 (e.g., having a first number of switches). M Individual rows and third number K Column, or first number M Individual columns and the third number K (rows). For example, rows of the first switch array 412 are electrically coupled to a first number of... MA power rail 116 or a configurable power plane 416, and the row electrical coupling of the second switch array 418 to a third number of arrays 404. K The output of each voltage regulator unit 406. Each row-column cross section of the second switch array 418 includes a switch assembly configured to control the coupling of a corresponding voltage regulator unit 406 to a corresponding configurable power plane 416 or a corresponding power rail 116. For each voltage regulator set 410 (e.g., Figure 4B In the first switch array 412, corresponding group switch components (set 410-1) are enabled to couple one or more corresponding voltage regulator units 406 (e.g., units 406-1 and 406-2) to a corresponding configurable power plane 416 or a corresponding power rail 116 (e.g., rail 116-1). Additionally, in some embodiments, the second switch array 418 and the first switch array 412 are integrated into a single switch array.

[0051] It should be noted that in some embodiments, the wires connecting the power rails 116-1 and 116-2 directly to the voltage regulator unit 406 in the voltage regulator assemblies 410-1 and 410-2 may not correspond to interconnects, and are only for illustrative purposes. Figure 4B Draw in the middle.

[0052] In some implementations, the plurality of voltage regulators 410 includes configurations for adjusting the first rail voltage. V RAIL1 (For example, 1.2V, 0.8V) The first voltage regulator assembly 410-1 outputs to the first power rail 116-1, and the first rail voltage is equal to the first reference voltage provided by the first reference circuit 408-1. V REF1 In other words, the output voltage level of each voltage regulator set 410 is set by its associated reference voltage, and the voltage regulator set 410 is configured to track its associated reference voltage provided by the corresponding reference circuit 408.

[0053] Return to reference Figure 4A In some embodiments, the PMIC module 112 further includes a voltage controller 420 coupled to a plurality of reference circuits 408. The voltage controller 420 is configured to generate a digital control signal 422 based on a first rail voltage associated with the first power rail 116-1, and to provide the digital control signal 422 to define the first reference voltage. V REF1A first reference circuit 408-1 is provided. A first power rail 116-1 extends to one or more electrical components (e.g., modules 102 to 108) to provide a first rail voltage to these components. The characteristics of the first power rail 116-1 (e.g., rail current, rail voltage) are determined based on the operation of one or more electrical components. A first reference voltage of the first reference circuit 408-1 is further determined and set based on the characteristics of the first power rail 116-1. In some embodiments, multiple reference circuits 408 are identical to each other. A digital control signal 422 determines the reference voltage V output by the multiple reference circuits 408. REF The magnitude of the reference circuit. Conversely, in some implementations, at least two of the plurality of reference circuits 408 are different from each other. In an example, each reference circuit 408 includes a digital-to-analog converter (DAC).

[0054] Additionally, in some embodiments, the first voltage regulator assembly 410-1 further includes a target number. N T (For example, 2) voltage regulator units 406 and configured to control up to a predefined rail current I R Delivered to the first power rail 116-1. Target number N T Based on predefined rail current I R And it is determined, for example, to be equal to a predefined rail current. I R Divided by the regulator current that can be delivered by each voltage regulator unit 406 I VGC Additionally, in some embodiments, the PMIC module 112 further includes a voltage controller 420 coupled to an array 404 of the voltage regulator unit 406. The voltage controller 420 is configured to base its signal on a predefined rail current associated with the first power rail 116-1. I Determining the target number N T Based on the target number N T One or more selection signals 424 are generated and provided to the array 404 of the voltage regulator unit 406 to select a target number of the first voltage regulator set 116-1. N T A voltage regulator unit 406 (e.g., units 406-1 and 406-2). In some embodiments, the mapping module 414 is part of the voltage controller 420.

[0055] In some implementations, the voltage regulator units 406 in the array 404 of voltage regulator units 406 are identical to each other. The output voltage of each voltage regulator unit 406 is based on a corresponding reference voltage received by the respective voltage regulator unit 406. V REF And thus determined. The rail current of the power rail 116. I R The higher the target number of voltage regulator units 406 grouped to drive the power rail 116. N T The larger.

[0056] Conversely, in some embodiments, at least two voltage regulator units 406 in the array 404 of voltage regulator units 406 are different from each other. For example, the output voltage of each voltage regulator unit 406 is based on a corresponding reference voltage received by the respective voltage regulator unit 406. V REF And this is determined. The two voltage regulator units 406 may have different drive capabilities (e.g., different regulator currents). This can be based on the rail current associated with the power rail 116. I R and the regulator current of the two voltage regulator units 406 I VGC Different numbers of two voltage regulator units 406 can be selected and combined.

[0057] Figure 5 This is a schematic diagram of an example voltage regulator unit 406 according to some embodiments. In some embodiments, the voltage regulator unit 406 includes features for receiving a target reference voltage V. REF Input reference interface 502 is used to receive input signals (e.g., rail voltage V). RAIL The input signal interface 504 is used to input the rail voltage V. RAIL Provided to the power rail (e.g., Figure 4B The output interface 506 of the power rail 116-1, the first feedback path 510 that couples the output interface 506 of the voltage regulator unit 406 to the input signal interface 504 of the voltage regulator unit 406, and the inductor 508 electrically coupled between the input signal interface 504 and the output interface 506.

[0058] In some implementations, the voltage regulator unit 406 includes an error amplifier 512, a pulse width modulator 514, a power stage 518, and a feedback path 510. The error amplifier 512 is configured to receive a reference voltage V. REF and rail voltage V RAILAmplified difference signal 522 is generated. A pulse width modulator 514 is coupled to an error amplifier 512, the pulse width modulator being configured to generate a pulse width and a characteristic frequency. f A pulse width modulation (PWM) periodic signal 516 is provided. In this example, the PWM modulator 514 includes a comparator and receives an input signal 515 having a sawtooth or triangular waveform. The PWM modulator 514 is coupled to an error amplifier 512 and configured to modulate the pulse width of the input signal 515. A power stage 518 is coupled to the PWM modulator 514 and configured to generate a rail voltage V based on the PWM periodic signal 516. RAIL In this example, power stage 518 includes one or more power field-effect transistors (FETs). Feedback path 510 is configured to couple the output of power stage 518 to the input of error amplifier 512, for example, in conjunction with inductor 508.

[0059] In some implementations, the voltage regulator unit 406 includes a signal generator 528, a power stage 518, and a first feedback path 510 that couples the output of the power stage to a signal input of the signal generator 528. The signal generator 528 is configured to receive a target reference voltage V. REF and rail voltage V RAIL A PWM periodic signal 516 with a target pulse width is generated. The power stage 518 is coupled to the signal generator 528 and configured to generate a rail voltage based on the PWM periodic signal 516 with the target pulse width. Furthermore, in some embodiments, in the voltage regulator unit 406, a second feedback path 530 couples the output of the power stage 518 to the signal modulator 532 of the signal generator 528. The second feedback path 530 is configured to generate a rail voltage V... RAIL The deviation rate from the target reference voltage V is higher than the deviation rate of the characteristic circuit of the voltage regulator unit 406. REF When the guide rail voltage V RAIL Pull back to the target reference voltage V REF .

[0060] Furthermore, in some embodiments, the second feedback path 530 further includes a change detector 534 and an amplification and modulation circuit 536. The change detector 534 is coupled to the output of the power stage 518 and configured to detect deviations from the target reference voltage V at a deviation rate. REF rail voltage V RAIL The amplification and modulation circuit 536 is coupled to the change detector 534 and the signal modulator 532, and is configured to operate at rail voltage V. RAIL Deviation rate from target reference voltage V REFThe pulse width of the PWM period signal 516 is adjusted in real time. In other words, in some embodiments, the change detector 534 is configured to sense rapid voltage changes in the feedback voltage signal in the first feedback path 510 (e.g., corresponding to rapid voltage changes in the output of the voltage regulator unit 406). The change detector 534 generates a modulation signal for modulating the signal modulator 532, thereby preventing the output of the voltage regulator unit 406 from deviating from the reference voltage V. REF .

[0061] In other words, in some implementations, the voltage regulation unit 406 is based on the use of a power stage 518, an integrated on-chip inductor 508, and a feedback voltage signal (e.g., carrying the rail voltage V in the first feedback path 510). RAIL This is implemented through one or more of the following control loops: The control loop tracks the voltage feedback signal and the selected reference voltage V. REF The difference between the two values ​​is used to generate a pulse-width modulation signal (e.g., PWM period signal 516) that drives the power stage 518. The output of the power stage 518 can drive the integrated on-chip inductor 508.

[0062] In some implementations, inductor 508 and output filter capacitor 538 form an output filter. The output filter may be part of or external to the corresponding voltage regulator unit 406. The output filter may be partially integrated into the corresponding voltage regulator unit 406. Output filter capacitor 538 may be embedded in the GPU or CPU package substrate, the substrate of SoC 120 (e.g., substrate 202), or the processor chip 212 (…). Figure 2A In some embodiments, for voltage regulator assembly 410, the output terminal of the on-chip inductor 508 of voltage regulator unit 406 of voltage regulator assembly 410 corresponds to output interface 506 and is coupled to output filter capacitor 538 via interconnect, which may be external to voltage regulator unit 406. In other words, voltage regulator units 406 of voltage regulator assembly 410 share a common output filter capacitor 538 and are separately routed to the common output filter capacitor via interconnect. Furthermore, in some embodiments, the feedback voltage signal carried by feedback path 510 is connected to the output filter capacitor via interconnect extending externally to voltage regulator unit 406.

[0063] Additionally, in some embodiments, the regulation control mechanism of the voltage regulator unit 406 employs a dual control loop, including a regulation control loop and a transient modulation loop 540. The regulation control loop is based on a first feedback path 510 and configured to be based on the reference voltage V. REFAn error signal (e.g., an amplified difference signal 522) generated by integrating the difference between the feedback voltage signal and the error signal is used to modulate the PWM period signal 516. In some embodiments, the control loop adjusts the reference voltage V. REF The difference between the input and output voltage signals is integrated, and includes a signal modulator 532 shared with the transient modulation circuit 540. The amplified difference signal 522 reflects the reference voltage V. REF The integral of the difference between the voltage and the feedback voltage signal, applied to modulate the PWM period signal 516, generates the rail voltage V to be output at the output interface 506 of the voltage regulator unit 406. RAIL Rail voltage V RAIL Stabilized at the associated reference voltage V REF Additionally, the transient modulation circuit 540 is configured to modulate the PWM period signal 516 based on the detection of the transient characteristics of the feedback voltage signal (e.g., rail voltage).

[0064] Figure 6 To illustrate the method for providing rail voltage V according to some implementation schemes RAIL Two examples of voltage regulator units 406-1 and 406-2 (also shown in...) Figure 4B The diagram shows a concept of voltage regulator units 406-1 and 406-2. Each of these two voltage regulator units includes a corresponding inductor 508 electrically coupled to the output interface 506 of the corresponding voltage regulator unit 406. In some embodiments, for each voltage regulator unit 406-1 or 406-2, the corresponding inductor 508 is integrated on-chip, for example, monolithically formed on the corresponding PMIC chip 204. In some embodiments, a power plane 416 can be configured to be embedded in the module substrate of the PMIC module 112 or the substrate 202 of the SoC 120 on which the PMIC module 112 is mounted. The two voltage regulator units 406-1 and 406-2 may be formed on a common chip substrate 602 or on two dissimilar chip substrates 602. The output interfaces 506 of the two voltage regulator units 406-1 and 406-2 are electrically coupled to the power plane 416, which is further coupled to a power rail 116. Figure 6 (Not shown in the text).

[0065] In some embodiments, inductor 508 is integrated on cell substrate 602, for example, above signal generator 528, power stage 518, and / or any other circuitry 408, 412, 418, or 420 of PMIC module 112. The input terminals of inductor 508 are coupled to the output of power stage 518, for example, using vias, metal layers, solder balls, redistribution layers (RDLs), or combinations thereof. In an example, the output terminals of inductor 508 correspond to the output of inductor 508 and are connected to interconnects that couple inductor 508 to bumps or solder balls of PMIC module 112. Bumps or solder balls are applied to electrically couple PMIC module 112 to other electrical components of SoC 120 (e.g., components 102 to 108). In some embodiments, each of the two terminals of inductor 508 includes a corresponding interconnect made of vias, metal layers, RDLs, or combinations thereof, and is configured to provide a Kelvin sensing point.

[0066] Figure 7A This is a perspective view of an example PMIC chip 204 according to some embodiments, including multiple inductors 508 coupled to multiple voltage regulator units 406, and Figure 7B and Figure 7C According to some implementation plans Figure 7A The figures 720 and 740 show two cross-sectional views of a portion of a PMIC chip 204 including two inductors 508 and two voltage regulator units 406. The PMIC chip 204 has a chip substrate 602 and includes twelve voltage regulator units 406 monolithically formed on the top surface of the chip substrate 602. Each voltage regulator unit 406 includes a corresponding inductor 508 integrated on the top surface of the chip substrate 602. In other words, the voltage regulator units 406 (e.g., transistors and metal interconnects) may be formed on the unit substrate 602 and partially beneath the inductors 508. The PMIC chip 204 includes two cross-sections AA' and BB' perpendicular to each other and perpendicular to the top surface of the chip substrate 602. Cross-section AA' is shown in... Figure 7B In the middle, and the cross-section BB' is shown in Figure 7C middle.

[0067] refer to Figure 7BIn some embodiments, inductor 508 includes three vias 722, 724, and 726. A first via 722 is coupled between the output of the power stage 518 of the corresponding voltage regulator unit 406 and the input terminal 508A of inductor 508, thereby driving current toward inductor 508. In some embodiments, a second via 724 is coupled between the output terminals 508B of the corresponding inductor 508. The output terminal 508B of the corresponding inductor 508 corresponds to the output port 506 of the voltage regulator unit 406. Alternatively, in some embodiments, the second via 724 is coupled between the output terminal 508B of the corresponding inductor 508 and the input signal interface 504 (…). Figure 5 The third via 726 is coupled between the output terminal 508B of the inductor 508 and other components of the SoC 120 (e.g., ...). Figure 1 The third via 726 is located between power rails 116 that power components 102 to 108 in the SoC 120, thereby providing current and power to enable the operation of other components of the SoC 120. In some embodiments, the third via 726 is located via a configurable power plane 416. Figure 6 The output terminal 508B of inductor 508 is coupled to power rail 116. In some embodiments, the third through-hole 726 is vertically aligned with the second through-hole 724. In some embodiments not shown, the third through-hole 726 is laterally displaced relative to the second through-hole 724 (i.e., not vertically aligned).

[0068] In some embodiments, the first via 722 and the second via 724 implement a Kelvin connection for sensing current through the conduction trace of inductor 508. Current sensing circuitry 728 is coupled to input terminal 508A and output terminal 508B of inductor 508 and configured to measure the voltage drop across inductor 508. Assuming the resistance of inductor 508 is known, the voltage drop is applied to determine the current through inductor 508.

[0069] In some embodiments, each of the two terminals 508A and 508B of inductor 508 includes a corresponding interconnect made of a through-hole, a metal layer, an RDL, or a combination thereof. The corresponding interconnect forms a Kelvin connection that can be coupled to a current sensing circuit associated with voltage regulator unit 406 for sensing the inductor current flowing through inductor 508. In some embodiments, the distance between the Kelvin connections of each voltage regulator unit 406 is substantially uniform in the array 404 of voltage regulator units 406 (e.g., in...). Figure 7A (In the middle). For each voltage regulator set 410, a single shared reference circuit 408 is used to achieve current balance among the different voltage regulator units 406.

[0070] refer to Figure 7CIn some embodiments, inductor 508 is formed on top of unit substrate 602 (e.g., silicon substrate) and includes at least two laminated magnetic thin film layers 742 and 744 surrounding conductor 746. Inductor 508 further includes an insulating film layer 748 and a dielectric filling structure 750. The two laminated magnetic thin film layers 742 and 744 are electrically isolated from conductor 746 by the insulating film layer 748 and the dielectric filling structure 750. In some embodiments, there is no gap in the housing formed by the two laminated magnetic thin film layers 742 and 744. Conversely, in some embodiments, there is a gap in the housing formed by the two laminated magnetic thin film layers 742 and 744. Furthermore, in some embodiments, each of the two laminated magnetic thin film layers 742 and 744 includes a stack of alternating magnetic and dielectric thin films.

[0071] Figure 8 For providing rail voltage V to electronic system 100 according to some implementation schemes RAIL The flowchart of instance method 800. Method 800 is composed of electronic system 100 (e.g., Figures 1 to 3B (In operation 802) Electronic system 100 groups the voltage regulator units 406 in the array 404 of voltage regulator units 406 to provide a plurality of voltage regulator sets 410. For each of the plurality of voltage regulator sets 410, electronic system 100 generates (operation 804) a corresponding reference voltage V through a corresponding one of a plurality of reference circuits 408. REF The corresponding components in the multiple reference circuits 408 are shared by one or more corresponding voltage regulator units 406 of the corresponding voltage regulator set 410 (operation 806). The corresponding voltage regulator set 410 is based on the corresponding reference voltage V. REF This generates (operation 808) the corresponding rail voltage V. RAIL The electronic system provides (operation 810) the corresponding rail voltage V. RAIL To drive the corresponding one of the multiple power rails 116.

[0072] In some embodiments, the electronic system 100 includes a substrate 202, and an array 404 of voltage regulator units 406 and a plurality of reference circuits 408 are disposed on the substrate in a spaced manner.

[0073] In some embodiments, the electronic system 100 includes a substrate, and an array 404 of voltage regulator units 406 and a plurality of reference circuits 408 are formed on the top surface of the substrate by semiconductor fabrication. The array 404 of voltage regulator units 406 and the plurality of reference circuits 408 are formed on two different chip regions of the substrate. In other words, each voltage regulator unit 406 does not have a separate and dedicated reference circuit 408 locally within the voltage regulator unit 406.

[0074] Each of the elements identified above can be stored in one or more memory devices and corresponds to a set of instructions for performing the functions described above. The modules or programs (i.e., instruction sets) identified above do not need to be implemented as separate software or firmware programs, procedures, modules, or data structures, and therefore can be combined or otherwise reconfigured in various embodiments. In some embodiments, the memory may optionally store a subset of the modules and data structures identified above. Furthermore, the memory may optionally store additional modules and data structures not described above.

[0075] For convenience, various examples of aspects of this disclosure are described as numbered entries (1, 2, 3, etc.). These entries are provided as examples and do not limit the technology of this disclosure. The identification of diagrams and component symbols is provided below only as examples and for illustrative purposes, and the entries are not limited by those identifications.

[0076] Clause 1. An electronic system comprising: an array of voltage regulator units, wherein the array of voltage regulator units is configured to provide a plurality of voltage regulator sets, and each voltage regulator set is configured to output a corresponding rail voltage and provide the corresponding rail voltage to a corresponding power rail among a plurality of power rails; and a plurality of reference circuits coupled to the array of voltage regulator units, wherein each of the plurality of reference circuits is shared by one or more corresponding voltage regulator units of the corresponding voltage regulator set and is configured to provide a corresponding reference voltage to the one or more corresponding voltage regulator units, and the corresponding voltage regulator set is configured to generate the corresponding rail voltage based on the corresponding reference voltage.

[0077] Clause 2. The electronic system according to Clause 1, further comprising a substrate, wherein the voltage regulator unit array and the plurality of reference circuits are disposed on the substrate spaced apart from each other.

[0078] Clause 3. The electronic system according to Clause 1 or 2, wherein the plurality of power rails comprises a first number of power rails and the plurality of reference circuits comprises a second number of reference circuits, the second number being equal to or less than the first number.

[0079] Clause 4. The electronic system according to any one of Clauses 1 to 3, wherein each of the plurality of power rails is uniquely associated with a dissimilar reference circuit in the plurality of reference circuits, the dissimilar reference circuits being configured to provide the respective reference voltage to each voltage regulator unit in the respective set of voltage regulators.

[0080] Clause 5. The electronic system according to any one of Clauses 1 to 4, wherein: the plurality of power rails comprises a first number of power rails; the plurality of reference circuits comprises a second number of reference circuits; the voltage regulator unit array comprises a third number of voltage regulator units; the second number is equal to or less than (≤) the third number; and the first number is equal to or less than (≤) the third number.

[0081] Clause 6. The electronic system according to any one of Clauses 1 to 5, wherein the plurality of voltage regulator sets includes a first voltage regulator set configured to output a first rail voltage to a first power rail, and the first rail voltage is equal to a first reference voltage provided by a first reference circuit.

[0082] Clause 7. The electronic system according to Clause 6, further comprising a voltage controller coupled to the plurality of reference circuits, wherein the voltage controller is configured to generate a digital control signal based on a first rail voltage associated with the first power rail and to provide the digital control signal to the first reference circuit defining the first reference voltage.

[0083] Clause 8. The electronic system according to Clause 6, wherein: the first voltage regulator set further includes a target number of voltage regulator units and is configured to deliver up to a predefined regulator current to the first power rail; and the target number is determined based on the predefined regulator current.

[0084] Clause 9. The electronic system according to Clause 8, further comprising a voltage controller coupled to the voltage regulator unit array; wherein the voltage controller is configured to determine the target number based on the predefined regulator current associated with the first power rail, generate one or more selection signals based on the target number, and provide the one or more selection signals to the voltage regulator unit array to select the target number of voltage regulator units of the first voltage regulator set.

[0085] Clause 10. The electronic system according to any one of Clauses 1 to 9, wherein the voltage regulator units in the voltage regulator unit array are identical to each other.

[0086] Clause 11. An electronic system according to any one of Clauses 1 to 9, wherein at least two voltage regulator units in the voltage regulator unit array are different from each other.

[0087] Clause 12. The electronic system according to any one of Clauses 1 to 11, wherein the plurality of reference circuits are identical to each other.

[0088] Clause 13. The electronic system according to any one of Clauses 1 to 12, wherein the first voltage regulator unit further comprises: a first signal generator configured to receive a target reference voltage and a first rail voltage and generate a periodic signal having a target pulse width; and a first power stage coupled to the first signal generator and configured to generate the first rail voltage based on the periodic signal having the target pulse width; and a first feedback path coupling the output of the first power stage to a signal input of the first signal generator.

[0089] Clause 14. The electronic system according to Clause 13, wherein the first voltage regulator unit further comprises: a second feedback path that couples the output of the first power stage to a signal modulator of the first signal generator, the second feedback path being configured to pull the first rail voltage back to the target reference voltage when the first rail voltage deviates from the target reference voltage at a deviation rate higher than the characteristic circuit rate of the first voltage regulator unit.

[0090] Clause 15. The electronic system according to Clause 14, wherein the second feedback path further comprises: a variation detector coupled to the output of the first power stage, the variation detector being configured to detect a first rail voltage deviating from the target reference voltage at the deviation rate; and an amplification and modulation circuit coupled to the variation detector and the signal modulator, the amplification and modulation circuit being configured to adjust the pulse width of the periodic signal in real time when the first rail voltage deviates from the target reference voltage at the deviation rate.

[0091] Clause 16. An electronic system according to any one of Clauses 1 to 12, wherein each voltage regulator unit further comprises: an error amplifier configured to receive the respective reference voltage and the respective rail voltage and generate an amplified difference signal; a pulse width modulator coupled to the error amplifier and configured to generate a periodic signal having a pulse width and a characteristic frequency; a power stage coupled to the pulse width modulator and configured to generate the respective rail voltage based on the periodic signal; and a feedback path coupling the output of the power stage to the input of the error amplifier.

[0092] Clause 17. The electronic system according to any one of Clauses 1 to 12, wherein the first voltage regulator unit further comprises: an input reference interface for receiving a target reference voltage; an input signal interface for receiving an input signal; an output interface for providing a first rail voltage to a first rail; a first feedback path coupling the output interface of the first voltage regulator unit to the input signal interface of the first voltage regulator unit; and an inductor electrically coupled between the input signal interface and the output interface.

[0093] Clause 18. The electronic system according to Clause 17, wherein the inductor comprises one of an integrated inductor formed on a substrate of an integrated circuit or a hybrid inductor mounted on the substrate, the substrate comprising a subset of the voltage regulator unit array.

[0094] Article 19. An apparatus comprising: a plurality of power rails configured to provide one or more rail voltages; and an electronic system according to any one of Articles 1 to 18.

[0095] Article 20. An integrated circuit comprising: a plurality of power rails configured to provide one or more rail voltages; and an electronic system according to any one of Articles 1 to 18.

[0096] Article 21. A power management integrated circuit (PMIC) comprising an electronic system according to any one of Articles 1 to 18.

[0097] Clause 22. A method comprising: grouping voltage regulator units in an array of voltage regulator units to provide a plurality of voltage regulator sets; and for each of the plurality of voltage regulator sets: generating a corresponding reference voltage by a corresponding of a plurality of reference circuits, wherein the corresponding of the plurality of reference circuits is shared by one or more corresponding voltage regulator units of the corresponding voltage regulator set; generating a corresponding rail voltage by the corresponding voltage regulator set based on the corresponding reference voltage; and providing the corresponding rail voltage to drive a corresponding of a plurality of power rails; wherein the method is implemented by an electronic system according to any one of Clauses 1 to 18.

[0098] The terminology used in the description of the various embodiments described herein is for the purpose of describing particular embodiments only and is not intended to be restrictive. As used in the description of the various described embodiments and the appended claims, the singular forms “a(a)”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. It should be further understood that the terms “includes,” “including,” “comprises,” and / or “comprising,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, it should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0099] As used herein, depending on the context, the term "if" may optionally be interpreted as meaning "when," "after," "in response to a determination," "in response to a detection," or "according to a determination." Similarly, depending on the context, the phrase "if determined" or "if [the stated condition or event] is detected" may optionally be interpreted as meaning "after determined," "in response to a determination," "after [the stated condition or event] is detected," "in response to the detection of [the stated condition or event]," or "according to a determination that [the stated condition or event] is detected."

[0100] For illustrative purposes, the foregoing description has been described with reference to specific embodiments. However, the illustrative statements above are not intended to be exhaustive or to limit the claims to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments were chosen and described in order to best explain the operating principles and practical applications so that those skilled in the art can understand them.

[0101] Although various diagrams illustrate several logical stages in a specific order, stages independent of this order can be reordered and other stages can be combined or decomposed. While some reorderings or other groupings are specifically mentioned, other reorderings or groupings will be obvious to those skilled in the art, and therefore the orderings and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that the stages can be implemented in hardware, firmware, software, or any combination thereof.

Claims

1. An electronic system comprising: A voltage regulator unit array, wherein the voltage regulator unit array is configured to provide a plurality of voltage regulator sets, and each voltage regulator set is configured to output a corresponding rail voltage and provide the corresponding rail voltage to a corresponding power rail among a plurality of power rails; and A plurality of reference circuits coupled to the voltage regulator unit array, wherein each of the plurality of reference circuits is shared by one or more corresponding voltage regulator units of a corresponding voltage regulator set and configured to provide a corresponding reference voltage to the one or more corresponding voltage regulator units, and the corresponding voltage regulator set is configured to generate the corresponding rail voltage based on the corresponding reference voltage.

2. The electronic system of claim 1, further comprising a substrate, wherein the voltage regulator unit array and the plurality of reference circuits are disposed on the substrate in a manner that is spaced apart from each other.

3. The electronic system according to claim 1 or 2, wherein the plurality of power rails comprises a first number of power rails, and the plurality of reference circuits comprises a second number of reference circuits, the second number being equal to or less than the first number.

4. The electronic system according to any one of claims 1 to 3, wherein each of the plurality of power rails is uniquely associated with a dissimilar reference circuit in the plurality of reference circuits, the dissimilar reference circuit being configured to provide the corresponding reference voltage to each voltage regulator unit in the corresponding set of voltage regulators.

5. The electronic system according to any one of claims 1 to 4, wherein: The plurality of power rails includes a first number of power rails; The plurality of reference circuits includes a second number of reference circuits; The voltage regulator unit array includes a third number of voltage regulator units; The second number is equal to or less than (≤) the third number; and The first number is equal to or less than (≤) the third number.

6. The electronic system according to any one of claims 1 to 5, wherein the plurality of voltage regulator sets includes a first voltage regulator set configured to output a first rail voltage to a first power rail, and the first rail voltage is equal to a first reference voltage provided by a first reference circuit.

7. The electronic system of claim 6, further comprising a voltage controller coupled to the plurality of reference circuits, wherein the voltage controller is configured to generate a digital control signal based on a first rail voltage associated with the first power rail and to provide the digital control signal to the first reference circuit defining the first reference voltage.

8. The electronic system according to claim 6, wherein: The first voltage regulator assembly further includes a target number of voltage regulator units and is configured to deliver up to a predefined regulator current to the first power rail; and The target number is determined based on the predefined regulator current.

9. The electronic system of claim 8, further comprising a voltage controller coupled to the voltage regulator unit array; The voltage controller is configured to determine the target number based on the predefined regulator current associated with the first power rail, generate one or more selection signals based on the target number, and provide the one or more selection signals to the voltage regulator unit array to select the target number of voltage regulator units in the first voltage regulator set.

10. The electronic system according to any one of claims 1 to 9, wherein the voltage regulator units in the voltage regulator unit array are identical to each other.

11. The electronic system according to any one of claims 1 to 9, wherein at least two voltage regulator units in the voltage regulator unit array are different from each other.

12. The electronic system according to any one of claims 1 to 11, wherein the plurality of reference circuits are identical to each other.

13. The electronic system according to any one of claims 1 to 12, wherein the first voltage regulator unit further comprises: a first signal generator configured to receive a target reference voltage and a first rail voltage and to generate a periodic signal having a target pulse width; and A first power stage, coupled to the first signal generator and configured to generate the first rail voltage based on the periodic signal having the target pulse width; and A first feedback path couples the output of the first power stage to the signal input of the first signal generator.

14. The electronic system of claim 13, wherein the first voltage regulator unit further comprises: A second feedback path couples the output of the first power stage to the signal modulator of the first signal generator. The second feedback path is configured to pull the first rail voltage back to the target reference voltage when the first rail voltage deviates from the target reference voltage at a deviation rate higher than the characteristic circuit rate of the first voltage regulator unit.

15. The electronic system of claim 14, wherein the second feedback path further comprises: A change detector, coupled to the output of the first power stage, is configured to detect the first rail voltage deviating from the target reference voltage at the deviation rate; and An amplification and modulation circuit, coupled to the variation detector and the signal modulator, is configured to adjust the pulse width of the periodic signal in real time as the first rail voltage deviates from the target reference voltage at the deviation rate.

16. The electronic system according to any one of claims 1 to 12, wherein each voltage regulator unit further comprises: An error amplifier configured to receive the corresponding reference voltage and the corresponding rail voltage and generate an amplified difference signal; A pulse width modulator, coupled to the error amplifier and configured to generate a periodic signal having a pulse width and a characteristic frequency; A power stage, coupled to the pulse width modulator and configured to generate the corresponding rail voltage based on the periodic signal; and A feedback path that couples the output of the power stage to the input of the error amplifier.

17. The electronic system according to any one of claims 1 to 12, wherein the first voltage regulator unit further comprises: Input reference interface, which is used to receive the target reference voltage; Input signal interface, which is used to receive input signals; Output interface, which is used to provide the first rail voltage to the first rail; A first feedback path couples the output interface of the first voltage regulator unit to the input signal interface of the first voltage regulator unit. and An inductor electrically coupled between the input signal interface and the output interface.

18. The electronic system of claim 17, wherein the inductor comprises one of: an integrated inductor formed on a substrate of an integrated circuit including a subset of the voltage regulator unit array; or a hybrid inductor mounted on the substrate.

19. An apparatus comprising: a plurality of power rails configured to provide one or more rail voltages; and an electronic system according to any one of claims 1 to 18.

20. An integrated circuit comprising: a plurality of power rails configured to provide one or more rail voltages; and an electronic system according to any one of claims 1 to 18.

21. A power management integrated circuit (PMIC) comprising an electronic system according to any one of claims 1 to 18.

22. A method comprising: Group the voltage regulator units in the voltage regulator unit array to provide multiple voltage regulator sets; and For each of the plurality of voltage regulator sets: A corresponding reference voltage is generated by a corresponding entity in a plurality of reference circuits, wherein the corresponding entity in the plurality of reference circuits is shared by one or more corresponding voltage regulator units of a corresponding voltage regulator set; The corresponding rail voltage is generated by the corresponding set of voltage regulators based on the corresponding reference voltage; and Provide the corresponding rail voltage to drive the corresponding one of the multiple power rails; The method is implemented by an electronic system according to any one of claims 1 to 18.

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