Adjusting instruction execution to enhance security

Abstract

Systems and techniques for secure computing systems are provided. For example, a process may include obtaining multiple instructions, wherein the multiple instructions include a sequential order in which the processor executes the multiple instructions. A process may include determining that two or more of the multiple instructions can be fused. A process may include determining that a random variable satisfies an instruction fusion condition. A process may include executing two or more of the multiple instructions as a single fused instruction based on the determination that two or more of the multiple instructions can be fused and that the random variable satisfies the instruction fusion condition.

Description

Technical Field

[0001] Various aspects of this disclosure relate to systems and techniques for providing enhanced security for computing systems. For example, according to some aspects, the systems and techniques can adjust instruction execution to enhance security. Background Technology

[0002] Computing devices typically employ various techniques to protect data. As examples, encryption and decryption techniques can be applied to data in various scenarios, such as writing data to or reading data from storage devices, encrypting and decrypting data blocks and / or volumes, encrypting and decrypting digital content, and performing inline cryptographic operations. Such encryption and decryption operations are usually performed, at least in part, using secure information assets such as cryptographic keys and derived cryptographic keys. There are scenarios where attacks are launched to attempt to gain access to such secure information assets. Therefore, it is generally advantageous to implement systems and techniques that protect such secure information assets. Summary of the Invention

[0003] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Accordingly, the following summary presents certain concepts in a simplified form relating to one or more aspects of the mechanisms disclosed herein, preceding the detailed description that follows.

[0004] Systems, methods, apparatuses, and computer-readable media for adjusting instruction execution to enhance security are disclosed. According to at least one example, a method for secure computing is provided. The method includes: obtaining a plurality of instructions, wherein the plurality of instructions includes a sequential order in which the plurality of instructions are executed by a processor; determining that two or more of the plurality of instructions can be fused; determining that a random variable satisfies an instruction fusion condition; and, based on determining that the two or more of the plurality of instructions can be fused and that the random variable satisfies the instruction fusion condition, executing the two or more of the plurality of instructions as a single fused instruction.

[0005] In another example, an apparatus for secure computing is provided, the apparatus including at least one memory and at least one processor coupled to the at least one memory. The at least one processor is configured to: obtain a plurality of instructions, wherein the plurality of instructions include a sequential order in which the processor executes the plurality of instructions; determine that two or more of the plurality of instructions can be fused; determine that a random variable satisfies an instruction fusion condition; and, based on the determination that the two or more of the plurality of instructions can be fused and that the random variable satisfies the instruction fusion condition, execute the two or more of the plurality of instructions as a single fused instruction.

[0006] In another example, a non-transitory computer-readable medium having instructions stored thereon is provided, which, when executed by one or more processors, cause the one or more processors to: obtain a plurality of instructions, wherein the plurality of instructions includes a sequential order in which the processor executes the plurality of instructions; determine that two or more of the plurality of instructions can be fused; determine that a random variable satisfies an instruction fusion condition; and, based on the determination that the two or more of the plurality of instructions can be fused and that the random variable satisfies the instruction fusion condition, execute the two or more of the plurality of instructions as a single fused instruction.

[0007] In another example, an apparatus for secure computing is provided. The apparatus includes: components for obtaining a plurality of instructions, wherein the plurality of instructions include a sequential order in which the plurality of instructions are executed by a processor; components for determining that two or more of the plurality of instructions can be fused; components for determining that a random variable satisfies an instruction fusion condition; and components for executing the two or more of the plurality of instructions as a single fused instruction based on the determination that the two or more of the plurality of instructions can be fused and that the random variable satisfies the instruction fusion condition.

[0008] In some aspects, one or more of the devices described above are, are part of, or include the following: mobile devices (e.g., mobile phones or so-called "smartphones" or other mobile devices), wearable devices, extended reality devices (e.g., virtual reality (VR) devices, augmented reality (AR) devices, or mixed reality (MR) devices), personal computers, laptop computers, server computers, vehicles (e.g., computing devices of vehicles), or other devices. In some aspects, a device includes one or more cameras for capturing one or more images. In some aspects, the device includes a display for displaying one or more images, notifications, and / or other displayable data. In some aspects, the device may include one or more sensors. In some cases, the one or more sensors may be used to determine the position and / or orientation of the device, the state of the device, and / or for other purposes.

[0009] While aspects are described herein by way of example, those skilled in the art will understand that such aspects can be implemented in many different arrangements and scenarios. The techniques described herein can be implemented using different platform types, devices, systems, shapes, sizes, and / or package arrangements. For example, some aspects can be implemented via integrated chip implementations or other devices based on non-modular components (e.g., end-user equipment, vehicles, communication equipment, computing devices, industrial equipment, retail / shopping devices, medical devices, and / or artificial intelligence devices). Aspects can be implemented in chip-level components, modular components, non-modular components, non-chip-level components, device-level components, and / or system-level components. Devices incorporating the described aspects and features may include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals may include one or more components for analog and digital purposes (e.g., hardware components including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders, and / or summers). The aspects described herein are intended to be practiced in a wide variety of devices, components, systems, distributed arrangements, and / or end-user equipment of various sizes, shapes, and configurations.

[0010] This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in isolation to define the scope of the claimed subject matter. This subject matter should be understood with reference to the appropriate portions of the entire specification, any or all drawings, and each claim.

[0011] The foregoing, as well as other features and embodiments, will become more apparent from the following description, claims and drawings. Attached Figure Description

[0012] Examples of specific implementations are described in detail below with reference to the accompanying figures:

[0013] Figure 1 These are illustrations demonstrating how secure operations, according to some examples of this disclosure, can reveal specific moments in the processing of sensitive data;

[0014] Figure 2 This is a block diagram illustrating examples of computing devices according to some examples of this disclosure;

[0015] Figure 3A This is a block diagram illustrating the execution of example instructions to adjust the configuration according to some examples of this disclosure;

[0016] Figure 3B This is a diagram of a catalog of example idioms based on some examples of this disclosure;

[0017] Figure 3C This is a diagram of an additional catalog of example idioms based on some examples of this disclosure;

[0018] Figure 4 This is a diagram illustrating examples of instruction execution of the same instruction sequence with different numbers of instruction execution cycles, according to some examples of this disclosure;

[0019] Figure 5A This is a diagram illustrating the waveform of the effect of instruction execution, which varies according to some examples of this disclosure, on an example of a fault injection attack;

[0020] Figure 5B It includes a diagram illustrating the waveforms of example effects of executing a counter-channel attack based on some examples of the instructions in this disclosure;

[0021] Figure 6A This is a block diagram illustrating the execution of additional example instructions based on some examples of this disclosure to adjust the configuration;

[0022] Figure 6B This is a diagram of an additional catalog of example idioms based on some examples of this disclosure;

[0023] Figure 7 This is a flowchart illustrating examples of procedures for adjusting instruction execution according to some examples of this disclosure; and

[0024] Figure 8 This is a diagram illustrating an example of a computing system according to some examples of this disclosure. Detailed Implementation

[0025] Certain aspects and embodiments of this disclosure are provided below. Some of these aspects and embodiments may be applied independently, and some may be combined, as will be apparent to those skilled in the art. Specific details are set forth in the following description for purposes of explanation in order to provide a thorough understanding of the various embodiments of this application. However, it will be apparent, however, that the various embodiments may be practiced without these specific details. The accompanying drawings and descriptions are not intended to be limiting.

[0026] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of exemplary embodiments will provide those skilled in the art with enabling descriptions for implementing the exemplary embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of this application as set forth in the appended claims.

[0027] Computing devices typically employ various techniques to protect data. For example, encryption and decryption techniques can be applied to data in various scenarios, such as writing data to or reading data from storage devices, encrypting and decrypting data blocks and / or volumes, encrypting and decrypting digital content, and performing inline cryptographic operations. Such encryption and decryption operations are typically performed, at least in part, using secure information assets.

[0028] In some examples, secure information assets can be cryptographic keys, subkeys, secondary keys, derived cryptographic keys, and / or any other secure information assets used to encrypt and / or decrypt data and / or ensure the authenticity of data used by a computing device. Such secure information assets can be stored in a secure information storage device. In one exemplary example, secure information assets may include a private key for a symmetric cryptography (also referred to herein as a secret key) and / or a private key for an asymmetric cryptography. In some cases, the secure information storage device may include a secure information asset storage device (e.g., an one-time programmable (OTP) storage device, a non-volatile memory device, a flash memory device, etc.). Secure information assets may be obtained from the secure information asset storage device during the execution of the computing device (e.g., at startup, restart, and / or during updates), stored in a separate storage device, and provided as needed to security components (e.g., cryptographic engines, key tables, key derivation functions, etc.) for performing secure operations (e.g., encryption and / or decryption of data). The security information assets thus obtained can be used directly by any number of security components and / or can be used to derive additional security information assets (e.g., derived keys used by a cryptographic engine to encrypt and / or decrypt data), which is an example of a security operation. In some cases, without departing from the scope of this disclosure, a security operation may include additional steps or transformations using the security information assets.

[0029] In some respects, as discussed above, the security components of a computing device may require security information assets (e.g., cryptographic keys) to perform one or more security operations (e.g., encrypting and / or decrypting data, generating derived cryptographic keys, any other steps and / or transformations performed using the security information assets, etc.).

[0030] However, the use and / or repeated reuse of secure information assets can enable attackers to obtain all or any part of these assets using various techniques, potentially compromising the security of computing devices. For example, attackers could employ fault injection techniques (e.g., laser fault injection, power supply fault injection, volume bias injection). In some cases, fault injection techniques may be used to compromise the security of computing devices during a single operation.

[0031] In some cases, attackers can leverage machine learning (ML) models (e.g., deep learning neural networks) to aid in side-channel attacks. As an example, an attacker could perform a side-channel attack by using a measuring device (e.g., an oscilloscope) to measure any number of characteristics of a computing device during its operation (e.g., voltage, power, electromagnetic output, timing information, sound, temperature, etc.). In some aspects, side-channel attacks based on statistical data analysis (also referred to herein as statistical side-channel attacks) may be particularly useful when security operations are performed multiple times. For example, a statistical side-channel attack could include measuring one or more characteristics of a computing device while performing multiple operations that transmit the same and / or related security information assets, and / or performing operations using the same and / or related security information assets as operands (collectively referred to herein as security operations), potentially enabling an attacker to obtain all or any part of the security information assets, thereby potentially compromising the security of the computing device.

[0032] In some cases, if an attacker can determine the timing of the operation delivering the secure operation, the measurement device can capture the characteristics of the computing device at high resolution on a timescale. In some cases, the amount of data an attacker can capture may be limited by the amount of storage available in the measurement device. In an exemplary example, the oscilloscope may include a measurement buffer (e.g., memory) capable of storing up to one million measurements. In some cases, if an attacker can determine the timing of a 100ms secure operation within one millisecond (ms), the measurement timescale may be approximately 100 nanoseconds (ns). However, if the attacker does not know the timing of the 100ms operation, the measurement timescale (e.g., 1 microsecond, 10 microseconds, and / or any other suitable timescale) can be significantly longer than when the timing information is known. In some cases, for longer measurement timescales, the data delivery, data storage, and / or data processing requirements for storing and processing on the attacker's device (e.g., high-order differential power analysis, deep learning ML attacks, etc.) to extract useful information relative to attacks with known timing information may be significantly more expensive.

[0033] In some cases, when a cryptographic key is being sent and / or received (e.g., when it is obtained from a security information asset storage device at startup, when it is obtained from a different storage device, when it is provided to a security component for performing security operations, etc.), used to derive other cryptographic keys, an attacker who performs a side-channel attack or fault injection attack may be able to deduce that cryptographic key and thus be able to use the key to decrypt data on a computing device and / or encrypt potentially malicious data using the correct key, which can then be used by the computing device.

[0034] Many techniques have been developed to reduce the vulnerability of security operations to side-channel attacks. For example, some techniques may include hiding security operations, applying constant timing, applying variable timing, executing dedicated operations, adding redundant operations (e.g., dummy operations), etc. However, in some cases, security operations may still be identifiable due to the similarity of instructions executed at different times. In some cases, one or more techniques can be implemented in the software executed by the computing system. Therefore, it would be beneficial to provide systems and techniques that reduce the similarity of operations executed under different types to improve security against side-channel attacks.

[0035] This document describes systems, apparatuses, electronic devices, methods (also referred to as processes), and computer-readable media (collectively referred to herein as "systems and technologies") used to modify instruction execution to increase security. In some aspects, modifying instruction execution (e.g., by changing the number of clock cycles used to execute instructions) may result in changes in signal timing that can be detected by an attacker.

[0036] In some cases, the systems and techniques described herein may fuse instructions during the instruction decoding and / or execution phases. In some specific implementations, adjusting instruction execution may include fusing two (or more) instructions that are typically decoded and / or executed sequentially (e.g., in sequential cycles) into a single instruction that can be executed simultaneously. As used herein, “fusion” refers to combining the decoding and / or execution of two or more ISA instructions into a single instruction. For example, the instructions included in a processor’s instruction set architecture (ISA) are typically executed sequentially by the processor. As used herein, the instructions included in a processor’s ISA may be referred to as ISA instructions.

[0037] In some examples, the systems and techniques described herein can determine that two ISA instructions scheduled for sequential execution may be compatible for fusion. For example, the systems and techniques can determine that two ISA instructions are compatible because they do not use the same hardware resources available within the processor (e.g., arithmetic logic unit (ALU), load / store unit (LSU), memory controller, branch unit, registers, etc.). As used herein, executing two ISA instructions simultaneously means, within at least one clock cycle, executing a first instruction of the two ISA instructions using a first subset of the hardware resources available to the processor and executing a second instruction of the two ISA instructions using a second subset of the hardware resources available to the processor, which is different from the first subset of the hardware resources available to the processor. In some specific implementations, more than two ISA instructions may be executed simultaneously without departing from the scope of this disclosure.

[0038] As used in this article, "idioms" refer to group instructions that are compatible with fusion. In some cases, fusion-compatible instructions may be included in an idiom catalog. In some aspects, when an idiom is detected during ISA instruction fetching, a random variable can be used to determine whether to fuse the ISA instructions included in the idiom or to execute the ISA instructions sequentially. In some cases, implementing instruction fusion can improve processor efficiency by reducing the total number of cycles required to execute fused instructions simultaneously, compared to executing the same instructions sequentially.

[0039] In some implementations, the system and techniques may include the splitting (e.g., partitioning) of instructions during decoding and / or execution. For example, splitting may include dividing an ISA instruction into two or more instructions. For example, an ISA instruction (e.g., addition + multiplication) may be replaced by two or more other ISA instructions (e.g., addition followed by multiplication). In some cases, the split catalog may include ISA instructions compatible with splitting. In some examples, a random variable may be used to determine whether to split an ISA instruction into multiple instructions or to execute the ISA instruction as a single instruction.

[0040] In some cases, by modifying instruction execution (e.g., performing ISA instruction fusion or ISA instruction splitting), similar operations performed at different times may be mistakenly perceived as different operations by an attacker. Therefore, modifying instruction execution can obfuscate security information assets, making it less likely for attackers (e.g., performing side-channel attacks, fault injection attacks, etc.) to identify all or any part of the security information assets, and thus less able to compromise the security of computing devices.

[0041] Various aspects of the systems and technologies described in this article will be discussed below with reference to the accompanying drawings.

[0042] Figure 1 The waveform 100 is illustrated as a security operation that might reveal timing information to an attacker. For example, an attacker might attempt to analyze waveform 100 to obtain information about one or more precise moments when the most sensitive security assets were processed. As shown, the power fluctuations between the start 105 and end 110 of an AES encryption operation (e.g., a secure operation) can differ from the power fluctuations before the start 105 and after the end 110 of the AES encryption operation, and can differ from the power fluctuations during the AES encryption operation. While AES encryption is provided as an example, other secure operations, including but not limited to number-theoretic transformation (NTT) computations, matrix-vector multiplication (A...), etc., are also possible. y), r and rG multiplication (e.g., elliptic curve point multiplication), events (e.g. for Elliptic Curve Digital Signature Algorithm (ECDSA)), secure hash algorithms (e.g., SHA-256, SHA-3), McEliece cryptography, bit-flipped key encapsulation (BIKE), Hamming quasi-cyclic (HQC) encryption, hash-based message authentication codes (e.g., HMAC-512), RNG seeding, and / or any combination thereof can also reveal information to an attacker through side-channel attacks.

[0043] Based on various examples, Figure 2 This is an illustration of an example computing device 200. The computing device 200 may include, but is not limited to, any of the following: one or more processors (e.g., components including integrated circuits, memory, input and output devices (not shown)), non-volatile storage hardware, one or more physical interfaces, any number of other hardware components (not shown), and / or any combination thereof. Examples of computing devices include, but are not limited to, mobile devices (e.g., laptops, smartphones, personal digital assistants, tablets, automotive computing systems, and / or any other mobile computing devices), Internet of Things (IoT) devices, servers (e.g., blade servers in blade server chassis, rack servers in racks, etc.), desktop computers, storage devices (e.g., disk drive arrays, Fibre Channel storage devices, Internet Small Computer System Interface (iSCSI) storage devices, tape storage devices, flash storage arrays, network-attached storage devices, etc.), network devices (e.g., switches, routers, multi-layer switches, etc.), wearable devices (e.g., network-connected watches or smartwatches, or other wearable devices), robotic devices, smart TVs, smart appliances, extended reality (XR) devices (e.g., augmented reality (AR), virtual reality (VR), etc.), any device including one or more SoCs, and / or any other type of computing device having the foregoing requirements. In one or more examples, any or all of the examples foregoing may be combined to create systems of such devices, which may be collectively referred to as computing devices. Other types of computing devices may be used without departing from the scope of the examples described herein.

[0044] like Figure 2 As illustrated, computing device 200 may include one or more antennas 202, one or more wireless communication modules 206, processor 210, memory 214, application module 218, user interface 250, microphone / speaker 252, keypad 254, display 256, secure information storage device 270, trusted execution environment 280, and security component 290.

[0045] As shown in the figure, computing device 200 may include one or more wireless communication modules 206 that can be connected to one or more antennas 202. The one or more wireless communication modules 206 include suitable devices, circuits, hardware and / or software for communicating with access points, networks, base stations and / or detecting signals to / from access points, networks, base stations and / or for communicating directly with other wireless devices within the network.

[0046] In some implementations, one or more wireless communication modules 206 may include a communication system (e.g., a CDMA system) suitable for communicating with a network of wireless base stations (e.g., a CDMA network). In some implementations, the wireless communication system may include other types of cellular telephone networks, such as TDMA, GSM, WCDMA, 4G / LTE, 5G / NR, etc. Additionally, any other type of wireless networking technology may be used, including, for example, WiMax (802.16), Wi-Fi (802.11), etc.

[0047] Processor (also referred to as controller) 210 may be connected to one or more wireless communication modules 206. Processor 210 may include one or more microprocessors, microcontrollers, and / or digital signal processors that provide processing functions as well as other computing and control functions. Processor 210 may be coupled to a storage medium (e.g., memory) 214 for storing data and software instructions for executing programmed functions within a mobile device. Memory 214 may be on processor 210 (e.g., within the same IC package), and / or memory may be external memory of the processor and functionally coupled via a data bus.

[0048] Multiple software engines and data tables may reside in memory 214 and may be utilized by processor 210 to manage communications, perform location determination functionality, and / or perform device control functionality. In some cases, memory 214 may include application module 218. It should be noted that the functionality of modules and / or data structures may be combined, separated, and / or structured in different ways depending on the specific implementation of computing device 200.

[0049] Application module 218 may include a process running on processor 210 of computing device 200 that may request data from one of the other modules of computing device 200. Applications typically run at higher layers of the software architecture and can be implemented in the rich execution environment of computing device 200, and may include indoor navigation applications, shopping applications, financial services applications, social media applications, location-aware service applications, etc.

[0050] In some examples, computing device 200 includes a secure information storage device 270. In some examples, secure information storage device 270 can be any storage device configured to store secure information assets (e.g., cryptographic keys, metadata, etc.). For example, secure information storage device 270 is a device that stores secure information assets and is first retrieved from it when needed on the computing device (e.g., for encrypting and / or decrypting data). In some cases, secure information storage device 270 may include a key repository or key table. Examples of secure information storage device 270 include, but are not limited to, various types of read-only memory, one-time programmable memory devices (e.g., one-time programmable fuses or other types of one-time programmable memory devices), non-volatile memory, etc. Secure information storage device 270 is operatively connectable to trusted execution environment 280 and / or security component 290. Although Figure 2 The computing device 200 is shown as including a single secure information storage device 270, but without departing from the scope of the examples described herein, the computing device 200 may include any number of secure information storage devices.

[0051] Processor 210 may include a Trusted Execution Environment 280. The Trusted Execution Environment 280 may also be referred to as a Trusted Management Environment, Trust Zone, Trusted Platform Module, etc. The Trusted Execution Environment 280 may be implemented as a secure area of ​​processor 210, which can be used to process sensitive data and store such sensitive data in an environment separate from the Rich Execution Environment, where operating systems and / or applications (such as those of application module 218) can execute. The Trusted Execution Environment 280 may be configured to execute secure applications (also referred to as trusted applications) that provide end-to-end security for sensitive data by enforcing confidentiality, integrity, and protection on the sensitive data stored therein. The Trusted Execution Environment 280 may be used to store encryption keys, access tokens, and other sensitive data.

[0052] Computing device 200 may include one or more security components 290. In some cases, security component 290 may be referred to as a trusted component, secure element, trusted element, etc. Computing device 200 may include security component 290 as a complement to or alternative to trusted execution environment 280. Security component 290 may include autonomous and tamper-proof hardware that can be used to execute secure applications and confidential data associated with such applications. Security component 290 may be used to store encryption keys, access tokens, and other sensitive data. Security component 290 may include near field communication (NFC) tags, subscriber identity module (SIM) cards, or other types of hardware devices that can be used to securely store data. Security component 290 may be integrated with the hardware of computing device 200 in a permanent or semi-permanent manner, or in some implementations, it may be a movable component of computing device 200 that can be used to securely store data and / or provide a secure execution environment for applications.

[0053] Examples of security applications that can be executed by computing device 200, processor 210, secure information storage device 270, trusted execution environment 280, security component 290, and / or any combination thereof include, but are not limited to, encrypting data, decrypting data, key derivation, performing data integrity verification, and performing authenticated encryption and decryption. In some examples, computing device 200 and / or portions thereof may be configured to perform various cryptographic service types by being configured to execute one or more cryptographic algorithms. For example, to perform encryption and decryption, one or more components of computing device 200 (e.g., secure information storage device 270, trusted execution environment 280, security component 290) may be configured to perform one or more of the following: Advanced Encryption Standard XOR-Encryption-XOR Adjustable Block Ciphertext Stealing (AES-XTS) algorithm, AES-Cryptographic Block Chaining (AES-CBC) algorithm, AES-Electronic Codebook (AES-EBC) algorithm, Cryptographic Salt-Sector Initialization Vector-AES-CBC (ESSIV-AES-CBC) algorithm, etc., including any variants of such algorithms (e.g., 128-bit, 192-bit, 256-bit, etc.). As another example, to perform integrity verification, one or more components of computing device 200 may be configured to perform hash algorithms, such as one or more members of the SHA family of hash algorithms. As yet another example, to perform authenticated encryption, one or more components of computing device 200 may be configured to perform the AES-Galois / Counter Mode (GCM) algorithm. In some respects, without departing from the scope of the examples described herein, one or more components of computing device 200 may be configured to perform any other cryptographic algorithms.

[0054] The computing device 200 may also include a user interface 250 that provides a suitable interface system enabling a user to interact with the computing device 200, such as a microphone / speaker 252, a keypad 254, and / or a display 256. The microphone / speaker 252 may provide voice communication services (e.g., using one or more wireless communication modules 206). The keypad 254 may include suitable buttons for user input. The display 256 may include a suitable display, such as, for example, a backlit LCD display, and may also include a touchscreen display for additional user input modes.

[0055] Although Figure 2 A specific number of components in a particular configuration is shown; however, those skilled in the art will understand that the computing device 200 may include more or fewer components, and / or components arranged in any number of alternative configurations, without departing from the scope of the examples described herein. Furthermore, although Figure 2 Although not shown, those skilled in the art will understand that computing device 200 can execute any amount or type of software or firmware (e.g., bootloader, operating system, hypervisor, virtual machine, computer application, mobile device application, etc.). Therefore, the examples disclosed herein should not be limited to... Figure 2 The configuration of the components shown. Figure 2 The components shown may or may not be discrete components. In some aspects, one or more of these components may be combined into distinct hardware elements, implemented in software, and / or otherwise implemented using software and / or hardware. As used herein, the term "device" may be a discrete component or apparatus, or may not be a discrete component. In some aspects, other devices may exist within, be part of, and / or utilize the same hardware components as the device.

[0056] Figure 3A This is a block diagram illustrating an example instruction execution adjustment configuration 300 used for adjusting instruction execution. As illustrated in the figure, Figure 3A Example instruction execution adjustment configuration 300 may include randomization engine 304 and idiom catalog 306. In the illustrated example, it is possible to adjust the configuration in the processor (e.g., Figure 2 Processor 210, Trusted Execution Environment 280 and / or Security Component 290, Figure 8 During the fetch operation 305 of the processor 810, four instructions 302 are fetched. Figure 3A In the illustrated example, the index n (where n is an integer) can represent the order of the sequence of operation cycles to be executed by the processor. For example, in the operation sequence, the operation with index n-2 can be executed immediately before the operation with index n-1. Figure 3AIn the illustrated example, the four instructions 302 fetched during fetch operation 305 may include instructions n-2, n-1, n, and n+1. In some cases, the four instructions 302 may include processor ISA instructions.

[0057] In some examples, the randomization engine 304 may include a random number generator (RNG), a pseudo-random number generator (PRNG), etc. In some cases, the randomization engine 304 may generate a random number that can be used to determine whether fusion-compatible instructions will be fused into a single operation or executed sequentially (e.g., according to a sequence of indices n). In the illustrated example, the random number output of the randomization engine 304 may be represented by the variable rand.

[0058] In some specific implementations, the idiom catalog 306 may include instructions as fusion candidates. Figure 3B This is a diagram of example idiom catalog 350, which provides idioms that can be obtained from... Figure 3A The instructions for executing the adjustment configuration 300 are an exemplary example of the idioms used in the catalog. Figure 3B In the example, the idiom catalog 350 includes an idiom list 352 and corresponding instruction fusion candidate operations 354. For example, line 362 of the idiom catalog 350 includes idioms for index loading. As illustrated, index loading idioms may correspond to an addition operation followed by an ld (load) operation. In another example, line 364 of the idiom catalog 350 includes idioms for loading pairs. As illustrated, loading pairs of idioms may correspond to two consecutive ld (load) operations. In another example, line 366 of the idiom catalog 350 includes idioms for storing pairs. As illustrated, storing pairs of idioms may correspond to two consecutive st (store) operations. Although... Figure 3B The catalog of example idioms 350 provides examples of idioms corresponding to pairs of instructions, but in some cases, idioms corresponding to three or more instructions may be used without departing from the scope of this disclosure.

[0059] Back Figure 3A The four instructions 302, the variable rand output by the randomization engine 304, and the idiom directory 306 can be input into the instruction fusion decision engine 308.

[0060] In some implementations, the instruction fusion decision engine 308 may determine whether four instructions 302 include those satisfying one or more instruction fusion conditions. As used herein, executing two ISA instructions simultaneously means executing the first instruction of the two ISA instructions using a first subset of the processor's available hardware resources and executing the second instruction of the two ISA instructions using a second subset of the processor's available hardware resources, which is different from the first subset of the processor's available hardware resources, within at least one clock cycle. Herein, an instruction fusion condition refers to a condition used to determine whether two or more instructions are fused. For example, a first instruction fusion condition (also referred to herein as a first condition) may include determining whether two or more consecutive instructions correspond to an idiom in the idiom list 352 of the idiom catalog 350. For example, for the first instruction of four instructions 302 (e.g., instruction n-2), the instruction fusion decision engine 308 may determine whether one or more instructions following the first instruction are included in the idiom catalog 306. In some cases, if the instruction fusion decision engine 308 determines that the first instruction and one or more instructions following the first instruction are included in the idiom catalog, the instruction fusion decision engine 308 may determine that the first condition (e.g., "Is it in the catalog?") is "true" for the first instruction. However, if the instruction fusion decision engine 308 determines that the second instruction following the first instruction (e.g., instruction n-1) is not part of any idiom in the idiom catalog 306, the instruction fusion decision engine 308 may determine that the first condition is "false" for the first instruction. In some cases, the instruction fusion decision engine 308 may not be able to determine the first condition for the final instruction obtained during the extraction operation 305 (e.g., instruction n+1) because the instruction fusion decision engine 308 may lack sufficient information (e.g., instruction n+2) to determine whether the final instruction is part of an idiom in the idiom catalog 306.

[0061] In some implementations, for instruction combinations for which the instruction fusion decision engine 308 determines the first condition to be "true", the instruction fusion decision engine 308 may obtain a random value for the variable rand. In the illustrated example, rand may be a binary number whose value may be zero (0) (e.g., logical false) or one (1) (e.g., logical true). In some aspects, if the instruction fusion decision engine 308 determines that the value of rand for a specific instruction combination in the catalog is equal to one (e.g., rand == 1), then the instruction fusion decision engine 308 may determine that the second instruction fusion condition (also referred to herein as the second condition) is "true". However, if the instruction fusion decision engine 308 determines that the value of rand for a specific instruction combination in the catalog is equal to zero (e.g., rand == 0), then the instruction fusion decision engine 308 may determine that the second condition is "false".

[0062] In some cases, the instruction fusion decision engine 308 may repeat the process of determining whether the first condition is "true" for each of the four instructions 302. In some cases, for each of the four instructions 302 where the first condition is "true", the instruction fusion decision engine 308 may determine whether the second condition is "true".

[0063] However, in some cases, once two or more instructions are merged into a single merged instruction, the instruction fusion decision engine 308 can be excluded from fusion consideration. In some cases, the instruction fusion decision engine 308 can bypass the check of whether the first condition is "true" for instructions included in a previously unchecked single merged instruction. In an exemplary example, if the instruction fusion decision engine 308 determines that the first condition is "true" for a first instruction followed by a second instruction and the second condition is "true" for a first instruction followed by a second instruction, the fusion decision engine 308 can combine the first and second instructions into a single merged instruction. In some examples, after combining the first and second instructions into a single merged instruction, the instruction fusion decision engine 308 can bypass the check of whether the first condition is "true" for the second instruction.

[0064] exist Figure 3A The exemplary example illustrates two distinct sequences of decoding operation 315 and execution operation 325. In some cases, the two distinct decoding operation sequences 315 may include determining which processor hardware resources (e.g., arithmetic logic unit (ALU), load / memory unit (LSU), memory controller, branch unit, registers, etc.) will be used to execute instructions and / or capture operands for the instructions to be executed. In some aspects, execution operation 325 may include using the compute module and / or any retrieved operands to execute the decoded instructions.

[0065] In the first illustrated sequence 310 (as indicated by the arrow marked "No"), a decoding operation sequence 312 and an execution operation sequence 314 are illustrated for the case where the instruction fusion decision engine 308 determines that none of the instructions in the four instructions 302 satisfy the first and second conditions. In some cases, the first illustrated sequence 310 may correspond to the case where the four instructions 302 do not contain any idioms. In some examples, the first illustrated sequence 310 may correspond to the case where one or more of the four instructions 302 include idioms, but for each event where two or more instructions correspond to idioms in the catalog, the value or rand obtained by the instruction fusion decision engine 308 is zero (0). As illustrated in the first illustrated sequence 310, decoding operations can be performed sequentially on each of the four instructions 302 (e.g., instructions n-2, n-1, n, and n+1). In the illustrated example, the execution of the instructions can be performed in one cycle after decoding the corresponding instruction. For example, instruction n-2 can be executed during the decoding of instruction n-1, instruction n-1 can be executed during the decoding of instruction n, and so on. Therefore, in Figure 3A In the example shown, the execution of instruction n+1 can occur four cycles after the decoding instruction n-2.

[0066] In the second illustrated sequence 320, a decoding operation sequence 322 and an execution operation sequence 324 are illustrated for the instruction fusion decision engine 308 to determine that the first condition (e.g., included in the idiom catalog 306) and the second condition (e.g., rand equals one (1)) are "true" for a particular instruction (e.g., instruction n-1). In the illustrated example, the execution of the instruction can be performed in one cycle after decoding the corresponding instruction. However, as illustrated, instruction n-1 and instruction n can be fused into a single decoding operation 326 and a single execution operation 328. In the decoding operation sequence 322, the instruction fusion decision engine 308 can decode instruction n-2 during a first decoding cycle, then decode the fused instruction including instruction n-1 and instruction n during a second decoding cycle, and finally decode instruction n+1 during a third decoding cycle. Similarly, in execution operation sequence 324, instruction fusion decision engine 308 may execute instruction n-2 during the first decoding cycle, then execute a fused instruction including instructions n-1 and n during the second execution cycle, and finally execute instruction n+1 during the third execution cycle. In the illustrated example, instruction fusion decision engine 308 may execute instruction n-2 during the same cycle as decoding instructions n-1 and n. As shown, instruction fusion decision engine 308 may execute a fused instruction including instructions n-1 and n while decoding instruction n+1. As illustrated in execution operation sequence 324, execution of instruction n+1 may occur three cycles after decoding instruction n-2. Figure 3AIn the examples, the first illustrated sequence 310 and the second illustrated sequence 320 demonstrate how instruction fusion can lead to changes in operation timing, which can potentially confuse attackers attempting to perform side-channel attacks and / or fault injection attacks. In some specific implementations, executing instructions n-1 and n as a single fused instruction reduces the total number of instructions executed by the processor. For example, the second illustrated sequence 320 comprises three execution cycles, while the first illustrated sequence 310 comprises four execution cycles. Therefore, instruction fusion reduces the total number of operations performed by the processor while enhancing security.

[0067] although Figure 3A The example illustrates the use of instruction execution adjustment configuration 300 for instruction fusion. In some cases, instruction execution adjustment configuration 300 may be additionally or alternatively used to perform other types of instruction execution adjustments. For example, in some cases, instruction execution adjustment configuration 300 may be used to perform instruction splitting. In some specific implementations, performing instruction splitting may be suitable in the ISA environment of a Complex Instruction Set Computer (CISC). In some cases, the ISA of a CISC processor may include functional ISA instructions that combine two or more other ISA instructions. In an exemplary example, ISA instructions may include two or more operations (e.g., addition and multiplication instructions) to be performed in a single cycle of the processor, which may also be performed as two or more ISA instructions (e.g., addition instructions, multiplication instructions) during consecutive cycles to produce different execution timings.

[0068] refer to Figure 3C The split directory 380 may include a list of split candidate instructions 382 and corresponding split instruction operations. For example, the first split candidate instruction 386 may be a multiplication / accumulation operation, while the corresponding split instruction operation may be a multiplication operation and a separate accumulation operation. Additional example split candidate instructions 382 may include, but are not limited to, pre-increment load, post-increment load, pre-decrement load, post-decrement load, pre-increment store, post-increment store, pre-decrement store, or post-decrement store.

[0069] Back Figure 3A The instruction execution adjustment configuration 300 can determine whether each of the four instructions 302 extracted during the extraction operation 305 is included. Figure 3CThe list of split candidate instructions 382 in the idiom directory 380. In some examples, if the instruction execution adjustment configuration 300 determines that an instruction is included in the list of split candidate instructions 382 in the idiom directory 380, the instruction execution adjustment configuration 300 may determine that the first condition (e.g., "Is it in the directory?") is "true". In some cases, for each of the four instructions 302 determined to be in the directory, the instruction execution adjustment configuration 300 may obtain the value of the random variable rand from the randomization engine 304. If the value of the random variable rand for the instruction included in the directory is equal to one (1), the instruction execution adjustment configuration 300 may determine that the second condition is "true" (e.g., rand == 1). In some cases, if both the first and second conditions are "true" for the instruction, the instruction execution adjustment configuration 300 may sequentially decode and / or execute the split instruction operation 384 corresponding to the split candidate instruction 382.

[0070] Figure 4 Figure 400 illustrates examples of instruction execution of the same instruction sequence with different numbers of instruction execution cycles. Figure 4 The illustrated example shows a sequence 410 of twelve instructions that begins with instruction n-2 and ends with instruction n+9. In some cases, instruction sequence 410 may represent the order in which the processor acquires instructions during one or more fetch operations. For example, sequence instruction 410 may include three sets of four instructions acquired during three consecutive fetch operations (e.g., Figure 3A The four instructions (302). In Figure 4 In the illustrated example, three different sets of consecutive instructions and idiom catalogs (e.g., Figure 3A 306. (List of common phrases) Figure 3B The idioms included in the idiom catalog (350) are matched. As illustrated in the figure, the sequence of instruction n-1 followed by instruction n corresponds to the first idiom and is marked as "match 1". Similarly, the sequence of instruction n+3 followed by instruction n+4 and then further followed by instruction n+5 corresponds to the second idiom and is marked as "match 2". In an additional example, the sequence of instruction n+8 followed by instruction n+8 corresponds to the third idiom and is marked as "match 3".

[0071] In some cases, the sequence 410 of twelve instructions may also correspond to a sequence of decoding and / or executing the sequence 410 of twelve instructions. For example, the sequence 410 of twelve instructions may correspond to a sequence of decoding and / or executing those twelve instructions, wherein none of the instructions are included in the fusion instructions (e.g., Figure 3A(The first illustrated sequence 310). For example, if the value of the variable rand is equal to zero for each of “match 0”, “match 1”, and “match 2” (e.g., rand == 0), then the sequence 410 of twelve instructions may correspond to a sequence for decoding and / or executing those twelve instructions. Thus, the sequence 410 of twelve instructions may include sequential execution 412 corresponding to the first idiom, sequential execution 414 corresponding to the second idiom, and sequential execution 416 corresponding to the third idiom.

[0072] exist Figure 4 In an exemplary example, the second instruction sequence 420 may represent the execution order of an extracted sequence of twelve instructions 410, wherein the fusion of instructions 422 corresponds to the first idiom, the fusion of instructions 424 corresponds to the second idiom, and the sequential execution of instructions 426 corresponds to the third idiom. In some cases, for instructions corresponding to the first and second idioms, the second instruction sequence 420 may correspond to a rand value equal to one (e.g., rand == 1), and for instructions corresponding to the third idiom, the second instruction sequence may correspond to a rand value equal to zero (e.g., rand == 0).

[0073] As illustrated in the figure, the third instruction sequence 430 can represent the execution order of the extracted sequence of twelve instructions 410, wherein the sequential execution of instructions 432 corresponds to the first idiom, the fusion of instructions 434 corresponds to the second idiom, and the sequential execution of instructions 436 corresponds to the third idiom. In some cases, for instructions corresponding to the second idiom, the third instruction sequence 430 can correspond to the value of rand being equal to one (e.g., rand == 1), and for instructions corresponding to both the first and third idioms, the third instruction sequence can correspond to the value of rand being equal to zero (e.g., rand == 0).

[0074] exist Figure 4 In the illustrated example, the arrows between the twelve-instruction sequence 410, the second instruction sequence 420, and the third instruction sequence 430 are used to highlight the difference in execution timing of instruction n+6. Although not highlighted, the first instruction sequence 410, the second instruction sequence 420, and the third instruction sequence 430 may also cause differences in the execution timing of other instructions, such as... Figure 4 exemplified.

[0075] Figure 5A Figure 500 illustrates a waveform showing the example impact of modified instruction execution on a fault injection attack. Figure 5AIn the illustrated example, the first waveform 502 illustrates the relative timing of the trigger 512 and the concern 514 within the execution of security operation 510. For example, concern 514 could represent the timing of performing fault injection (e.g., laser fault injection) to achieve a desired result (e.g., bypassing authentication operations). Figure 5A In the example shown, the timing of trigger 512 is aligned with all waveforms in waveforms 502, 504, 506, and 508.

[0076] As illustrated, waveform 504 represents the execution of an instruction, which is a modified execution, where peak 522 in waveform 504 corresponds to point of interest 514 in waveform 502, but with a different time offset relative to trigger 512. Similarly, waveform 506 represents the execution of an instruction, which is a modified execution, where peak 524 corresponds to point of interest 514 in waveform 502, but with a different time offset relative to trigger 512. However, waveform 508 represents the execution of an instruction, which is a modified execution, where peak 526 corresponds to point of interest 514 in waveform 502, but with the same time offset relative to trigger 512. In some cases, the timing differences of trigger 512 relative to point of interest 514, peak 522, peak 524, and peak 526 may be based on instruction fusion and / or splitting (e.g., by means of...). Figure 3A The instruction execution configuration is adjusted (300), resulting in different instruction execution timings.

[0077] Figure 5B Figure 550 shows a waveform illustrating the example impact of a side-channel attack on the execution of an example change instruction. Figure 5B In the illustrated example, waveform 552 illustrates the execution of an operation that may include concern 560, which could be targeted by an attacker in a side-channel attack. As illustrated, waveforms 554 and 556 illustrate the execution of the same operation as illustrated in waveform 502, but with one or more instruction execution adjustments that differ from the instruction execution illustrated in waveform 502 (e.g., via...). Figure 3A The instruction execution adjustment configuration 300). In some cases, attackers may exploit the averaging of repeatedly executed operations to improve the signal-to-noise ratio (SNR) of concern 560. However, as Figure 5B As illustrated, the sum of waveforms 552, 554, 556, and multiple other repetitions of the same operation performed with varying instructions, totaling 558, may, when averaged, appear noisy and / or otherwise appear to belong to instructions different from waveform 552. In some cases, the average of waveforms 552, 554, 556, and other repetitions of the same operation can be determined by dividing the sum of the waveforms 558 by the total number of waveforms. Figure 5BAs illustrated, using different instruction execution based on instruction execution adjustments can prevent attackers from successfully executing side-channel attacks.

[0078] Figure 6A This is a block diagram illustrating the execution of additional example instructions to adjust configuration 600. Figure 6A In the example, the four instructions 602 can correspond to Figure 3A The four instructions 302 and the randomization engine 604 can correspond to Figure 3A The randomization engine 304, the first illustrated sequence 610 can correspond to Figure 3A The first illustrated sequence 310, the decoding operation sequence 612 can correspond to Figure 3A The decoding operation sequence 312, operation 614 can correspond to Figure 3A Operation 314, the second illustrated sequence 620 can correspond to Figure 3A The second illustrated sequence 320, the decoding operation sequence 622 can correspond to Figure 3A The decoding operation sequence 322 and the execution operation sequence 624 can correspond to Figure 3A The execution sequence is 324.

[0079] refer to Figure 6B The idiom catalog 650 can correspond to Figure 6A The list of common phrases is 606. Figure 6B In the example shown, idiom list 652 can correspond to Figure 3B The list of idioms 352, and the corresponding instruction fusion candidate operation 654 can correspond to Figure 3B The corresponding instruction fusion candidate operation is 354. In Figure 6B In the illustrated example, the idiom catalog 650 may include an additional idiom enable value 656 corresponding to each idiom in the idioms 652.

[0080] In the illustrated example, with Figure 3A Similar to the instruction fusion decision engine 308, the instruction fusion decision engine 608 can be used to determine whether a first condition (e.g., "Is it in the directory?") is "true" and whether a second condition (e.g., rand == 1) is "true". However, as Figure 6AAs illustrated, the instruction fusion decision engine 608 can also be configured to determine whether a third fusion condition (e.g., "Is the idiom enabled?") is "true". As used herein, the third fusion condition is also referred to as the third condition. For example, if the additional example instruction execution adjustment configuration 600 determines that the idiom enable value 656 corresponding to idiom 652 in the idiom catalog 650 is equal to one (1), then the additional example instruction execution adjustment configuration 600 can determine that the third condition is "true". In some cases, the idiom enable value 656 can be determined at runtime to introduce further diversification between several executions of a particular operation of interest (e.g., a security operation). In some cases, if the additional example instruction execution adjustment configuration 600 determines that the first, second, and third conditions are "true", then the additional example instruction execution adjustment configuration 600 can replace the instructions included in the idioms of the idiom catalog 606 with the corresponding instruction fusion candidate operation 654 included in the idiom catalog 606. In some cases, it is possible to... Figure 3A The command execution adjusts the configuration 300. Figure 3B 350 and / or Figure 3C The instruction execution adjustment described in the idiom catalog 380 is similar to the adjustment of the decoding operation 615 and / or the execution operation 625 by attaching example instruction execution adjustment configuration 600 (e.g., merging and / or splitting).

[0081] Figure 7 This is a flowchart illustrating an example of wireless communication process 700. Process 700 and / or other processes described herein may be performed by a computing device (or apparatus) or a component of a computing device (e.g., chipset, codec, etc.). The computing device may be an extended reality (XR) device (e.g., a virtual reality (VR) device or an augmented reality (AR) device), a mobile device (e.g., a mobile phone), a network-connected wearable device such as a watch, a vehicle or a component or system of a vehicle, or other types of computing devices. In one example, process 700 and / or other processes described herein may be performed by... Figure 2 The computational device 200 performs the operation. In another example, one or more processes may be performed by... Figure 8 The computing system 800 shown is executed. For example, it has... Figure 8 The computing device of the computing system 800 shown may include Figure 2 The components of the computing device 200, and are implementable Figure 7 The operation of process 700 and / or other processes described herein. The operation of process 700 may be implemented in one or more processors (e.g., Figure 8Software components executed and running on the processor 810, processors such as DSPs, GPUs, NPUs, etc., or other processors. Furthermore, in process 700, the transmission and reception of signals by the computing device may be achieved, for example, through one or more antennas, one or more transceivers (e.g., multiple wireless transceivers), and / or other communication components of the computing device (e.g., Figure 8 It is implemented using the communication interface 840.

[0082] At box 702, the computing device (or a component thereof) has access to a plurality of instructions. In some aspects, these plurality of instructions include instructions generated by a processor (e.g., Figure 2 The processor 210, trusted execution environment 280, and security component 290 execute multiple instructions (e.g., Figure 3A Execution sequence 314 Figure 6A The execution sequence of operations (614) is ordered. In some respects, each of these multiple instructions is included in the processor's ISA.

[0083] At box 704, the computing device (or its components) can (e.g., via...) Figure 3A Command fusion decision engine 308 Figure 6A The instruction fusion decision engine 608 determines that two or more of the multiple instructions can be fused (e.g., corresponding to...). Figure 3B (Idioms in the 350-word idiom catalog).

[0084] At box 706, the computing device (or a component thereof) can determine that a random variable satisfies the instruction fusion condition. In some aspects, determining that the random variable satisfies the instruction fusion condition includes determining that the value of the random variable is one (1) or true.

[0085] At box 708, the computing device (or its components) may execute two or more of the multiple instructions as a single fused instruction based on the determination that two or more of the instructions can be fused and that the random variable satisfies the instruction fusion condition (e.g., Figure 3A (Single execution operation 328). In some cases, the processor is configured to execute the two or more instructions simultaneously. In some examples, executing the two or more instructions as a single fused instruction reduces the total number of operations performed by the processor, relative to executing the two or more instructions sequentially.

[0086] In some respects, two or more of the plurality of instructions comprise two instructions. In some cases, executing two or more of the plurality of instructions as a single fused instruction includes combining the two instructions into a single instruction. In some respects, the two instructions are executed simultaneously by different hardware components of the processor.

[0087] In some examples, a catalog of idioms (e.g., Figure 3B The idiom catalog 350 includes multiple idioms. In some cases, each of the multiple idioms includes a sequence of two or more instructions that can be merged and a corresponding merging instruction for that sequence of two or more instructions that can be merged.

[0088] In some cases, the computing device (or its components) may determine that a first additional instruction among the plurality of instructions cannot be fused with a second additional instruction among the plurality of instructions. In some examples, the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions, according to the order in which the processor executes the plurality of instructions. In some examples, the computing device (or its components) may, based on the determination that the first additional instruction among the plurality of instructions cannot be fused with the second additional instruction among the plurality of instructions, execute the first additional instruction sequentially after executing the single fused instruction.

[0089] In some implementations, the computing device (or its components) may determine that a first additional instruction among the plurality of instructions can be fused with a second additional instruction among the plurality of instructions. In some cases, the second additional instruction among the plurality of instructions follows the first additional instruction among the plurality of instructions in the order in which the processor executes the plurality of instructions. In some examples, the computing device (or its components) may determine that a second random variable does not satisfy the second instruction fusion condition. In some aspects, the computing device (or its components) may, based on the determination that the second random variable does not satisfy the second instruction fusion condition, execute the first additional instruction among the plurality of instructions sequentially after executing the single fusion instruction. In some implementations, the computing device (or its components) may execute the second additional instruction among the plurality of instructions sequentially after executing the first additional instruction among the plurality of instructions. In some aspects, to determine that the second random variable does not satisfy the second instruction fusion condition, the processor may further determine that the value of the random variable is zero (0) or false.

[0090] In some examples, the processes described herein (e.g., process 700 and / or other processes described herein) may be performed by a computing device or apparatus (e.g., computing device 200). In another example, they may be performed by a device having Figure 8 The computing device execution process 700 of the computing system 800 shown is executed.

[0091] Figure 8 This is a diagram illustrating an example of a computing system used to implement certain aspects of this technology. Specifically, Figure 8An example of computing system 800 is provided, which can be any computing device, such as an internal computing system, a remote computing system, a camera, or any component thereof, wherein the components of the system communicate with each other using connection 805. Connection 805 can be a physical connection using a bus, or a direct connection to processor 810, such as in a chipset architecture. Connection 805 can also be a virtual connection, a networking connection, or a logical connection.

[0092] In some embodiments, the computing system 800 is a distributed system, wherein the functions described herein may be distributed across a data center, multiple data centers, a peer-to-peer network, etc. In some embodiments, one or more of the described system components represent a plurality of such components, each performing some or all of the functions described for that component. In some embodiments, the components may be physical devices or virtual devices.

[0093] Example computing system 800 includes at least one processing unit (CPU or processor) 810 and a connection 805 that communicatively couples various system components, including system memories 815 such as read-only memory (ROM) 820 and random access memory (RAM) 825, to processor 810. Computing system 800 may include a cache 812 of high-speed memory directly connected to, closely adjacent to, or integrated into processor 810. Example computing system 800 also includes one or more cryptographic function blocks 811 connected to the processor. For example, one or more cryptographic function blocks 811 may include functions for performing, but not limited to, NTT calculations, matrix-vector multiplication (A... The cryptographic blocks 811 can be directly or indirectly connected to each other. This includes y), r, and rG multiplication (e.g., elliptic curve point multiplication), events (e.g., for Elliptic Curve Digital Signature Algorithm (ECDSA)), secure hash algorithms (e.g., SHA-256, SHA-3), McEliece cryptography, bit-flipped key encapsulation (BIKE), Hamming quasi-cyclic (HQC) encryption, hash-based message authentication codes (e.g., HMAC-512), and RNG-seed cryptographic blocks. In some cases, multiple cryptographic blocks 811 may be directly or indirectly connected to each other. In some specific implementations, one or more cryptographic blocks 811 may include one or more cooperative processing units.

[0094] Processor 810 may include any general-purpose processor and hardware or software services, such as services 832, 834, and 836 stored in storage device 830, which are configured to control processor 810 and dedicated processors (e.g., arithmetic processors, cryptographic processors, and / or any combination thereof) in which software instructions are incorporated into the actual processor design. Processor 810 may be a substantially independent computing system containing multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors may include different computing units of variable size and characteristics. In some cases, multi-core processors may be symmetric or asymmetric. In some examples, one or more cryptographic function blocks 811 may be symmetric or asymmetric.

[0095] To enable user interaction, the computing system 800 includes an input device 845 that can represent any number of input mechanisms, such as a microphone for voice, a touch-sensitive screen for gesture or graphic input, a keyboard, a mouse, motion input, voice input, etc. The computing system 800 may also include an output device 835 that can be one or more of a plurality of output mechanisms. In some cases, a multimodal system allows the user to provide multiple types of input / output to communicate with the computing system 800.

[0096] The computing system 800 may include a communication interface 840, which typically manages and controls user input and system output. The communication interface may perform or facilitate the receiving and / or transmitting of wired or wireless communications using wired and / or wireless transceivers, including using audio jacks / plugs, microphone jacks / plugs, Universal Serial Bus (USB) ports / plugs, Apple™ Lightning™ ports / plugs, Ethernet ports / plugs, fiber optic ports / plugs, dedicated wired ports / plugs, 3G, 4G, 5G and / or other cellular data network wireless signaling, Bluetooth™ wireless signaling, Bluetooth™ Low Energy (BLE) wireless signaling, IBEACON™ wireless signaling, Radio Frequency Identification (RFID) wireless signaling, Near Field Communication (NFC) wireless signaling, Dedicated Short Range Communication (DSRC) wireless signaling, and 802.11. The communication interface 840 may include those communications such as Wi-Fi wireless signal transmission, Wireless Local Area Network (WLAN) signal transmission, Visible Light Communication (VLC), Global Microwave Access Interoperability (WiMAX), Infrared (IR) wireless signal transmission, Public Switched Telephone Network (PSTN) signal transmission, Integrated Services Digital Network (ISDN) signal transmission, Ad Hoc Network signal transmission, Radio Wave Signal Transmission, Microwave Signal Transmission, Infrared Signal Transmission, Visible Light Signal Transmission, Ultraviolet Light Signal Transmission, Wireless Signal Transmission along the electromagnetic spectrum, or some combination thereof. The communication interface 840 may also include one or more Global Navigation Satellite System (GNSS) receivers or transceivers used to determine the location of the computing system 800 based on one or more signals received from one or more satellites associated with one or more GNSS systems. GNSS systems include, but are not limited to, the U.S. Global Positioning System (GPS), the Russian Global Navigation Satellite System (GLONASS), the Chinese BeiDou Navigation Satellite System (BDS), and the European Galileo GNSS. There are no limitations on operation on any particular hardware arrangement, and therefore the basic features here can be easily replaced to obtain improved hardware or firmware arrangements as they are developed.

[0097] Storage device 830 may be a non-volatile and / or non-transitory and / or computer-readable storage device, and may be a hard disk or other type of computer-readable medium capable of storing data accessible by a computer, such as magnetic tape, flash memory cards, solid-state storage devices, digital versatile discs, cartridges, floppy disks, hard disks, magnetic tapes, magnetic stripes, any other magnetic storage media, flash memory, memristor memory, any other solid-state storage, CD-ROM, rewritable CD, digital video disc (DVD), Blu-ray Disc (BDD), holographic disc, another optical medium, secure digital storage (SD) cards, micro-secure digital storage (microSD) cards, Memory Stick. ® Cards, smart card chips, EMV chips, Subscriber Identity Module (SIM) cards, mini / micro / nano / micro SIM cards, another integrated circuit (IC) chip / card, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash EPROM, cache memory (e.g., layer 1 (L1) cache, layer 2 (L2) cache, layer 3 (L3) cache, layer 4 (L4) cache, layer 5 (L5) cache, other (L#) cache), resistive random access memory (RRAM / ReRAM), phase change memory (PCM), spin-transfer torque RAM (STT-RAM), another memory chip or cassette and / or combinations thereof.

[0098] Storage device 830 may include software services, servers, etc., which enable the system to perform functions when the code defining such software is executed by processor 810. In some embodiments, hardware services performing specific functions may include software components stored in a computer-readable medium that are connected to necessary hardware components, such as processor 810, connection 805, output device 835, etc., to perform the function. The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media capable of storing, containing, or carrying instructions and / or data. Computer-readable media may include non-transitory media in which data can be stored and which does not include carrier waves and / or transient electronic signals propagated wirelessly or via wired connections. Examples of non-transitory media include, but are not limited to, magnetic disks or magnetic tapes, optical storage media (such as optical discs (CDs) or digital versatile optical discs (DVDs)), flash memory, non-volatile memory fast (NVMe) memory, write-once read-many (WORM) memory, electronic fuse OTP memory, I-fuse OTP memory, gate oxide breakdown antifuse memory, Intel Optane memory, memory, or memory devices. Computer-readable media may store code and / or machine-executable instructions thereon, which may represent procedures, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuitry by delivering and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be delivered, forwarded, or transmitted via any suitable means, including memory sharing, message delivery, token delivery, network transmission, etc.

[0099] Specific details have been provided in the foregoing description to offer a thorough understanding of the various embodiments and examples presented herein, but those skilled in the art will recognize that this application is not limited thereto. Therefore, although exemplary embodiments of this application have been described in detail herein, it is to be understood that the inventive concept may be embodied and adopted in various other ways, and the appended claims are intended to be construed as including such variations, unless limited by prior art. Various features and aspects of the applications described above may be used individually or in combination. Furthermore, without departing from the broader scope of this specification, the embodiments may be used in any number of environments and applications beyond those described herein. Therefore, the specification and drawings should be considered illustrative rather than restrictive. For illustrative purposes, the methods are described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in a different order than described.

[0100] For clarity, in some instances, this technology may be presented as comprising various functional blocks, which include devices, device components, steps, or routines embodied in a method, either in software or a combination of hardware and software. Additional components may be used in addition to those shown in the figures and / or described herein. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form to avoid obscuring these embodiments with unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without necessary detail to avoid obscuring the embodiments.

[0101] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0102] Individual implementations may be described above as processes or methods depicted as flowcharts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation may be executed in parallel or concurrently. Furthermore, the order of operations may be rearranged. A process terminates when its operations are completed, but a process may have additional steps not included in the accompanying drawings. Processes may correspond to methods, functions, procedures, subroutines, subroutines, etc. When a process corresponds to a function, the termination of the process may correspond to the function returning to the calling function or the main function.

[0103] The processes and methods described in the examples above can be implemented using stored computer-executable instructions or computer-executable instructions otherwise available from a computer-readable medium. Such instructions may include, for example, instructions and data that configure, or otherwise configure, a general-purpose computer, special-purpose computer, or processing device to perform a function or group of functions. The portion may be accessible via a network of the computer resources used. The computer-executable instructions may be, for example, binary, intermediate format instructions such as assembly language, firmware, or source code. Examples of computer-readable media that can be used to store the instructions, the information used, and / or information created during the methods according to the described examples include disks or optical discs, flash memory, USB devices with non-volatile memory, networked storage devices, etc.

[0104] In some implementations, computer-readable storage devices, media, and memories may include cables or wireless signals containing bit streams, etc. However, when referred to, non-transitory computer-readable storage media explicitly exclude media such as energy, carrier signals, electromagnetic waves, and the signals themselves.

[0105] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may, in some cases, be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, etc.

[0106] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof, and can take any form factor of various form factors. When implemented in software, firmware, middleware, or microcode, program code or code segments (e.g., computer program products) for performing necessary tasks can be stored in a computer-readable or machine-readable medium. A processor can perform the necessary tasks. Examples of form factors include: laptop computers, smartphones, mobile phones, tablet devices, or other small form factor personal computers, personal digital assistants, rack-mounted devices, self-contained devices, etc. The functionality described herein can also be embodied in peripheral devices or interlocking cards. By further example, such functionality can also be implemented on circuit boards in different chips or different processes running on a single device.

[0107] Instructions, media for delivering such instructions, computing resources for executing them, and other structures for supporting such computing resources are example components for providing the functionality described in this disclosure.

[0108] The techniques described herein can also be implemented in electronic hardware, computer software, firmware, or any combination thereof. Such techniques can be implemented in any of a variety of devices, such as general-purpose computers, wireless communication devices (mobile phones), or integrated circuit devices with multiple uses, including applications in wireless communication devices (mobile phones) and other devices. Any feature described as a module or component can be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, the techniques can be implemented at least in part by a computer-readable data storage medium comprising program code including instructions that, when executed, perform one or more of the methods, algorithms, and / or operations described above. The computer-readable data storage medium can form part of a computer program product, which may include packaging material. The computer-readable medium may include memory or data storage media, such as random access memory (RAM) (such as synchronous dynamic random access memory (SDRAM)), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic or optical data storage media, etc. Additionally or alternatively, the technology may be implemented at least in part by a computer-readable communication medium that carries or conveys program code in the form of instructions or data structures that can be accessed, read and / or executed by a computer, such as propagated signals or waves.

[0109] The program code can be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such processors can be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor; however, in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Therefore, as used herein, the term "processor" may refer to any of the foregoing structures, any combination of the foregoing structures, or any other structure or means suitable for implementing the techniques described herein.

[0110] Those skilled in the art will understand that the less than ("<") and greater than (">") symbols or terms used herein may be replaced with less than or equal to ("≤") and greater than or equal to ("≥") symbols without departing from the scope of this description.

[0111] When a component is described as being “configured” to perform certain operations, such configuration can be achieved, for example, by designing electronic circuits or other hardware to perform the operations, by programming programmable electronic circuits (e.g., microprocessors or other suitable electronic circuits) to perform the operations, or any combination thereof.

[0112] The phrase “coupled to” or “communicatively coupled to” means that any component is physically connected directly or indirectly to another component, and / or that any component is in communication with another component directly or indirectly (e.g., connected to that other component via a wired or wireless connection and / or other suitable communication interface).

[0113] Claims using phrases such as "at least one processor, the at least one processor being configured to," "at least one processor being configured to," "one or more processors, the one or more processors being configured to," or "one or more processors being configured to," or other languages, indicate that one or more processors (in any combination) are capable of performing associated operations. For example, a claim using the phrase "at least one processor, the at least one processor being configured to: X, Y, and Z" means that a single processor can be used to perform operations X, Y, and Z; or that multiple processors are each assigned a specific subset of tasks involving operations X, Y, and Z, such that the multiple processors together perform X, Y, and Z; or that a group of multiple processors work together to perform operations X, Y, and Z. In another example, a claim using the phrase "at least one processor, the at least one processor being configured to: X, Y, and Z" could mean that any single processor can perform only a subset of operations X, Y, and Z.

[0114] When referring to one or more elements that perform functions (e.g., steps of a method), one element may perform all functions, or more than one element may jointly perform these functions. When more than one element jointly performs these functions, each function does not need to be performed by every single element (e.g., different functions may be performed by different elements), and / or each function does not need to be performed by only one element as a whole (e.g., different elements may perform different sub-functions of a function). Similarly, when referring to one or more elements configured to cause another element (e.g., a device) to perform functions, one element may be configured to cause another element to perform all functions, or more than one element may be jointly configured to cause another element to perform these functions.

[0115] When referring to an entity that performs or is configured to perform functions (e.g., steps of a method) (e.g., any entity or device described herein), the entity may be configured to cause one or more elements (individually or collectively) to perform those functions. One or more components of the entity may include at least one memory, at least one processor, at least one communication interface, another component configured to perform one or more of those functions, and / or any combination thereof. When referring to an entity that performs functions, the entity may be configured to cause one component to perform all functions, or to cause more than one component to perform those functions collectively. When the entity is configured to cause more than one component to perform those functions collectively, each function does not need to be performed by every single component (e.g., different functions may be performed by different components), and / or each function does not need to be performed by only one component as a whole (e.g., different components may perform different sub-functions of a function).

[0116] The exemplary aspects of this disclosure include:

[0117] Aspect 1: An apparatus for secure processing, the apparatus comprising: a memory including instructions; and a processor coupled to the memory and configured to: obtain a plurality of instructions, wherein the plurality of instructions include a sequential order in which the processor executes the plurality of instructions; determine that two or more of the plurality of instructions can be fused; determine that a random variable satisfies an instruction fusion condition; and, based on the determination that the two or more of the plurality of instructions can be fused and that the random variable satisfies the instruction fusion condition, execute the two or more of the plurality of instructions as a single fused instruction.

[0118] Aspect 2: The apparatus according to aspect 1, wherein each of the plurality of instructions is included in the instruction set architecture (ISA) of the processor.

[0119] Aspect 3: The apparatus according to any one of Aspects 1 to 2, wherein the two or more instructions among the plurality of instructions comprise two instructions, wherein executing the two or more instructions among the plurality of instructions as the single fused instruction comprises: combining the two instructions into a single instruction.

[0120] Aspect 4: The apparatus according to any one of Aspects 1 to 3, wherein the two instructions are executed simultaneously by different hardware components of the processor when executed by the processor.

[0121] Aspect 5: The apparatus according to any one of Aspects 1 to 4, wherein the idiom catalog includes a plurality of idioms, wherein each of the plurality of idioms includes a sequence of two or more instructions capable of being merged and a corresponding fusion instruction corresponding to the sequence of two or more instructions capable of being merged.

[0122] Aspect 6: The apparatus according to any one of Aspects 1 to 5, wherein, in order to determine that the random variable satisfies the instruction fusion condition, the processor is further configured to: determine that the value of the random variable is - (1) or true.

[0123] Aspect 7: The apparatus according to any one of Aspects 1 to 6, wherein, in order to execute two or more of the plurality of instructions as the single fused instruction, the processor is further configured to execute the two or more instructions simultaneously.

[0124] Aspect 8: The apparatus according to any one of aspects 1 to 7, wherein executing the two or more instructions as the single fused instruction, relative to executing the two or more instructions in sequence, reduces the total number of operations performed by the processor.

[0125] Aspect 9: The apparatus according to any one of Aspects 1 to 8, wherein the processor is further configured to: determine that a first additional instruction among the plurality of instructions cannot be fused with a second additional instruction among the plurality of instructions, wherein the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions in the order in which the processor executes the plurality of instructions; and, based on the determination that the first additional instruction among the plurality of instructions cannot be fused with the second additional instruction among the plurality of instructions, execute the first additional instruction sequentially after executing the single fusion instruction.

[0126] Aspect 10: The apparatus according to any one of Aspects 1 to 9, wherein the processor is further configured to: determine that a first additional instruction among the plurality of instructions is fused with a second additional instruction among the plurality of instructions, wherein the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions in the order in which the processor executes the plurality of instructions; determine that a second random variable does not satisfy a second instruction fusion condition; based on the determination that the second random variable does not satisfy the second instruction fusion condition, execute the first additional instruction among the plurality of instructions sequentially after executing the single fusion instruction; and execute the second additional instruction among the plurality of instructions sequentially after executing the first additional instruction among the plurality of instructions.

[0127] Aspect 11: The apparatus according to any one of Aspects 1 to 10, wherein, in order to determine that the second random variable does not satisfy the second instruction fusion condition, the processor is further configured to: determine that the value of the random variable is zero (0) or false.

[0128] Aspect 12: A method for secure processing, the method comprising: obtaining a plurality of instructions, wherein the plurality of instructions includes a sequential order in which the plurality of instructions are executed by a processor; determining that two or more of the plurality of instructions can be fused; determining that a random variable satisfies an instruction fusion condition; and, based on determining that the two or more of the plurality of instructions can be fused and that the random variable satisfies the instruction fusion condition, executing the two or more of the plurality of instructions as a single fused instruction.

[0129] Aspect 13: According to the method of aspect 12, each of the plurality of instructions is included in the ISA of the processor.

[0130] Aspect 14: The method according to any one of Aspects 12 to 13, wherein the two or more instructions among the plurality of instructions comprise two instructions, wherein executing the two or more instructions among the plurality of instructions as the single fused instruction comprises: combining the two instructions into a single instruction.

[0131] Aspect 15: According to the method of aspect 14, wherein the two instructions are executed simultaneously by different hardware components of the processor when executed by the processor.

[0132] Aspect 16: The method according to any one of Aspects 12 to 15, wherein the idiom catalog includes a plurality of idioms, wherein each of the plurality of idioms includes a sequence of two or more instructions capable of being merged and a corresponding fusion instruction corresponding to the sequence of two or more instructions capable of being merged.

[0133] Aspect 17: The method according to any one of Aspects 12 to 16, wherein determining that the random variable satisfies the instruction fusion condition comprises: determining that the value of the random variable is - (1) or true.

[0134] Aspect 18: The method according to any one of aspects 12 to 17, wherein executing two or more of the plurality of instructions as the single fused instruction comprises: executing the two or more instructions simultaneously.

[0135] Aspect 19: The method according to any one of aspects 12 to 18, wherein executing the two or more instructions as the single fused instruction, relative to executing the two or more instructions in sequence, reduces the total number of operations performed by the processor.

[0136] Aspect 20: The method according to any one of aspects 12 to 19, the method further comprising: determining that a first additional instruction among the plurality of instructions cannot be merged with a second additional instruction among the plurality of instructions, wherein the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions in the order in which the plurality of instructions are executed by the processor; and, based on determining that the first additional instruction among the plurality of instructions cannot be merged with the second additional instruction among the plurality of instructions, sequentially executing the first additional instruction after executing the single merge instruction.

[0137] Aspect 21: The method according to any one of Aspects 12 to 20, the method further comprising: determining that a first additional instruction among the plurality of instructions is fused with a second additional instruction among the plurality of instructions, wherein the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions in the order in which the plurality of instructions are executed by the processor; determining that a second random variable does not satisfy a second instruction fusion condition; based on determining that the second random variable does not satisfy the second instruction fusion condition, executing the first additional instruction among the plurality of instructions sequentially after executing the single fusion instruction; and executing the second additional instruction among the plurality of instructions sequentially after executing the first additional instruction among the plurality of instructions.

[0138] Aspect 22: According to the method of aspect 21, determining that the second random variable does not satisfy the second instruction fusion condition includes: determining that the value of the random variable is zero (0) or false.

[0139] Aspect 23: A non-transitory computer-readable medium having instructions stored thereon, the instructions, when executed by one or more processors, causing the one or more processors to: obtain a plurality of instructions, wherein the plurality of instructions includes a sequential order in which the processor executes the plurality of instructions, wherein the one or more processors include the processor; determine that two or more of the plurality of instructions can be fused; determine that a random variable satisfies an instruction fusion condition; and, based on the determination that the two or more of the plurality of instructions can be fused and that the random variable satisfies the instruction fusion condition, execute the two or more of the plurality of instructions as a single fused instruction.

[0140] Aspect 24: The non-transitory computer-readable medium according to aspect 23, wherein each of the plurality of instructions is included in the ISA of the processor.

[0141] Aspect 25: A non-transitory computer-readable medium according to any one of aspects 23 to 24, wherein two or more of the plurality of instructions comprise two instructions, wherein executing the two or more of the plurality of instructions as the single fused instruction comprises: combining the two instructions into a single instruction.

[0142] Aspect 26: The non-transitory computer-readable medium according to aspect 25, wherein the two instructions are executed simultaneously by different hardware components of the processor when executed by the processor.

[0143] Aspect 27: A non-transitory computer-readable medium according to any one of Aspects 23 to 26, wherein the idiom catalog includes a plurality of idioms, wherein each of the plurality of idioms includes a sequence of two or more instructions capable of being fused and a corresponding fusion instruction corresponding to the sequence of two or more instructions capable of being fused.

[0144] Aspect 28: A non-transitory computer-readable medium according to any one of aspects 23 to 27, wherein determining that the random variable satisfies the instruction fusion condition comprises: determining that the value of the random variable is - (1) or true.

[0145] Aspect 29: A non-transitory computer-readable medium according to any one of aspects 23 to 28, wherein executing two or more of the plurality of instructions as the single fused instruction comprises: executing the two or more instructions simultaneously.

[0146] Aspect 30: A non-transitory computer-readable medium according to any one of aspects 23 to 29, wherein executing the two or more instructions as the single fused instruction, relative to sequentially executing the two or more instructions of the plurality of instructions, reduces the total number of operations performed by the processor.

[0147] Aspect 31: An apparatus for secure processing, the apparatus comprising: a memory including instructions; and a processor coupled to the memory and configured to: obtain a plurality of instructions, wherein the plurality of instructions include a sequential order in which the processor executes the plurality of instructions; determine that an instruction among the plurality of instructions is capable of adjusted execution; determine that a random variable satisfies an instruction fusion condition; and execute the instruction as a second plurality of instructions based on the determination that the instruction among the plurality of instructions is capable of adjusted execution and that the random variable satisfies the instruction fusion condition.

[0148] Aspect 32: According to the apparatus of aspect 31, wherein executing one of the plurality of instructions using the adjusted execution comprises: splitting the instruction into a second plurality of instructions.

[0149] Aspect 33: The apparatus according to any one of aspects 31 to 32, wherein the instructions are included in the ISA of the processor.

[0150] Aspect 34: The apparatus according to any one of aspects 31 to 33, wherein each of the plurality of instructions is included in the ISA of the processor.

[0151] Aspect 35: The apparatus according to any one of aspects 31 to 34, wherein the split catalog includes a plurality of instructions capable of being executed in an adjusted manner and a corresponding second plurality of instructions.

[0152] Aspect 36: A non-transitory computer-readable storage medium having instructions stored thereon, the instructions causing the one or more processors, when executed, to perform any of the operations described in aspects 1 to 30.

[0153] Aspect 37: An apparatus comprising components for performing the method according to any one of aspects 1 to 30.

[0154] Aspect 38: A non-transitory computer-readable storage medium having instructions stored thereon, the instructions causing the one or more processors, when executed, to perform any of the operations described in aspects 31 to 35.

[0155] Aspect 39: An apparatus comprising components for performing secure processing according to any one of aspects 31 to 35.

[0156] Aspect 40: An apparatus comprising components for performing the method according to any one of aspects 31 to 35.

[0157] Aspect 41: A method comprising the operation according to any one of aspects 31 to 35.

[0158] Aspect 42: A method comprising operations according to any one of aspects 1 to 30 and any one of aspects 31 to 35.

[0159] Aspect 43: An apparatus for secure processing. The apparatus includes (e.g., implemented in a circuit) a memory and one or more processors (e.g., one or more processors) coupled to the memory. The one or more processors are configured to perform operations according to any one of aspects 1 to 30 and any one of aspects 31 to 35.

[0160] Aspect 44: A computer-readable storage medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform operations according to any one of aspects 1 to 30 and any one of aspects 31 to 35.

[0161] Aspect 45: An apparatus comprising components for performing operations according to any one of aspects 1 to 30 and any one of aspects 31 to 35.

Claims

1. An apparatus for secure handling, the apparatus comprising: Memory, the memory including instructions; and A processor, coupled to the memory and configured to: Obtain multiple instructions, wherein the multiple instructions include a sequential order in which the processor executes the multiple instructions; Determine that two or more of the plurality of instructions can be fused; Determine that the random variable satisfies the instruction fusion condition; as well as Based on the determination that two or more of the plurality of instructions can be fused and the random variable satisfies the instruction fusion condition, the two or more of the plurality of instructions are executed as a single fused instruction.

2. The apparatus of claim 1, wherein each of the plurality of instructions is included in the instruction set architecture (ISA) of the processor.

3. The apparatus of claim 1, wherein the two or more instructions of the plurality of instructions comprise two instructions, wherein executing the two or more instructions of the plurality of instructions as the single fused instruction comprises: Combine the two instructions into a single instruction.

4. The apparatus of claim 3, wherein the two instructions are executed simultaneously by different hardware components of the processor when executed by the processor.

5. The apparatus of claim 1, wherein the idiom catalog comprises a plurality of idioms, wherein each of the plurality of idioms comprises a sequence of two or more instructions capable of being merged and a corresponding fusion instruction corresponding to the sequence of two or more instructions capable of being merged.

6. The apparatus of claim 1, wherein, In order to determine that the random variable satisfies the instruction fusion condition, the processor is further configured to: determine that the value of the random variable is - (1) or true.

7. The apparatus of claim 1, wherein, In order to execute two or more of the plurality of instructions as a single fused instruction, the processor is further configured to execute the two or more instructions simultaneously.

8. The apparatus of claim 1, wherein executing the two or more instructions as the single fused instruction, relative to sequentially executing the two or more instructions of the plurality of instructions, reduces the total number of operations performed by the processor.

9. The apparatus of claim 1, wherein the processor is further configured to: Determining that a first additional instruction among the plurality of instructions cannot be merged with a second additional instruction among the plurality of instructions, wherein, in the order in which the processor executes the plurality of instructions, the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions; and Based on the determination that the first additional instruction among the plurality of instructions cannot be merged with the second additional instruction among the plurality of instructions, the first additional instruction is executed sequentially after the execution of the single merge instruction.

10. The apparatus of claim 1, wherein the processor is further configured to: Determine that a first additional instruction among the plurality of instructions can be fused with a second additional instruction among the plurality of instructions, wherein the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions in the order in which the processor executes the plurality of instructions; It is determined that the second random variable does not satisfy the fusion condition of the second instruction; Based on the determination that the second random variable does not satisfy the second instruction fusion condition, the first additional instruction among the plurality of instructions is executed sequentially after the execution of the single fusion instruction; as well as The second additional instruction among the plurality of instructions is executed sequentially after the first additional instruction among the plurality of instructions is executed.

11. The apparatus of claim 10, wherein, In order to determine that the second random variable does not satisfy the second instruction fusion condition, the processor is further configured to: determine that the value of the random variable is zero (0) or false.

12. A method for secure processing, the method comprising: Obtain multiple instructions, wherein the multiple instructions include the order in which the processor executes the multiple instructions; Determine that two or more of the plurality of instructions can be fused; Determine that the random variable satisfies the instruction fusion condition; as well as Based on the determination that two or more of the plurality of instructions can be fused and the random variable satisfies the instruction fusion condition, the two or more of the plurality of instructions are executed as a single fused instruction.

13. The method of claim 12, wherein each of the plurality of instructions is included in the ISA of the processor.

14. The method of claim 12, wherein the two or more instructions of the plurality of instructions comprise two instructions, wherein executing the two or more instructions of the plurality of instructions as the single fused instruction comprises: Combine the two instructions into a single instruction.

15. The method of claim 14, wherein the two instructions are executed simultaneously by different hardware components of the processor when executed by the processor.

16. The method of claim 12, wherein the idiom catalog comprises a plurality of idioms, wherein each of the plurality of idioms comprises a sequence of two or more instructions capable of being merged and a corresponding fusion instruction corresponding to the sequence of two or more instructions capable of being merged.

17. The method of claim 12, wherein determining that the random variable satisfies the instruction fusion condition comprises: Determine the value of the random variable as either -(1) or true.

18. The method of claim 12, wherein executing the two or more instructions of the plurality of instructions as the single fused instruction comprises: The two or more instructions are executed simultaneously.

19. The method of claim 12, wherein executing the two or more instructions as the single fused instruction, relative to sequentially executing the two or more instructions of the plurality of instructions, reduces the total number of operations performed by the processor.

20. The method according to claim 12, further comprising: Determine that a first additional instruction among the plurality of instructions can be fused with a second additional instruction among the plurality of instructions, wherein the second additional instruction among the plurality of instructions immediately follows the first additional instruction among the plurality of instructions in the order in which the processor executes the plurality of instructions; It is determined that the second random variable does not satisfy the fusion condition of the second instruction; Based on the determination that the second random variable does not satisfy the second instruction fusion condition, the first additional instruction among the plurality of instructions is executed sequentially after the execution of the single fusion instruction; as well as The second additional instruction among the plurality of instructions is executed sequentially after the first additional instruction among the plurality of instructions is executed.

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