Enhanced processing core scheduler scheme for multi-core processing systems

Abstract

This disclosure provides systems, methods, and apparatuses for memory systems supporting enhanced processing core scheduling schemes. In a first aspect, a wireless communication apparatus includes a processing system and memory coupled to the processing system. The processing system is configured to enable the apparatus to: receive core workload information and cache miss information for one or more cores of the processing system; and adjust which cores to use based on the core workload information and cache miss information. Other aspects and features are also claimed and described.

Description

Technical Field

[0001] The present disclosure relates in general to an apparatus and method for controlling the processing cores of a multi-core processing system. More specifically, some aspects relate to an apparatus and method for controlling the scheduling operations of a multi-core processing system to support core activation or core switching based on cache miss information to reduce overall power consumption and memory latency. Background Technology

[0002] As the value and use of information continue to increase, individuals and businesses are seeking additional ways to process and store it. Furthermore, the use of information in various locations and the expectation of information portability continue to grow. Therefore, users are increasingly turning to portable electronic devices such as mobile phones, digital cameras, and laptops. Portable electronic devices typically employ processing systems with multiple processing cores to efficiently process data while reducing power consumption.

[0003] Some multi-core processing systems may include a variety of different types of processing cores designed for different operations or situations. For example, a processing system may have low-power cores and high-performance cores suitable for specific tasks such as computation or coding. The processing system's scheduler or core controller can distribute tasks among cores to balance workloads across cores and can activate or deactivate cores based on CPU workload and / or performance status (e.g., normal or reduced power consumption modes). Summary of the Invention

[0004] The following summary outlines some aspects of this disclosure to provide a basic understanding of the techniques discussed. This summary is not an exhaustive overview of all the intended features of this disclosure, nor is it intended to identify key or essential elements of all aspects of this disclosure, nor to define the scope of any or all aspects of this disclosure. The sole purpose of this summary is to present, in a general form, some concepts of one or more aspects of this disclosure as a prelude to the more detailed description that follows.

[0005] The aspects disclosed herein describe the core control logic components for multi-core processing systems, such as those with different types of processing cores. As an illustrative example, the big.LITTLE processing architecture includes large and small cores, often referred to as silver and gold cores. When reducing power consumption or balancing power and performance, the core control logic components (often referred to as the scheduler) can activate cores, deactivate cores, and / or migrate tasks to balance workloads and prevent bottlenecks. The scheduler frequently uses core workload information to determine how to schedule core tasks. In the aspects disclosed herein, the scheduler also considers cache miss rate information to determine how to schedule core tasks and manage cores. Utilizing cache miss rate information allows the scheduler to determine whether a bottleneck is solely due to CPU workload or whether it is caused by cache misses or latency issues. If the bottleneck is partly due to cache misses or latency issues, the scheduler can take more appropriate scheduling actions to address the cache-related bottleneck, rather than simply adding more processing power that may not resolve the bottleneck.

[0006] In one aspect of this disclosure, a wireless communication device includes: a processing system; and a memory coupled to the processing system, wherein the processing system is configured to cause the device to: receive core workload information and cache miss information of one or more cores of the processing system; and adjust which cores to use based on the core workload information and cache miss information.

[0007] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as the basis for modifying or designing other structures for achieving the same purpose as this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and manner of operation) and the associated advantages will be better understood from the following description when considered in conjunction with the accompanying drawings. Each figure in the drawings is provided for illustrative and descriptive purposes and not as a definition of limitation of the claims.

[0008] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or the use of devices that can be implemented via integrated chip implementations and other non-modular component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to use cases or applications, the applicability of various types of the described innovations is evident. The scope of implementations ranges from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical contexts, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily involve multiple components (e.g., hardware components, including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.) for analog and digital purposes. The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., with different sizes, shapes, and constructions. Attached Figure Description

[0009] A further understanding of the nature and advantages of this disclosure can be achieved by referring to the following figures. In the figures, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numeral and a second numeral for differentiation between similar components. If only the first reference numerals are used in the specification, the description applies to any one of the similar components having the same first reference numerals, regardless of the second reference numerals.

[0010] Figure 1 This is a block diagram illustrating a data processing system including a memory system according to an embodiment of the present invention.

[0011] Figure 2 This is a block diagram illustrating an example electronic device including a processing system according to one or more aspects of this disclosure.

[0012] Figure 3This is a block diagram of an implementation of a system comprising a multi-cluster heterogeneous processor architecture according to some aspects of this disclosure, the multi-cluster heterogeneous processor architecture including a processor scheduler and a cache scheduler for providing an enhanced processing core scheduling scheme for determining active cores based on cache miss rate information.

[0013] Figure 4 This is a flowchart illustrating an enhanced processing core scheduling scheme for determining the activity of a multi-core processor based on cache miss rate information, according to some aspects of this disclosure.

[0014] Figure 5 This is a block diagram illustrating an example of an enhanced processing core scheduling scheme for determining the activity of a multi-core processor based on cache miss rate information, supported by some aspects of this disclosure.

[0015] Figure 6A and Figure 6B Each is a block diagram illustrating an example of a processing core adjustment of an enhanced processing core scheduling scheme described herein and in accordance with some aspects of this disclosure.

[0016] Figure 7 This is a flowchart illustrating an enhanced processing core scheduling scheme for determining the activity of a multi-core processor based on cache miss rate information, according to some aspects of this disclosure.

[0017] Figure 8 This is a block diagram illustrating details of an example wireless communication system according to one or more aspects of this disclosure.

[0018] The same reference numerals and names in different figures denote the same elements. Detailed Implementation

[0019] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to limit the scope of this disclosure. Rather, the detailed description includes specific details for providing a thorough understanding of the subject matter of the invention. It will be apparent to those skilled in the art that these specific details are not necessary in every situation, and in some cases, well-known structures and components are shown in block diagram form for clarity of presentation.

[0020] This disclosure provides systems, apparatus, methods, and computer-readable media that support data processing, including techniques for scheduling cores in a multi-core processing system. Aspects of this disclosure provide operational and logical components used in which operations of an enhanced core scheduling scheme are used to adjust cores and / or core workloads based on cache usage information, such as cache miss rates. For example, a scheduler for a multi-core processing system may adjust cores based on core workload and cache usage information to better identify bottlenecks. For example, a bottleneck may be caused by a lack of processing resources (e.g., processing circuitry) or by cache latency (e.g., processing circuitry waiting for information for computation). These different causes of bottlenecks cannot be determined solely based on CPU usage information, and bottlenecks can be more appropriately mitigated if the true cause or root cause of the bottleneck is known. Aspects of this disclosure implement core switching or core activation based on core workload and cache usage information. For example, core workload and cache usage information may be compared to corresponding thresholds.

[0021] Specific embodiments of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure provides techniques for improving the performance of processing systems, such as increased throughput and reduced power consumption.

[0022] Figure 1 A data processing system 100 according to one or more aspects of this disclosure is illustrated, which may be included in a mobile computing device. A memory system 110 may be coupled to a host device 102 via one or more channels. For example, the host device 102 and the memory system 110 may be coupled via a serial interface including a single channel for transmitting data or a parallel interface including two or more channels for transmitting data. In some aspects, control data may be transmitted via the same channel as the data, or control data may be transmitted via additional channels. The host device 102 may be a portable electronic device such as a mobile phone, MP3 player, or laptop computer, or a non-portable electronic device such as a desktop computer, game console, television (TV), media player, or projector. As another example, the host device 102 may be an automotive computer system. In some examples, the memory system 110 may be included in the host device 102. Therefore, the data processing system 100 may be any of the example host devices described herein that include the memory system 110.

[0023] The memory system 110 can perform operations in response to commands (e.g., requests) from the host device 102. For example, the memory system 110 can store data provided by the host device 102, and the memory system 110 can also provide the stored data to the host device 102. The memory system 110 can be used by the host device 102 as main memory, short-term memory, or long-term memory. As an example of main memory, the host device 102 can use the memory system 110 to supplement or replace system memory by using it to store temporary data (such as data related to the operating system and / or threads executing in the operating system). As an example of short-term memory, the host device 102 can use the memory system 110 to store page files for the operating system. As an example of long-term memory, the host device 102 can use the memory system 110 to store user files (e.g., documents, videos, pictures) and / or application files (e.g., word processing executables, game applications).

[0024] According to the host interface protocol used to couple the memory system 110 to one or more channels of the host device 102, the memory system 110 can be implemented using any of a variety of storage devices. The memory system 110 can be implemented using any of the following storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro MMC, secure digital (SD) card, mini SD, micro SD, universal serial bus (USB) storage device, universal flash storage (UFS) device, compact flash (CF) card, smart media (SM) card, or memory stick.

[0025] The memory system 110 may include a memory module 150 and a controller 130 coupled to the memory module 150 via one or more channels. The memory module 150 may store and retrieve data in memory blocks 152, 154, and 156 under the control of the controller 130, which may execute commands received from the host device 102. The controller 130 is configured to control data exchange between the memory module 150 and the host device 102. Storage components in the memory module 150 (such as memory blocks 152, 154, and 156) may be implemented as volatile memory devices (such as dynamic random access memory (DRAM) and static random access memory (SRAM)) or non-volatile memory devices (such as read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (SCRAM), or NAND flash memory).

[0026] The controller 130 and memory module 150 may be formed as integrated circuits on one or more semiconductor dies (or other substrates). In some aspects, the controller 130 and memory module 150 may be integrated into a single chip. In some aspects, the memory module 150 may include one or more chips coupled in series or parallel to each other and coupled to the controller 130, which is on a separate chip. In some aspects, the memory module 150 and controller 130 chips are integrated in a single package, such as in a stacked package (PoP) system. In some aspects, the memory system 110 is integrated on a single chip along with one or more or all of the components of the host device 102 (e.g., application processor, system memory, digital signal processor, modem, graphics processing unit, memory interface, input / output interface, network adapter), such as in a system-on-a-chip (SoC). The controller 130 and memory module 150 can be integrated into a semiconductor device to form a memory card, such as a PCMCIA card, a compact flash (CF) card, a smart media card (SMC), a memory stick, a multimedia card (MMC), an RS-MMC, a micro MMC, a secure digital (SD) card, a mini SD, a micro SD, an SDHC, and a universal flash storage (UFS) device.

[0027] The controller 130 of the memory system 110 can control the memory module 150 in response to commands from the host device 102. The controller 130 can execute read commands to provide data from the memory module 150 to the host device 102. The controller 130 can execute write commands to store data provided from the host device 102 into the memory module 150. The controller 130 can execute other commands (such as programming and erasing commands) to manage the data in the memory module 150. The controller 130 can also execute other commands to manage control of the memory system 110, such as setting the configuration registers of the memory system 110. By executing commands according to the configuration specified in the configuration registers, the controller 130 can control the operation of the memory module 150, such as read operations, write operations, programming operations, and erase operations.

[0028] Controller 130 may include several components configured to execute received commands. For example, controller 130 may include host interface (I / F) unit 132, processor 134, error correction code (ECC) unit 138, power management unit (PMU) 140, NAND flash memory controller (NFC) 142, and / or memory 144. Power management unit (PMU) 140 may provide and manage power for components within controller 130 and / or memory module 150.

[0029] The host IF unit 132 can process commands and data provided from the host device 102 and can communicate with the host device 102 via at least one of a variety of interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Rapid Interconnect (PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE). For example, the host IF unit 132 can be a parallel interface such as an MMC interface, or a serial interface such as an Ultra-High Speed ​​Class 1 (UHS-I) / UHS Class 2 (UHS-II) or Universal Flash Storage (UFS) interface.

[0030] ECC unit 138 can detect and correct errors in data read from memory module 150 during a read operation. When the number of error bits exceeds a threshold number of correctable error bits, ECC unit 138 may fail to correct the error bits, which may cause ECC unit 138 to output an error correction failure signal indicating that the correction of error bits has failed. In some aspects, ECC unit 138 may not be provided, or ECC unit 138 may be configurable to be active for some or all of the memory modules in memory module 150. ECC unit 138 may use decoding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbine codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis decoding modulation (TCM), or block decoding modulation (BCM).

[0031] NFC 142 provides an interface between controller 130 and memory module 150, allowing controller 130 to control memory module 150 in response to commands received from host device 102. NFC 142 can generate control signals for memory module 150, such as signals for row lines and bit lines, and process data under the control of processor 134. Although NFC 142 is described as a NAND flash memory controller, other controllers can perform similar functions for other memory types used as memory module 150.

[0032] Memory 144 can serve as working memory for memory system 110 and controller 130. Memory 144 can store data used to drive memory system 110 and controller 130. When controller 130 controls the operation of memory module 150 (such as, for example, read operation, write operation, program operation, or erase operation), memory 144 can store data used by controller 130 and memory module 150 for operation. Memory 144 can be implemented using volatile memory (such as, for example, static random access memory (SRAM) or dynamic random access memory (DRAM)). In some aspects, memory 144 can store address maps, program memory, data memory, write buffers, read buffers, and mapping buffers, etc.

[0033] Processor 134 can control the general operation of memory system 110 and control write or read operations on memory module 150 in response to write or read requests received from host device 102, respectively. For example, processor 134 can execute firmware, which may be referred to as flash translation layer (FTL), to control the general operation of memory system 110. Processor 134 may be implemented, for example, using a microprocessor, central processing unit (CPU), or application-specific integrated circuit (ASIC).

[0034] Figure 2 This is a block diagram illustrating an example electronic device including a data processing system 100 according to one or more aspects of this disclosure. The electronic device 200 may include a user interface 210, a memory 220, an application processor 230, a network adapter 240, and a storage system 250 (which may be...). Figure 1 (One implementation of the data processing system 100). The application processor 230 can be coupled to other components via a bus such as a peripheral component interface (PCI) bus (including a PCI fast (PCIe) bus).

[0035] Application processor 230 can execute computer program code, including applications, drivers, and operating systems, to coordinate the performance of tasks by components included in electronic device 200. For example, application processor 230 can execute a storage driver for accessing storage system 250. Application processor 230 may be part of a system-on-a-chip (SoC) that includes one or more other components shown in electronic device 200.

[0036] Memory 220 may operate as main memory, working memory, buffer memory, or cache memory of electronic device 200. Memory 220 may include volatile random access memory (such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM) or non-volatile random access memory (such as phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM)). In some aspects, application processor 230 and memory 220 may be combined using a stacked package (POP).

[0037] Network adapter 240 can communicate with external devices. For example, network adapter 240 can support wired communication and / or various wireless communications, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), Global Microwave Access Interoperability (WiMAX), Wireless Local Area Network (WLAN), Ultra Wideband (UWB), Bluetooth, Wireless Display (Wi-Di), etc., and can thereby communicate with wired and / or wireless electronic devices (e.g., mobile electronic devices).

[0038] Storage system 250 can store data (e.g., data received from application processor 230) and send the data stored therein to application processor 230. Storage system 250 can be a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), NAND flash memory, NOR flash memory, or 3-dimensional (3-D) NAND flash memory. Storage system 250 can be a removable storage medium, such as a memory card or external drive. For example, storage system 250 may correspond to the above reference. Figure 1 The memory system 110 described may be an SSD, eMMC, UFS or other flash memory system.

[0039] User interface 210 provides one or more graphical user interfaces (GUIs) for inputting data or commands to application processor 230 or for outputting data to external devices. For example, user interface 210 may include user input interfaces (such as virtual keyboards, touch screens, cameras, microphones, gyroscope sensors, or vibration sensors) and user output interfaces (such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) display devices, active matrix OLED (AMOLED) display devices, light-emitting diodes (LEDs), speakers, or haptic motors).

[0040] Figure 3 This is a block diagram of an embodiment of a system 300 including a multi-cluster heterogeneous processor architecture according to some embodiments of the present disclosure. System 300 can be implemented in any computing device, including personal computers, workstations, servers, and portable computing devices (PCDs) (such as cellular phones, portable digital assistants (PDAs), portable game consoles, handheld computers, or tablet computers). The multi-cluster heterogeneous processor architecture includes multiple processor clusters coupled to a cache controller 301. As known in the art, each processor cluster may include one or more processors or processor cores (e.g., central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), etc.) with a corresponding dedicated cache.

[0041] exist Figure 3 In the implementation scheme, processor clusters 302 and 304 may include a “big.LITTLE” heterogeneous architecture as described above, wherein processor cluster 302 includes a Little core cluster and processor cluster 304 includes a Big core cluster. The Little core processor cluster 302 includes multiple Central Processing Unit (CPU) cores 308 and 310, which are relatively slower and consume less power than CPU cores 314 and 316 in the Big core processor cluster 304. The Big core cluster CPU cores 314 and 316 can be distinguished from the Little core cluster CPU cores 308 and 310 by, for example, relatively higher instructions per cycle (IPC), higher operating frequency, and / or having microarchitectural features that achieve relatively higher performance at the expense of additional power. Furthermore, additional processor clusters may be included in system 300, such as processor cluster 306 including, for example, GPU cores 320 and 322, machine learning cores, etc.

[0042] Processor clusters 302, 304, and 306 may have independent cache memories used by the corresponding processors in system 300 to reduce the average time of accessing data from main memory 344. In embodiments, the independent cache memories and main memory 344 may be organized into a hierarchical structure of cache levels (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), etc.). Processor cluster 302 may include L2 cache 312, processor cluster 304 may include L2 cache 318, and processor cluster 306 may include L2 cache 324. L1 cache (not shown and optionally part of the CPU) and L2 cache may correspond to dedicated caches. Processor cores and / or clusters may also have shared caches, such as L3 cache and higher-level caches, that can be shared among multiple cores and / or clusters. Figure 3 As shown, the core of the cluster can share some or all of the shared cache 350.

[0043] like Figure 3As shown, the cache controller 301 may include a cache scheduler 340, a cache interconnect 311, and multiple cache monitors 326, 328, and 330, which are used to monitor the performance of L2 caches 312, 318, and 324, respectively. The cache interconnect 311 includes an interconnect or bus with associated logical components for maintaining consistency between main memory 344 and L2 caches 312, 318, and 324. As described in more detail below, the cache scheduler 340 includes logical components configured to monitor processor and cache performance and manage task scheduling for processor clusters 302, 304, and 306 based on the power and performance requirements of system 300. Figure 3 As shown, the cache controller 301 may include and / or control the shared cache 350.

[0044] Additionally, system 300 includes a processor controller 352 coupled to multiple processor clusters 302, 304, and 306. Processor controller 352 may include a processor core scheduler 354 and multiple processor monitors 362, 364, and 366, respectively, for monitoring the performance of the processor cores in processor clusters 302, 304, and 306. As described in more detail below, processor core scheduler 354 includes logical components configured to monitor processors and optionally cache performance, and to manage task scheduling for processor clusters 302, 304, and 306 based on the power and performance requirements of system 300.

[0045] Figure 4 This is a flowchart illustrating a method for an enhanced processing core scheduling scheme based on cache miss rate information, according to some embodiments of this disclosure. In some specific embodiments, the method may be... Figure 1 Processor 134 Figure 2 Application processor 230, Figure 3 System 300 or processor core scheduler 354, or Figure 5 The processing system 502 or scheduler 506 shall execute it.

[0046] Method 400 includes: at block 402, determining core usage information. For example, a scheduler of a processing device or system (e.g., a multi-core processing device, such as a multi-core processing device with a big.LITTLE architecture) may obtain (e.g., determine, detect, or receive) information indicating core usage information, such as core CPU usage information. Core usage information may also be referred to as core workload information and may include or correspond to one or more of the following: IPC (instructions per clock cycle) information, MIPS (millions of instructions per second) information, frequency level information, CPU activity duration information (e.g., time or percentage), or any combination thereof.

[0047] Method 400 includes: at block 404, determining cache miss rate information. For illustration, the scheduler may obtain (e.g., determine, detect, or receive) information indicating cache miss rate information, such as dedicated CPU cache miss rate information (e.g., L2 cache), shared CPU cache miss rate information (e.g., L3 cache and / or LLCC), or combinations thereof. Cache miss rate information may also be referred to as cache workload information and may include or correspond to one or more of the following: cache misses per thousand instructions (MPKI) information, cache accesses per thousand instructions (APKI) information, cache miss rate information (e.g., MPKI divided by APKI), CPU stall time information, CPU stall ratio information, CPU stall due to cache miss information, million cycles per second (MCPS) information, or any combination thereof. MCPS information may indicate the amount of CPU stall due to cache latency.

[0048] Method 400 includes, at box 406, identifying the CPU bottleneck and its cause. For illustration, the scheduler may determine the existence and nature of a CPU bottleneck (e.g., a bottleneck caused by CPU workload / latency or cache workload / latency information) based on core usage information and cache miss rate information. The scheduler may perform different scheduling actions based on identifying a bottleneck or based on identifying that there is no bottleneck. See also... Figure 6A and Figure 6B A diagram further illustrates this type of scheduling action.

[0049] like Figure 4 As shown, the scheduler can use one or more conditions (such as one or more thresholds) to identify bottlenecks. For example, the scheduler can compare cache miss rate information with corresponding thresholds to identify cache-related bottlenecks. As another example, the scheduler can compare core usage information with corresponding thresholds to identify CPU-related bottlenecks.

[0050] Method 400 includes actions performed by the scheduler in response to bottleneck determination, at blocks 408-412. In response to the scheduler determining CPU and cache bottlenecks, at block 408, the method includes switching at least one active core of a first type to at least one core of a second type, such as one with a larger and / or more responsive cache. For example, the scheduler may switch one or more silver cores with smaller caches to gold cores with larger caches to address both cache and CPU bottlenecks. Core switching can more efficiently address CPU workloads caused by cache misses or latency compared to introducing additional, smaller, more efficient cores with smaller caches.

[0051] In response to the scheduler determining a CPU bottleneck and determining that there is no cache bottleneck, at block 410, the method includes: activating at least one additional core of the first type, in addition to the currently active cores of the first type. For example, the scheduler may activate one or more additional silver cores or bring those one or more additional silver cores online to add additional processing resources to address a CPU bottleneck not caused by cache misses or cache latency issues. The additional cores may be inactive cores, paused cores, or a combination thereof. Adding a smaller, additional core can address the bottleneck more efficiently than introducing a larger core or switching cores.

[0052] In response to the scheduler determining that there is no bottleneck (or at least no CPU bottleneck), at block 412, the method includes: maintaining the currently active core. For example, the scheduler may not activate one or more additional cores of the current core type or introduce one or more additional cores, or introduce another core type. Alternatively, if the workload is sufficiently low, if the cache miss rate is sufficiently low, or both (such as being less than a corresponding second threshold), the scheduler may reduce the core count and / or migrate tasks from higher cache cores to lower cache cores to save power. Reducing cores or switching cores under low workload and miss rate can save power without affecting performance or affecting performance in a user-perceptible manner.

[0053] Figure 5 This is a block diagram 500 illustrating a processing system architecture for the enhanced processing core scheduling scheme described herein, according to some embodiments of this disclosure. Figure 5 The image shows a processing system 502. The processing system 502 is coupled to a DDR 504 and a scheduler 506.

[0054] Processing system 502 includes one or more processing cores 512, each with its own dedicated cache, and includes a shared cache for the one or more processing cores 512. Processing cores 512 may include various types of processing cores and may be arranged as clusters of similar types of processing cores. Different clusters and / or types of processing cores may have different sizes to handle different workloads and consume different amounts of power. Additionally, different types of processing cores may have different amounts of dedicated cache, such as L2 cache.

[0055] One or more processing cores 512 may include core 522 of a first cluster (e.g., a silver core) and core 524 of a second cluster (e.g., a gold core). Core 522 of the first cluster includes first cluster core 532, and core 524 of the second cluster includes second cluster core 542. Shared caches include L3 cache 514 and LLCC 516. Figure 5 In the example, the first cluster core 532 in the first cluster core 522 has less cache than the second cluster core 542 in the second cluster core 524. Additionally, in some implementations, specific cores in the cluster may have more cache than the cores of the cluster, such as silver+ cores, gold+ cores, main cores, etc. For illustration, a specific core in the first cluster core 532 may have more L2 cache than other cores in the first cluster core 532 of the first cluster core 522.

[0056] DDR may include or correspond to Figure 3 The main memory 344, and the scheduler 506 may include or correspond to Figure 3 The cache controller 301, processor controller 352, or both. For illustration, scheduler 506 may include or correspond to processor core scheduler 354. Scheduler 506 may include or correspond to entities configured to perform core scheduling and control operations (such as, see reference 354). Figure 4 The enhanced processing core scheduling scheme described herein includes logical components (e.g., core control logic components), such as scheduler 506, which can be configured to receive core usage information and cache miss rate information, and determine which cores to schedule, i.e., which cores are active. For example, scheduler 506 can receive core usage information and cache miss rate information, and determine which cores to schedule, i.e., which cores are active. Figure 3 The core or processing core controller or scheduler shown receives core usage information, and the scheduler 506 can receive information from, for example, core usage information. Figure 3 The core (e.g., its L2 cache) or cache controller or scheduler receives cache miss rate information. Scheduler 506 can compare this information on a per-core basis with one or more corresponding thresholds 562 to determine whether to adjust active cores, such as reference... Figure 4 As described, threshold 562 may include: one or more core workload thresholds, such as core busy or core online thresholds and core not busy or core offline thresholds; and one or more cache workload thresholds, such as cache busy or cache bottleneck thresholds and cache not busy or no bottleneck thresholds.

[0057] At various times during operation, the processing system 502 may have cores in different states or conditions (such as active, inactive, suspended, etc.). Figure 5In the example, processing system 502 has active cores 552 and inactive cores 554. For illustration, a portion of the first cluster cores 532 is active, and another portion of the first cluster cores 532 is paused. In some specific implementations, other cores may be inactive or paused. As described above and referenced... Figure 4 Scheduler 506 performs one or more operations to identify and resolve bottlenecks, such as one or more determinations or comparisons using one or more thresholds in threshold 562. Scheduler 506 can adjust core status to adjust workload and power consumption, such as activating one or more cores, unpausing one or more cores, or deactivating one or more cores. Scheduler 506 can adjust core status, such as... Figure 6A and Figure 6B As shown and further described herein.

[0058] Figure 6A and Figure 6B Each is an example of an implementation scheme according to this disclosure. Figure 5 A block diagram of the enhanced processing core scheduling scheme operation of the processing system architecture (processing system 502).

[0059] refer to Figure 6A , Figure 6A Examples of core switching operations according to some embodiments of this disclosure are depicted. For example, scheduler 506 (e.g., its cache usage and miss rate monitor) can identify cache-related bottlenecks in one or more processor cores of processing system 502 and can determine to switch from a lower cache core to a higher cache core. Figure 6A As shown in the example, scheduler 506 switches from two silver cores to a single gold core by disabling cores 1 and 2 and activating core 7. Scheduler 506 can determine whether to switch from a lower cache core to a higher cache core based on core usage information and cache miss rate information received from cores 1 and 2 indicating a CPU bottleneck caused by a cache bottleneck. For example, the core usage information and cache miss rate information may exceed corresponding thresholds, such as a core busy threshold and a cache miss rate threshold.

[0060] Switching from two silver cores to a single gold core reduces power consumption and provides performance benefits (e.g., increased IPC) compared to introducing or reactivating two additional silver cores to reduce cache bottlenecks. For illustration, in some specific implementations, a single gold core (e.g., core 7) may have the same amount of L2 cache or more than four silver cores (e.g., cores 1 through 4).

[0061] refer to Figure 6B , Figure 6BExamples of core activation operations according to some embodiments of this disclosure are depicted. For example, scheduler 506 (e.g., its cache usage and miss rate monitor) can determine CPU-related bottlenecks (e.g., CPU bottlenecks with low or acceptable cache miss rates) of one or more processor cores of processing system 502 that are not caused by cache-related bottlenecks, and can determine to activate inactive or suspended lower cache cores. Figure 6B As shown in the example, in addition to the two currently active silver cores (core 1 and core 2), scheduler 506 also activates two additional (e.g., suspended) silver cores (core 3 and core 5).

[0062] Scheduler 506 can determine to add additional lower cache cores based on core usage information and cache miss rate information received from cores 1 and 2 indicating that the CPU bottleneck is not caused by a cache bottleneck. For example, the core usage information may be greater than a corresponding threshold, such as a core busy threshold, and the cache miss rate information may be less than a cache miss threshold.

[0063] Adding two additional silver cores reduces power consumption and provides performance benefits compared to migrating tasks to two or more larger gold cores. For illustration, in some specific implementations, four silver cores (e.g., cores 1 to 4) may have less power consumption than a single gold core (e.g., core 7) or a combination of multiple gold cores (e.g., cores 7 and 8).

[0064] While the aspects described herein include adding more lower cache cores, silver cores, or small cores, in other specific implementations, the system (e.g., its scheduler) may reduce the number of cores when core utilization drops below a threshold amount indicated by core workload information, or may add more higher cache cores, gold cores, or large cores when higher cache cores or gold cores are already in use, or when core utilization and cache miss rate drop to above corresponding threshold amounts indicated by core workload information and cache miss information.

[0065] Additionally, while the aspects described herein include switching from lower cache cores, silver cores, or small cores to higher cache cores, gold cores, or large cores, in other specific implementations, when core utilization and cache miss rate drop below corresponding threshold amounts indicated by core workload information and cache miss information, the system (e.g., its scheduler) may switch from higher cache cores, gold cores, or large cores to lower cache cores, silver cores, or small cores.

[0066] Figure 7This is a flowchart illustrating an enhanced processing core scheduling scheme 700, according to some embodiments of the present disclosure, for determining active cores by a multi-processor core processing system based on cache miss rate information. In some specific embodiments, the method may be... Figure 1 The controller 130 of the memory system 110 Figure 2 Storage system 250, Figure 3 System 300 or processor core scheduler 354, or Figure 5 The processing system 502 or scheduler 506 shall execute it.

[0067] Method 700 includes, at block 702, receiving core workload information and cache miss information for one or more cores of the processing system by a scheduler of the processing system comprising multiple processing cores. For example, processor core scheduler 354 or scheduler 506 may determine or receive information indicating core workload and information indicating cache miss rates for one or more active cores of the processing system. For illustration, processor core scheduler 354 may receive cache workload information for a specific processor core from a corresponding cache monitor or processor monitor, and may receive core workload information for a specific processor core from a corresponding processor monitor. As another example, scheduler 506 may receive cache workload information and core workload information from processing system 502 (such as from its cores and caches).

[0068] At box 704, method 700 includes: adjusting which cores to use by a scheduler based on core workload information and cache miss information. For example, the scheduler may adjust which cores are active, suspended, and / or disabled based on core workload information and cache miss information. For illustration, processor core scheduler 354 or scheduler 506 may compare core workload information and cache miss information with corresponding thresholds (such as threshold 562) to determine which cores to use, and then based on that determination, activate additional cores, deactivate cores, switch cores (e.g., migrate workloads from at least one active core to at least one other suspended or inactive core, and reactivate previously active cores), and / or maintain currently active cores, as referenced above. Figures 4 to 6B As described. As an illustrative example, scheduler 506 may compare core workload information with a core workload threshold (e.g., a core busy threshold) of threshold 562, and may compare cache miss rate information with a cache miss rate threshold of threshold 562.

[0069] In other specific implementations, the device (e.g., such as a processor, processing system, or device) may perform additional blocks (or the device may be configured to further perform additional operations). For example, the device (e.g., network node 105 or UE 115) may perform operations as described in the reference. Figures 3 to 8 One or more operations as described. As another example, the device may perform the operations described in the reference above. Figures 3 to 7 The one or more aspects described or presented below.

[0070] In a first aspect, an apparatus includes: a processing system; and a memory coupled to the processing system, wherein the processing system is configured to cause the apparatus to: receive core workload information and cache miss information of one or more cores of the processing system; and adjust which cores to use based on the core workload information and the cache miss information.

[0071] In a second aspect, either alone or in combination with the first aspect, the core workload information indicates core usage information for each core.

[0072] In a third aspect, either alone or in combination with the first or second aspect, the core usage information includes per-core information for one or more of the following: instructions per clock (IPC) information, millions of instructions per second (MIPS) information, frequency level information, CPU activity duration information, or any combination thereof.

[0073] In the fourth aspect, either alone or in combination with one or more of the above aspects, the cache miss information indicates cache miss rate information.

[0074] In the fifth aspect, either alone or in combination with one or more of the aspects mentioned above, the cache miss rate information includes per-core dedicated CPU cache miss rate information, shared CPU cache miss rate information, or a combination thereof.

[0075] In a sixth aspect, either alone or in combination with one or more of the foregoing aspects, the dedicated CPU cache miss rate information includes Level 2 (L2) cache miss rate information, and the shared CPU cache miss rate information includes Level 3 (L3) cache miss rate information, last level (LL) cache miss rate information, or a combination thereof.

[0076] In the seventh aspect, either alone or in combination with one or more of the above aspects, the cache miss rate information includes one or more of the following: cache misses per thousand instructions (MPKI) information, cache accesses per thousand instructions (APKI) information, cache miss rate percentage information, CPU stall time information, CPU stall ratio information, or million cycles per second (MCPS) information.

[0077] In the eighth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including:

[0078] The core status of at least one core of the processing system is determined based on the core workload information, the cache miss information, or both.

[0079] In the ninth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including: comparing the core workload information with a core workload threshold; and comparing the cache miss information with a cache miss rate threshold.

[0080] In a tenth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including: comparing the core workload information with a core workload threshold; and comparing the cache miss information with a cache miss rate threshold based on the result of the comparison between the core workload information and the core workload threshold.

[0081] In the eleventh aspect, the processing system is configured to adjust which cores to use, including switching from cores with lower dedicated cache size to cores with higher dedicated cache size.

[0082] In a twelfth aspect, the processing system is configured to switch cores by: activating a paused core or an inactive core with a first cache size; migrating a task from an active core with a second cache size to the paused core or the inactive core, wherein the second cache size is less than the first cache size.

[0083] In the thirteenth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including: activating one or more suspended cores, inactive cores, or both.

[0084] In the fourteenth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including: activating paused or inactive cores of the same type as the currently active core.

[0085] In the fifteenth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system has a big.LITTLE architecture.

[0086] In the sixteenth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system has multiple types of cores, including a first type of core and a second type of core that is different from the first type of core.

[0087] In the seventeenth aspect, either alone or in combination with one or more of the foregoing aspects, the first type corresponds to a silver core and the second type corresponds to a gold core.

[0088] In the eighteenth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is further configured to: receive second core workload information and second cache miss information for the one or more cores of the processing system; and determine not to adjust the core status based on the second core workload information not meeting the core workload condition and the second cache miss information not meeting the cache miss condition.

[0089] In the nineteenth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including: determining to activate one or more additional cores based on the core workload information satisfying core workload conditions and based on the cache miss information not satisfying cache miss rate conditions.

[0090] In the twentieth aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including: determining which cores to switch based on the core workload information meeting a core workload threshold and based on the cache miss information meeting a cache miss rate threshold.

[0091] In the twenty-first aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is further configured to: determine a CPU bottleneck based on the core workload information and the core workload threshold information; and, in response to determining the CPU bottleneck, determine the cause of the CPU bottleneck based on the cache miss information and the cache miss rate threshold information.

[0092] In the twenty-second aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to determine the CPU bottleneck by comparing CPU MIPS information with a CPU MIPS threshold, and wherein the processing system is configured to determine the cause of the CPU bottleneck by comparing L2 cache miss information with an L2 cache miss rate threshold.

[0093] In the twenty-third aspect, either alone or in combination with one or more of the foregoing aspects, the processing system is configured to adjust which cores to use, including: determining the current L2 cache size of the currently active core; and determining whether one or more cores with more L2 cache than the current L2 cache size are available.

[0094] A twentieth aspect, a method includes: receiving core workload information and cache miss information of one or more cores of a processing system; and adjusting which cores of the processing system to be used based on the core workload information and the cache miss information.

[0095] In a twentieth aspect, a wireless communication device includes: a wireless transceiver; a processing system; and a memory coupled to the processing system, wherein the processing system is configured to cause the device to: receive core workload information and cache miss information of one or more cores of the processing system; and adjust which cores to use based on the core workload information and the cache miss information.

[0096] A twentieth aspect, an apparatus includes: a processing system including a plurality of cores and a core controller; and a memory coupled to the processing system, wherein the core controller is configured to cause the processing system to: receive core workload information and cache miss information of one or more cores of the processing system; and adjust which cores to use based on the core workload information and the cache miss information.

[0097] In a twentieth aspect, an apparatus includes: components for receiving core workload information and cache miss information of one or more cores of a processing system; and components for adjusting which of the one or more cores to be used based on the core workload information and the cache miss information.

[0098] In a twenty-eighth aspect, a non-transitory computer-readable medium includes: program code executable by a computer to cause the computer to receive core workload information and cache miss information of one or more cores of a processing system; and program code executable by a computer to cause the computer to adjust which cores to use.

[0099] The operation of method 400 or method 700 and the corresponding aspects described above can be performed by user equipment (UE) (such as reference). Figure 8 The UE described herein may be used to perform this operation. For example, example operations of method 400 or method 700 (also referred to as “boxes”) may enable UE 815 (e.g., a wireless communication device) to support an enhanced write buffer refresh scheme for writing data to a main storage device capable of storing multiple data bits per storage cell by optimizing the available contiguous memory space in the write buffer after the refresh operation.

[0100] Figure 8 This is a block diagram illustrating details of an example wireless communication system according to one or more aspects. The wireless communication system may include a wireless network 800. The wireless network 800 may, for example, include a 5G wireless network. As those skilled in the art will recognize, Figure 8 The components appearing in this network are likely to have corresponding components in other network arrangements (including, for example, cellular network arrangements and non-cellular network arrangements (e.g., device-to-device, peer-to-peer, or self-organizing network arrangements)).

[0101] Figure 8 The illustrated wireless network 800 includes multiple base stations 805 and other network entities. A base station can be a station communicating with a UE and may also be referred to as an evolved Node B (eNB), a next-generation eNB (gNB), and an access point, etc. Each base station 805 can provide communication coverage for a specific geographic area. In 3GPP, the term "cell" can refer to a specific geographic coverage area of ​​a base station or a base station subsystem serving that coverage area, depending on the context in which the term is used. In the specific implementation of the wireless network 800 herein, base stations 805 may be associated with the same operator or different operators (e.g., the wireless network 800 may include multiple operator wireless networks). Additionally, in the specific implementation of the wireless network 800 herein, base station 805 may use one or more frequencies (e.g., licensed spectrum, unlicensed spectrum, or one or more bands of combinations thereof) from the same frequencies as neighboring cells to provide wireless communication. In some examples, a single base station 805 or UE 815 may be operated by more than one network operating entity. In some other examples, each base station 805 and UE 815 may be operated by a single network operating entity.

[0102] Base stations can provide communication coverage for macro cells, small cells (such as pico cells or femto cells), or other types of cells. Macro cells typically cover a relatively large geographic area (e.g., a radius of several kilometers) and allow unrestricted access by UEs with service subscriptions to a network provider. Small cells (such as pico cells) typically cover a relatively small geographic area and allow unrestricted access by UEs with service subscriptions to a network provider. Small cells (such as femto cells) also typically cover a relatively small geographic area (e.g., a home) and, in addition to unrestricted access, provide restricted access by UEs associated with the femto cell (e.g., UEs in a Closed Subscriber Group (CSG), UEs of users in a home, etc.). A base station for a macro cell may be referred to as a macro base station. A base station for a small cell may be referred to as a small cell base station, pico base station, femto base station, or home base station. Figure 8 In the examples shown, base stations 805d and 805e are conventional macro base stations, while base stations 805a to 805c are macro base stations implemented using one of 3D, full-dimensional (FD), or massive MIMO. Base stations 805a to 805c utilize their higher-dimensional MIMO capabilities to employ 3D beamforming in elevation and azimuth beamforming to increase coverage and capacity. Base station 805f is a small cell base station, which can be a home node or a portable access point. A base station can support one or more (e.g., two, three, and four cells, etc.) cells.

[0103] The Wireless Network 800 can support synchronous or asynchronous operation. For synchronous operation, base stations can have similar frame timings, and transmissions from different base stations can be roughly aligned in time. For asynchronous operation, base stations can have different frame timings, and transmissions from different base stations may not be aligned in time. In some scenarios, the network can be enabled or configured to handle dynamic switching between synchronous and asynchronous operations.

[0104] UE 815 is distributed throughout the wireless network 800, and each UE can be stationary or mobile. It should be understood that although mobile devices are generally referred to as UEs in standards and specifications issued by 3GPP, such devices may additionally or otherwise be referred to by those skilled in the art as mobile station (MS), subscriber station, mobile unit, subscriber unit, radio unit, remote unit, mobile device, radio device, wireless communication device, remote device, mobile subscriber station, access terminal (AT), mobile terminal, radio terminal, remote terminal, handphone, terminal, user agent, mobile client, client, gaming device, augmented reality device, vehicle component, vehicle equipment or vehicle module, or some other suitable term. In this document, a “mobile” device or UE does not necessarily have the ability to move and may be stationary. Some non-limiting examples of mobile devices include specific implementations that may include one or more UEs in UE 815, including mobile phones, cellular phones (handphones), smartphones, Session Initiation Protocol (SIP) phones, Wireless Local Loop (WLL) stations, laptop computers, personal computers (PCs), notebooks, netbooks, smartbooks, tablet devices, and personal digital assistants (PDAs). Additionally, mobile devices can be IoT or “Internet of Everything” (IoE) devices, such as automobiles or other transportation vehicles, satellite radios, Global Positioning System (GPS) devices, Global Navigation Satellite System (GNSS) devices, logistics controllers, aircraft, smart energy or security devices, solar panels or solar arrays, urban lighting, water supply or other infrastructure; industrial automation and enterprise equipment; consumer and wearable devices, such as glasses, wearable cameras, smartwatches, health or fitness trackers, mammalian implantable devices, posture tracking devices, medical devices, digital audio players (e.g., MP3 players), cameras, game consoles, etc.; and digital home or smart home devices, such as home audio, video and multimedia equipment, appliances, sensors, vending machines, smart lighting, home security systems, smart meters, etc. In one aspect, a UE can be a device that includes a Universal Integrated Circuit Card (UICC). In another aspect, a UE can be a device that does not include a UICC. In some aspects, a UE that does not include a UICC may also be referred to as an IoE device. Figure 8 The UEs 815a to 815d shown in the illustration are examples of mobile smartphone-type devices accessing the wireless network 800. The UE can also be a machine specifically configured for connected communications, including machine-type communications (MTC), enhanced MTC (eMTC), and narrowband IoT (NB-IoT). Figure 8 The UEs 815e to 815k shown are examples of various machines configured for communication to access the wireless network 800.

[0105] Mobile devices (such as UE 815) can communicate with any type of base station (whether macro base station, pico base station, femto base station, or relay station). Figure 8 In this context, the communication link (represented by a lightning bolt) indicates radio transmissions between the UE and a serving base station (which is designated to serve the UE on the downlink or uplink), or expected transmissions between base stations, as well as backhaul transmissions between base stations. The UE may operate as a base station or other network node in some scenarios. Backhaul communication between base stations of the Wireless Network 800 can be performed using wired or wireless communication links.

[0106] In operation, at wireless network 800, base stations 805a to 805c use 3D beamforming and cooperative spatial technologies such as Cooperative Multipoint (CoMP) or Multi-Connection to serve UEs 815a and 815b. Macro base station 805d performs backhaul communication with base stations 805a to 805c and the small cell (base station 805f). Macro base station 805d also transmits multicast services subscribed to and received by UEs 815c and 815d. Such multicast services may include mobile TV or streaming video, or may include other services for providing community information, such as weather emergencies or alerts, such as Amber Alerts or Grey Alerts.

[0107] The specific implementation of the wireless network 800 supports mission-critical communication with ultra-reliable and redundant links for mission-critical equipment such as the UE 815e used as an air vehicle. Redundant communication links with the UE 815e include links from macro base stations 805d and 805e, as well as small cell base station 805f. Other machine-type devices such as the UE 815f (thermometer), UE 815g (smart meter), and UE 815h (wearable device) can communicate directly with base stations such as the small cell base station 805f and macro base station 805e via the wireless network 800, or in a multi-hop configuration by communicating with another user equipment that relays its information to the network, such as the UE 815f transmitting temperature measurement information to the smart meter UE 815g, which then reports it to the network via the small cell base station 805f. The wireless network 800 can also provide additional network efficiency through dynamic, low-latency TDD or low-latency FDD communication, such as in vehicle-to-vehicle (V2V) mesh networks between UEs 815i to 815k communicating with macro base station 805e.

[0108] In various specific implementations, technologies and devices can be used in wireless communication networks such as Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, Orthogonal FDMA (OFDMA) networks, Single Carrier FDMA (SC-FDMA) networks, LTE networks, GSM networks, fifth-generation (5G) or new radio (NR) networks (sometimes referred to as "5GNR" networks, systems, or devices), and other communication networks. As described herein, the terms "network" and "system" can be used interchangeably. For example, a CDMA network can implement radio technologies such as Universal Terrestrial Radio Access (UTRA) and cdma2000. UTRA includes Wideband CDMA (W-CDMA) and Low Chip Rate (LCR). CDMA2000 encompasses the IS-2000, IS-95, and IS-856 standards. For example, a TDMA network can implement radio technologies such as the Global System for Mobile Communications (GSM). The 3rd Generation Partnership Project (3GPP) defines the standard for GSM EDGE (Enhanced Data Rate GSM Evolution) Radio Access Network (RAN) (also known as GERAN). OFDMA networks can implement radio technologies such as Evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, and flash-OFDM. UTRA, E-UTRA, and GSM are part of the Universal Mobile Telecommunications System (UMTS). In particular, Long Term Evolution (LTE) is a UMTS version using E-UTRA. Different network types can use different Radio Access Technologies (RATs) and RANs.

[0109] In some specific implementations, the devices of the wireless network 800 may include or access memory systems, such as those mentioned in the reference above. Figures 1 to 4 The described flash memory system. As a non-limiting example, UE 815 may include or correspond to Figure 1 and Figure 3 The host device 102, and Figure 1 and Figure 3 The memory system 110 may include or correspond to a storage device integrated in or removably coupled to the UE 815, such as an SSD, MMC, eMMC, RS-MMC, micro MMC, SD card, mini SD, micro SD, USB storage device, UFS device, CF card, SM card, or Memory Stick. Additionally or alternatively, the base station 805 may include or correspond to a storage device integrated in or removably coupled to the UE 815. Figure 1 and Figure 3 The host device 102, and Figure 1 and Figure 3The memory system 110 may include or correspond to a storage device integrated in or removably coupled to the base station 805, such as an SSD, MMC, eMMC, RS-MMC, micro MMC, SD card, mini SD, micro SD, USB storage device, UFS device, CF card, SM card, or memory stick.

[0110] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, implementations or uses may be achieved via integrated chip implementations or other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail or purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to use cases or applications, the applicability of various types of the described innovations is evident. The scope of implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more of the described aspects. In some practical contexts, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. The innovations described herein are expected to be implemented in a wide variety of specific implementations of different sizes, shapes and constructions, including both large and small devices, chip-level components, multi-component systems (e.g., radio frequency (RF) chains, communication interfaces, processors), distributed deployments, end-user equipment, etc.

[0111] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0112] This article references Figures 1 to 8The components, functional blocks, and modules described include processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, etc., or any combination thereof. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other terms. Furthermore, the features discussed herein can be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0113] For those skilled in the art: Reference Figures 1 to 5 and Figure 8 The described one or more boxes (or operations) may be combined with one or more boxes (or operations) described in another drawing with reference to the accompanying drawings. For example, Figure 1 One or more boxes (or operations) can be associated with Figure 3 A combination of one or more boxes (or actions). As another example, with... Figure 1 One or more associated boxes can be associated with Figure 4 or Figure 5 A combination of one or more boxes (or operations). Additionally or alternatively, refer to the above. Figures 1 to 3 One or more operations described can be compared with the reference Figures 4 to 5 or Figure 8 The described combination of one or more operations. Additionally or alternatively, one or more operations of the methods described herein may be performed in a different order than those described herein. For example, method 600 of Figure 6 or... Figure 7 The operations of method 700 can be performed out of order, or in accordance with Figures 6 to 700. Figure 7 The different execution orders shown.

[0114] Those skilled in the art will also recognize that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein are merely examples, and that components, methods, or interactions of various aspects of this disclosure can be combined or performed in ways other than those illustrated and described herein.

[0115] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the specific implementations disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been broadly described in terms of functionality and illustrated in the aforementioned exemplary components, blocks, modules, circuits, and processes. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0116] Hardware and data processing means for implementing the various exemplary logic, logic blocks, modules, and circuits described herein can be implemented or executed using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some embodiments, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processes and methods may be performed by circuitry specific to a given function.

[0117] In one or more aspects, the described functions may be implemented in hardware, digital electronic circuits, computer software, firmware, including the structures disclosed in this specification and their structural equivalents or any combination thereof. Implementation of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus.

[0118] If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. The process of the methods or algorithms disclosed herein can be implemented in a processor-executable software module that can reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that can be implemented to transfer a computer program from one location to another. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible to a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operation of a method or algorithm may reside as a set of code and instructions or any combination of code and instructions on a machine-readable medium and a computer-readable medium that may be incorporated into a computer program product.

[0119] Various modifications to the specific embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific embodiments without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific embodiments shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles disclosed herein, and the novel features thereof.

[0120] Additionally, those skilled in the art will readily recognize that, for the convenience of describing the accompanying drawings, contrasting terms such as “upper” and “lower” or “front” and “back” or “top” and “bottom” are sometimes used, indicating relative positioning on a correctly oriented page corresponding to the orientation of the drawings, and may not reflect the correct orientation of any device as implemented.

[0121] Certain features described in this specification in the context of a single embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even originally claimed in this way, one or more features from the claimed combination may be removed from that combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0122] Similarly, although operations are depicted in a specific order in the figures, this should not be construed as requiring such operations to be performed in the indicated specific order or sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the figures may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be combined with the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any illustrated operation. In some contexts, multitasking and parallel processing are advantageous. Moreover, the separation of the various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, some other embodiments also fall within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result.

[0123] As used herein (including the claims), the term “or” in a list of two or more items means that any one of the listed items may be used alone, or any combination of two or more listed items may be used. For example, if a composition is described as containing component A, B, or C, the composition may contain A alone; B alone; C alone; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein (including the claims), “or” in a list of items beginning with “at least one of” indicates a separate list, such that a list such as “at least one of A, B, or C” refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination of any of these items. The term “substantially” is defined as being substantially, but not necessarily entirely, what is specified (and includes what is specified; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel), as understood by one of ordinary skill in the art. In any disclosed specific implementation, the term “substantially” may be used in place of “[percentage]” for the specified content, where the percentage includes 0.1%, 1%, 5% or 10%.

[0124] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, said apparatus comprising: Processing system; and A memory coupled to the processing system; The processing system is configured to enable the device to: Receive core workload information and cache miss information of one or more cores of the processing system; as well as The core workload information and cache miss information are used to determine which cores to use.

2. The device according to claim 1, wherein the core workload information indicates core usage information for each core.

3. The device of claim 2, wherein the core usage information includes per-core information for one or more of the following: instructions per clock (IPC) information, millions of instructions per second (MIPS) information, frequency level information, CPU activity duration information, or any combination thereof.

4. The device of claim 1, wherein the cache miss information indicates cache miss rate information, and wherein the cache miss rate information includes per-core dedicated CPU cache miss rate information, shared CPU cache miss rate information, or a combination thereof.

5. The device according to claim 4, wherein the dedicated CPU cache miss rate information includes Level 2 (L2) cache miss rate information, and wherein the shared CPU cache miss rate information includes Level 3 (L3) cache miss rate information, last level (LL) cache miss rate information, or a combination thereof.

6. The device according to claim 5, wherein the cache miss rate information includes one or more of the following: cache misses per thousand instructions (MPKI) information, cache accesses per thousand instructions (APKI) information, cache miss rate percentage information, CPU stall time information, CPU stall ratio information, or million cycles per second (MCPS) information.

7. The device of claim 1, wherein the processing system is configured to adjust which cores to use, comprising: The core status of at least one core of the processing system is determined based on the core workload information, the cache miss information, or both.

8. The device of claim 1, wherein the processing system is configured to adjust which cores to use, comprising: Compare the core workload information with the core workload threshold; as well as The cache miss information is compared with the cache miss rate threshold.

9. The device of claim 1, wherein the processing system is configured to adjust which cores to use, comprising: Compare the core workload information with the core workload threshold; as well as Based on the comparison result between the core workload information and the core workload threshold, the cache miss information is compared with the cache miss rate threshold.

10. The device of claim 9, wherein the processing system is configured to adjust which cores to use, comprising: Switch from a core with a smaller dedicated cache size to a core with a larger dedicated cache size.

11. The device of claim 10, wherein the processing system is configured to switch cores comprising: Activate a paused or inactive core with the first cache size; The task is migrated from an active core with a second cache size to the paused core or the inactive core, wherein the second cache size is smaller than the first cache size; as well as The core of the activity with the second cache size is disabled.

12. The device of claim 11, wherein the processing system is configured to adjust which cores to use, comprising: Activate one or more paused cores, inactive cores, or both.

13. The device of claim 12, wherein the processing system is configured to adjust which cores to use, comprising: Activate a paused or inactive core of the same type as the currently active core.

14. The apparatus of claim 11, wherein the processing system is further configured to: Receive second core workload information and second cache miss information of one or more cores of the processing system; and The core status is determined not to be adjusted based on the fact that the second core workload information does not meet the core workload condition and the second cache miss information does not meet the cache miss condition.

15. The device of claim 1, wherein the processing system is configured to adjust which cores to use, comprising: Based on the core workload information satisfying the core workload condition and based on the cache miss information not satisfying the cache miss rate condition, one or more additional cores are activated.

16. The device of claim 1, wherein the processing system is configured to adjust which cores to use, comprising: The core switching is determined based on whether the core workload information meets the core workload threshold and whether the cache miss information meets the cache miss rate threshold.

17. The apparatus of claim 1, wherein the processing system is further configured to: The CPU bottleneck is determined based on the core workload information and core workload threshold information; and In response to identifying the CPU bottleneck, the cause of the CPU bottleneck is determined based on the cache miss information and the cache miss rate threshold information.

18. The apparatus of claim 17, wherein the processing system is configured to determine the CPU bottleneck by comparing CPU MIPS information with a CPU MIPS threshold, and wherein the processing system is configured to determine the cause of the CPU bottleneck by comparing L2 cache miss information with an L2 cache miss rate threshold.

19. The device of claim 1, wherein the processing system is configured to adjust which cores to use, comprising: Determine the current L2 cache size of the core of the current activity; as well as Determine whether one or more cores with more L2 cache than the current L2 cache size are available.

20. A method comprising: Receive and process core workload information and cache miss information for one or more cores of the system. as well as The core workload information and cache miss information are used to determine which cores of the processing system should be used.

Images