Multi-gate transistor pixel circuit, display device and control method thereof

Abstract

A pixel circuit is disclosed, comprising at least a first transistor, a light-emitting element, and a driving circuit. The first transistor is a multi-gate transistor, such as a multi-mode transistor (MMT). The first transistor includes: a current-controlling gate configured to control the amplitude of a current supplied from a source region of the first transistor based on a first voltage applied to the current-controlling gate, the current-controlling gate being disposed opposite to the source electrode of the first transistor; and a switching gate configured to block or allow current flow in a channel region of the first transistor based on a second voltage applied to the switching gate. The light-emitting element is connected to the source or drain of the first transistor such that, in use, the current flowing through the light-emitting element is controlled by the current-controlling gate of the first transistor and is blocked or allowed to flow through the light-emitting element under the control of the switching gate of the first transistor. The driving circuit is configured to independently control the first voltage and the second voltage to independently control the amplitude of the current and the duration of current flow through the light-emitting element. A corresponding method for controlling such a pixel circuit and a display device including multiple pixel circuits are also disclosed.

Description

Technical Field

[0001] This invention relates to pixel circuits. More specifically, this invention relates to pixel circuits including multi-gate (or multiple-gate) transistors, display devices including such pixel circuits, and control methods thereof. Background Technology

[0002] Self-emissive electronic information displays comprise arrays of millions of pixels, which are in turn composed of light-emitting devices (LEDs) and electronic circuitry controlling the brightness of the LEDs. Pixel circuitry primarily consists of transistors (which act as current sources or switches, with conventional transistors providing both functions simultaneously by biasing gate-controlled channel regions) and capacitors. A simple pixel circuit, in addition to the LEDs, also has two transistors and one capacitor (2T1C), but due to the non-ideal nature of all the electronic components, these simple circuits cannot provide uniformity over a large area, resulting in unacceptable non-uniformity or flickering in the image. For this reason, more complex pixel architectures (power-inefficient pixel driving / programming techniques) (e.g., seven transistors and two capacitors, 7T2C) are used, at the cost of pixel size and the complexity of the electronic driving scheme. Therefore, it would be desirable to have smaller pixel circuitry to increase density and thus achieve higher image resolution, preferably with improved uniformity and power efficiency compared to existing solutions. Summary of the Invention

[0003] According to a first aspect of the invention, a pixel circuit is provided, the pixel circuit comprising: a first transistor including a current-control gate and a switching gate, the current-control gate being configured to control the amplitude of a current supplied by a source region (e.g., a source-gate overlap region) of the first transistor depending on a first voltage applied to the current-control gate, the switching gate being configured to block or allow current flow in a channel region of the first transistor depending on a second voltage applied to the switching gate; a light-emitting element connected to the source or drain of the first transistor such that, in use, current flowing through the light-emitting element is controlled by a current set by the current-control gate of the first transistor, and is blocked or allowed to flow through the light-emitting element under the control of the switching gate of the first transistor; and a driving circuit configured to independently control the first voltage and the second voltage to independently control the amplitude of the current and the duration of current flow through the light-emitting element.

[0004] In some embodiments, according to a first aspect, the first transistor includes: a source; a drain spaced apart from the source; a semiconductor region disposed between the source and the drain; and an insulating region disposed above the semiconductor region; wherein a current-controlled gate is configured to control the amplitude of a current flowing through the semiconductor region between the source and the drain depending on a first voltage applied to the current-controlled gate, the current-controlled gate being separated from the source by the semiconductor region and the insulating region; and wherein a switching gate is configured to block or allow the current to flow through the semiconductor region between the source and the drain depending on a second voltage applied to the switching gate.

[0005] In some embodiments, according to the first aspect, the drive circuit includes: a first capacitor connected to a current-controlled gate such that, in use, a voltage on the first capacitor can be applied to the current-controlled gate as a first voltage; and a second capacitor connected to a switching gate such that, in use, a voltage on the second capacitor can be applied to the switching gate as a second voltage.

[0006] In some embodiments, according to the first aspect, the driving circuit further includes a second transistor connected between the second capacitor and the first reference voltage node, such that in use, when the second transistor is in the ON state, the voltage on the second capacitor can be reset to the voltage at the first reference voltage node.

[0007] In some embodiments, according to the first aspect, the driving circuit further includes a third transistor connected between the current-controlled gate and the switching gate, such that in use, when the third transistor is in the ON state, the voltage at the current-controlled gate is the same as the voltage at the switching gate.

[0008] In some implementations, according to the first aspect, the third transistor is further connected in series with the second transistor.

[0009] In some implementations, according to the first aspect, the driving circuit further includes a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to the data signal input.

[0010] In some implementations, according to the first aspect, the source of the first transistor is connected to the data signal input via both its source and drain, such that during use, when both the third and fourth transistors are on, the first and second capacitors can be charged to a value equal to V. DATA + V th The voltage, its V DATA It is the voltage at the data signal input, and V thIt is the threshold voltage of the first transistor.

[0011] In some implementations, according to the first aspect, the driving circuit further includes a fifth transistor connected between the source of the first transistor and the data signal input.

[0012] In some implementations, according to the first aspect, the respective gates of the fourth and fifth transistors are connected to a first control input for receiving a first control signal.

[0013] In some implementations, according to the first aspect, the driving circuit further includes a sixth transistor connected between the source of the first transistor and a ground plane, such that in use, the sixth transistor can be switched to an on state to allow current to flow through the first transistor and the light-emitting component, and can be switched to an off state to isolate the data signal input from the ground plane.

[0014] In some embodiments, according to the first aspect, the driving circuit further includes a seventh transistor connected in series between the first transistor and the light-emitting component, such that in use, when the seventh transistor is in the ON state, current can flow through the first transistor and the light-emitting component.

[0015] In some embodiments, according to the first aspect, the driving circuit further includes an eighth transistor connected between the first capacitor and the second reference voltage node, such that in use, when the eighth transistor is turned on, the first capacitor can be charged to the voltage at the second reference voltage node.

[0016] In some implementations, according to the first aspect, the respective gates of the second transistor and the eighth transistor are connected to a second control input for receiving a second control signal, and the respective gates of the third transistor and the fourth transistor are connected to a third control input for receiving a third control signal.

[0017] In some embodiments, according to the first aspect, the driving circuit includes: a capacitor connected between the source and current-controlled gate of a first transistor; and a second transistor connected between the current-controlled gate and a data signal input, wherein the switching gate and drain of the first transistor are connected to a ground plane.

[0018] According to a second aspect of the present invention, a display device is provided, the display device comprising a plurality of pixel circuits according to the first aspect.

[0019] In some implementations, according to the second aspect, the display device includes a control circuit system configured to provide control signals to a plurality of pixel circuits to control the switching of one or more transistors within each pixel circuit.

[0020] According to a third aspect of the invention, a method for controlling a pixel circuit is provided, the pixel circuit including a first transistor including a current control gate and a switching gate, the current control gate being configured to control the amplitude of a current supplied from a source region of the first transistor depending on a first voltage applied to the current control gate, the switching gate being configured to block or allow current flow in a channel region of the first transistor depending on a second voltage applied to the switching gate, the pixel circuit further including a light-emitting element and a driving circuit, the light-emitting element being connected to the source or drain of the first transistor such that, in use, current flowing through the light-emitting element is controlled by the current control gate of the first transistor and is blocked or allowed to flow through the light-emitting element under the control of the switching gate of the first transistor, the method comprising: during an emission phase, using the driving circuit to independently control the first voltage and the second voltage to independently control the amplitude of the current and the duration of current flow through the light-emitting element.

[0021] In some embodiments, according to a third aspect, the driving circuit includes a first capacitor connected to a current-controlled gate and a second capacitor connected to a switching gate, wherein during the emission phase, a voltage on the first capacitor is applied as a first voltage to the current-controlled gate, and a voltage on the second capacitor is applied as a second voltage to the switching gate.

[0022] In some implementations, according to a third aspect, the method includes: during a reset phase, setting a first capacitor to a first voltage level and setting a second capacitor to a second voltage level.

[0023] In some embodiments, according to a third aspect, the driving circuit further includes a second transistor connected between the second capacitor and the first reference voltage node, such that in use, when the second transistor is in the ON state, the voltage on the second capacitor can be reset to the voltage at the first reference voltage node, and wherein the driving circuit further includes a third transistor connected between the current control gate and the switching gate, such that in use, when the third transistor is in the ON state, the voltage at the current control gate is the same as the voltage at the switching gate, wherein setting the first capacitor to a first voltage level and setting the second capacitor to a second voltage level includes: switching the second transistor and the third transistor to the ON state so that the first voltage level and the second voltage level of the first capacitor and the second capacitor are respectively set to the voltage at the first reference voltage node.

[0024] In some implementations, according to the third aspect, during the reset phase, the voltage at the first reference voltage node is maintained at a voltage level higher than the maximum level of the first or second voltage to be applied to the current control gate and the switching gate, respectively, during the transmit phase.

[0025] In some embodiments, according to a third aspect, the driving circuit further includes a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect a second capacitor to a data signal input, the method comprising: during a first stage of the programming phase, switching the third transistor and the fourth transistor to an on state to connect both the first capacitor and the second capacitor to the data signal input so as to set the respective charge levels of the first capacitor and the second capacitor based on the voltage at the data signal input during the first stage; and during a second stage of the programming phase, switching the third transistor to an off state while the fourth transistor is on state so as to further set the charge level of the second capacitor based on the voltage at the data signal input during the second stage.

[0026] In some embodiments, according to the third aspect, the driving circuit further includes a fifth transistor connected between the source of the first transistor and the data signal input, and a sixth transistor connected between the source of the first transistor and a ground plane, wherein during the first and second stages of the programming phase, the fifth transistor switches to an on state to connect the fourth transistor to the data signal input via the source and drain of the first transistor, and the sixth transistor switches to an off state to isolate the data signal input from the ground plane, and wherein during the transmit phase, the sixth transistor switches to an on state to allow current to flow through the first transistor and the light-emitting component, and the fifth transistor switches to an off state.

[0027] In some implementations, according to the third aspect, the driving circuit further includes a seventh transistor connected in series between the first transistor and the light-emitting component, wherein during the emission phase, the seventh transistor switches to an on state, allowing current to flow through the first transistor and the light-emitting component.

[0028] In some embodiments, according to the third aspect, the driving circuit further includes a second transistor connected between the second capacitor and the first reference voltage node, such that in use, when the second transistor is turned on, the voltage on the second capacitor can be reset to the voltage at the first reference voltage node, and wherein the driving circuit further includes an eighth transistor connected between the first capacitor and the second reference voltage node, such that in use, when the eighth transistor is turned on, the first capacitor can be charged to the voltage at the second reference voltage node, wherein setting the first capacitor to a first voltage level and setting the second capacitor to a second voltage level includes: switching the second transistor on to set the second voltage level of the second capacitor to the voltage at the first reference voltage node; and switching the eighth transistor on to set the first voltage level of the first capacitor to the voltage at the second reference voltage node.

[0029] In some implementations, according to the third aspect, the first reference voltage node includes a ground plane such that the voltage at the first reference voltage node is a ground voltage.

[0030] In some embodiments, according to a third aspect, the driving circuit further includes a third transistor connected between a current-controlled gate and a source-controlled gate, such that, in use, when the third transistor is in the ON state, the voltage at the current-controlled gate is the same as the voltage at the source-controlled gate, and the driving circuit further includes a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect a second capacitor to a data signal input, the method comprising: during a programming phase, switching the third transistor and the fourth transistor to the ON state to connect both the first capacitor and the second capacitor to the data signal input, so as to set the respective charge levels of the first capacitor and the second capacitor depending on the voltage at the data signal input during the programming phase. Attached Figure Description

[0031] Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 A multi-gate transistor including a current-controlled gate and a switching gate is shown according to an embodiment of the present invention; Figure 2 A first pixel circuit including a multi-gate transistor is shown according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating a method for controlling a pixel circuit including a multi-gate transistor according to an embodiment of the present invention; Figure 4This is a timing diagram showing the reset phase, programming phase, holding phase, and emission phase during the operation of the first pixel circuit; Figure 5 The current flow in the first pixel circuit is shown during the reset phase; Figure 6 The current flow in the first pixel circuit during the first stage of pulse amplitude modulation in the programming phase is shown. Figure 7 The current flow in the first pixel circuit during the second stage of pulse width modulation in the programming phase is shown. Figure 8 The first pixel circuitry during the holding phase is shown; Figure 9 The current flow in the first pixel circuitry during the emission phase is shown; Figure 10 The transmission characteristics of a conventional thin-film transistor (TFT) on a linear scale (left side) and a semi-logarithmic scale (middle side) are shown, as well as the output characteristics on a linear scale (right side). Figure 11 The transport characteristics of a multi-gate multimode transistor (MMT) with a current-controlled gate are shown on a linear scale (left panel) and a semi-logarithmic scale (right panel). Figure 12 The multi-gate MMT transfer characteristics for switching gates are shown in linear scale (left panel) and semi-logarithmic scale (right panel); Figure 13 The linearly scaled output characteristics of the multi-gate MMT in the first pixel circuit are shown. Figure 14 The node voltages in the first pixel circuit during the reset and programming phases are shown. Figure 15 The node voltage and drain current during the operation of the first pixel circuit are shown; Figure 16 The node voltage and drain current for pulse amplitude modulation (PAM) operation providing the first pixel circuitry are shown. Figure 17 The node voltage and drain current providing pulse width modulation (PWM) operation for the first pixel circuit are shown; Figure 18 A second pixel circuit including a multi-gate transistor is shown according to an embodiment of the present invention; Figure 19 This is a timing diagram showing the reset and programming phases during the operation of the second pixel circuit; Figure 20 The current flow in the second pixel circuit during the reset phase is shown; Figure 21 The current flow in the second pixel circuit is shown during the programming phase; Figure 22 The current flow in the second pixel circuitry during the emission phase is shown; Figure 23 The transfer characteristics of the multi-gate transistor in the second pixel circuit are shown on a linear scale (left panel) for the current-controlled gate (CG1) and on a semi-logarithmic scale (right panel) for the switching gate. Figure 24 The output characteristics of the multi-gate transistor in the second pixel circuit are shown in linear scale (left image) and semi-logarithmic scale (right image); Figure 25 The diagram shows the results for various interface charge values. Q i The switching gate transfer characteristics of the multi-gate transistor in the second pixel circuit; Figure 26 The diagram shows the node voltages in the second pixel circuit for two values ​​of the data signal during the reset, programming, and transmit phases (left panel) and a close-up of the node voltages for a data signal value equal to 3 V (right panel). Figure 27 The drain current of the multi-gate transistor across the frame duration of the second pixel circuit is shown for three values ​​of the data signal; Figure 28 A third pixel circuit including a multi-gate transistor is shown according to an embodiment of the present invention; Figure 29 A fourth pixel circuit including a multi-gate transistor is shown according to an embodiment of the present invention; Figure 30 This is a timing diagram showing the hold, programming, and emission phases during the operation of the fourth pixel circuit; Figure 31 The current flow in the fourth pixel circuit is shown during the programming phase; Figure 32 The current flow in the fourth pixel circuit is shown during the emission phase; Figure 33 A fifth pixel circuit including a multi-gate transistor is shown according to an embodiment of the present invention; Figure 34 A display device comprising multiple pixel circuits according to an embodiment of the present invention is shown; Figure 35 A sixth pixel circuit including a multi-gate transistor is shown according to an embodiment of the present invention; Figure 36This is a timing diagram showing the programming, holding, and emission phases during the operation of the sixth pixel circuit; Figure 37 The current flow in the sixth pixel circuit is shown during the programming phase; Figure 38 The charge stored in the corresponding capacitor in the sixth pixel circuit during the holding phase is shown; Figure 39 The current flow in the sixth pixel circuit during the emission phase is shown; Figure 40 A seventh pixel circuit including a multi-gate transistor is shown according to an embodiment of the present invention; Figure 41 This is a timing diagram showing the reset, programming, and emission phases during the operation of the seventh pixel circuit; Figure 42 The current flow in the seventh pixel circuit during the reset phase is shown; Figure 43 The current flow in the seventh pixel circuit during the first programming phase is shown. Figure 44 The diagram illustrates the current flow in the seventh pixel circuitry during the second programming phase and the charge stored in a capacitor connected to the source control gate; and Figure 45 The current flow in the seventh pixel circuit during the emission phase is shown. Detailed Implementation

[0032] In the following detailed description, only certain exemplary embodiments of the invention are illustrated and described by way of illustration only. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the scope of the invention. Therefore, the drawings and descriptions should be considered illustrative and non-limiting in nature. Throughout the specification, the same element symbols denote the same elements.

[0033] For convenience, in the following description, various device geometries according to embodiments of the invention are described with respect to the orientation shown in the accompanying drawings. When terms such as “above,” “over,” “lateral,” and “vertical” are used in the specification, these terms should not be construed as indicating that such embodiments are limited to the specific orientation shown in the accompanying drawings. It should be readily understood that the device described herein will be able to operate correctly regardless of the physical orientation of the device or the apparatus comprising it, and therefore the following description should be interpreted accordingly.

[0034] As mentioned above, existing pixel circuits typically have complex architectures at the expense of pixel size and the complexity of electronic driving schemes. To address this problem, embodiments of the present invention provide pixel circuits based on high-functionality and robust multi-gate transistors, which thus benefit from improvements in both operation and layout efficiency. A multi-mode transistor (MMT) is a type of multi-gate transistor that uses two gate electrodes to control the magnitude of the drain current independently of the on / off channel switching. The functionality and properties of this type of device are unique, and leveraging this unique device behavior requires custom circuitry that can utilize the separation of current generation and channel switching to create compact, high-functionality circuitry.

[0035] In the following description, various pixel circuits according to embodiments of the invention will be described in more detail. It should be understood that, in this context, the term "pixel circuit" refers to a circuit that controls the emission of each physical pixel in a display comprising an array of such pixels (e.g., red, green, or blue pixels in an RGB display). When considering an image formed by the display, the term "pixel" can also be used to describe the light components that form the image. In practice, each image pixel is formed by light emitted from multiple physical pixels in the display (e.g., a group of pixels comprising a red, a green, and a blue light-emitting component, each having an associated pixel circuit for controlling the emission of that component). Therefore, physical pixels (and pixel circuits) can sometimes be referred to as "subpixels."

[0036] Now for reference Figure 1 A multi-gate transistor including a current-controlled gate and a switching gate according to an embodiment of the present invention is shown. The multi-gate transistor 100 includes a source 101, a drain 102, a first gate 103, and a second gate 104. The source 101 and drain 102 are spaced apart from each other and separated by a semiconductor region 105. In other words, the source 101 and drain 102 are separated by the semiconductor region 105. The contact between the source 101 and the semiconductor 105 forms a potential barrier. For example, the potential barrier between the source 101 and the semiconductor 105 can be provided by selecting suitable materials for the source 101 and the semiconductor region 105, by doping the materials of the source 101 and / or the semiconductor region 105, or by forming a heterojunction contact between two or more semiconductor materials.

[0037] The source 101, drain 102, first gate 103, second gate 104, and semiconductor region 105 can each be formed from any suitable material or combination of materials. Examples of materials that can be used for the source 101, drain 102, first gate 103, and / or second gate 104 include, but are not limited to: metals; conductive or semiconductor metal oxides; conductive or semiconductor polymers; doped semiconductors; graphene; and two-dimensional (2D) materials. Examples of materials that can be used for the semiconductor region 105 include, but are not limited to: crystalline silicon, polycrystalline silicon, or amorphous silicon; crystalline films; semiconductor metal oxides; transition metal dichalcogenides; graphene; carbon nanotubes; semiconductor nanowires; organic semiconductors; and 2D semiconductors.

[0038] A first gate 103 is disposed above at least a portion of the source 101 and is separated from the source 101 by a semiconductor region 105 and an electrically insulating material 106 disposed above the semiconductor region 105. The electrically insulating material 106 may generally be referred to as an "insulating region" and may consist entirely of the same material or may consist of different insulating materials in different parts of the device. A region of semiconductor material 105 located on the source 101 (e.g., a source-gate overlap region) may be referred to as a "source region" of the semiconductor 105. When a potential difference greater than a certain threshold is applied to the first gate 103, an accumulation layer is formed in the source region at the interface between the semiconductor 105 and the insulator 106. Similarly, a second gate 104 is disposed above the gap 107 between the source 101 and the drain 102 and is separated from the source 101 and the drain 102 by the semiconductor region 105 and the electrically insulating material 106. Depending on the embodiment, the second gate 104 may or may not vertically overlap with the drain 102. When a potential difference greater than a certain threshold is applied to the second gate 104, an accumulation layer is formed at the interface between the semiconductor 105 and the insulator 106 in the gap 107 between the source 101 and the drain 102 (also called the "source-drain gap" 107).

[0039] In some embodiments, the multi-gate transistor 100 may include an interface layer between the source 101 and the semiconductor region 105 for controlling the properties of the potential barrier. For example, the interface layer may be formed by depositing a different material on the source 101 before depositing the semiconductor region 105, or by doping a surface region of the source 101. As a further example, in some embodiments, the interface layer may be formed by treating the source material before depositing the semiconductor region 105, for example by oxidizing the surface of the source 101 before depositing the semiconductor region 105, or by applying a suitable chemical treatment to modify the surface chemical properties of the source material.

[0040] In some embodiments, the source 101 may not directly overlap with the first gate 103. Instead, a region of the semiconductor 105 on one side of the source 101 may be doped to provide a region overlapping with the first gate 103. As a further alternative, in some embodiments, a different material, such as another metal, may be deposited on one side of the source metallization layer 101 along the direction of the drain 102, and the first gate 103 may be formed over or overlap with such other material region adjacent to the source 101.

[0041] In this embodiment, source 101 and drain 102 are arranged such that when a potential difference greater than a certain threshold is applied across source 101 and drain 102, a depletion layer is formed in semiconductor region 105 adjacent to source 101 across the entire cross-section of semiconductor layer 105 at the edge of source 101 closest to drain 102. In this embodiment, source 101 comprises a single continuous layer, but in other embodiments, source 101 may comprise multiple separate portions electrically connected in parallel to semiconductor region 105. In some embodiments, the depletion layer may not be formed across the entire cross-section of semiconductor layer 105, but device performance may be affected due to increased saturation voltage and reduced inherent gain.

[0042] The first gate 103 and the second gate 104 are configured together to form a continuous conductive layer at the interface between the semiconductor region 105 and the insulator 106. In this embodiment, the conductive layer is an accumulated layer, but in other embodiments, an inversion layer may be formed as the conductive layer. In this context, "continuous" means that the conductive layer extends from the drain 102 across the gap 107 between the source 101 and the drain 102 over at least a portion of the source 101. Thus, the conductive layer provides a path for current to flow between the source 101 and the drain 102 in the semiconductor region 105. In this way, when the correct voltage is applied to both the first gate 103 and the second gate 104, the multi-gate transistor 100 functions in a manner similar to a conventional source-gate transistor (SGT).

[0043] The operation of the multi-gate transistor 100 can be understood by referring to the Mode I and Mode II currents, such as... Figure 1 As shown in the image. Figure 1 The figure illustrates an example of a multi-gate transistor 100 according to an embodiment of the present invention operating in a mode similar to SGT. This operating mode of the multi-gate transistor 100 can be referred to as an "SGT-like" mode. In the SGT-like operating mode, two distinct current modes exist due to the source pinch-off effect. Mode I current I1 is determined by the electric field in the depletion region 105a at the tip of the source 101. This can be referred to as a high-field mode. The mode I current has a high temperature coefficient and a high electric field dependence.

[0044] The Mode II current I2 is injected along the remaining length of source 101 (i.e., away from the source-drain gap) and encounters resistance in the horizontal accumulation layer 105b as it travels along the length of source 101 through semiconductor 105. The Mode II current also encounters resistance vertically as it is injected from source contact 101 through semiconductor 105, and therefore, the Mode II current is essentially an ohmic current. Thus, the Mode II current is linearly proportional to the voltage applied to the first gate 103. The total current ID flowing into drain 102 is equal to the sum of the Mode I and Mode II currents, i.e., ID = (I1 + I2).

[0045] As described above, in this embodiment, when the correct voltage is applied to both the first gate 103 and the second gate 104, the multi-gate transistor 100 operates in a manner similar to a conventional SGT. However, unlike a conventional SGT, the multi-gate transistor 100 of this embodiment includes multiple gates 103, 104. The magnitudes of the Mode I and Mode II currents can be controlled by changing the voltage applied to the first gate 103. Figure 1 The diagram provides a first gate 103 and a second gate 104. The first gate 103 can be used to control charge injection from the source electrode 101, while the second gate 104 can be used to control the conductive channel between the source 101 and the drain 102 without affecting charge injection. Therefore, the first gate 103 is hereinafter referred to as the "current control gate", and the second gate 104 is hereinafter referred to as the "switching gate".

[0046] Furthermore, by appropriately designing the current control gate 103 to protect the source 101 from the electric field generated by the switching gate 104, the coupling between the switching gate 104 and the source 101 can be reduced. For example, in this embodiment, the current control gate 103 includes an extension 103a that hangs over the gap between the current control gate 103 and the switching gate 104. The extension 103a serves to protect the source 101 from the influence of the switching gate 104. Since the current control gate 103 is separated from the switching gate 104 by an insulator 106, different voltages can be applied to the current control gate 103 and the switching gate 104, and the current control gate 103 can electrically protect the source 101 from the potential difference applied to the switching gate 104. In this way, device operation can be improved because the voltage of the drain 102 and the voltage of the switching gate 104 will not affect the amount of injected current. When a voltage is applied to the switching gate 104, a current is allowed to flow within the semiconductor region 105 in the gap 107 between the source 101 and the drain 102. This can be viewed as switching the transistor from "off" to "on," hence the second gate 104 can be called the "switching gate." Simultaneously, the magnitude of the current flowing between the source 101 and the drain 102 is determined by the potential applied to the current control gate 103.

[0047] Because the current flowing between source 101 and drain 102 can scale linearly with the voltage of current-controlled gate 103, the multi-gate transistor 100 can be considered as a linear variable resistor or a linear voltage-controlled current source with an integrated switch in a single device. If switching gate 104 is "on," meaning the voltage applied to switching gate 104 is higher than a certain threshold and the voltage on current-controlled gate 103 is lower than the corresponding threshold of current-controlled gate 103, the device remains "off," and no current flows between source 101 and drain 102. Therefore, switching gate 104 controls the on / off behavior, and when transistor 100 is in the "on" state, current-controlled gate 103 acts as a current source to control the device.

[0048] Therefore, by providing separate current control gate 103 and switching gate 104, the on-state (on / off) of the device can be controlled in a part of the device, i.e., by changing the voltage applied to the switching gate 104, while the amplitude of the current through the multi-gate transistor 100 can be set in a separate part of the device, i.e., by changing the voltage applied to the current control gate 103.

[0049] exist Figure 1In the illustrated embodiment, the drain 102 is laterally spaced from the source 101, a semiconductor region 105 is disposed above the source 101 and drain 102, and a current control 103 and a switching gate 104 are disposed on the side of the semiconductor region 105 opposite to the source 101 and drain 102. However, in other embodiments, different device geometries are possible. For example, in some embodiments, the drain may be disposed above the source, and the control gate and the switching gate may be disposed on one side of the source and drain. Examples of cross-sections of multi-gate devices are not necessarily related to rectangular devices viewed from a top view, but may refer to rectangular devices, circular designs (e.g., Corbino), or cylindrical devices, where the illustrated cross-section is a slice rotated about a vertical edge to form a cylindrical structure.

[0050] In this embodiment, the current-controlled gate 103 and the switching gate 104 are disposed at the same height above the source 101 and the drain 102. To separate the two gates, the current-controlled gate 103 and the switching gate 104 are spaced apart from each other and separated by an electrical insulator 106. Furthermore, to achieve a continuous electric field across the source 101 and the source-drain gap 107, the current-controlled gate 103 includes a portion 103a extending above the gap separating the current-controlled gate 103 from the switching gate 104. In other embodiments, a similar extension may be formed by the switching gate 104 instead of the current-controlled gate 103. However, it may be advantageous to form the extension 103a as part of the current-controlled gate 103 rather than as part of the switching gate 104, because the extension 103a formed by the current-controlled gate 103 can help protect the source 101 from the switching gate 104, as described above.

[0051] like Figure 1 As shown, a portion of the current-controlled gate 103 or the switching gate 104 may extend to the same lateral positioning as the adjacent edge of the other of the current-controlled gate 103 and the switching gate 104, such that a continuous electric field can be maintained on the source 101 and the source-drain gap 107. In some embodiments, the extension 103a may overlap with the switching gate 104, meaning that a portion of the extension 103a is located directly above a portion of the switching gate 104. Furthermore, the extension 103a is vertically separated from the edge of the other of the current-controlled gate 103 and the switching gate 104 to ensure that the current-controlled gate 103 and the switching gate 104 are electrically isolated from each other within the device.

[0052] Therefore, the multi-gate transistor 100 is an example of a transistor type in which one gate (i.e., the current-control gate CG1) can be used to independently control the magnitude of the current supplied by the source region of the multi-gate transistor, depending on a first voltage applied to the current-control gate, which is disposed opposite to the source electrode of the multi-gate transistor, and where another gate (i.e., the switching gate CG2) can be used to block or allow current flow in the channel region of the multi-gate transistor, depending on a second voltage applied to the switching gate. Here, the term "independently control" is used to mean that a change in the voltage applied to one of the gates has little noticeable effect on the property controlled by the other gate. For example, the fact that the current-control gate CG1 "independently controls" the magnitude of the current can be understood to mean that the voltage applied to the switching gate CG2 has little effect on the magnitude of the current. In other words, the channel region (i.e., the portion of the semiconductor region affected by the voltage on the switching gate CG2) does not control the magnitude of the current in the multi-gate transistor, which is quite different from conventional transistors in which the gates in the channel region simultaneously control both current and switching.

[0053] In a multi-gate transistor—where a current-controlled gate CG1 can be used to independently control the amplitude of the current supplied by the source region of the multi-gate transistor depending on a first voltage applied to the current-controlled gate, the current-controlled gate being disposed opposite to the source electrode of the multi-gate transistor—the source electrode may include an energy barrier. The energy barrier can be configured to provide reduced transconductance compared to an ohmic or quasi-ohmic source. In such an embodiment, the energy barrier can control the amplitude of the current over a wider range of current-controlled gate voltages (e.g., to achieve improved linearity of drain current for grayscale in pixel-based displays, to achieve superlinear dependence of drain current, and to achieve low leakage), and is inherently controlled by the current-controlled gate depending on the first voltage applied to the current-controlled gate.

[0054] In some embodiments of the invention, when certain high-mobility semiconductors are used in a multi-gate MMT, a field plate structure may be included on the source (and optionally also on the drain) to provide shielding against a lateral drain electric field that may affect the height of the energy barrier at the source edge and cause an undesirable increase in drain current. In some cases, the field plate may be implemented as a separate electrode rather than a metal extension. It will be understood that, in addition to Figure 1 In addition to those shown, adding supplementary or auxiliary electrodes that promote or improve device performance in this way does not depart from the scope of the invention.

[0055] In embodiments of the invention, a multi-gate transistor can be used in the pixel circuit to control the current flow through a light-emitting element connected to the source or drain of the multi-gate transistor, such that in use, the current flowing through the light-emitting element is controlled by the current-controlled gate of the multi-gate transistor and is either blocked or allowed to flow through the light-emitting element under the control of the switching gate of the multi-gate transistor. Such a pixel circuit may also include a driving circuit configured to independently control the first voltage and the second voltage to independently control the amplitude of the current and the duration of current flow through the light-emitting element. Examples of such a pixel circuit are described in more detail below.

[0056] Figure 2 A first pixel circuit including a multi-gate transistor according to an embodiment of the present invention is shown. The first pixel circuit includes a first transistor M1, which is a multi-gate transistor including a separate current-control gate and a switching gate for controlling the amplitude of the current flowing between the source and drain independently of turning the current on / off. In this embodiment, the first transistor M1 has a... Figure 1 The transistor 100 shown has a similar structure and includes a source, a drain spaced apart from the source, a semiconductor region disposed between the source and drain, an insulating region disposed above the semiconductor region, a current-control gate CG1 in the source region, and a switching gate CG2 in the channel (source-drain gap) region. The current-control gate CG1 can be used to control the amplitude of the current flowing through the semiconductor region between the source and drain depending on a first voltage applied to the current-control gate, and is separated from the source by the semiconductor region and the insulating region. The switching gate CG2 can be used to allow current to flow through the semiconductor region between the source and drain depending on a second voltage applied to the switching gate; in other words, it switches the transistor M1 between an on state and an off state.

[0057] The first pixel circuit further includes: a light-emitting element (e.g., a light-emitting diode (LED) or an organic light-emitting diode (OLED)) connected to the source or drain of a first transistor such that, in use, the current flowing through the light-emitting element is controlled by the first transistor; and a driving circuit configured to independently control the first voltage and the second voltage in order to independently control the amplitude of the current and the duration of the current flowing through the light-emitting element.

[0058] In this embodiment, the driving circuit of the first pixel circuit includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected to the current control gate CG1, such that in use, the voltage on the first capacitor C1 can be applied to the current control gate CG1 as a first voltage. The second capacitor C2 is connected to the switching gate CG2, such that in use, the voltage on the second capacitor C2 can be applied to the switching gate CG2 as a second voltage. By providing separate capacitors C1 and C2 for each of the current control gate CG1 and the switching gate CG2, the driving circuit can independently control the voltage applied to the respective gates CG1 and CG2 during the emission phase by charging each capacitor C1 and C2 to an appropriate level before the start of the emission phase.

[0059] Continue to refer to Figure 2 In this embodiment, the driving circuit of the first pixel circuit further includes a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. As will become apparent from the following description, in some embodiments of the pixel circuit including multi-gate transistors, depending on whether the functionality associated with each such transistor is required in any given implementation, some or all of the second transistors M2 to the seventh transistor M7 may be omitted from the driving circuit.

[0060] The second transistor M2 is connected between the second capacitor C2 and the first reference voltage node. In other words, the second transistor M2 is configured to block or allow current flow between the second capacitor C2 and the first reference voltage node, depending on whether the second transistor M2 is in an on or off state. Here, the term "on state" refers to a state in which the transistor can conduct and generate current between its source and drain, while "off state" refers to a state in which essentially no current can flow between the source and drain. The transistor can be switched between its on and off states by applying an appropriate voltage to its gate electrode. Those skilled in the art will be familiar with the operating principles of conventional transistors (e.g., thin-film transistors TFTs), and a detailed description will not be provided here. During the operation of the first pixel circuit, the second transistor M2 can therefore be switched to the on state to reset the voltage on the second capacitor C2 to the voltage (VREF) at the first reference voltage node. The second transistor M2 is further connected to the switching gate CG2 of M1. In some embodiments, the second transistor M2 may be connected to the current control gate CG1 instead of the switching gate CG2.

[0061] The third transistor M3 is connected between the current-controlled gate CG1 and the switching gate CG2. In other words, the third transistor M3 is configured to block or allow current flow between the electrical nodes represented by the current-controlled gate CG1 and the switching gate CG2, depending on whether the third transistor M3 is in the on or off state. During the operation of the first pixel circuit, the third transistor M3 can therefore be switched on to allow the voltages at the current-controlled gate CG1 and the switching gate CG2 to be equal. The third transistor M3 can be further connected in series with the second transistor M2 such that when both the second transistor M2 and the third transistor M3 are in the on state, a reference voltage VREF is applied to both the first capacitor C1 and the second capacitor C2, assuming that the first capacitor C1 and the second capacitor C2 are connected to the current-controlled gate CG1 and the switching gate CG2, respectively.

[0062] The fourth transistor M4 is connected in series with the third transistor M3, and further connected between the data signal input DATA and the second capacitor C2. In this way, when the fourth transistor M4 is on, current can flow between the second capacitor C2 and the data signal input. Additionally, since the fourth transistor M4 is connected in series with the third transistor M3, current can flow between the first capacitor C1 and the data signal input when both the third transistor M3 and the fourth transistor M4 are on. It should be understood that in the context of this disclosure, the term "connected" does not necessarily mean "directly connected," and allows for the possibility that other components can be connected between the two components / nodes in question. For example, regarding the discussion of M4 above, it should be understood that in the first pixel circuit, the fourth transistor M4 is connected to the data signal input DATA via the first transistor M1 and the fifth transistor M5; therefore, both the first and fifth transistors must also be switched on to connect M4 to the data signal input DATA. Figure 2 As shown in the diagram, the fourth transistor M4 is thus configured to connect the second capacitor C2 to the data signal input DATA when the fourth transistor M4 is switched on by the signal SEL 1. However, in other embodiments, the fourth transistor M4 may be directly connected to the data signal input so that the DATA signal is applied directly to the first capacitor C1 and the second capacitor C2.

[0063] In this embodiment, the source of the first transistor M1 is connected to the data signal input DATA via the source and drain of the first transistor M1, so that during use, when both the third transistor M3 and the fourth transistor M4 are in the ON state, the first capacitor C1 and the second capacitor C2 can discharge to a value equal to V. DATA + V th The voltage, where V DATAIt is the voltage at the data signal input, and V th This is the threshold voltage of the first transistor M1 with respect to CG1. This is achieved through a diode connection from the first transistor M1 to the fourth transistor M4. The contact control (source energy barrier control) property of the first transistor M1 ensures that it is always in saturation when its drain-to-source voltage is equal to or higher than its gate-to-source voltage CG1. This voltage programming method compensates for the inter-device variability of the threshold voltage.

[0064] In this embodiment, the driving circuit further includes a fifth transistor M5 and a sixth transistor M6 to allow the source of the first transistor M1 to be interchangeably connected to the ground plane GND or the data signal input DATA. The fifth transistor M5 is connected between the source of the first transistor M1 and the data signal input DATA. The sixth transistor M6 is connected between the source of the first transistor M1 and the ground plane GND. In use, the sixth transistor M6 can be switched to an ON state to allow current to flow through the first transistor M1 and the light-emitting component D1, and can be switched to an OFF state to isolate the source of the first transistor M1 from the ground plane GND (e.g., when the fifth transistor M5 is ON to connect the source of the first transistor M1 to the data signal input DATA).

[0065] In some implementation schemes, such as in Figure 2 As in the first pixel circuit, the respective gates of the fourth transistor M4 and the fifth transistor M5 can be connected to the first control input to receive the first control signal SEL1. In this way, the fourth transistor M4 and the fifth transistor M5 can be simultaneously turned on or off using a single control signal SEL1, thereby simplifying the control of the drive circuit.

[0066] In other embodiments, the fifth transistor M5 and the sixth transistor M6 can be omitted, such that the source of the first transistor M1 is permanently connected to the data signal input DATA. For example, in such an embodiment, when the data signal DATA is used to program pixels on other rows of the display, the supply voltage ELVDD can be temporarily reduced below the threshold voltage of the light-emitting element D1 to prevent the light-emitting element D1 from emitting while other pixels are being programmed.

[0067] In this embodiment, the driving circuit further includes a seventh transistor M7, which is connected in series between the first transistor M1 and the light-emitting element D1. In use, the seventh transistor M7 can be switched on to allow current to flow through the first transistor M1 and the light-emitting element D1. In some embodiments, the respective gates of the sixth transistor M6 and the seventh transistor M7 can be connected to a transmit control input to receive a transmit control signal EM. In this way, the sixth transistor M6 and the seventh transistor M7 can be simultaneously turned on or off using a single transmit control signal EM, thereby simplifying the control of the driving circuit.

[0068] Figure 3 This is a flowchart illustrating a method for controlling a pixel circuit including a multi-gate transistor according to an embodiment of the present invention. This method can be used to control... Figure 2 The first pixel circuit shown, or a similar method, can be used to control other types of pixel circuits, as disclosed herein.

[0069] The method begins by executing the reset phase in step S301. During the reset phase, the first capacitor C1 is set to a first voltage level, and the second capacitor C2 is set to a second voltage level. Figure 2 In the pixel circuit, the first voltage level and the second voltage level are the same; in other words, the first capacitor C1 and the second capacitor C2 are charged to the same voltage (VREF) during the reset phase. However, in other embodiments, the first capacitor C1 and the second capacitor C2 may be charged to different corresponding voltages during the reset phase.

[0070] Next, the method proceeds to the programming stage in step S302. During the programming stage, the corresponding charge levels of the first capacitor C1 and the second capacitor C2 are set to the desired levels; in other words, the voltage levels applied to the current control gate CG1 and the switching gate CG2 respectively during the emit phase.

[0071] In this embodiment, the method then proceeds to a holding phase S303, where the charge levels on the first capacitor C1 and the second capacitor C2 are maintained while other pixels in the display (e.g., pixels in other rows of the display) are programmed. The timing of the holding phase S303 relative to the programming phase S302 can vary depending on the positioning of the current pixel row in the pixel array. For example, for a pixel array including… n The first row (row 1) of the array can be directly processed from the reset stage S301 to the programming stage S302, followed by processing rows 2 through 303. n When programming, proceed to the holding phase S303. On the other hand, for the first... nThe line maintenance phase S303 occurs before the programming phase S302 because for all other lines (1 to...) n -1) When programming, always keep the first n Rows. For the middle rows (rows 2 to 1), ... n -1) There will be two holding phases, one before the programming phase for that row and one after the programming phase for that row, where the relative duration of the two holding phases varies from one another depending on the positioning of each row in the pixel array. Generally, one or more holding phases are applied to any given pixel row such that the pixels in that row are held (i.e., the charge is maintained on the first capacitor C1 and the second capacitor C2) while the pixels in other rows are being programmed.

[0072] Then, in this embodiment, once the other pixels have been programmed, the method proceeds to the emission phase in step S304. In this way, all pixels in the display emit light simultaneously during the emission phase S304. Alternatively, in other embodiments, each pixel row may enter the emission phase S304 immediately after that row has been programmed, without waiting for the other rows on the display to be programmed. During the emission phase, the driving circuitry applies a first voltage and a second voltage stored in the first capacitor C1 and the second capacitor C2 to the current control gate CG1 and the switching gate CG2, respectively, to independently control the amplitude of the current and the duration of current flow through the light-emitting element D1.

[0073] Now refer to Figures 4 to 9 Describe the operation of the pixel circuit during each of the reset, programming, hold, and emit phases. Figure 4 This is a timing diagram illustrating the reset, programming, holding, and emission phases during the operation of the first pixel circuit. Specifically, Figure 4 The relative states (e.g., low or high, or specified analog voltage levels) of the various control signals (i.e., DATA, RESET, SEL1, SEL2, EM, and RAMP) used in the operation of the first pixel circuit are shown.

[0074] Figure 5The current flow in the first pixel circuit during the reset phase S301 is illustrated. During the reset phase S301, the potential on the gates of the first transistor M1 (specifically, the current control gate CG1 and the switching gate CG2) is raised to a level higher than the maximum level of the first or second voltage that may be applied to the current control gate CG1 and the switching gate CG2 respectively during the emission phase S304. This is achieved by setting the control signals reset and SEL2 to a high logic state and holding the ramp signal to ground potential (GND). This has the following effect: nodes CG1 and CG2 are connected by closing the third transistor M3 (e.g., making the third transistor M3 on and conducting), and simultaneously capacitors C1 and C2 are connected to potential VREF via the second transistor M2, which is now also closed (e.g., making the second transistor M2 on and conducting). M1, M2, C1, and C2 can be set such that the potentials at nodes CG1 and CG2 can reach a value quite close to the reference VREF within a short time period (typically about 1 or a few microseconds (μs)). During the reset phase S301, the current control gate CG1 and the switching gate CG2 do not need to reach the same potential or a specific potential value, as long as they are appropriately high. During this phase, signals EM and SEL1 remain low, causing transistors M4, M5, M6, and M7 to be turned off, and the pixel becomes completely dark because no current flows through the light-emitting component D1.

[0075] Figure 6 The diagram illustrates the current flow in the first pixel circuit during the first stage of programming phase S302. In the first stage of programming phase S302 (which may be referred to as the Pulse Amplitude Modulation (PAM) programming stage), the desired amplitude of the current that will flow through the light-emitting component D1 during the emission phase S304 is set. This current will be controlled by the potential on the current-controlled gate CG1 of the first transistor M1. The emission control signal EM remains low, causing the sixth transistor M6 and the seventh transistor M7 to be off, thus preventing any current from flowing through the light-emitting component D1 or from the source node to ground (GND). The ramp voltage is maintained at zero volts (off state), and the reset signal is driven low to turn off the second transistor M2 and disconnect VREF from the rest of the pixel circuit. The voltage on the data line stabilizes at a desired level VDATA1, which is related to the voltage required at the current-controlled gate CG1 for which the correct / desired current will flow through the light-emitting component D1 during the emission phase S304. Signal SEL1 is driven high to turn on the fourth transistor M4 and the fifth transistor M5.

[0076] Since the current-controlled gate CG1 and the switching gate CG2 are connected together via a third transistor M3 that remains closed, the predetermined voltage is significantly higher than VDATA1. The first capacitor C1 and the second capacitor C2 will discharge over a period of approximately 1 or a few μs until the potential at the current-controlled gate CG1 and the switching gate CG2 reaches VDATA1. DATA1 + V th1 The value of V th1 This is the threshold voltage of the first transistor M1 with respect to its current-controlled gate CG1 region. This is achieved through a diode connection from the first transistor M1 to the fourth transistor M4, and this is possible because the contact control properties of the first transistor M1 ensure that it is always saturated when its drain-to-source voltage is equal to or higher than its CG1 gate-to-source voltage. This voltage programming method compensates for the inter-device variability of the threshold voltage.

[0077] However, in other embodiments, the data signal DATA may not be applied through the first transistor M1. For example, in some embodiments, the data signal input may be connected to the first capacitor C1, the second capacitor C2, the current control gate CG1, or the switching gate CG2, such that current can flow from the data signal input to the first capacitor C1 and the second capacitor C2 without passing through the first transistor M1.

[0078] Figure 7 The diagram illustrates the current flow in the first pixel circuit during the second stage of the programming phase (which may be referred to as the pulse width modulation (PWM) programming stage). During the PWM programming stage, the signal timing remains unchanged except for SEL2, which is driven low, thus switching the third transistor M3 to the off state and disconnecting the previously short-circuited current control gate CG1 and switching gate CG2. The current control gate CG1 is now disconnected from the rest of the pixel circuit, and its potential relative to ground is maintained by the charge stored in the first capacitor C1, which, in a typical implementation, can be approximately a few tenths of a picofarad (pF). The voltage on the data line is now reduced to the value VDATA2.

[0079] This method utilizes the fact that the first transistor M1 can operate with a constant drain current when its switching gate CG2 voltage is lower than its current control gate CG1 voltage, because switching gate CG2 does not significantly affect the magnitude of the drain current within a given voltage range. At the start of this phase, the voltage at switching gate CG2 is V. DATA1 + V th1 The second capacitor C2 (again, typically set to a few tenths of a pF) discharges through the fourth transistor M4, the first transistor M1, and the fifth transistor M5 until the potential at the switching gate CG2 reaches V. DATA2 + Vth2 (where V) th2 (This refers to the threshold voltage of the channel region controlled by the switching gate CG2), which again occurs in a typical time interval of about 1 or a few μs, and again compensates for the threshold displacement variation between the first transistors M1 in neighboring pixels.

[0080] Figure 8 The first pixel circuitry during the hold phase S303 is shown, wherein the fourth transistor M4 and the fifth transistor M5 are turned off by driving the signal SEL1 low. The corresponding voltages are stored on the current-control gate CG1 and the switching gate CG2 by the first capacitor C1 and the second capacitor C2. The hold phase continues as all pixels are programmed sequentially, as described above. In some embodiments, the display can be configured such that all pixels can be programmed simultaneously, for example by providing a dedicated data signal input for each pixel; in this case, the hold phase can be completely omitted.

[0081] Figure 9 The current flow in the first pixel circuit during the emission phase S304 is illustrated, where the sixth transistor M6 and the seventh transistor M7 are turned on by driving the signal EM high. This drives the SOURCE node of the first transistor M1 close to GND and toward the DRAIN node driven by the supply voltage ELVDD, thereby turning on the first transistor M1. A current flow having an amplitude controlled by the potential at the current-controlled gate CG1 passes through the light-emitting component D1, the sixth transistor M6 and the seventh transistor M7, and the first transistor M1, and the light-emitting component D1 emits light with a brightness proportional to the drain current of the first transistor M1 set by the potential on the current-controlled gate CG1.

[0082] The emission phase S304 can be relatively long compared to the duration of other phases. For example, depending on the implementation, the emission phase S304 can range from a few milliseconds to a few seconds. During this time, the voltage on node RAMP decreases linearly to a negative value, which reduces the potential at the switching gate CG2 through capacitive coupling via the second capacitor C2. When the voltage at the switching gate CG2 reaches a sufficiently low value, the first transistor M1 turns off, thereby cutting off the current through the light-emitting element D1 and stopping light emission. The interval during which the light-emitting element D1 is allowed to emit is determined by the value of the potential programmed on the switching gate CG2 during the PWM programming phase. The turn-off currents of transistors M2, M3, M4, and M5, as well as parasitic couplings between nodes CG1, CG2, DRAIN, and SOURCE, can cause deviations from ideal behavior. Therefore, the relative sizes of the capacitors and transistors can be determined based on their electrical characteristics and the desired frame time.

[0083] Now refer to Figures 10 to 17Briefly describe the computer simulation results of the behavior of the first pixel circuit during the aforementioned stages. Figures 10 to 13 The electrical characteristics of the transistors used in the simulation are given in the figure, and the main parameters of the simulation are given in Table 1.

[0084]

[0085] Table 1

[0086] Assuming that the control transistors M2 to M7 (i.e., the second to seventh transistors) have the transmission characteristics of a conventional TFT, such as... Figure 10 The scale is shown in both linear and semi-logarithmic formats. Figure 10 The output characteristics shown exhibit poor saturation behavior, but the high current makes these devices particularly suitable for rapid switching. It should be understood that components in a circuit (e.g., transistors) do not necessarily behave precisely as described above. Figure 10 As shown, and even if some or all of the transistors in the transistor behave differently... Figure 10 The behavior shown in the curves is different, but the pixel circuit can still operate correctly.

[0087] Figure 11 The transfer characteristics of the current-controlled gate CG1 are shown on both semi-logarithmic and linear scales. Figure 12 The transfer characteristics of the switching gate CG2 are shown on both semi-logarithmic and linear scales, and... Figure 13 The output characteristics of the multi-gate transistor in the first pixel circuit are shown. Since switching gate CG2 does not modulate the drain current, the characteristics tend to be flat. This means that higher CG2 voltages do not affect the drain current and are utilized in the circuit. The output characteristics show low voltage saturation with a flat curve, which is desirable in analog circuit design.

[0088] Figure 14 The node voltages in the first pixel circuit during the reset and programming phases are shown. Figure 15 The node voltage and drain current during the operation of the first pixel circuit are shown. Figure 16 The node voltages and drain currents, as a result of the circuit's PAM capability, are shown, and Figure 17 The node voltages and drain currents are shown as a result of the circuit's PWM capability. From Figure 16 It can be seen that different CG1 voltages increase the current and thus increase the amplitude of PAM, while from Figure 17 It can be seen that different CG2 voltages result in changes in the pulse width used for PWM.

[0089] Now refer to Figures 18 to 27 A second pixel circuit according to an embodiment of the present invention is described. For example... Figure 18As shown, the second pixel circuit includes a first transistor M1, which is related to... Figure 1 The multi-gate transistor shown is similar to the multi-gate transistor in the diagram. (And...) Figure 2 Similar to the first pixel circuit, the second pixel circuit includes second transistors M2, M3, and M4 connected in a similar manner to the second transistors M2, M3, and M4 of the first pixel circuit, and includes first capacitor C1, second capacitor C2, and light-emitting element D1, similar to the first capacitor and second capacitor of the first pixel circuit. For the sake of brevity, a detailed description of such features common to both the first and second pixel circuits (and therefore already described above) will not be repeated here.

[0090] In this embodiment, the driving circuit of the second pixel circuit includes an eighth transistor M8 connected between the first capacitor C1 and the second reference voltage node. During operation of the second pixel circuit, the eighth transistor M8 can be switched on to charge the first capacitor C1 to the voltage (REF) at the second reference voltage node. In some embodiments, such as Figure 18 As shown, the respective gates of the second transistor M2 and the eighth transistor M8 can be connected to a second control input to receive a second control signal (SEL n-1), where the second control input is the selection signal for the previous row. Similarly, the respective gates of the third transistor M3 and the fourth transistor M4 can be connected to a third control input to receive a third control signal (SEL n). In this way, the second transistor M2 and the eighth transistor M8, as well as the third transistor M3 and the fourth transistor M4, can be simultaneously turned on or off using a single respective control signal SEL n-1 or SEL n, thereby simplifying the control of the drive circuit. For example, row n of such an array of pixels in a display can be programmed via the signal SEL n and the selection signal SEL n-1 for the previous row. Column m of the pixel array can be programmed via the data m (DATA m) signal.

[0091] Now refer to Figures 19 to 22 Describe the operation of the pixel circuit during each of the reset phase S301, programming phase S302, holding phase S303, and emission phase S304. Figure 19 This is a timing diagram illustrating the reset, programming, holding, and emission phases during the operation of the second pixel circuit. Specifically, Figure 19The relative states (e.g., low or high, or analog voltage levels) of various control signals (i.e., DATA m, SEL n-1, and SEL n) used in the operation of the first pixel circuit are shown. The reset and programming phases are repeated until all rows have been programmed, after which the transmission phase proceeds, where programmed pixels across all rows simultaneously emit light. Alternatively, as described above, in some embodiments, a transmission signal EM can be appropriately generated for each row. n This allows the emit phase to begin for a given row once the reset and programming have been completed (i.e., instead of entering the hold phase for that row while programming other rows).

[0092] Figure 20 The current flow in the second pixel circuit during reset phase S301 is illustrated. The eighth transistor M8 performs a function similar to the second transistor M2 and the third transistor M3 in the first pixel circuit by connecting the first capacitor C1 to the second reference node (REF) during the reset phase. The reset phase in the second pixel circuit differs from that in the first pixel circuit in that the second capacitor C2 discharges to ground (GND) via the second transistor M2, whereas in the first pixel circuit, the second capacitor C2 charges to the same high voltage VREF as the first capacitor C1 during reset phase S301.

[0093] More specifically, in the reset phase S301, two elements are implemented to achieve circuit functionality in the second pixel circuit. First, light emission is suppressed by grounding the input of the switching gate CG2 of the first transistor M1, thus blocking current from flowing through the light-emitting component D1. This is achieved by turning on the second transistor M2 and thus draining the charge stored in the second capacitor C2 to ground GND. In some embodiments, the voltage at the first reference node can be a voltage other than ground, such as a relatively low reference voltage.

[0094] Secondly, and simultaneously, the first capacitor C1 is charged to a relatively high potential by connecting the current-controlled gate CG1 terminal of the first transistor M1 to a common constant reference potential REF via the eighth transistor M8, which is closed by the same control signal as the second transistor M2. This control signal, representing selection n-1 (SEL n-1), is the same signal that performs the function of selection n (SEL n) in the previous row of pixels. For this reason, the duration for which signals selection n-1 and selection n are asserted can be the same in practice, and this duration should be approximately a few microseconds in a typical display in order to allow programming of all rows on the display within a reasonable time. The third transistor M3 and the fourth transistor M4 remain off during this stage, gated by the signal SEL, which remains low. The magnitude of the final voltage stored on the first capacitor C1 at the end of the reset stage S301 can be set to a level significantly higher than the final value required at that node at the end of the programming stage S302. As will become clear from the following explanation, the charge stored on the first capacitor C1 during the reset phase should be sufficient so that when the first capacitor C1 subsequently shares charge with the second capacitor C2 during the PAM programming phase, their combined charge is still higher than the charge that the common node CG1 / CG2 (via the third transistor M3) will require at the end of the PAM programming phase. In other words, at the end of the PAM programming phase, the two capacitors together should have more charge than required, such that this excess can be discharged via the data signal input DATA, thereby simultaneously programming the capacitors to have the correct charge while also compensating for the threshold voltage of the first transistor M1.

[0095] Figure 21 The current flow in the second pixel circuit during programming phase S302 is illustrated. Unlike the programming phase in the first pixel circuit (which includes two distinct stages (PAM and PWM programming stages)), in this embodiment, the programming phase of the second pixel circuit comprises a single stage. During the programming phase in the second pixel circuit, the third transistor (M3) and the fourth transistor (M4) are switched on to connect both the first capacitor C1 and the second capacitor C2 to the data signal input DATA m, so that the corresponding charge levels of the first capacitor C1 and the second capacitor C2 are set depending on the voltage at the data signal input.

[0096] More specifically, in the programming stage S302 of the second pixel circuit, the desired amplitude of the current that will flow through the light-emitting component D1 during the emission stage S304 is set. This current will be controlled by the potential on the current-controlled gate CG1 of the first transistor M1. In some embodiments, if a low current level is desired, the current may be controlled by the potential on the switching gate CG2. During this stage, signal SELn is active and SELn-1 is inactive, therefore the third transistor M3 and the fourth transistor M4 are closed, and the second transistor M2 and the eighth transistor M8 are off (e.g., in an off state and not conducting). Therefore, the following simultaneous effect occurs.

[0097] First, the first capacitor C1 and the second capacitor C2 each now have a terminal connected to ground and another terminal connected together via the third transistor M3. At the start of this stage, the first capacitor C1 has a relatively large charge, while the second capacitor C2 has been completely discharged to ground. When the third transistor M3 begins to conduct, the two capacitors C1 and C2 share the charge, with the goal of establishing a common potential on the first capacitor C1 and the second capacitor C2. This potential should be higher than the final potential required at the current-controlled gate CG1 at the end of the programming stage S302. This can be achieved, for example, through a combination of the magnitude of the REF voltage, the timing of the reset stage S301 and the programming stage S302, and the relative sizes of the first capacitor C1 and the second capacitor C2.

[0098] Secondly, when capacitor C2 begins to charge, the first transistor M1 closes and begins to conduct. Since the fourth transistor M4 also conducts, node DRAIN, the current-controlled gate CG1, and the switching gate CG2 are now effectively short-circuited. This arrangement also means that the first transistor M1 is connected in a diode configuration, where both its gates CG1 and CG2 are shorted to the drain. The charge flow shared between the first capacitor C1 and the second capacitor C2 reaches DATA m through the fourth transistor M4 and the first transistor M1, until the potential at the current-controlled gate CG1 and the switching gate CG2 equals the voltage of DATA m plus the threshold voltage of the first transistor M1 (in principle, with respect to the current-controlled gate CG1).

[0099] Therefore, in connecting the data signal DATA m to the first capacitor C1 and the second capacitor C2 via the first transistor M1 (and via the third transistor M3 and the fourth transistor M4), the programming stage S302 in the second pixel circuit follows a similar approach to the programming stage of the first pixel circuit. This voltage programming method compensates for the inter-device variability of the threshold voltage. However, as described above with reference to the first pixel circuit, in other embodiments based on the second pixel circuit, the data signal DATA m may not be applied via the first transistor M1.

[0100] During the programming phase S302 of the second pixel circuit, there is no emission from the light-emitting component D1 because it is reverse-biased by a voltage at node DRAIN that is relatively large compared to the supply voltage VDD. For this reason, the first transistor M1 should have a relatively high threshold voltage compared to the light-emitting component D1 to allow node DRAIN to maintain a relatively high voltage during programming even when the value of the DATA m input is low.

[0101] When signal SEL n is applied, the first capacitor C1 and the second capacitor C2 share charge, and the resulting potential is higher than the maximum required voltage on the current control gate CG1 during the emission phase S304. Simultaneously, the first transistor M1 is turned on and biased in a diode configuration. The light-emitting component D1 is not turned on because it is reverse-biased by the potential at DRAIN. The first capacitor C1 and the second capacitor C2 discharge through the third transistor M3 and the fourth transistor M4, as well as the first transistor M1, and conduction stops when the current control gate CG1 and the switching gate CG2 are equal to DATA m plus the threshold voltage of the first transistor M1 (with respect to the current control gate CG1).

[0102] Once both signals SEL n and SEL n-1 have been decremented, the current row n of the pixel will enter the emission stage S304 after the programming stage S302 in the second pixel circuit. However, there may still be other rows to be programmed. In this case, if the data signal DATA m is common (i.e., shared among pixels), the data presented to the common DATA m signal may cause unnecessary emission from the programmed rows for a short duration equivalent to the programming time. Even if these are imperceptible to the human eye, they can cause image degradation due to deviations from the desired local image brightness. In some implementations, this problem can be mitigated by... Figure 19 The solution is to reduce the supply voltage VDD below the threshold voltage of the light-emitting component D1 during the duration of the sequence "All rows programmed". From the perspective of a given pixel, the time period during which the supply voltage VDD is reduced below the threshold voltage of the light-emitting component D1 can be regarded as equivalent to the holding phase S303 of the first pixel circuit.

[0103] Figure 22The current flow in the second pixel circuit during the emission phase S304 is shown, where all transistors except the first transistor M1 are off. The DATA m signal is driven to a specific low potential, and emission occurs because the supply voltage VDD is set to forward bias the light-emitting component D1 and saturate the first transistor M1. This phase lasts for the duration of the frame time. Compared to the first pixel circuit, the second pixel circuit does not include the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7, and therefore, the component count (and thus, physical size) of the second pixel circuit is reduced compared to the first pixel circuit.

[0104] The relatively small size of the first capacitor C1 and the second capacitor C2 implies that the parasitic capacitances of the first transistors M1 through M4 and the eighth transistor M8 play a role in charge sharing, especially when switching the various switches (transistors) in the second pixel circuit on and off. In some implementations, the data signal DATAm can be preprocessed to compensate for any kickback effect on the potential at the set current control gate CG1. In some cases, if transistor M1 operates in source control mode instead of channel control mode (such as under high drain current), the precise potential at the switching gate CG2 may not be particularly important.

[0105] The second pixel circuit can be tuned to achieve low linear sensitivity of the drain current to the current-controlled gate CG1 potential. This means that small changes at the transistor input due to the discharge of the first capacitor C1 will only produce small and potentially imperceptible final changes in the brightness of the emitted light. Conversely, the first transistor M1 can be designed with superlinear / exponential dependence of the drain current, in which case a much higher dynamic range can be achieved relying solely on current-controlled gate CG1 / source control, making precise programming of the switching gate CG2 voltage far less demanding. This, in turn, allows for a reduction in the layout area allocated to the second capacitor C2.

[0106] In some implementations, the first transistor M1 can be configured such that the current-controlled gate CG1 has an exponential transfer characteristic, meaning that the threshold voltage of the multimode transistor can be kept close to zero. Therefore, the value presented on the DATA m bus can be considerably higher than VDD minus the threshold voltage of the light-emitting element D1, which significantly reduces the problems described regarding the hold phase S303, since all presented data will be significantly higher than the potential assigned to the DATA m line during the emit phase S304.

[0107] The threshold values ​​of the light-emitting element D1 and the multimode transistor M1, as well as the supply voltage VDD, can be configured such that during the programming phase S302, when the light-emitting element D1 is reverse-biased, its photocurrent does not significantly affect operation. However, in principle, this may not be a problem in practice, since the photocurrent will discharge to VDD and DATA m.

[0108] As an alternative to configuring the first transistor M1 with a high threshold voltage, the potential on the ground wire GND can be... Figure 19 During the entire duration of the “all rows are programmed” phase, the potential rises to a value corresponding to the threshold of the light-emitting component D1, and then returns to zero potential during the common emission phase S304.

[0109] Figures 23 to 25 The electrical characteristics of the transistors used in the simulation are given in Section 1, and the main simulation parameters are listed in Table 2. Similar to the simulation for the first pixel circuit, in this simulation of the second pixel circuit, the electrical characteristics of the control transistors M2-M4 and M8 are based on, as shown in Table 2. Figure 10 The electrical characteristics of a conventional TFT are shown.

[0110]

[0111] Table 2

[0112] Figure 23 The transfer characteristics for the current-controlled gate CG1 are shown on a linear scale (left panel), and the transfer characteristics for the switched gate are shown on a logarithmic scale (right panel), demonstrating that above a certain bias, the switched gate CG2 does not affect the drain current. The transfer characteristics for the switched gate CG2 show that this gate does not modulate the current, and therefore the characteristics tend to flatten. Here, the first transistor M1 utilizes interface charge to ensure a specific threshold voltage for circuit operation.

[0113] Figure 24 The output characteristics of the multi-gate transistor in the second pixel circuit are shown on a linear scale (left) and a logarithmic scale (right). The output characteristics (left: linear scale, right: logarithmic scale) show a low voltage saturation (below 1 V) curve that is primarily flat, which is desirable in analog circuit design. Here, the first transistor M1 changes its threshold voltage relative to the current-controlled gate CG1, making it suitable for low CG1-source voltage V. CG1S Keep it in the off state. Here, ~100 nanoamps (nA) is shown as the typical drain current corresponding to near-maximum brightness of the light-emitting element D1. The output characteristics remain flat over a few volts, which is sufficient for all operating conditions (e.g., 1.5 V to 2.5 V, taking into account the temperature and aging effects of the light-emitting element D1).

[0114] Figure 25 The diagram shows the results for various interface charge values ​​Q. i The switching gate transfer characteristics of the first transistor M1 in the second pixel circuit. In V CG1S With moderate and extremely low values, the device operating state can be changed by shifting the threshold voltage in the current-controlled gate CG1 region. Here, changing the interface charge value is shown merely as an example of a mechanism that can achieve the desired functionality. In other embodiments, other methods can be used to change the threshold voltage of the first transistor M1 relative to the light-emitting element D1 as needed to achieve proper operation of the pixel circuitry.

[0115] Figure 26 The diagram shows the node voltages in the second pixel circuit for two values ​​of the data signal during the reset, programming, and transmit phases (left image) and a close-up of the node voltage for a data signal value equal to 3 V (right image). Figure 27 The drain current of the multi-gate transistor is shown across the frame duration of the second pixel circuit. The drain current of the multi-mode transistor remains constant throughout the frame duration of the pixel circuit, indicating that variations in the rail supply VDD are well tolerated.

[0116] Now for reference Figure 28 This diagram illustrates a third pixel circuit including a multi-gate transistor according to an embodiment of the present invention. The third pixel circuit can be understood as a simplified representation showing the common structure of both the first pixel circuit and the second pixel circuit. The third pixel circuit includes a first transistor M1, which is a multi-gate transistor of the type described above. The third pixel circuit also includes a light-emitting element D1 connected to the source or drain of the first transistor M1, such that in use, the current flowing through the light-emitting element is controlled by the first transistor M1, and the third pixel circuit includes a driving circuit 110 configured to independently control the first voltage and the second voltage in order to independently control the amplitude of the current and the duration of the current flow through the light-emitting element.

[0117] Now for reference Figure 29This diagram illustrates a fourth pixel circuit including a multi-gate transistor according to an embodiment of the present invention. The fourth pixel circuit includes a first transistor M1, which is a multi-gate transistor of the type described above, and includes a light-emitting element D1 and a driving circuit. The driving circuit of the fourth pixel circuit includes a capacitor C connected between the source of the first transistor M1 and a current-controlled gate CG1, and includes a second transistor M2 connected between the current-controlled gate CG1 and a data signal input DATA. Both the switching gate CG2 and the drain of the first transistor M1 are connected to the ground plane GND. Therefore, the fourth pixel circuit includes a total of two transistors and one capacitor, and can be referred to as a "2T1C" pixel circuit.

[0118] In the programming stage S302 of the fourth pixel circuit, the row n of the pixel array is programmed via signal selection n (SEL n). The column m is programmed via data m (DATA m) signal. The switching gate CG2 and drain terminal of the first transistor M1 are connected to a reference potential (e.g., ground plane GND). Although the reference potential is grounded (GND) in this embodiment, in other embodiments, a different potential can be used as the reference potential. For example, if all potentials are shifted up or down by the theoretically same amount, the circuit operation will remain consistent with the reference mentioned below. Figures 30 to 32 The same as described above.

[0119] Figure 30 This is a timing diagram illustrating the hold, programming, and emission phases during the operation of the fourth pixel circuit. In this implementation, the hold phase occurs first and is relatively simple. The hold phase occurs for all pixels in the array while programming is being performed on the other rows and columns. During the hold phase, the emission signal EM is brought to an appropriate high potential (e.g., the same potential as GND for convenience). This reverse-biases the light-emitting component D1, thus preventing current flow and therefore preventing light emission. During the hold phase, the SEL(n) signal is low, so the second transistor M2 is off and not conducting. The capacitor C retains its charge. The source node S is connected to the drain potential (GND) through the source-drain leakage path of the first transistor M1. Since the potential difference between the source and switching gate CG2 of the first transistor M1 (i.e., its drain-source potential difference) is zero, no current flows in the circuit, and therefore the first transistor M1 remains off during the hold phase.

[0120] Figure 31 The diagram illustrates the current flow in the fourth pixel circuit during the programming phase, which in this embodiment follows the holding phase. During the programming phase, the desired amplitude of the current that will flow through the light-emitting component D1 during the emission phase is set. This current is controlled by the potential on the gate of the current-controlled gate CG1 of the first transistor M1.

[0121] When signal SEL(n) is applied, the second transistor M2 is turned on, and the voltage across capacitor C becomes DATA(m), that is, it increases or decreases as capacitor C is charged or discharged through the second transistor M2. The source of the first transistor M1 (i.e., node S) remains close to GND potential (except for the minimum parasitic capacitive coupling between devices). DATA(m) is selected in the usual manner to control the first transistor M1, allowing a certain current to flow through the light-emitting component D1 during the emission phase. Once the desired voltage has been stored in capacitor C, the SEL(n) signal is grounded, and the DATA(m) signal becomes a value independent of the current pixel. Therefore, the pixel returns to the hold phase.

[0122] Figure 32 The current flow in the fourth pixel circuit during the emission phase is shown, which occurs once all pixels have been programmed via the aforementioned hold and program phases. The second transistor M2 is turned off, so the charge stored on C will maintain the potential difference between the current-controlled gate CG1 and the source of the first transistor M1, as programmed.

[0123] When the transmitted signal EM (which can be a common signal applied to all pixels) is at a suitable negative potential relative to GND, the following effect occurs: - The light-emitting component D1 is forward biased and can emit light; - The drain-source voltage of the first transistor M1 is positive, and therefore the first transistor M1 can conduct current; - The source voltage CG2- of the first transistor M1 is positive, and therefore the channel of the first transistor M1 is turned on, thereby achieving conduction without affecting the magnitude of the drain current; - The CG1-source voltage of the first transistor M1 remains as programmed, thereby allowing control over the amplitude of the current flowing through the first transistor M1. Generally, this amplitude will depend neither on the CG2-source and drain-source voltages of the first transistor M1, nor on the absolute amplitude of the emitted signal EM potential relative to GND.

[0124] Compared to the first and second pixel circuits, the fourth pixel circuit is more compact due to the use of fewer transistors, resulting in increased display resolution. Furthermore, using a multi-gate transistor as the first transistor M1 in the fourth pixel circuit offers several advantages over using conventional thin-film transistors (TFTs), including: 1. Better discretization between gray levels. Compared to conventional TFTs, multi-gate transistors require a higher voltage on CG1. This may result in a slight loss in power consumption, but it increases the available range (e.g., assigning 256 or 1024 luminance hues within it), thus producing superior image quality and potentially reducing flicker.

[0125] 2. Reduce charge leakage from C via M1, thereby making C smaller to increase display resolution, or reducing the minimum refresh rate to improve energy efficiency. Reverse leakage through M1 is reduced due to the relative potentials between nodes S, CG1, and SEL(n) = 0 during the emission phase, as well as the range of {DATA(m)}, allowing the correct voltage to be maintained on C for a longer period, or conversely, maintaining the same performance but with a smaller C area.

[0126] 3. Reduce or eliminate the impact of the I × R supply voltage drop. Conventional TFTs require subthreshold driving to allow for reduced drain-source voltage for superior energy efficiency and to minimize the impact of drain-source voltage variations on current. Since the supply current is drawn via wiring with varying resistances, drain-source voltage variations can differ for different pixels in the array. Conventional transistors have poor saturation; however, MMTs allow for earlier and flatter saturation. Therefore, even for large CG1-S voltage values, the drain-source voltage drop of the MMT will be small, and the current variation with drain-source voltage will be minimal. This allows for improved image uniformity across the display area. Similarly, changes in LED forward voltage with current and / or aging do not affect the magnitude of the current supplied by the MMT.

[0127] 4. Reduced routing complexity. Pixels only require DATA, SEL, and two supply rail signals, just like a conventional 2T1C circuit. Functionality is achieved without the cost of additional routing or timing complexity.

[0128] 5. Compact pixel size to achieve increased resolution, minimum feature size, and CG1 overlap. MMT allows the use of small drive transistors, including interleaving S and CG1, thus effectively producing the same footprint as conventional TFTs.

[0129] 6. By keeping the CG2-S potential constant, the transistor channel is maintained at a fairly similar voltage, thereby enabling further improvement of the metrics discussed in point 3 above.

[0130] Now for reference Figure 33The diagram illustrates a fifth pixel circuit according to an embodiment of the invention. Similar to the fourth pixel circuit, the fifth pixel circuit is an example of a pixel circuit design where the data signal DATA m is applied directly to the capacitor C, rather than via the driving transistor (M1) as in the first and second pixel circuits. The fifth pixel circuit is similar to the fourth pixel circuit except that the switching gate CG2 of the first transistor M1 is connected to the transmit signal input instead of ground. Therefore, this method uses the switching gate CG2 of the first transistor (in this embodiment, it is the MMT) as the transmit enable input, thereby allowing programming of the voltage on the capacitor C when the light-emitting element D1 is turned off. This can help increase image contrast and energy efficiency, while providing a more compact implementation compared to alternative circuit designs employing additional switching transistors (e.g., M2, M3, etc.) connected in series with the driving transistor (first transistor M1). The lateral structure of the MMT interleaves the switching gate CG1 and the source contact S, thereby reducing the overall footprint of the first transistor M1 compared to alternatives with two transistors connected in series.

[0131] Therefore, pixel circuits according to embodiments of the present invention, such as a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, have been described that utilize the capability of multi-gate transistors to perform functions that would previously require multiple conventional transistors. In this way, the number of components (e.g., transistors) required in the pixel circuit can be reduced compared to conventional solutions.

[0132] A display device may include multiple such pixel circuits, such as Figure 34 As shown in the diagram. The display device 3400 includes a display panel 3420, which includes a plurality of pixel circuits 3421, each pixel circuit including a pixel circuit according to an embodiment of the present invention (e.g., any of the pixel circuits disclosed herein). The pixel circuits may be arranged in a plurality of rows 1 to 2. n The display device 3400 may further include a control circuitry system 3410 configured to provide control signals (e.g., EM, DATA, RESET, SEL, etc.) to a plurality of pixel circuits to control the switching of one or more transistors within each pixel circuit 3421. The control signals may be applied to the pixel circuits 3421 via one or more transmission lines 3411. In some embodiments, the control circuitry system 3410 may be omitted; for example, the display panel 3420 may be configured to receive control signals from an external source outside the device 3400.

[0133] Furthermore, since the switching behavior (i.e., on / off) of the multi-gate transistors and the amplitude of the current flowing through the light-emitting element during the emission phase can be independently controlled, the pixel circuit according to embodiments of the present invention allows setting both the amplitude of the quasi-constant current through the light-emitting element and the desired emission time. This, in turn, enables the realization of high-resolution, high-brightness, and high-efficiency displays with excellent image quality (e.g., based on micro-LED emitters as light-emitting elements). The ability to independently control the switching and current amplitude also enables the implementation of PAM and PWM control schemes, implemented individually or in combination (PWAM).

[0134] The low saturation voltage of multi-gate transistors allows for the following advantages: reduced supply voltage ELVDD and proportional energy savings during the emission phase; highly precise setting of the output or drain current of the multi-gate transistor (e.g., by selecting the potential at the current-controlled gate CG1) due to the potentially low transconductance in such a device; and the maintenance of a constant output current even during large changes in the switching gate CG2 voltage, provided the potential at the current-controlled gate CG1 remains constant. This is central to achieving the combined PAM and PWM functionality, maintaining a constant current set by the current-controlled gate CG1 as long as the switching gate CG2 is above a certain value. The low sensitivity of the multi-gate transistor's output current to changes in the CG1-S voltage means that small changes at the transistor's input will result in small and potentially imperceptible final changes in the brightness of the emitted light.

[0135] Now refer to Figures 35 to 39 A sixth pixel circuit according to an embodiment of the present invention is described. For example... Figure 35 As shown, the sixth pixel circuit includes a first transistor M1, which is related to... Figure 1 The multi-gate transistor shown is similar to a multi-gate transistor. Like the fourth and fifth pixel circuits, the sixth pixel circuit is an example of a pixel circuit design where the data signal is applied directly to the capacitor, rather than via a driving transistor (M1) as in the first and second pixel circuits. Figure 2 The first pixel circuit and Figure 18 Similar to the second pixel circuit, the sixth pixel circuit includes a first capacitor C1 and a second capacitor C2 connected to the current control gate CG1 and the switching gate CG2 of the first transistor M1, respectively, as well as a light-emitting component D1. Also similar to... Figure 2 The first pixel circuit and Figure 18Similar to the second pixel circuit, the sixth pixel circuit includes a second transistor M2 connected to the switching gate CG2, and a third transistor M3 connected to the current control gate CG1. For the sake of brevity, a detailed description of such features common to the first, second, and sixth pixel circuits (and therefore already described above) will not be repeated here.

[0136] The sixth pixel circuit differs from the first and second pixel circuits in several ways. First, in the first and second pixel circuits, the third transistor M3 is connected between the current control gate CG1 and the switching gate CG2, allowing the third transistor M3 to be controlled to open or close the electrical connection between the current control gate CG1 and the switching gate CG2. However, in the sixth pixel circuit, the third transistor M3 is connected between the current control gate CG1 and the first data signal input. The first data signal input is configured to receive the first data signal DATA1 during use. In this way, the current control gate CG1 can be electrically connected or disconnected from the first data signal input by switching the third transistor M3 between an on and off state. During operation of the sixth pixel circuit, the third transistor M3 can therefore be turned on to charge the first capacitor C1 to the voltage of the first data signal DATA1.

[0137] Secondly, in the first pixel circuit, the second transistor M2 is connected between the switching gate CG2 and the reference node (VREF in the first pixel circuit; GND in the second pixel circuit), while in the sixth pixel circuit, the second transistor M2 is connected between the switching gate CG2 and the second data signal input. The second data signal input is configured to receive the second data signal DATA2 during use. In this way, the switching gate CG2 and the second data signal input can be electrically connected or disconnected by switching the second transistor M2 between an on and off state. During the operation of the sixth pixel circuit, the second transistor M2 can therefore be turned on to charge the second capacitor C2 to the voltage of the second data signal DATA2.

[0138] Third, different control signals are used in the first pixel circuit and the second pixel circuit (RESET and SEL2 in the first pixel circuit; SEL in the second pixel circuit). n -1 and SEL n The same control signal (SEL n) is applied to the respective gates of the second transistor M2 and the third transistor M3 in the sixth pixel circuit, where both the gates of the second transistor M2 and the third transistor M3 are connected to a common input. Therefore, in use, the same control signal (SEL n) is applied to the gates of both the second transistor M2 and the third transistor M3 in the sixth pixel circuit. Thus, in the sixth pixel circuit, the second transistor M2 and the third transistor M3 are configured to switch concurrently (i.e., simultaneously).

[0139] The sixth pixel circuit also includes a first emission (Em.) control unit 3501 and a second emission control unit 3502. The first emission control unit 3501 is connected to the drain of the first transistor M1. In this embodiment, the first emission control unit 3501 is connected between the drain of the first transistor M1 and the light-emitting element D1. In other embodiments, the first emission control unit 3501 may be connected between the light-emitting element D1 and the supply voltage line (VDD). As yet another alternative, in some embodiments, the light-emitting element D1 may be connected between the source of the first transistor M1 and ground (GND), in which case the first emission control unit 3501 may be connected between the drain of the first transistor M1 and the supply voltage line VDD.

[0140] The second emission control component 3502 is connected to the source of the first transistor M1. In this embodiment, the second emission control component 3502 is connected between the source of the first transistor M1 and GND. Furthermore, as described above, in some embodiments, the light-emitting component D1 may be connected between the source of the first transistor M1 and GND. In such embodiments, the second emission control component 3502 may be connected between the source of the first transistor M1 and the light-emitting component D1, or the second emission control component 3502 may be connected between the light-emitting component D1 and GND.

[0141] The first transmit control unit 3501 and the second transmit control unit 3502 can be turned on or off under the control of a suitable control signal (which may be referred to as a transmit control signal). For example, the first transmit control unit 3501 and the second transmit control unit 3502 may include transistors controlled by the transmit control signal, similar to those described above. Figure 2 The first pixel circuit describes the sixth transistor M6 and the seventh transistor M7. When both the first emission control unit 3501 and the second emission control unit 3502 are in the ON state (i.e., ON), current is allowed to flow through the first transistor M1 from the voltage supply lines VDD and GND through the light-emitting unit D1.

[0142] In the example implementation, the first emission control component 3501 and the second emission control component 3502 may be optional, such that one or both of them can be omitted. For example, the first transistor D1 may be directly connected to the light-emitting component D1, and may also be directly connected to GND. The emission control components 3501 and 3502 may be used, for example, to improve the LED's off-state performance, and may not be necessary for the operation of the circuit.

[0143] Now refer to Figures 36 to 39The sixth pixel circuit is described in the programming phase S302, holding phase S303, and emission phase S304 (e.g., as referenced). Figure 3 The operation of each period in the above). Figure 36 This is a timing diagram illustrating the programming, holding, and emission phases during the operation of the sixth pixel circuit. Specifically, Figure 36 The various control signals used in the operation of the first pixel circuit (i.e., DATA1) are shown. m DATA2 m and SEL n The relative state of the pixels (e.g., low or high, or analog voltage level). The programming and holding phases are repeated until all rows have been programmed, after which the process proceeds to the emission phase, where the programmed pixels across all rows simultaneously begin emitting light. Alternatively, as described above, in some embodiments, a separate emission signal EM can be generated for each row in the display. n This allows the emission phase to begin for a given row once programming is complete, while programming other rows is underway (in which case the hold phase can be omitted). In one example, the length and / or positioning of the hold phase S303 within the timing diagram can vary because each row of the display can be programmed sequentially, allowing the row duration of a row to be varied. Figure 36 It can follow the row duration of the previous row within the "all rows are programmed" time.

[0144] In one example, for positively programmed pixels, i.e., row n and column m, the values ​​of DATA1m and DATA2m can be correlated only when SEL(n) is high. Outside of this time, DATA1m and DATA2m can have values ​​correlated with rows other than row n, such that their values ​​can be independent of pixels in row n.

[0145] In one example Figure 36 The length and location of the hold phase within a timing diagram can vary for different sequences because each row of the display can be programmed sequentially. Therefore, for example, the row duration of a timing diagram (e.g., Figure 36 As shown in the diagram, the row duration of the previous sequence diagram within the "all rows are programmed" timeframe can be followed.

[0146] Figure 37 The current flow in the sixth pixel circuit during programming phase S302 is illustrated. Unlike the programming phase in the first pixel circuit (which includes two distinct stages (PAM and PWM programming stages)), in this embodiment, the programming phase of the sixth pixel circuit comprises a single stage. During the programming phase in the sixth pixel circuit, both the second transistor M2 and the third transistor M3 are controlled by the control signal SEL. nSwitch to the ON state. In this way, the first capacitor C1 and the second capacitor C2 are simultaneously connected and charged to the first data signal input and the second data signal input, respectively.

[0147] Therefore, as Figure 36 As shown, when the control signal SEL is used during the programming phase n When driven to a high level, the first data signal DATA1 m The voltage is applied to the first capacitor C1, while the second data signal DATA2 is transmitted. m The voltage is applied to the second capacitor C2. Due to the first data signal DATA1 m Second data signal DATA2 m They can be generated independently to have different transient voltages, such as Figure 36 As shown in the exemplary programming phase, the first capacitor C1 and the second capacitor C2 can therefore be independently charged to any arbitrary voltage during the programming phase (i.e., depending on the corresponding first data signal DATA1). m Or the second data signal DATA2 m (voltage).

[0148] In this way, during programming phase S302, the desired amplitude of the current that will flow through the light-emitting component D1 during emission phase S304 is set. This current will be controlled by the potential on the current-controlled gate CG1 of the first transistor M1. In some embodiments, if a low current level is desired, the current controlled by CG1 can be limited by the potential on the switching gate CG2, since CG2 cannot control the current in any other way but can only limit it. During this phase, the signal SEL... n The circuit is active (i.e., at a high level), so the second transistor M2 and the third transistor M3 are closed.

[0149] Figure 38 This shows the charge stored in the sixth pixel circuit during the holding phase S303. During this phase, the control signal SEL is... n Driven to a low level, both the second transistor M2 and the third transistor M3 are switched to the off (i.e., non-conducting) state. Furthermore, both the first emission control unit 3501 and the second emission control unit 3502 are in the off state, and therefore, no current flows between the source and drain of the first transistor M1 or through the light-emitting component D1. The sixth pixel circuit can remain in the hold phase until all rows of the display have been programmed.

[0150] Figure 39 The current flow in the sixth pixel circuit during the emission phase S304 is shown, where the control signal SEL nThe value remains low, keeping the second transistor M2 and the third transistor M3 in the off state. During the emission phase S304, both the first emission control unit 3501 and / or the second emission control unit 3502 (if included in the circuit) switch to the on state (i.e., conduct), allowing the current generated by CG1 through CG2 to flow from the voltage supply lines VDD and GND through the first transistor M1 via the first transistor M1 to the light-emitting element D1. Therefore, emission occurs because the light-emitting element D1 is forward biased and the first transistor M1 is saturated. This phase lasts for the duration of the frame time.

[0151] The sixth pixel circuit can be tuned to achieve low linear sensitivity of the drain current to the current-controlled gate CG1 potential. This means that small changes at the input of the first transistor M1 due to the discharge of the first capacitor C1 will only produce small and potentially imperceptible final changes in the brightness of the emitted light. Conversely, the first transistor M1 can be designed to have a superlinear / exponential dependence of the drain current, in which case a much higher dynamic range can be achieved by relying solely on the current-controlled gate CG1 / source control, making precise programming of the switching gate CG2 voltage far less demanding. This, in turn, allows for a reduction in the layout area allocated to the second capacitor C2.

[0152] Now refer to Figures 40 to 45 A seventh pixel circuit according to an embodiment of the present invention is described. For example... Figure 40 As shown, the seventh pixel circuit includes a first transistor M1, which is related to... Figure 1 The multi-gate transistor shown is similar to other multi-gate transistors. Like the fourth, fifth, and sixth pixel circuits, the seventh pixel circuit is an example of a pixel circuit design where the data signal is applied directly to the capacitor, rather than via a driving transistor (M1) as in the first and second pixel circuits. Figure 2 The first pixel circuit and Figure 18 Similar to the second pixel circuit, the seventh pixel circuit includes a first capacitor C1 and a second capacitor C2 connected to the current control gate CG1 and the switching gate CG2 of the first transistor M1, respectively, as well as a light-emitting component D1. Also similar to... Figure 2 The first pixel circuit and Figure 18 The second pixel circuit is similar, and the seventh pixel circuit includes a second transistor M2 connected to the switching gate CG2, and a third transistor M3 connected to the current control gate CG1 and the switching gate CG2.

[0153] Additionally, similar to the sixth pixel circuit, the seventh pixel circuit may optionally include a first emission control component 4001 and / or a second emission control component 4002. Like the sixth pixel circuit, the first emission control component 4001 and the second emission control component 4002 may be, for example, similar to those described above. Figure 2 The first pixel circuit describes the sixth transistor M6 and the seventh transistor M7.

[0154] Therefore, in many respects, the seventh pixel circuit is similar to the sixth pixel circuit. For the sake of brevity, the detailed description of such features common to the first, second, sixth, and seventh pixel circuits (and thus already described above) will not be repeated here.

[0155] The seventh pixel circuit differs from the sixth pixel circuit in that, instead of providing corresponding first and second data signal inputs for programming the first and second capacitors, as in the sixth pixel circuit, the third transistor M3 in the seventh pixel circuit is connected between the current control gate CG1 and the switching gate CG2. Therefore, the third transistor M3 is connected in an arrangement similar to that of the third transistor M3 in the second pixel circuit. Similar to the second pixel circuit, in the seventh pixel circuit, the respective gates of the second transistor M2 and the third transistor M3 are configured to receive different control signals, denoted here as SEL. n and SEL n -1. Therefore, in the seventh pixel circuit, the second transistor M2 and the third transistor M3 can switch independently of each other.

[0156] Now refer to Figures 42 to 45 Describe the operation of the seventh pixel circuit during each of the reset phase S301, programming phase S302, holding phase S303, and emission phase S304. Figure 41 This is a timing diagram illustrating the reset, programming, and emission phases during the operation of the seventh pixel circuit. Specifically, Figure 41 The various control signals (i.e., DATA) used in the operation of the first pixel circuit are shown. m SEL n and SEL n -1, where SEL n-1 This could be the relative state of the SEL signal in the previous row (e.g., low or high, or an analog voltage level). Figure 41 The voltage at the current control gate (VCG1) and the voltage at the switching gate (VCG2) during each operating phase of the seventh pixel circuit were also plotted.

[0157] like Figure 41As shown, the programming and holding phases are repeated until all rows have been programmed, after which the process proceeds to the emission phase, where programmed pixels across all rows simultaneously emit light. Alternatively, as described above, in some embodiments, a separate emission signal EM can be generated for each row in the display. n This allows the emission phase to begin on a given line once programming has been completed, while programming other lines is in progress (in which case the hold phase can be omitted).

[0158] Figure 42 The current flow in the seventh pixel circuit during the reset phase S301 is shown. During the reset phase S301, the signal SEL... n -1 is driven high, thus driving the signal SEL n Drive to low level. This is because the signal SEL is... n The signal is applied to the gate of the second transistor M2, therefore the second transistor M2 is in the off state during the reset phase S301. Simultaneously, because the signal SEL... n -1 is applied to the gate of the third transistor M3, so the third transistor M3 is in the ON state during the reset phase S301. Therefore, during the reset phase S301, charge can flow between the first capacitor C1 and the second capacitor C2 via the third transistor M3, and capacitors C1 and C2 can share charge, so that they store the same potential relative to ground GND.

[0159] Figure 43 The current flow in the seventh pixel circuit during the first programming phase is shown. In the first programming phase, the signal SEL... n -1 remains high, while the signal SEL is also maintained. n Drive to high level. This is because the signal SEL is... n The signal is applied to the gate of the second transistor M2, thus putting the second transistor M2 into the ON state during the first programming stage. Simultaneously, due to the signal SEL... n -1 is applied to the gate of the third transistor M3, so the third transistor M3 is also in the ON state during the first programming stage. Therefore, during the first programming stage, both the first capacitor C1 and the second capacitor C2 are connected to the same data signal input, the data signal DATA. m The data signal input is applied. In the case of the first capacitor C1, the first capacitor C1 is connected to the data signal input via the third transistor M3 and the second transistor M2, as follows: Figure 43 As shown in the image.

[0160] Data signal DATA mThe capacitor C1 is set to an appropriate value to charge (or discharge) the first capacitor C1 to the voltage required for the operation of the first transistor M1 during the emission phase. Since the second capacitor C2 is also connected to the data signal input, it is also charged to the same voltage as the first capacitor C1 during the first programming phase (or to substantially the same voltage, ignoring minor variations due to the threshold voltage across the third transistor M3). Therefore, the operation of the seventh pixel circuit then proceeds to the second programming phase to charge the second capacitor C2 to the desired voltage level.

[0161] Figure 44 This illustrates the current flow in the seventh pixel circuit during the second programming phase. In this phase, the signal SEL... n The signal is kept high, keeping the second transistor M2 on, and thus the second capacitor C2 remains connected to the data signal input during the second programming phase. However, during the second programming phase, the signal SEL... n -1 drives the signal low, thus turning off the third transistor M3 and consequently disconnecting the first capacitor C1 from the data signal input. In this state, the data signal DATA... m Then, it is set to an appropriate value to charge the second capacitor C2 to its desired voltage level. Simultaneously, the first capacitor C1 remains charged based on the data signal DATA during the first programming phase. m The previous value (i.e., the DATA value during the first programming phase) m The voltage set by (value).

[0162] Figure 45 The current flow in the seventh pixel circuit during the emission phase S304 is shown, where the control signal SEL n and SEL n Both transistors -1 and -1 remain low, keeping the second transistor M2 and the third transistor M3 off. During the emission phase S304, both the first emission control unit 4001 and the second emission control unit 4002 (if included in the circuit design) switch to the on state (i.e., conduct), allowing current to flow through the first transistor M1 from the voltage supply lines VDD and GND through the light-emitting element D1. Therefore, emission occurs because the light-emitting element D1 is forward biased and the first transistor M1 is saturated. This phase lasts for the duration of the frame time.

[0163] Comparing the sixth pixel circuit and the seventh pixel circuit, the sixth pixel circuit can therefore be understood as an example of a pixel circuit where the value of the data signal can be set independently of other data signals by simultaneously providing its own data signal to each capacitor C1, C2, while charging the two capacitors C1, C2 independently. In this case, the ability to independently set the voltage of the first capacitor C1 and the second capacitor C2, and therefore independently control the switching and current characteristics of the first transistor M1 during the emission phase, is transmitted via the corresponding data signal DATA1. m DATA2 m This is achieved through independent control.

[0164] In contrast, the seventh pixel circuit can be understood as an example of a pixel circuit, in which two capacitors C1 and C2 use the same data signal DATA. m To program, but the data signal DATA m It can be applied independently to one capacitor without applying to the other (i.e., during the second programming phase). In this way, the ability to independently set the voltage of the first capacitor C1 and the second capacitor C2, and therefore independently control the switching and current characteristics of the first transistor M1 during the transmit phase, is achieved by transmitting the data signal DATA at different points in time. m Different values ​​are applied to the first capacitor C1 and the second capacitor C2 to achieve this.

[0165] Embodiments of the invention have been described, wherein the light-emitting element is connected to the source or drain of a multi-gate transistor (e.g., an MMT), such that in use, the current flowing through the light-emitting element is controlled by the current-controlled gate of a first transistor and is either blocked or allowed to flow through the light-emitting element under the control of the switching gate of the first transistor. In some embodiments, in addition to the current-controlled gate and the switching gate, the multi-gate transistor may also include one or more auxiliary gates.

[0166] One or more auxiliary gates can be controlled, for example, by allowing adjustment of the current to control the gate and switching the threshold voltage (V) of one or both gates. th Additional functionality can be provided by injecting charge into the region via a threshold voltage (V0). For example, the auxiliary gate can be used to inject charge into the region via a threshold voltage (V0). thCG1 The gate is shifted to supplement the function of the current-controlled gate, and an additional auxiliary gate can shift the corresponding threshold voltage in the channel region to supplement the switching gate (V) in the channel region. thCG2The functionality of an auxiliary gate complements that of a multimode transistor, provided that each individual auxiliary gate maintains the device's ability to individually control charge injection and switching. Another example of complementing transistor functionality is the use of an auxiliary gate positioned near the source region (e.g., a laterally adjacent current-controlled gate) to shield the drain's electric field from affecting the source region, thereby further improving the device's contact control operation. As another example, an auxiliary gate at the drain can be used to mitigate unwanted charge carrier generation at the drain when the device is in the off-state (off-state leakage).

[0167] Furthermore, embodiments of the invention have been described, wherein the pixel circuit includes a plurality of transistors (e.g., M1, M2, M3, etc.) that are individually turned on / off as needed. It should be understood that in all the above embodiments, any given transistor can in practice be implemented as a single device (e.g., a single TFT) or as a plurality of devices connected in series (e.g., two TFTs).

[0168] While certain embodiments of the invention have been described herein with reference to the accompanying drawings, it should be understood that many variations and modifications will be possible without departing from the scope of the invention as defined in the appended claims.

Claims

1. A pixel circuit, comprising: A first transistor, the first transistor comprising: A current-controlled gate, the current-controlled gate being configured to control the magnitude of a current supplied by the source region of the first transistor based on a first voltage applied to the current-controlled gate; and A switching gate, the switching gate being configured to block or allow current flow in the channel region of the first transistor depending on a second voltage applied to the switching gate; A light-emitting element, the light-emitting element being connected to the source or drain of the first transistor, such that, in use, the current flowing through the light-emitting element is controlled by the current-controlled gate of the first transistor, and is either blocked or allowed to flow through the light-emitting element under the control of the switching gate of the first transistor; and A driving circuit configured to independently control the first voltage and the second voltage in order to independently control the amplitude of the current and the duration of current flow through the light-emitting component.

2. The pixel circuit according to claim 1, wherein the first transistor comprises: Source pole; Drain, which is spaced apart from the source; A semiconductor region is disposed between the source and the drain; and An insulating region is disposed above the semiconductor region; The current-controlled gate is configured to control the magnitude of the current flowing through the semiconductor region between the source and the drain based on the first voltage applied to the current-controlled gate, the current-controlled gate being separated from the source by the semiconductor region and the insulating region; and The switching gate is configured to block or allow current to flow between the source and the drain through the semiconductor region, depending on the second voltage applied to the switching gate.

3. The pixel circuit according to claim 1 or 2, wherein the driving circuit comprises: A first capacitor is connected to the current-controlled gate such that, in use, the voltage on the first capacitor can be applied to the current-controlled gate as the first voltage. and A second capacitor is connected to the switching gate such that, in use, the voltage on the second capacitor can be applied to the switching gate as the second voltage.

4. The pixel circuit according to claim 3, wherein the driving circuit further comprises: The second transistor is connected between the second capacitor and the first reference voltage node, such that in use, when the second transistor is turned on, the voltage on the second capacitor can be reset to the voltage at the first reference voltage node.

5. The pixel circuit according to claim 3 or 4, wherein the driving circuit further comprises: A third transistor is connected between the current-controlled gate and the switching gate, such that when the third transistor is in the ON state, the voltage at the current-controlled gate is the same as the voltage at the switching gate.

6. The pixel circuit of claim 5, wherein the third transistor is further connected in series with the second transistor.

7. The pixel circuit according to claim 5 or 6, wherein the driving circuit further comprises: A fourth transistor is connected in series with the third transistor, and the fourth transistor is further connected between the data signal input and the second capacitor.

8. The pixel circuit of claim 7, wherein the source of the first transistor is connected to the data signal input via the source and drain of the first transistor, such that in use, when both the third transistor and the fourth transistor are in the ON state, the first capacitor and the second capacitor can be charged to equal V. DATA + V th The voltage, where V DATA It is the voltage at the input of the data signal, and V th It is the threshold voltage of the first transistor.

9. The pixel circuit according to claim 8, wherein the driving circuit further comprises: A fifth transistor is connected between the source of the first transistor and the data signal input.

10. The pixel circuit of claim 9, wherein the respective gates of the fourth transistor and the fifth transistor are connected to a first control input for receiving a first control signal.

11. The pixel circuit according to claim 8, 9, or 10, wherein the driving circuit further comprises: A sixth transistor is connected between the source of the first transistor and the ground plane, such that, in use, the sixth transistor can be switched to an on state to allow current to flow through the first transistor and the light-emitting component, and can be switched to an off state to isolate the data signal input from the ground plane.

12. The pixel circuit according to any one of the preceding claims, wherein the driving circuit further comprises: A seventh transistor is connected in series between the first transistor and the light-emitting component, such that when the seventh transistor is in the ON state, current can flow through the first transistor and the light-emitting component.

13. The pixel circuit according to claim 8, wherein the driving circuit further comprises: An eighth transistor is connected between the first capacitor and the second reference voltage node, such that when the eighth transistor is turned on, the first capacitor can be charged to the voltage at the second reference voltage node.

14. The pixel circuit of claim 13, wherein the respective gates of the second transistor and the eighth transistor are connected to a second control input for receiving a second control signal, and the respective gates of the third transistor and the fourth transistor are connected to a third control input for receiving a third control signal.

15. The pixel circuit according to claim 1 or 2, wherein the driving circuit comprises: A capacitor connected between the source and the current-controlled gate of the first transistor; and The second transistor is connected between the current-controlled gate and the data signal input. The switching gate and the drain of the first transistor are connected to the ground plane.

16. A display device, comprising: A plurality of pixel circuits, each pixel circuit comprising the pixel circuit according to any one of claims 1 to 15.

17. The display device according to claim 16, further comprising: A control circuit system configured to provide control signals to the plurality of pixel circuits to control the switching of one or more transistors within each pixel circuit.

18. A method for controlling a pixel circuit, the pixel circuit including a first transistor, the first transistor comprising: A current-controlled gate, the current-controlled gate being used to control the magnitude of a current supplied by the source region of the first transistor based on a first voltage applied to the current-controlled gate; The pixel circuit further includes: a light-emitting element connected to the source or drain of the first transistor, such that, in use, current flowing through the light-emitting element is controlled by the current-controlled gate of the first transistor and is blocked or allowed to flow through the light-emitting element under the control of the switching gate of the first transistor; and a driving circuit, the method comprising: During the emission phase, the driving circuit is used to independently control the first voltage and the second voltage in order to independently control the amplitude of the current and the duration of the current flow through the light-emitting component.

19. The method of claim 18, wherein the driving circuit includes a first capacitor connected to the current control gate and a second capacitor connected to the switching gate. During the transmission phase, the voltage on the first capacitor is applied as the first voltage to the current control gate, and the voltage on the second capacitor is applied as the second voltage to the switching gate.

20. The method of claim 19, comprising: During the reset phase, the first capacitor is set to a first voltage level and the second capacitor is set to a second voltage level.

21. The method of claim 20, wherein the driving circuit further comprises a second transistor connected between the second capacitor and the first reference voltage node, such that in use, when the second transistor is in the ON state, the voltage on the second capacitor can be reset to the voltage at the first reference voltage node, and wherein the driving circuit further comprises a third transistor connected between the current control gate and the switching gate, such that in use, when the third transistor is in the ON state, the voltage at the current control gate is the same as the voltage at the switching gate, wherein setting the first capacitor to the first voltage level and setting the second capacitor to the second voltage level comprises: The second transistor and the third transistor are switched on to set the first voltage level and the second voltage level of the first capacitor and the second capacitor, respectively, to the voltage at the first reference voltage node.

22. The method of claim 21, wherein during the reset phase, the voltage at the first reference voltage node is maintained at a voltage level higher than the maximum level of the first voltage or the second voltage to be applied to the current control gate and the switching gate, respectively, during the transmit phase.

23. The method of claim 21 or 22, wherein the driving circuit further includes a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to a data signal input, the method comprising: During the first stage of the programming phase, the third and fourth transistors are switched on to connect both the first and second capacitors to the data signal input, so that the corresponding charge levels of the first and second capacitors are set based on the voltage at the data signal input during the first stage. During the second stage of the programming phase, the third transistor is switched to the off state while the fourth transistor is in the on state, so as to further set the charge level of the second capacitor based on the voltage at the data signal input during the second stage.

24. The method of claim 23, wherein the driving circuit further comprises a fifth transistor connected between the source of the first transistor and the data signal input, and a sixth transistor connected between the source of the first transistor and a ground plane. During the first and second stages of the programming phase, the fifth transistor is switched to the ON state to connect the fourth transistor to the data signal input via the source and drain of the first transistor, and the sixth transistor is switched to the OFF state to isolate the data signal input from the ground plane. During the emission phase, the sixth transistor is switched to the ON state to allow current to flow through the first transistor and the light-emitting component, and the fifth transistor is switched to the OFF state.

25. The method according to any one of claims 18 to 24, wherein the driving circuit further comprises a seventh transistor connected in series between the first transistor and the light-emitting component. During the emission phase, the seventh transistor is switched to the ON state, allowing current to flow through the first transistor and the light-emitting component.

26. The method of claim 20, wherein the driving circuit further comprises a second transistor connected between the second capacitor and the first reference voltage node, such that in use, when the second transistor is turned on, the voltage on the second capacitor can be reset to the voltage at the first reference voltage node, and wherein the driving circuit further comprises an eighth transistor connected between the first capacitor and the second reference voltage node, such that in use, when the eighth transistor is turned on, the first capacitor can be charged to the voltage at the second reference voltage node, wherein setting the first capacitor to the first voltage level and setting the second capacitor to the second voltage level comprises: Switch the second transistor to the ON state so that the second voltage level of the second capacitor is set to the voltage at the first reference voltage node; as well as The eighth transistor is switched on to set the first voltage level of the first capacitor to the voltage at the second reference voltage node.

27. The method of claim 26, wherein the first reference voltage node includes a ground plane such that the voltage at the first reference voltage node is a ground voltage.

28. The method of claim 26 or 27, wherein the driving circuit further comprises a third transistor connected between the current-controlled gate and the source-controlled gate, such that, in use, when the third transistor is in an on-state, the voltage at the current-controlled gate is the same as the voltage at the source-controlled gate, and the driving circuit comprises a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to a data signal input, the method comprising: During the programming phase, the third and fourth transistors are switched on to connect both the first and second capacitors to the data signal input so that the respective charge levels of the first and second capacitors are set depending on the voltage at the data signal input during the programming phase.

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