Interstage clamping circuit

Abstract

An apparatus is disclosed for implementing a clamping circuit with an interstage matching network or between two amplifier stages to provide power clamping. In an example aspect, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, an interstage matching network, a power amplifier, and a clamping circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The clamping circuit includes a transistor and a resistor coupled to the transistor. The clamping circuit is coupled to the interstage matching network via a node coupled between the driver amplifier output and the power amplifier input.

Description

Technical Field

[0001] This disclosure relates in general to signal communication or signal processing using electronic devices, and more specifically to the use of clamping circuitry between two amplifier stages, such as having an interstage matching network. Background Technology

[0002] Electronic devices include traditional computing devices such as desktop computers, laptops, smartphones, wearable devices like smartwatches, and internet servers. They also include other types of computing devices such as personal voice assistants (e.g., smart speakers), wireless access points or routers, thermostats and other automation controllers, robots, automotive electronics, devices embedded in other machines such as refrigerators and industrial tools, Internet of Things (IoT) devices, and medical devices. These diverse electronic devices provide services related to productivity, communication, social interaction, security, health and safety, remote management, entertainment, transportation, and information dissemination. Therefore, electronic devices play a vital role in modern society.

[0003] In today's interconnected world, many services provided by electronic devices rely at least in part on electronic communication. Electronic communication may include, for example, the use of one or more networks (such as the Internet, Wi-Fi, etc.). ® Electronic communication refers to the exchange of wireless or wired signals transmitted over a network (or cellular network) between two or more electronic devices. Therefore, electronic communication can include wireless transmission and reception or wired transmission and reception. To transmit and receive communications, electronic devices may use transceivers, such as wireless transceivers designed for wireless communication.

[0004] Therefore, electronic communication can be achieved by transmitting signals between two wireless transceivers at two different electronic devices. For example, using a wireless transmitter, a smartphone can send wireless signals over the air to a base station (as part of uplink communication) to support mobile services. Using a wireless receiver, a smartphone can receive wireless signals transmitted from a base station over the air (as part of downlink communication) to enable mobile services. For smartphones, mobile services may include making voice and video calls, engaging in social media interactions, sending messages, watching movies, sharing videos, and performing searches. Other mobile services may include using map information or navigation instructions, finding friends, generally participating in location-based services, transferring money, obtaining another service such as ride-hailing, and so on.

[0005] Many of these mobile services rely, at least in part, on the transmission or reception of wireless signals between two or more electronic devices. Therefore, researchers, electrical engineers, and designers of electronic devices strive to develop wireless transceivers and other wireless hardware that can effectively utilize wireless signals to provide these and other mobile services. Summary of the Invention

[0006] Power clamps protect components of wireless interface devices. In one approach, a power clamp is employed on a controller die to protect power amplifiers on separate integrated circuit dies. However, the wiring distance between such a power clamp on the controller die and the power amplifier on the amplifier die can be sufficient to degrade the actual power clamping provided at the power amplifier to a level below the target power clamping protection threshold. To shorten this routing distance and at least reduce the difference between the target protection level and the achieved protection level, this document describes employing clamping circuitry, such as incorporating an inter-stage matching network, between two amplifier stages. In some cases, the inter-stage matching network may be coupled between the driver amplifier and the power amplifier, and the clamping circuitry may provide power clamping to protect the power amplifier. In an example embodiment, the integrated circuit die may include amplifier circuitry with a driver amplifier feeding a power amplifier. The integrated circuit die may also include clamping circuitry coupled along a signal chain via a node, which may be part of an inter-stage matching network coupled between the two amplifiers. In an exemplary operation, multiple diodes and multiple transistors are coupled together to a differential clamping circuit that clamps the voltage level of a node. The clamping circuit also clamps current before it “reaches” the input of the power amplifier from the output of the driver amplifier. In some cases, corresponding resistors are coupled to each of a pair of cross-coupled transistors in the differential clamping circuit. These resistors can increase the balance between the positive and negative voltage swings of the clamp, including by utilizing differential signals. Therefore, the clamping circuit can provide power clamping for amplifier circuitry, such as providing power clamping for a power amplifier coupled “downstream” of the output of the driver amplifier. Furthermore, power clamping can be implemented while having a significantly shorter routing distance between the power clamper and the power amplifier. These and other exemplary aspects of interstage clamping circuits are described herein.

[0007] In an example, an apparatus is disclosed. The apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, a power amplifier, an interstage matching network, and a clamping circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The clamping circuit is coupled to the interstage matching network via a node coupled between the driver amplifier output and the power amplifier input. The clamping circuit includes a transistor and a resistor coupled to the transistor.

[0008] In one example, an apparatus for clamping power using an interstage matching network is disclosed. The apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, a power amplifier, and an interstage matching network. The driver amplifier includes a driver amplifier input and a driver amplifier output, wherein the driver amplifier input is coupled to the input port. The power amplifier includes a power amplifier input and a power amplifier output, wherein the power amplifier output is coupled to the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The amplifier circuit also includes components for clamping the power of a signal flowing through the interstage matching network between the driver amplifier and the power amplifier using a transistor and a resistor coupled to the transistor.

[0009] In an example, a method is disclosed for clamping power relative to amplifier circuitry via clamping circuitry or for operating a power clamp coupled to an interstage matching network. The method includes amplifying a signal using a driver amplifier to generate a first amplified signal. The method also includes propagating the first amplified signal through the interstage matching network. The method additionally includes, in conjunction with this propagation, clamping the first amplified signal using a transistor and a resistor coupled to the transistor to generate an intermediate signal. The method further includes amplifying the intermediate signal using a power amplifier to generate a second amplified signal. Attached Figure Description

[0010] Figure 1 An environment with an example electronic device is illustrated, the example electronic device having a wireless interface device, the wireless interface device including at least one example amplifier circuit with clamping circuitry.

[0011] Figure 2 These are schematic diagrams illustrating an example radio frequency (RF) front end and an example transceiver, each of which may include at least one amplifier circuit with clamping circuitry.

[0012] Figure 3 This is a schematic diagram illustrating an example amplifier die including amplifier circuitry having an interstage matching network coupled between a driver amplifier and a power amplifier, and a clamping circuit coupled to the interstage matching network.

[0013] Figure 4 This is a circuit diagram illustrating an example clamping circuit that can be coupled to the interstage matching network of an amplifier circuit to provide power clamping in single-ended or differential implementations.

[0014] Figure 5 This is a circuit diagram illustrating an example differential clamping circuit that can be coupled to the interstage matching network of an amplifier circuit to provide power clamping.

[0015] Figure 6-1 and Figure 6-2 A circuit diagram illustrating an example differential amplifier circuit is depicted, which has a driver amplifier, an interstage matching network, and a power amplifier, and has multiple example nodes, at which differential clamping circuitry can be coupled to provide power clamping.

[0016] Figure 7 This is a flowchart illustrating an example process for clamping power relative to an amplifier circuit via a clamping circuit or for operating a power clamp coupled to an interstage matching network. Detailed Implementation

[0017] Introduction and Overview

[0018] To facilitate the transmission and reception of wireless signals, electronic devices may use wireless interface devices, including wireless transceivers and / or radio frequency (RF) front-ends. Wireless interface devices comprise various electrical and electronic components that operate based on voltage and current and use such voltages and currents to process signals. These components are designed to operate within specified voltage and current ranges. If operating conditions deviate from these specified ranges, the components may generate fault signaling. Furthermore, deviations from specified operating conditions may damage the components, especially if the operating current or voltage exceeds the corresponding specified range.

[0019] To protect components of a circuit, such as transistors used for amplification or switching, the circuit may include a power clamp. A power clamp prevents the power experienced by a component from exceeding a power level that could damage the component. For this purpose, a power clamp may limit voltage levels or current magnitudes. This may include limiting voltage and current according to a permissible but optional interpretation of the word "OR" to encompass an inclusive OR relationship. In some cases, a power clamp may also be used, or alternatively, to provide, for example, overvoltage protection or electrostatic discharge (ESD) protection.

[0020] In some wireless interface device environments, at least a portion of the control functionality is decoupled from the amplifier functionality. For example, the controller die may be decoupled from the amplifier die. To name just a few examples, the controller die may be implemented using complementary metal-oxide-semiconductor (CMOS) or silicon-on-insulator (SOI) process technologies. The amplifier die includes amplifier circuitry (or amplification circuitry), which may include driver amplifiers and power amplifiers. Before being amplified by the amplifier die, the controller die may use filters, pre-driver amplifiers, combinations thereof, etc., to condition signals, such as radio frequency (RF) signals.

[0021] In one method of protecting circuitry components, an input clamp is deployed at the controller die to meet power protection specifications for the components on both the controller and amplifier dies. However, with an input clamp on the controller die, the routing of the RF input signal is relatively complex relative to the components on the amplifier die. The RF input signal enters the controller die and propagates through multiple blocks or stages to modulate the signal. These blocks may include input attenuators, input clamps, input switches, pre-driver amplifiers, etc. The modulated RF signal then leaves the controller die and travels to the amplifier die, which includes the power amplifier. This significant routing distance can cause problems for the RF signal. First, the routing distance degrades the quality of the signal itself, such as by altering the signal's phase. Second, the wiring distance shifts the target power clamp protection threshold to an actual power clamp protection threshold that may be lower than the target threshold.

[0022] This makes the components of amplifier dies (including power amplifiers) susceptible to damage from voltages and currents exceeding specified limits. Consequently, power amplifier circuitry may be damaged, and the die may become unusable. The discovery of unusable dies during testing at the manufacturing facility results in financial losses. Furthermore, dies damaged after deployment in electronic devices pose additional risks, as consumer electronics such as cellular phones may become inoperable and be returned by consumers.

[0023] To at least reduce this wiring distance between the input power clamp and the power amplifier, this document describes other methods for protecting circuit components in which the power clamp is incorporated into an integrated circuit die (or integrated circuit chip) having a driver amplifier or power amplifier. For example, the amplifier die or at least one or more transistors thereof can be implemented using gallium arsenide (GaAs) semiconductor technology. The power clamp may be coupled to a node of the amplifier circuitry on the amplifier die. In some aspects, the amplifier circuitry includes a driver amplifier that feeds the power amplifier. A node may be coupled between the driver amplifier and the power amplifier.

[0024] In some cases, an interstage matching network may be coupled between the driver amplifier and the power amplifier. In at least some of these cases, a node may be associated with the interstage matching network. For example, a node may be part of a wire, a metal trace, or another electrical conductor that forms at least a portion of the interstage matching network or couples two or more of its components together. Thus, a power clamp may be coupled to the interstage matching network between the driver amplifier and the power amplifier.

[0025] In some implementations, the power clamp can be implemented using a clamping circuit. The clamping circuit includes at least one transistor coupled between a first node (such as a node associated with an interstage matching network) and a second node (such as another node of an amplifier circuit, e.g., for a differential power amplifier). The other node of the amplifier circuit may also be associated with an interstage matching network. The clamping circuit may also include one or more diodes coupled in series and at least one resistor coupled to the at least one transistor, as described below. A number of diodes connected in series can at least partially establish the trigger point for the power clamp. The clamping circuit can limit the voltage level at the node or the magnitude of the current flowing through the node toward the input of the power amplifier based on the trigger point of the power clamp.

[0026] A second clamping circuit, coupled to the node "in the opposite manner" to the transistor terminals or diode junctions, prevents reverse voltages. In other words, the first clamping circuit prevents positive signal oscillations or forward-biased signal oscillations, and the second clamping circuit prevents negative signal oscillations or reverse-biased signal oscillations. In some implementations, these two clamping circuits can also be combined to implement a differential clamping circuit to protect differential amplifiers, such as differential power amplifiers.

[0027] Therefore, certain specific implementations of the description include an input power clamp disposed on the same die as the power amplifier, which is part of the amplifier circuitry. The power clamp can be implemented using clamping circuitry or coupled to an interstage matching network of the amplifier circuitry, including clamping circuitry coupled to an interstage matching network of the amplifier circuitry. The clamping circuitry can provide voltage or current clamping at the interstage matching network of the amplifier circuitry between the driver amplifier and the power amplifier. Therefore, this clamping at the interstage matching network can limit the power input to the power amplifier, which, from a signal flow or signal processing perspective, "follows" the driver amplifier and the interstage matching network.

[0028] At least the power amplifier section of an amplifier circuit can be implemented using single-ended or differential circuitry. For differential power amplifiers, this document describes how interstage clamping circuitry can be used to reduce the size of the clamping voltage step available to the circuit designer. Therefore, specific implementations of some of the descriptions allow for finer control over the clamping voltage of the design. Furthermore, resistors in the clamping circuit can facilitate more balanced clamping, including when using a differential power amplifier. For example, including a resistor coupled between the two terminals of the transistor in the clamping circuit can make the positive power clamping level and the negative power clamping level closer to equal compared to a clamping circuit that omits such resistors.

[0029] The on-die power clamping method described herein provides a significantly shorter routing distance along the RF signal chain between the power clamper and the power amplifier. This shorter routing distance is achieved without significantly increasing the size of the amplifier die. Therefore, the target power clamping protection threshold can be achieved more definitively and with less signal degradation at the power amplifier. Furthermore, the overall product cost is reduced by omitting or removing the power clamper from the controller die.

[0030] Therefore, the clamping circuit described herein can be coupled to an interstage matching network stage unit via at least one node to provide input clamping functionality for at least the power amplifier. Example implementations of power clamps based at least on differential configurations offer the opportunity for finer control over the trigger point of power clamping at the input of the power amplifier via nodes in the interstage matching network. Furthermore, resistors including transistors coupled to the clamping circuit can create a more balanced clamping effect between the positive and negative portions of the differential amplifier circuitry or its differential signaling. Moreover, a stronger clamping effect can be achieved (e.g., enforced or defined) as the voltage at the node increases, providing superior protection. Additional example implementations for providing power clamping protection using clamping circuits with interstage matching networks are described herein.

[0031] Description Example

[0032] Figure 1 An example environment 100 is illustrated with electronic device 102 having a wireless interface device 120, which includes at least one example amplifier circuit 130 with clamping circuitry 138. This document describes an example specific implementation of the amplifier circuit 130, which may be part of a transceiver, radio frequency front-end (RFFE), etc., of a device. In environment 100, example electronic device 102 communicates with base station 104 via wireless link 106.

[0033] exist Figure 1 In this design, electronic device 102 is depicted as a smartphone. However, electronic device 102 can be implemented as any suitable computing device or other electronic device. Examples of devices that can be implemented as electronic device 102 include cellular base stations, broadband routers, access points, cellular or mobile phones, gaming devices, navigation devices, media devices, laptop computers, desktop computers, tablet computers, server computers, network attached storage (NAS) devices, smart appliances, vehicle-based communication systems, Internet of Things (IoT) devices, sensor or security devices, asset trackers, fitness management devices, wearable devices such as smart glasses or smartwatches, wireless power devices (transmitters or receivers), medical devices, and the like.

[0034] Base station 104 communicates with an example smartphone implementation of electronic device 102 via wireless link 106, which can be implemented as any suitable type of wireless link carrying communication signals. Although depicted as a base station tower of a cellular radio network, base station 104 can be represented or implemented as another device, such as a satellite, terrestrial broadcast tower, access point, peer-to-peer device, mesh network node, fiber optic interface, or another electronic device generally described above. Therefore, wireless link 106 or its extensions can be connected between electronic device 102 and base station 104 in any of a variety of ways.

[0035] Wireless link 106 may include a downlink that transmits data or control information from base station 104 to electronic device 102. Wireless link 106 may also include an uplink that transmits other data or control information from electronic device 102 to base station 104. Wireless link 106 may be implemented using any suitable wireless communication protocol or standard. Examples of such protocols and standards include 3GPP Long Term Evolution (LTE) standards, such as 4G, 5G, or 6G cellular standards; IEEE 802.11 standards, such as 802.11g, ac, ax, ad, aj, or ay standards (e.g., Wi-Fi). ® 6 or WiGig ® ); IEEE 802.16 standard (e.g., WiMAX) ® );Bluetooth ® Standards; Ultra-wideband (UWB) standards (e.g., IEEE 802.15.4); etc. In some implementations, the wireless link 106 may provide power wirelessly, and the electronic device 102 or base station 104 may include a power source.

[0036] As shown with respect to some specific embodiments, electronic device 102 may include at least one application processor 108 and at least one computer-readable storage medium 110 (CRM 110). Application processor 108 may include any type of processor, such as a central processing unit (CPU) or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored in CRM 110. CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., magnetic disk or magnetic tape), etc. In the context of this disclosure, CRM 110 is implemented to store instructions 112, data 114, and other information of electronic device 102, and therefore CRM 110 does not include transiently propagated signals or carrier waves.

[0037] Electronic device 102 may also include one or more input / output ports 116 (I / O ports 116) and at least one display 118. The I / O ports 116 enable data exchange or interaction with other devices, networks, or users. The I / O ports 116 may include serial ports (e.g., Universal Serial Bus (USB)). ® Display 118 may include ports such as parallel ports, Ethernet ports, audio ports, infrared (IR) ports, camera ports, or other sensor ports. Display 118 may be implemented as a display screen or projection that presents graphical images provided by other components of electronic device 102, such as a user interface (UI) associated with an operating system, program, or application. Alternatively or additionally, display 118 may be implemented as a display port or virtual interface through which graphical content of electronic device 102 is conveyed or presented.

[0038] Electronic device 102 also includes at least one wireless interface device 120 and at least one antenna 122. Example wireless interface device 120 provides connectivity to appropriate networks and peer devices via a wireless link, which may be configured similarly or differently from wireless link 106. Wireless interface device 120 can facilitate communication over any suitable type of wireless network, such as wireless local area network (LAN) (WLAN), wireless personal area network (PAN) (WPAN), peer-to-peer (P2P) network, mesh network, cellular network, wireless wide area network (WAN) (WWAN), and / or navigation network (e.g., North American Global Positioning System (GPS) or another Satellite Positioning System (SPS) or Global Navigation Satellite System (GNSS)). In the context of example environment 100, electronic device 102 can bidirectionally communicate various data and control information with base station 104 via wireless interface device 120. However, electronic device 102 can communicate directly with other peer devices, alternative wireless networks, etc. Additionally, as described above, electronic device 102 may alternatively be implemented as base station 104 or another device as illustrated herein.

[0039] As shown, the wireless interface device 120 may include at least one communication processor 124, at least one transceiver 126 (e.g., a wireless transceiver 126), and at least one radio frequency front-end 128 (RFFE 128). These components process data information, control information, and signals associated with transmitting information to the electronic device 102 via antenna 122. The communication processor 124 may be implemented as at least a part of a system-on-chip (SoC), a modem processor, or a baseband radio processor (BBP) that implements a digital communication interface for data, voice, message sending and receiving, or other applications of the electronic device 102. The communication processor 124 may include a digital signal processor (DSP) or one or more signal processing blocks (not shown) for encoding and modulating data for transmission and for demodulating and decoding received data. Additionally, the communication processor 124 may also manage (e.g., control or configure) aspects or operations of the transceiver 126, the RF front-end 128, and other components of the wireless interface device 120 to implement various communication protocols or communication technologies.

[0040] In some cases, application processor 108 and communication processor 124 may be combined into a single module or integrated circuit (IC), such as a SoC. Regardless, application processor 108, communication processor 124, or a processor may be substantially operatively coupled to one or more other components (such as CRM 110 or display 118) to enable control of various components of electronic device 102 or other interactions with those components. For example, at least one processor 108 or 124 may present one or more graphic images on a display screen embodiment of display 118 based on one or more wireless signals transmitted or received by a component of wireless interface device 120 via at least one antenna 122. Furthermore, application processor 108 or communication processor 124 (including combinations thereof) may be implemented using digital circuitry that implements the logic or functionality described herein. Additionally, communication processor 124 may also include memory (not depicted separately) for storing data and processor-executable instructions (e.g., code), such as the same or another CRM 110, or associated with it.

[0041] As shown, the wireless interface device 120 may include at least one amplifier circuit 130 (or amplifier circuit 130) described below. More specifically, transceiver 126 may include at least one amplifier circuit 130-2, or RF front end 128 may include at least one amplifier circuit 130-1 (subject to the optional but permissible inclusion or interpretation of the word "or," including both components may have at least one amplifier circuit 130). Transceiver 126 may also include circuitry and logic for filtering, switching, amplification, channelization, frequency conversion, etc. Frequency conversion functionality may include up-conversion or down-conversion of frequencies performed by a single conversion operation (e.g., using a direct conversion architecture) or by multiple conversion operations (e.g., using a superheterodyne architecture). Generally, transceiver 126 may include filters, switches, amplifiers, mixers, etc., for routing and conditioning signals transmitted or received via antenna 122.

[0042] In addition to amplifier circuit 130-2, transceiver 126 may also include analog-to-digital converter (ADC) or digital-to-analog converter (DAC). Figure 1 (Not shown in the diagram). In operation, the ADC converts an analog signal into a digital signal, and the DAC converts a digital signal into an analog signal. Generally, the ADC or DAC may be implemented as part of the communication processor 124, as part of the transceiver 126, or separately from both (e.g., as another part of the SoC or as part of the application processor 108).

[0043] The components or circuitry of transceiver 126 can be implemented in any suitable manner, such as utilizing combined transceiver logic or individually as respective transmitter and receiver entities. In some cases, transceiver 126 is implemented using multiple or different parts to perform the corresponding transmit and receive operations (e.g., using...). Figure 2 (Implemented by separate send and receive chains as described in the text). Although in Figure 1 Although not shown, transceiver 126 may also include logic for performing in-phase / quadrature (I / Q) operations such as combining, phase correction, modulation, demodulation, etc.

[0044] RF front-end 128 may include one or more filters, multiple switches, or one or more amplifiers (such as amplifier circuit 130-1) for conditioning signals received via antenna 122 or for conditioning signals to be transmitted via antenna 122. RF front-end 128 may also include phase shifters (PS), peak detectors, power meters, gain control blocks, antenna tuning circuitry, n-way multiplexers, baluns, etc. Configurable components of RF front-end 128 (such as phase shifters, automatic gain controllers (AGC), or switches) may be controlled by communication processor 124 to enable communication in various modes, communication utilizing different frequency bands and / or carrier aggregation (CA), or communication using beamforming.

[0045] In some embodiments, antenna 122 is implemented as at least one antenna array comprising multiple antenna elements. Therefore, as used herein, “antenna” can refer to at least one discrete or separate antenna, at least one antenna array comprising multiple antenna elements, or a portion of an antenna array (e.g., an antenna element), depending on the context or specific implementation. At least one antenna 122 can also be part of a module comprising one or more other components of RF front-end 128 (e.g., amplifier circuitry 130-1 or a filter), or at least one antenna 122 can be a separate component.

[0046] exist Figure 1 In this document, the example amplifier circuit 130 is depicted as having amplifier circuit 130-2 as part of transceiver 126, amplifier circuit 130-1 as part of RF front-end 128, etc. However, the specific implementations of amplifier circuit 130 described herein may additionally or alternatively be used in other parts of wireless interface device 120 or other parts of electronic device 102. As explained above, amplifier circuit 130 may be included in electronic devices other than cellular phones (such as base station 104). For base stations (or mobile phones), by way of example only, the transmit or receive chain of transceiver 126 and / or RF front-end 128 may include amplifier circuit 130 as described herein. Other electronic devices that may employ amplifier circuit 130 include laptops, communication hardware for vehicles, wireless access points, etc., as described herein.

[0047] In an example implementation, amplifier circuit 130 may include at least one port 132, such as input port 132-1 and output port 132-2 (or more generally, a first port 132-1 and a second port 132-2). As illustrated, amplifier circuit 130 may include at least one driver amplifier 134, at least one power amplifier 136, at least one clamping circuit 138, and at least one interstage matching network 140. In some cases, driver amplifier 134 and power amplifier 136 are coupled in series between input port 132-1 and output port 132-2. As shown, driver amplifier 134 may be coupled closer to input port 132-1 than power amplifier 136, and power amplifier 136 may be coupled closer to output port 132-2 than driver amplifier 134. Therefore, driver amplifier 134 may be coupled between input port 132-1 and power amplifier 136, and power amplifier 136 may be coupled between driver amplifier 134 and output port 132-2.

[0048] Furthermore, driver amplifier 134, interstage matching network 140, and power amplifier 136 may be coupled in series between input port 132-1 and output port 132-2. Coupling may include electromagnetic coupling, such as having two or more inductors forming at least one converter that functions as a balun to generate differential signaling. As shown, interstage matching network 140 may be coupled between driver amplifier 134 and power amplifier 136 to facilitate signal propagation therebetween. Clamping circuitry 138 may be coupled to interstage matching network 140 to provide power clamping functionality for one or more portions, units, or stages of amplifier circuitry 130 as described herein.

[0049] As depicted, the signal flow can proceed from input port 132-1 to driver amplifier 134 and through the driver amplifier. A first amplified signal can propagate from driver amplifier 134 as an intermediate signal (e.g., an interstage signal) to interstage matching network 140 and through the interstage matching network. At power amplifier 136, the first amplified signal or intermediate signal is amplified to generate a second amplified signal. The second amplified signal is output from power amplifier 136 and can travel to output port 132-2. In conjunction with interstage matching network 140, clamping circuit 138 can clamp the power level of the intermediate signal to generate a clamping signal for protecting downstream components. In this case, power amplifier 136 can safely amplify the clamping signal.

[0050] This article primarily describes the two amplifiers of amplifier circuit 130 from the perspective of driver amplifier 134 and power amplifier 136. However, two or more amplifiers coupled to or protected by clamping circuit 138 may generally be referred to as the first amplifier and the second amplifier. Such other amplifiers can be or may include any type of amplifier for any purpose, such as low-noise amplifiers, operational amplifiers, amplifiers of any given class, combinations thereof, etc. The first amplifier and the second amplifier may be coupled together via interstage matching network 140.

[0051] Despite Figure 1 In China (and in Figures 2 to 6-2 The diagram explicitly depicts a specific number and arrangement of components, but the illustrated circuit including amplifier circuit 130 may include more or fewer of any such components, as well as other components not shown. Furthermore, components may be arranged and interconnected in different ways. An exemplary embodiment of clamping circuit 138 and at least one node coupled thereto is described below with reference to several figures. Figure 3 , Figure 4 and Figure 5 Begin. However, this document will then refer to... Figure 2 Example implementations of the transceiver and RF front end are described.

[0052] Figure 2 Each of these examples may include a clamping circuit 138 ( Figure 2 A schematic diagram 200 of at least one amplifier circuit 130 (not shown) includes an example RF front end 128 and an example transceiver 126. Figure 2 Antenna 122 and communication processor 124 are also depicted. Communication processor 124 transmits one or more data signals to other components (such as...). Figure 1 The application processor 108 is used for further processing at 224 (e.g., for processing at the application level). As shown, circuit 200 may include a first amplifier circuit 130-1, a second amplifier circuit 130-2, a third amplifier circuit 130-3, or a fourth amplifier circuit 130-4, including one to four such amplifier circuits. However, circuit 200 may include different numbers of amplifiers (e.g., more or fewer amplifiers), may include amplifiers or other components coupled together in different ways, may include amplifiers located in different positions, may include amplifiers implemented with two or more stages, and so on.

[0053] As illustrated from left to right, in the example implementation, antenna 122 is coupled to RF front-end 128, and RF front-end 128 is coupled to transceiver 126. Transceiver 126 is coupled to communication processor 124. The example RF front-end 128 includes at least one signal propagation path 222. The at least one signal propagation path 222 may include at least one amplifier circuit 130, such as amplifier circuit 130-1 and amplifier circuit 130-3. The example wireless transceiver 126 includes at least one receive chain 202 (or receive path 202) and at least one transmit chain 252 (or transmit path 252). Although only one RF front-end 128, one transceiver 126, and one communication processor 124 are shown at circuit 200, electronic device 102 or its wireless interface device 120 may include multiple instances of any or all of these components. Additionally, although... Figure 2 Only certain components are explicitly depicted and shown as coupled together in a particular manner, but transceiver 126 or RF front end 128 may include other components not illustrated (e.g., switches or buffers), more or fewer components, component arrangements coupled in different ways, etc.

[0054] In some implementations, the RF front-end 128 couples the antenna 122 to the transceiver 126 via a signal propagation path 222. In operation, the signal propagation path 222 carries a signal between the antenna 122 and the transceiver 126. During or as part of signal propagation, the signal propagation path 222 may modulate the propagating signal, for example, using amplifier circuitry 130-1 or 130-3. This enables the RF front-end 128 to couple the wireless signal 220 from the antenna 122 to the transceiver 126 as part of a reception operation. The RF front-end 128 also enables the transmission signal to be coupled from the transceiver 126 to the antenna 122 as part of a transmission operation to transmit the wireless signal 220. Although Figure 2 Not explicitly shown, but the RF front end 128 or its signal propagation path 222 may include one or more other components, such as an amplifier or another amplifier circuit (e.g., a driver amplifier, power amplifier, or low-noise amplifier), a filter, an n-way multiplexer, a phase shifter, a dual signal generator, one or more switches, etc.

[0055] In some implementations, transceiver 126 may include at least one receive chain 202, at least one transmit chain 252, or at least one receive chain 202 and at least one transmit chain 252. From left to right, receive chain 202 may include a low-noise amplifier 204 (LNA 204), a filter 206, a mixer 208 for frequency down-conversion, and an ADC 210. Transmit chain 252 may include a power amplifier 254 (PA 254), a filter 256, a mixer 258 for up-conversion, and a DAC 260. However, receive chain 202 or transmit chain 252 may include other components, such as additional amplifiers or filters (e.g., baseband frequency, intermediate frequency, RF filters), multiple mixers, one or more buffers, or at least one local oscillator, which may be electrically or electromagnetically positioned anywhere along the depicted receive and transmit chains.

[0056] The receive chain 202 is coupled between the signal propagation path 222 of the RF front-end 128 and the communication processor 124, for example, via a low-noise amplifier 204 and an ADC 210. The transmit chain 252 is coupled between the signal propagation path 222 and the communication processor 124, for example, via a power amplifier 254 and a DAC 260. The transceiver 126 may also include at least one phase-locked loop 232 (PLL 232) coupled to the mixer 208 or the mixer 258. For example, the transceiver 126 may include one PLL 232 for each transmit chain / receive chain pair, one PLL 232 for each transmit chain, one PLL 232 for each receive chain, multiple PLL 232 per chain, etc.

[0057] As shown in some example implementations of the receive chain 202 along the signal propagation direction, antenna 122 is coupled to low-noise amplifier 204 via signal propagation path 222 and its amplifier circuit 130-3. Low-noise amplifier 204 is coupled to filter 206. Filter 206 is coupled to mixer 208, and mixer 208 is coupled to ADC 210. ADC 210 is then coupled to communication processor 124. As shown in some example implementations of the transmit chain 252 along the signal propagation direction, communication processor 124 is coupled to DAC 260, and DAC 260 is coupled to mixer 258. Mixer 258 is coupled to filter 256, and filter 256 is coupled to power amplifier 254. Power amplifier 254 is coupled to antenna 122 via amplifier circuit 130-1 of signal propagation path 222. Although only one receive chain 202 and one transmit chain 252 are explicitly shown, the electronic device 102 or its transceiver 126 may include multiple instances of any one or both components. Although the ADC 210 and DAC 260 are illustrated as being individually coupled to the communication processor 124, they may share a bus or other mechanism for communicating with the processor 124. Furthermore, the ADC 210 or DAC 260 may be part of the communication processor 124 instead of the illustrated transceiver 126, or may be separate from both the transceiver 126 and the communication processor 124.

[0058] As part of the example signal reception operation, amplifier circuit 130-3 of signal propagation path 222 amplifies the received signal and forwards the amplified signal to low-noise amplifier 204. Low-noise amplifier 204 receives the amplified signal from RF front-end 128 and, based on the received signal, provides another amplified signal to filter 206. Filter 206 filters the other amplified signal and provides the filtered signal to mixer 208. Mixer 208 performs a frequency conversion operation on the other filtered signal to down-convert from one frequency to a lower frequency (e.g., from radio frequency (RF) to intermediate frequency (IF), or from RF or IF to baseband frequency (BBF)). Mixer 208 may use at least one PLL 232 to perform frequency down-conversion in a single conversion step or through multiple conversion steps. Mixer 208 may provide the down-converted signal to ADC 210 for conversion and forward as a digital signal to communication processor 124.

[0059] As part of the example signal transmission operation, mixer 258 receives an analog signal at BBF from DAC 260 (or, if the signal has already been up-converted once by another mixer (not shown)). Mixer 258 upconverts the analog signal to a higher frequency (such as upconverting to an RF frequency) to generate an RF signal with a target synthesized frequency using the signal generated by PLL 232. Mixer 258 provides the RF or other up-converted signal to filter 256. Filter 256 filters the RF signal and provides the filtered signal to power amplifier 254. Thus, after being filtered by filter 256, power amplifier 254 amplifies the filtered signal and provides the amplified signal to signal propagation path 222 for signal conditioning. RF front-end 128 may use, for example, amplifier circuit 130-1 of signal propagation path 222 to provide an additional amplified signal to antenna 122 for transmission as wireless signal 220.

[0060] As described herein, example implementations of amplifier circuit 130 may be used at any or more of example amplifier circuits 130-1, 130-2, 130-3, or 130-4 in transceiver 126 or RF front end 128, or at other signal amplification locations in electronic device 102. Figure 2 (Not shown in the image). In some cases, if the first amplifier circuit 130-1 of the RF front end 128 includes (e.g., Figure 1 and Figure 3 If the transceiver 126 comprises a driver amplifier 134, a power amplifier 136, an interstage matching network 140, and a clamping circuit 138, then the power amplifier 254 or amplifier circuit 130-2 may be omitted, or the transceiver 126 may "replace" the driver amplifier or its pre-driver amplifier. Additionally or alternatively, the second amplifier circuit 130-2 may include the driver amplifier, clamping circuit 138, and interstage matching network 140. Figure 2 (Not explicitly shown in the text), they are combined with the depicted power amplifier 254 (e.g., as part of the second amplifier circuit 130-2).

[0061] In some cases, the third amplifier circuit 130-3 of the RF front end 128 includes an interstage matching network 140 and a clamping circuit 138 (e.g., as shown in the image). Figure 1 and Figure 3 (shown) Two or more amplifiers combined. At least one of these two or more amplifiers may be implemented as a low-noise amplifier for receiving signal processing. Additionally or alternatively, the fourth amplifier circuit 130-4 may include a driver amplifier, an interstage matching network 140, and a clamping circuit 138 (shown). Figure 2(Not explicitly shown in the text), these are combined with the depicted low-noise amplifier 204 (e.g., as part of the fourth amplifier circuit 130-4). Alternatively, the fourth amplifier circuit 130-4 may include multiple low-noise amplifiers combined with an inter-stage matching network 140 and clamping circuit 138 providing clamping functionality for the propagating signal. Typically, the amplifier circuit 130 with clamping circuit 138 can be deployed anywhere in the transceiver 126, RF front-end 128, another part of the wireless interface device 120, or another part of the electronics 102 to protect the input of any type of amplifier.

[0062] However, circuit 200 only depicts some examples for transceiver 126 and / or RF front-end 128. In some cases, the various components illustrated using separate schematic boxes or circuit elements in the figures may be manufactured or packaged in different discrete ways. For example, one physical module may include components of RF front-end 128 and a portion of components of transceiver 126, and another physical module may combine communication processor 124 with the remaining components of transceiver 126. Furthermore, in some cases, antenna 122 may be co-packaged with at least some components of RF front-end 128 (e.g., co-packaged with amplifier circuitry 130 and at least one filter) or co-packaged with those components of transceiver 126. Although Figure 2 Some amplifiers in the design are described as including clamping circuit 138 ( Figure 2 The amplifier circuit 130 (not shown) is used to clamp power in conjunction with the interstage matching network 140 as described herein, but any one or more such amplifier circuits may alternatively be implemented without clamp circuit 138, or as an amplifier circuit that clamps voltage or current in a different manner.

[0063] In additional or alternative embodiments, one or more components may be physically or logically “displaced” to different parts of the wireless interface device 120 compared to the illustrated circuitry 200, and / or may be incorporated into different modules. For example, a low-noise amplifier 204 or a power amplifier 254 may be alternatively or additionally deployed in the RF front end 128, such as as at least part of amplifier circuitry 130-3 or amplifier circuitry 130-1, respectively. Reference will be made to the following... Figure 3 Examples of amplifier circuits 130-1 or 130-2 with power amplifier 136 (or power amplifier 254) are described below. In some cases, power amplifier 136 may be implemented using power amplifier 254 or using that power amplifier.

[0064] Figure 3This is a schematic diagram 300 illustrating an example amplifier die 304 including amplifier circuitry 130, which has an interstage matching network 140 coupled between a driver amplifier 134 and a power amplifier 136, and a clamping circuitry 138 coupled to the interstage matching network 140. As illustrated, schematic diagram 300 includes a controller die 302 and an amplifier die 304. The controller die 302 and the amplifier die 304 can be (e.g., Figure 1 and Figure 2 The communication processor 124 and (e.g., Figure 1 and Figure 2 The antennas 122 are coupled together in series. More generally, the two separate integrated circuit dies or chips may be referred to as the first die and the second die.

[0065] In exemplary operation, the controller die 302 receives signals from the communication processor 124. Although Figure 3 Although not shown, other components (e.g., mixers, filters, or DACs) may be coupled between the communication processor 124 and the input of the controller die 302. The controller die 302 may generate a regulated signal 318 as part of a signal control process. The output of the controller die 302 provides the regulated signal 318, and the regulated signal 318 is coupled to the input of the amplifier die 304. Although not shown, one or more components may be coupled between the output of the controller die 302 and the input of the amplifier die 304.

[0066] An amplifier die 304, including at least one amplifier, amplifies the regulated signal 318 to generate an amplified signal 328. After amplification, the amplifier die 304 provides the amplified signal 328 at its output. The amplified signal 328 can be relayed to the antenna 122. Although Figure 3 Not shown, but other components (e.g., mode switches, filters, another amplifier or front-end module (FEM)) may be coupled between the output of amplifier die 304 and antenna 122.

[0067] As shown in the figure, the controller die 302 includes at least one attenuator 312 (ATT 312), at least one pre-driver amplifier 314 (PDA 314), and at least one output matching network 316 (OMN 316). The attenuator 312, pre-driver amplifier 314, and output matching network 316 are coupled in series between the input and output of the controller die 302. However, the controller die 302 may include more, fewer, or different components. Furthermore, the depicted components and other components may be arranged or coupled in a manner similar to or different from those depicted.

[0068] In one approach (not shown), a power clamp may be coupled between attenuator 312 and pre-driver amplifier 314. Such a power clamp can limit the power input to downstream components, such as power amplifier 136. However, as described above, the relatively long signal path between the pre-driver amplifier 314 of controller die 302 and the power amplifier 136 of amplifier die 304 creates signaling problems. These problems include signal degradation and the inability to reach the target power clamp protection threshold at power amplifier 136.

[0069] In an exemplary implementation, to at least partially mitigate these issues, this document describes incorporating at least one clamping circuit 138 at the interstage matching network 140 on amplifier die 304 as at least a portion of at least one power clamp 310. The clamping circuit 138 can provide power clamping to the integrated circuit die relative to the power of a signal supplied, for example, to the input of power amplifier 136. In addition to amplifier circuit 130, amplifier die 304 may also include an input matching network 322 (IMN 322) and an output matching network 326 (OMN 326). The input matching network 322, amplifier circuit 130, and output matching network 326 can be coupled together in series between the input and output of amplifier die 304.

[0070] As shown, input matching network 322 may be coupled between the input of amplifier die 304 and amplifier circuit 130 (e.g., via input port 132-1 of amplifier circuit 130). Output matching network 326 may be coupled between amplifier circuit 130 (e.g., via output port 132-2 of amplifier circuit 130) and the output of amplifier die 304. Amplifier circuit 130 may be coupled between input matching network 322 and output matching network 326 in a series connection between the input and output of amplifier die 304. However, amplifier die 304 may include more, fewer, and / or different components. Furthermore, the depicted components and other components may be arranged or coupled in a similar or different manner than those depicted.

[0071] As illustrated, amplifier circuit 130 includes at least one driver amplifier 134 (DA 134), at least one power amplifier 136 (PA 136), and at least one interstage matching network 140 (ISMN 140). Driver amplifier 134 includes a driver amplifier input and a driver amplifier output. Power amplifier 136 includes a power amplifier input and a power amplifier output. In some cases, driver amplifier 134, interstage matching network 140, and power amplifier 136 are coupled in series between input port 132-1 and output port 132-2 of amplifier circuit 130. As shown, driver amplifier 134 may be coupled closer to input port 132-1 than power amplifier 136, and power amplifier 136 may be coupled closer to output port 132-2 than driver amplifier 134. Therefore, driver amplifier 134 may be coupled between input port 132-1 and power amplifier 136, and power amplifier 136 may be coupled between driver amplifier 134 and output port 132-2.

[0072] Interstage matching network 140 can be coupled between two stages, for example, the first stage corresponding to driver amplifier 134 and the second stage corresponding to power amplifier 136. Therefore, driver amplifier 134 can be coupled between input port 132-1 of amplifier circuit 130 (via driver amplifier input) and interstage matching network 140 (via driver amplifier output). Power amplifier 136 can be coupled between interstage matching network 140 (via power amplifier input) and output port 130-2 of amplifier circuit 132 (via power amplifier output).

[0073] Clamping circuitry 138 may be coupled to interstage matching network 140 to provide power clamping functionality for one or more portions, units, stages, or components of amplifier die 304 (including amplifier circuitry 130). For example, as at least part of power clamper 310, clamping circuitry 138 may provide power protection for downstream components, including power protection for the input of power amplifier 136. Clamping circuitry 138 may be coupled to, for example, wires, traces, or other electrical paths between driver amplifier 134 and power amplifier 136; to nodes between two or more components of interstage matching network 140 (e.g., between a capacitor and an inductor, or between two capacitors); to nodes or electrical paths that propagate signals from the output of driver amplifier 134 to the input of power amplifier 136; some combination thereof; and so on. Reference below. Figures 4 to 6-2 This describes an example of the coupling between clamping circuit 138 and interstage matching network 140.

[0074] As depicted, a signal flow can proceed as signal 330 from input port 132-1 to driver amplifier 134. Signal 330 can be implemented as an input signal, a regulated signal, a pre-amplified signal, a combination thereof, etc. Driver amplifier 134 generates a first amplified signal 332-1 based on amplified signal 330. From driver amplifier 134, the first amplified signal 332-1 can propagate as an intermediate signal 334 (e.g., as an interstage signal 334) through interstage matching network 140. Interstage matching network 140 can couple the intermediate signal 334 to the input of power amplifier 136, which generates a second amplified signal 332-2 based on the intermediate signal 334. The second amplified signal 332-2 output from power amplifier 136 can travel to output port 132-2 of amplifier circuit 130, and then to output matching network 326. Output matching network 326 can couple the second amplified signal 332-2 to the output of amplifier die 304 as amplified signal 328.

[0075] Signals (such as regulated signal 318, signal 330, first amplified signal 332-1, intermediate signal 334, second amplified signal 332-2, or amplified signal 328) may be different signals in terms of average power, frequency, phase, position or location in the circuit, single-ended or differential, or combinations thereof. However, one or more of these signals may constitute the same signal in terms of being transmitted as a signal propagating along the transmission chain toward the antenna, having the same modulation, carrying the same information in the signal, or combinations thereof.

[0076] For clarity, clamping circuit 138 is in Figure 3 The middle is illustrated as being coupled to the left side of the inter-level matching network 140. For example... Figure 3 As depicted, the left side of the interstage matching network 140 is closer to its input than its output. However, the clamping circuit 138 may be coupled to any portion of the interstage matching network 140 or any node of one or more nodes. Such portions or nodes may alternatively be closer to the power amplifier 136 or at least closer to the central portion of the interstage matching network 140, to name just a few examples.

[0077] This article primarily describes the two amplifiers of amplifier circuit 130 from the perspective of driver amplifier 134 and power amplifier 136. However, two or more amplifiers, including at least one amplifier protected by clamping circuit 138, may generally be referred to as the first amplifier and the second amplifier. Such other amplifiers can be or may include any type of amplifier for any purpose, such as low-noise amplifiers, operational amplifiers, amplifiers of any given category, combinations thereof, etc.

[0078] Figure 4This is a circuit diagram 400 illustrating example clamping circuit 138, whose example clamping circuit can be coupled to (e.g., Figure 1 , Figure 3 , Figure 6-1 and Figure 6-2 The amplifier circuit 130 includes an interstage matching network 140 to provide power clamping in either a single-ended or differential implementation. The clamping circuit 138 includes at least two nodes that can be used to couple the clamping circuit 138 to a larger circuit, such as via the interstage matching network 140. These at least two nodes include a first node 402-1 and a second node 402-2. See below for further details. Figure 4 and Figure 5 And further reference Figure 6-1 and Figure 6-2 To describe the example circuit connection.

[0079] In an example implementation, the clamping circuit 138 includes at least one transistor 404 coupled between the first node 402-1 and the second node 402-2. For example, a channel terminal of the transistor 404 (e.g., a first channel terminal) may be coupled to the first node 402-1. Furthermore, another channel terminal of the transistor 404 (e.g., a second channel terminal) may be coupled to the second node 402-2. Control terminals of the transistor 404 may be coupled to other components of the clamping circuit 138, as described below.

[0080] This document describes and depicts several transistors in the accompanying figures, which are incorporated herein by reference. These transistors can be implemented in different ways or as different transistor types. Example transistor types include field-effect transistors (FETs), junction FETs (JFETs), metal-oxide-semiconductor FETs (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), heterojunction bipolar transistors (HBTs), combinations thereof, etc. Manufacturers can fabricate FETs as n-channel or p-channel transistor types and can fabricate BJTs as NPN or PNP transistor types. For example, a heterojunction bipolar transistor (HBT) type can be considered as a form or subset of the bipolar junction transistor (BJT) type. Although some transistors are depicted as HBTs in the figures, one or more of these transistors can be implemented as different transistor types, such as another type of BJT, FET, etc.

[0081] Each transistor may include at least one control terminal and one or more channel terminals. For a FET, the control terminal may correspond to the gate terminal, and the channel terminal may correspond to either the source or drain terminal. For a BJT (including an HBT), the control terminal may correspond to the base terminal, and the channel terminal may correspond to either the emitter or collector terminal. In some circuit configurations, the source terminal of a FET may resemble the emitter terminal of a BJT. Similarly, the drain terminal of a FET may resemble the collector terminal of a BJT.

[0082] Continue to refer to Figure 4 In the illustrated example clamping circuit 138, the collector terminal of transistor 404 is coupled to a first node 402-1. The emitter terminal of transistor 404 is coupled to a second node 402-2. The base terminal of transistor 404 is coupled to other components of clamping circuit 138, as described below. However, transistor 404 may alternatively be coupled to the first node 402-1 and the second node 402-2, or to other illustrated components of clamping circuit 138.

[0083] As illustrated, two or more diodes 406 may be coupled together in series between the first node 402-1 and the base terminal (or gate terminal) of the transistor 404. The number of diodes in these two or more diodes 406 can at least partially set the voltage level that triggers the protection of the clamping circuit 138. For example, the voltage drop across each diode (which may depend on the material or process technology) multiplied by the number of diodes can establish a voltage level to turn on at least one transistor 404 of the clamping circuit 138. Thus, the clamping circuit 138 as described herein is used (e.g., Figure 3 The power clamp 310 can be designed to provide protection at different power level thresholds. This can be achieved, at least in part, by deploying different numbers of trigger diodes for two or more diodes 406 to establish a clamping voltage implemented by the clamping circuit 138.

[0084] At least one resistor 408 is shown coupled between the base terminal (or gate terminal) of transistor 404 and the second node 402-2. Generally, resistor 408 may be coupled between two terminals of transistor 404. More specifically, resistor 408 may be coupled between the control terminal and the channel terminal of transistor 404. For example, if transistor 404 is implemented as a bipolar junction transistor (BJT) (e.g., a heterojunction bipolar transistor (HBT)), the control terminal of transistor 404 may include the base terminal of the BJT, and the channel terminal of transistor 404 may include the emitter terminal of the BJT. The resistor may include two terminals: a first terminal and a second terminal. Figure 4As illustrated, the first terminal of resistor 408 can be coupled to the first terminal of transistor 404, and the second terminal of resistor 408 can be coupled to the second terminal of transistor 404.

[0085] The resistance value of resistor 408 can also at least partially set the trigger voltage at which clamping protection begins. Generally, as the resistance value of resistor 408 increases, the trigger voltage for initiating clamping decreases. Furthermore, in response to the clamping circuit 138 being deployed in a differential implementation, resistor 408 can promote greater clamping balance between the positive and negative circuit components of the differential amplifier circuit, and between positive and negative differential signaling. References will follow... Figure 5 This describes an example differential implementation of the clamping circuit 138.

[0086] In addition to at least one transistor 404, Figure 4 Components depicted as part of clamping circuit 138 may be omitted from clamping circuit 138, or may be coupled to at least one transistor 404 while being separate from clamping circuit 138. Furthermore, certain components are depicted or described as having a specific number, such as singular, plural, multiple, one, two, three, etc. However, each of these components may have a different number. By way of example only, the series-connected diode string 406 can alternatively be implemented using a single diode 406.

[0087] In the example implementation, the clamping circuit 138 may be coupled or incorporated into the amplifier circuit 130 in various ways, and coupled to different nodes of the circuit, as described herein. To couple the clamping circuit 138 to the circuit, a first node 402-1 may be connected to a node of the amplifier circuit 130, such as to a first circuit node 430-1, and a second node 402-2 may be connected to another node of the circuit, such as to a second circuit node 430-2.

[0088] To clamp the signal from the positive swing angle, the first node 402-1 can be coupled to a node of the inter-stage matching network. The inter-stage matching network node can be (e.g., Figure 1 , Figure 3 , Figure 6-1 and Figure 6-2 This is part of the inter-stage matching network 140. The second node 402-2 can be coupled to the power distribution node. The power distribution node can be implemented using, for example, a power supply voltage node (e.g., a power rail) or a ground node (e.g., a ground plane). For example, utilizing an NPN BJT (or n-channel FET) for transistor 404, the power distribution node can be implemented using a ground node (…). Figure 4(Not shown in the figure) to achieve this. However, the two example power distribution node types (e.g., supply voltage node and ground node) can be interchanged, such as if the transistor or diode doping is swapped (e.g., PNP becomes NPN or p-channel becomes n-channel), or if the direction of coupling of the depicted components is swapped relative to the voltage potential.

[0089] Therefore, to prevent positive signal sway, the first circuit node 430-1 may correspond to a node of the interstage matching network 140, or otherwise coupled between the output of the driver amplifier 134 and the input of the power amplifier 136. The second circuit node 430-2 may correspond to a power distribution node of the circuit. However, the clamping circuit 138 can also be used to prevent reverse signal sway, for example, by “flipping” the coupling of the first node 402-1 and the second node 402-2 to the amplifier circuit 130. For this purpose, the first node 402-1 of the clamping circuit 138 may be coupled to a power distribution node, and the second node 402-2 may be coupled to an interstage matching network node. Therefore, to clamp the signal from the reverse sway angle, the first circuit node 430-1 may correspond to a power distribution node of the circuit. The second circuit node 430-2 may correspond to a node of the interstage matching network 140, or otherwise coupled between the output of the driver amplifier 134 and the input of the power amplifier 136.

[0090] Therefore, clamping circuit 138 can be used to prevent positive and negative signal sway by being appropriately coupled to a circuit (such as amplifier circuit 130). In a single-ended environment, the nodes of the interstage matching network 140 to which a pair of clamping circuits are coupled can be the same node. However, each clamping circuit 138 can be coupled to the same node via a different node 402 to enable the prevention of both positive and negative signal sway. One clamping circuit is coupled via a first node 402-1, and the other clamping circuit is coupled via a second node 402-2. Similarly, the power distribution node to which a pair of clamping circuits are coupled can also be the same power distribution node, and the corresponding node 402 to which each clamping circuit 138 is coupled to the same power distribution node of each clamping circuit is also different.

[0091] In the example operation, the positive oscillation clamping circuit configuration can clamp at the inter-stage matching network node (e.g., Figure 3 The intermediate signal 334 is configured to have a "positive" voltage level. A reverse-swing clamping circuit can clamp the intermediate signal 334 at the inter-stage matching network node. Therefore, the input of downstream amplifiers (such as power amplifier 136) can be protected from voltage or current levels that could damage components (such as one or more portions of the transistors in power amplifier 136). The clamping circuit can respond at least in part to a plurality of diodes 406 of the respective clamping circuit 138 (e.g., as shown in the image). Figure 4 The number of diodes (shown) affects the voltage level, clamping the forward or reverse voltage swing at the nodes of the interstage matching network. Alternatively, the clamping circuit 138 may increase the clamping action on the voltage at the nodes of the interstage matching network as the voltage at the nodes increases.

[0092] The following text is for reference only. Figure 6-1 and Figure 6-2 Example instances of amplifier circuits are described, including an example inter-stage matching network 140 with multiple nodes to which clamping circuit 138 can be coupled. However, reference is made below. Figure 5 To describe the differential configuration of clamping circuit 138.

[0093] Figure 5 This is a circuit diagram 500 illustrating an example differential clamping circuit 138D, which can be coupled to an interstage matching network 140 of an amplifier circuit 130 to provide power clamping. In an example specific implementation, the differential clamping circuit 138D may include (e.g., Figure 4 The differential clamping circuit 138D has positive and negative versions. As shown in the figure, the differential clamping circuit 138D includes a positive transistor 404P and a negative transistor 404M. The differential clamping circuit 138D also includes a positive diode group 406P and a negative diode group 406M. The differential clamping circuit 138D also includes a positive resistor 408P and a negative resistor 408M.

[0094] like Figure 5 As illustrated, the differential clamping circuit 138D can be coupled to the central node Int_P, such as (e.g., Figure 1 , Figure 3 , Figure 6-1 and Figure 6-2 (of) inter-level matching network 140 positive nodes, or (for example, Figure 6-1 and Figure 6-2 The positive inter-level matching network node 430P of the differential inter-level matching network 140. Similarly, the differential clamping circuit 138D can be coupled to the negative intermediate node Int_M, such as the negative node of the inter-level matching network 140, or (e.g., Figure 6-1 and 6-2 The negative interstage matching network node 430M of the differential interstage matching network 140. Positive transistor 404P and negative transistor 404M can be cross-coupled to each other, as indicated at 502. For example, the emitter (or source) terminal of positive transistor 404P can be coupled to the collector (or drain) terminal of negative transistor 404M at the negative interstage matching network node 430M. Similarly, the emitter (or source) terminal of negative transistor 404M can be coupled to the collector (or drain) terminal of positive transistor 404P at the positive interstage matching network node 430P.

[0095] The emitter (or source) terminals of the positive transistor 404P and the negative transistor 404M do not need to be coupled to a ground node or another power distribution node, as indicated at 504. Similarly, the positive resistor 408P and the negative resistor 408M do not need to be coupled to a ground node or another power distribution node, as also indicated at 504. Instead, the emitter (or source) terminals of the positive transistor 404P and the negative transistor 404M are coupled to the positive resistor 408P and the negative resistor 408M, respectively, as indicated at 504.

[0096] In some cases, each resistor 408 is coupled between two terminals of the corresponding transistor 404. For example, each corresponding resistor 408 may be coupled between the channel terminal (e.g., the emitter terminal of a BJT (or the source terminal of a FET)) and the control terminal (e.g., the base terminal of an HBT (or the gate terminal of a FET)) of the corresponding transistor 404. By way of example only, a positive resistor 408P is coupled between the base and emitter terminals of a positive transistor 404P, and a negative resistor 408M is coupled between the base and emitter terminals of a negative transistor 404M. Each resistor 408 may be coupled via a node between the control terminal of the corresponding transistor 404 and two or more diodes 406 connected in series.

[0097] Figure 5 The differential configuration at least partially enables each "half" of the differential clamping circuit 138D to have a usable trigger voltage that differs by 0.6V (e.g., for GaAs technology). For example, in an example circuit design with three diodes in diode group 406, the "left half" of the differential clamping circuit 138D (such as...) Figure 5 The circuit (described) triggers at 2.4 volts, but the "right half" of the differential clamp circuit 138D triggers at 3.0 volts. By appropriately designing the two halves of the differential clamp circuit 138D with two trigger voltages differing by 0.6 volts, a 0.3 volt step can be achieved for power clamp triggering. This allows for finer control of the trigger voltage to meet given design specifications. Implementation as follows... Figure 4 The two clamping circuits 138 shown (e.g., for positive and reverse signal oscillation) can similarly reduce the trigger voltage step granularity.

[0098] Figure 6-1 and Figure 6-2 Figure 600 illustrates an example differential amplifier circuit 130, which includes a driver amplifier 134, an interstage matching network 140, and a power amplifier 136. The example differential amplifier circuit 130 also includes multiple example nodes (e.g., Figure 5The differential clamping circuit 138D can be coupled at these multiple nodes to provide power clamping. For example, at block diagram 600 (… Figure 6-1 As indicated in the upper left corner, Figure 6-1 The "left" part of the circuit is depicted as circuit 600-1, and Figure 6-2 The "right" part of the circuit is depicted as circuit 600-2. The circled letters "A", "B", "C" and "D" indicate... Figure 6-1 and Figure 6-2 The four electrical connection points between the circuit sections. Figure 6-1 and Figure 6-2 Together, an integrated circuit die 602 is depicted, which includes multiple inputs or outputs that can be implemented using pins, pads, or other electrical contact nodes to couple signaling to or from the integrated circuit die 602. Figure 6-1 and Figure 6-2 Examples of such inputs and outputs described include Rf.in, Int_P, Int_M, Rf.out_P, RF.out_M, Vcc1, Vcc2, etc.

[0099] In an example implementation, the driver amplifier 134 may be single-ended and generate a single-ended first amplified signal 332-1. An interstage matching network 140 converts the single-ended amplified signal 332-1, or the single-ended portion of the intermediate signal 334, into a differential intermediate signal 334. The differential intermediate signal 334 includes a positive intermediate signal 334P and a negative intermediate signal 334M. The interstage matching network 140 may include a balun (e.g., a converter) to perform the signal conversion from single-ended to differential.

[0100] In the specific implementation example, the inter-level matching network 140 can be implemented using a T-network. For example, across... Figure 6-1 and Figure 6-2 As shown, the T-network of the interstage matching network 140 includes a first capacitor coupled between the driver amplifier output and the power amplifier input, and a second capacitor also coupled between the driver amplifier output and the power amplifier input. The first and second capacitors are coupled in series along a combined electrical and electromagnetic path between the output of the driver amplifier 134 and the input of the power amplifier 136. The T-network also includes at least one inductor coupled between the interstage matching network node 430 and a power distribution node (such as a ground node). Using a converter, one inductor can be electrically coupled to the ground node, and the other inductor can be electrically coupled to the interstage matching network node 430. The two inductors are electromagnetically coupled together. Therefore, the driver amplifier 134 can be electromagnetically coupled to the power amplifier 136.

[0101] Interstage matching network node 430 may, for example, be coupled between the first capacitor and the second capacitor. Therefore, in the illustrated example, the interstage matching network 140 is implemented using a T-network, which includes two capacitors for each of the positive and negative signal paths along the "top" of the T-network and at least one inductor along a "column" of the T-network. Assuming the intermediate signal 334 is single-ended on the "left" side of the converter, then... Figure 6-1 The capacitors in a portion of the interstage matching network 140 shown can be operated as capacitors for both the positive and negative signal paths.

[0102] At least one inductor of the converter can be used as part of a T-network for interstage matching. However, the T-network can be implemented differently. For example, two capacitors can be swapped with two inductors along the “top” of the T-network, and inductors can be swapped with capacitors along a “column” of the T-network. Furthermore, more or different components can be incorporated into the T-network. For example, the converter or other balun can be separate from the components of the T-network. Additionally or alternatively, the interstage matching network 140 can be implemented using a Pi network. The Pi network can include any number of components, including reactive components such as inductors and capacitors. The interstage matching network 140 can also be implemented using different networks, more than one network, different components, active or passive components, different couplings between components, some combination thereof, etc.

[0103] The positive intermediate signal 334P is coupled to the input of the positive transistor T_P of the differential power amplifier 136. The positive transistor T_P amplifies the positive intermediate signal 334P to generate the positive second amplified signal 332-2P. The positive second amplified signal 332-2P can be forwarded to the positive output (Rf.out_P). The negative intermediate signal 334M is coupled to the input of the negative transistor T_M of the differential power amplifier 136. The negative transistor T_M amplifies the negative intermediate signal 334M to generate the negative second amplified signal 332-2M. The negative second amplified signal 332-2M can be forwarded to the negative output (Rf.out_M).

[0104] like Figure 6-1 and Figure 6-2 As shown, connection points “B” and “C” can correspond to positive inter-level nodes (Int_P) and negative inter-level nodes (Int_M), respectively. These nodes can correspond to positive nodes or positive inter-level matching network node 430P of inter-level matching network 140, and negative nodes or negative inter-level matching network node 430M of inter-level matching network 140, respectively. In some aspects, each of the positive inter-level matching network node 430P and the negative inter-level matching network node 430M can be coupled to (using opposite first nodes 402-1 and second nodes 402-2) Figure 4The two clamping circuits 138 are identical. Therefore, an inter-stage matching network node 430 can be coupled to ( Figure 4 The first clamping circuit 138 is configured in a positive swing configuration, and another interstage matching network node 430 can be coupled to the second clamping circuit 138 in a reverse swing configuration. Thus, each clamping circuit 138 can be coupled to the positive interstage matching network node 430P and the negative interstage matching network node 430M, but via the opposite nodes in the first node 402-1 and the second node 402-2.

[0105] In the specific implementation of the example, Figure 5 The differential clamping circuit 138D is coupled to the positive-to-negative inter-stage matching network node 430P and the negative-to-negative inter-stage matching network node 430M via... Figure 6-1 and Figure 6-2 The differential amplifier circuit 130. Regarding the positive inter-stage matching network node 430P, the positive "half" of the differential clamping circuit 138D (e.g., as...) Figure 5 The depicted left side with positive transistor 404P prevents positive signal oscillation at the positive center node Int_P. On the other hand, the negative "half" of the differential clamping circuit 138D (e.g., as...) Figure 5 The right side of the diagram with negative transistor 404M prevents the reverse signal from wobbling at the positive center node Int_P.

[0106] Regarding the negative half of the differential clamping circuit 138D (e.g., the negative half of the inter-negative matching network node 430M),... Figure 5 The depicted right side with negative transistor 404M prevents positive signal sway at the negative intermediate node Int_M. On the other hand, the positive "half" of the differential clamping circuit 138D (e.g., as...) Figure 5 The depiction of the left side with the positive transistor 404P prevents the reverse signal from wobbling at the negative intermediate node Int_M. In these ways, it is possible to use... Figure 5 The differential clamping circuit 138D is used to prevent positive and negative signal oscillations at the two differential intermediate nodes Int_P and Int_M. This differential clamping circuit can use signals from... Figure 4 It is formed by two clamping circuits 138.

[0107] Also refer to Figure 5In some cases, the positive inter-stage matching network node 430P may be coupled to the collector terminal of the positive transistor 404P (or the drain terminal of the FET). The positive inter-stage matching network node 430P may also be coupled to the emitter terminal of the negative transistor 404M (or the source terminal of the FET). Conversely, the negative inter-stage matching network node 430M may be coupled to the collector terminal of the negative transistor 404M (or the drain terminal of the FET). The negative inter-stage matching network node 430M may also be coupled to the emitter terminal of the positive transistor 404P (or the source terminal of the FET).

[0108] Although the differential clamping circuit 138D is shown as coupled to Figure 6-1 and Figure 6-2 The example describes a specific node of the differential interstage matching network 140, but each differential clamping circuit 138D can be coupled to other nodes of the differential amplifier circuit 130, including different nodes coupled to the differential interstage matching network 140. Furthermore, as described above, the interstage matching network 140 can be implemented using a Pi network, with different components, with more or fewer components, etc.

[0109] Figure 7 This is a flowchart illustrating an example process 700 for clamping power relative to amplifier circuitry via clamping circuitry or for operating a power clamp coupled to an interstage matching network. Process 700 includes four blocks 702-708 specifying operations that can be performed for the method. However, the operations are not necessarily limited to the order shown in the figures or described herein, as these operations can be implemented in an alternative order or in a fully or partially overlapping manner. Furthermore, more, fewer, and / or different operations can be implemented to perform the corresponding or alternative processes.

[0110] In the specific implementation of the example, the operation represented by the illustrated box for each process can be performed by an electronic device (such as...). Figure 1 The electronic device 102 or its wireless interface device 120 performs the operation. More specifically, the operation of the corresponding process can be performed by an integrated circuit die (e.g., Figure 3 Amplifier die 304 or Figure 6-1 and Figure 6-2 The bare die 602) or the amplifier circuit 130 including a first amplifier and a second amplifier performs the operation. Although some descriptions herein focus specifically on amplifiers and power clamps operating on single-ended or differential signaling, the principles described with respect to one (e.g., corresponding to devices, circuits, techniques, and processes) may also apply to the other. In other words, the principles described are generally applicable to both differential and single-ended signaling environments.

[0111] At block 702, a driver amplifier is used to amplify the signal to generate a first amplified signal. For example, amplifier circuit 130 may use driver amplifier 134 to amplify signal 330 to generate a first amplified signal 332-1. For example, the transistor in the common-emitter configuration (or common-source configuration of a FET) of driver amplifier 134 may amplify the signal to be transmitted.

[0112] At block 704, the first amplified signal propagates through an interstage matching network. For example, amplifier circuit 130 can propagate the first amplified signal 332-1 through interstage matching network 140. In some cases, interstage matching network 140 may include a T-network or a Pi-network and may operate for single-ended or differential signaling. Furthermore, interstage matching network 140 may include a balun (such as a converter) to convert the single-ended first amplified signal 332-1 into a differential signal.

[0113] At block 706, in conjunction with propagation, a transistor and a resistor coupled to the transistor are used to clamp the first amplified signal to generate an intermediate signal. For example, amplifier circuit 130 may clamp the first amplified signal 332-1 in conjunction with signal propagation through interstage matching network 140 to generate an intermediate signal 334 using at least one transistor 404 and at least one resistor 408 coupled to transistor 404. For this purpose, one or more of a forward-switch configuration of clamping circuit 138, a reverse-switch configuration of clamping circuit 138, or a differential clamping circuit 138D may clamp the intermediate signal 334 to generate a clamped signal with reduced voltage or current. Resistor 408 may be coupled between two terminals of transistor 404, such as between a control terminal and a channel terminal.

[0114] At block 708, a power amplifier is used to amplify the intermediate signal to generate a second amplified signal. For example, amplifier circuit 130 may use power amplifier 136 to amplify intermediate signal 334 to generate second amplified signal 332-2. Therefore, if the power of intermediate signal 334 is clamped by at least one clamping circuit 138, power amplifier 136 may safely amplify the clamped intermediate signal 334 with at least one transistor T without damaging at least one transistor T. In some cases, at least one transistor T may include a positive transistor T_P and a negative transistor T_M for differential signals.

[0115] In an example, clamping circuit 130 may further enhance the clamping balance between the positive and negative voltage swings of differential signaling, for example, based on the routing current through the positive resistor 408P and the negative resistor 408M of differential clamping circuit 138D.

[0116] In some aspects, transistor 404 may include a positive transistor 404P, and resistor 408 may include a positive resistor 408P. In at least some of these cases, the positive resistor 408P may be coupled between the control terminal of the positive transistor 404P and the first channel terminal of the positive transistor 404P (e.g., the emitter terminal of the HBT). Clamping of block 706 may include clamping the first amplified signal 332-1 using a negative transistor 404M and a negative resistor 408M. Here, the negative resistor 408M may be coupled between the control terminal of the negative transistor 404M and the second channel terminal of the positive transistor 404P (e.g., the collector terminal of the HBT).

[0117] Specific implementation examples

[0118] This section describes some aspects of example implementations and / or example configurations relating to the apparatus and / or processes presented above.

[0119] Example aspect 1: An apparatus comprising:

[0120] An amplifier circuit, comprising an input port and an output port, includes:

[0121] A driver amplifier, the driver amplifier including a driver amplifier output, the driver amplifier being coupled between the input port and the output port;

[0122] A power amplifier, the power amplifier including a power amplifier input, the power amplifier being coupled between the driver amplifier output and the output port;

[0123] Interstage matching network, the interstage matching network being coupled between the driver amplifier output and the power amplifier input; and

[0124] A clamping circuit, coupled to the interstage matching network via a node coupled between the driver amplifier output and the power amplifier input, the clamping circuit including a transistor and a resistor coupled to the transistor.

[0125] Example aspect 2: The apparatus according to example aspect 1, wherein the resistor is coupled between the two terminals of the transistor.

[0126] Example aspect 3: The apparatus according to example aspect 2, wherein:

[0127] The transistor's two terminals include a control terminal and a channel terminal; and

[0128] The resistor is coupled between the control terminal of the transistor and the channel terminal of the transistor.

[0129] Example aspect 4: The apparatus according to example aspect 3, wherein:

[0130] The transistor includes a bipolar junction transistor (BJT);

[0131] The control terminal of the transistor includes the base terminal of the bipolar junction transistor; and

[0132] The channel terminal of the transistor includes the emitter terminal of the bipolar junction transistor.

[0133] Example aspect 5: The apparatus according to any one of the foregoing example aspects further includes:

[0134] An integrated circuit die, the integrated circuit die including the amplifier circuit,

[0135] The clamping circuit is configured to provide power clamping for a signal propagating from the driver amplifier output to the power amplifier input.

[0136] Example aspect 6: The apparatus according to any one of the foregoing example aspects, wherein the node is coupled between the channel terminal of the transistor of the driver amplifier and the control terminal of the transistor of the power amplifier.

[0137] Example aspect 7: The apparatus according to any one of the foregoing example aspects, wherein the inter-level matching network includes a T-network.

[0138] Example aspect 8: The apparatus according to example aspect 7, wherein the T network comprises:

[0139] A first capacitor is coupled between the output of the driver amplifier and the input of the power amplifier.

[0140] A second capacitor is coupled between the driver amplifier output and the power amplifier input; and

[0141] At least one inductor is coupled between an interstage matching network node and a power distribution node, the interstage matching network node being coupled between a first capacitor and a second capacitor.

[0142] Example aspect 9: The apparatus according to example aspect 8, wherein:

[0143] The at least one inductor comprises two or more inductors electromagnetically coupled together to form at least one converter; and

[0144] The node coupled between the driver amplifier output and the power amplifier input corresponds to the interstage matching network node.

[0145] Example aspect 10: The apparatus according to any one of the foregoing example aspects, wherein the inter-level matching network includes a Pi network.

[0146] Example aspect 11: The apparatus according to any one of the foregoing example aspects, wherein:

[0147] The transistor includes a control terminal and a channel terminal;

[0148] The clamping circuit includes one or more diodes coupled between the control terminal and the channel terminal of the transistor; and

[0149] The channel terminal of the transistor is coupled to the node.

[0150] Example aspect 12: The apparatus according to example aspect 11, wherein:

[0151] The one or more diodes include a plurality of diodes coupled in series between the control terminal and the channel terminal of the transistor; and

[0152] The clamping circuit is configured to clamp the voltage at the node in response to a voltage level based at least in part on the number of diodes among the plurality of diodes.

[0153] Example aspect 13: The apparatus according to example aspect 12, wherein the clamping circuit is configured to increase the clamping action on the voltage at the node as the voltage at the node increases.

[0154] Example aspect 14: The apparatus according to any one of the foregoing example aspects, wherein:

[0155] The transistor includes a positive transistor of the clamping circuit, and the resistor includes a positive resistor of the clamping circuit.

[0156] The positive transistor is coupled between the positive node of the inter-stage matching network and the negative node of the inter-stage matching network.

[0157] The clamping circuit includes a negative transistor and a negative resistor coupled to the negative transistor; and

[0158] The negative transistor is coupled between the positive node and the negative node of the inter-level matching network.

[0159] Example aspect 15: The apparatus according to example aspect 14, wherein:

[0160] The first channel terminal of the positive transistor is coupled to the positive node of the interstage matching network, and the second channel terminal of the positive transistor is coupled to the negative node of the interstage matching network; and

[0161] The first channel terminal of the negative transistor is coupled to the negative node of the interstage matching network, and the second channel terminal of the negative transistor is coupled to the positive node of the interstage matching network.

[0162] Example aspect 16: The apparatus according to example aspect 15, wherein:

[0163] The first channel terminal of the positive transistor includes the collector terminal of the positive transistor, and the second channel terminal of the positive transistor includes the emitter terminal of the positive transistor; and

[0164] The first channel terminal of the negative transistor includes the collector terminal of the negative transistor, and the second channel terminal of the negative transistor includes the emitter terminal of the negative transistor.

[0165] Example aspect 17: The apparatus according to example aspect 15 or 16, wherein:

[0166] The positive resistor is coupled between the control terminal of the positive transistor and the negative node of the interstage matching network; and

[0167] The negative resistor is coupled between the control terminal of the negative transistor and the positive node of the interstage matching network.

[0168] Example aspect 18: The apparatus according to any one of the foregoing example aspects further includes:

[0169] A wireless interface device, the wireless interface device including the amplifier circuit.

[0170] Example aspect 19: The apparatus according to example aspect 18 further includes:

[0171] Display screen; and

[0172] One or more processors, operatively coupled to at least a portion of the display screen and the wireless interface device, the one or more processors being configured to present one or more graphic images on the display screen based on one or more wireless signals transmitted using the amplifier circuitry of the wireless interface device.

[0173] Example aspect 20: An apparatus comprising:

[0174] An amplifier circuit, comprising an input port and an output port, includes:

[0175] A driver amplifier, the driver amplifier including a driver amplifier input and a driver amplifier output, the driver amplifier input being coupled to the input port;

[0176] A power amplifier, the power amplifier including a power amplifier input and a power amplifier output, the power amplifier output being coupled to the output port;

[0177] Interstage matching network, the interstage matching network being coupled between the driver amplifier output and the power amplifier input; and

[0178] A component for clamping the power of a signal flowing through the interstage matching network between the driver amplifier and the power amplifier using a transistor and a resistor coupled to the transistor.

[0179] Example aspect 21: The apparatus according to example aspect 20, wherein:

[0180] The power amplifier includes a differential power amplifier, and the signal includes a differential signal; and

[0181] The amplifier circuit also includes components for balancing the positive and negative clamping of the differential signal.

[0182] Example aspect 22: A method comprising:

[0183] Use a driver amplifier to amplify the signal to generate the first amplified signal;

[0184] The first amplified signal is propagated through an inter-stage matching network;

[0185] In conjunction with the propagation, a transistor and a resistor coupled to the transistor are used to clamp the first amplified signal to generate an intermediate signal; and

[0186] A power amplifier is used to amplify the intermediate signal to generate a second amplified signal.

[0187] Example aspect 23: The method according to example aspect 22, wherein the clamping includes:

[0188] Increase the balance of clamping between the positive and negative voltage swings of differential signaling.

[0189] Example aspect 24: The method described according to example aspect 22 or 23, wherein:

[0190] The transistor includes a positive transistor, and the resistor includes a positive resistor;

[0191] The positive resistor is coupled between the control terminal of the positive transistor and the first channel terminal of the positive transistor; and

[0192] The clamping includes using a negative transistor and a negative resistor to clamp the first amplified signal, the negative resistor being coupled between the control terminal of the negative transistor and the second channel terminal of the positive transistor.

[0193] in conclusion

[0194] As used herein, the term "coupling" refers to a relationship between two or more components that are operatively communicable to each other to implement a feature or capability described herein. For example, coupling can be achieved using physical lines such as metallic traces or wires, or electromagnetic coupling such as transducers. Coupling can include direct coupling or indirect coupling. Direct coupling refers to connecting discrete circuit elements via the same node without intermediate components. Indirect coupling refers to connecting discrete circuit elements via one or more other devices or other discrete circuit elements, including two or more different nodes.

[0195] The term "port" (e.g., including "first port" or "amplifier port") at least indicates a point of electrical connection at or near the input or output of a component or between two or more components (e.g., active or passive circuit elements or parts). Although a port may sometimes be visually depicted as a single point (or circle) in a drawing, a port may represent an interconnecting portion of a physical circuit or network having at least approximately the same voltage potential at or along that portion. In other words, a single-ended port may represent at least one point (e.g., a node) among a plurality of points along a conductive medium (e.g., a wire or trace) present between the electrically connected components. In some cases, "port" may represent at least one node that represents or corresponds to an input or output of a component (such as a matching network, amplifier circuit, or a portion thereof). Similarly, "terminal" or "node" may represent one or more points having at least approximately the same voltage potential, where "terminal" is relative to the input or output of a component.

[0196] The terms “first,” “second,” “third,” and other numerically related indicators are used herein to identify or distinguish items that are similar or analogous to each other in a given context (such as a particular embodiment, a single diagram, a given component, or a claim). Thus, a first item in one context may differ from a first item in another. For example, an item identified as a “first signal” in one context may be identified as a “second signal” in another. Similarly, a “first port” or “first transistor” in one claim may be referred to as a “second port” or a “third transistor” in different claims, respectively.

[0197] Unless the context otherwise requires, the use of the word “or” in this document is to be interpreted as “inclusive or” or the use of a term that allows the inclusion or application of one or more items linked by the word “or” (e.g., the phrase “A or B” can be interpreted as allowing only “A”, only “B”, or both “A” and “B”). Additionally, as used herein, the phrase “at least one of” in a list of items refers to any combination of those items (including single members). For example, “at least one of a, b, or c” can cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). Furthermore, the items represented in the figures and the terms discussed herein can indicate one or more items or terms, and therefore, the singular or plural forms of these items and terms can be referred to interchangeably in this written description.

[0198] Although specific implementations of the interstage clamping circuit have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, specific features and methods are disclosed as exemplary implementations for implementing the interstage clamping circuit.

Claims

1. An apparatus, the apparatus comprising: An amplifier circuit, comprising an input port and an output port, includes: A driver amplifier, the driver amplifier including a driver amplifier output, the driver amplifier being coupled between the input port and the output port; A power amplifier, the power amplifier including a power amplifier input, the power amplifier being coupled between the driver amplifier output and the output port; Interstage matching network, the interstage matching network being coupled between the driver amplifier output and the power amplifier input; and A clamping circuit, coupled to the interstage matching network via a node coupled between the driver amplifier output and the power amplifier input, the clamping circuit including a transistor and a resistor coupled to the transistor.

2. The apparatus of claim 1, wherein the transistor is coupled between two terminals of the transistor.

3. The apparatus according to claim 2, wherein: The transistor's two terminals include a control terminal and a channel terminal; and The resistor is coupled between the control terminal of the transistor and the channel terminal of the transistor.

4. The apparatus according to claim 3, wherein: The transistor includes a bipolar junction transistor (BJT); The control terminal of the transistor includes the base terminal of the bipolar junction transistor; and The channel terminal of the transistor includes the emitter terminal of the bipolar junction transistor.

5. The apparatus according to claim 1, further comprising: An integrated circuit die, the integrated circuit die including the amplifier circuit, The clamping circuit is configured to provide power clamping for a signal propagating from the driver amplifier output to the power amplifier input.

6. The apparatus of claim 1, wherein the node is coupled between the channel terminal of the transistor of the driver amplifier and the control terminal of the transistor of the power amplifier.

7. The apparatus of claim 1, wherein the inter-level matching network comprises a T-network.

8. The apparatus of claim 7, wherein the T network comprises: A first capacitor is coupled between the output of the driver amplifier and the input of the power amplifier. A second capacitor is coupled between the output of the driver amplifier and the input of the power amplifier. and At least one inductor is coupled between an interstage matching network node and a power distribution node, the interstage matching network node being coupled between a first capacitor and a second capacitor.

9. The apparatus according to claim 8, wherein: The at least one inductor comprises two or more inductors electromagnetically coupled together to form at least one converter; and The node coupled between the driver amplifier output and the power amplifier input corresponds to the interstage matching network node.

10. The apparatus of claim 1, wherein the inter-level matching network comprises a Pi network.

11. The apparatus according to claim 1, wherein: The transistor includes a control terminal and a channel terminal; The clamping circuit includes one or more diodes coupled between the control terminal and the channel terminal of the transistor; and The channel terminal of the transistor is coupled to the node.

12. The apparatus according to claim 11, wherein: The one or more diodes include a plurality of diodes coupled in series between the control terminal and the channel terminal of the transistor; and The clamping circuit is configured to clamp the voltage at the node in response to a voltage level based at least in part on the number of diodes among the plurality of diodes.

13. The apparatus of claim 12, wherein the clamping circuit is configured to increase the clamping action on the voltage at the node as the voltage at the node increases.

14. The apparatus according to claim 1, wherein: The transistor includes a positive transistor of the clamping circuit, and the resistor includes a positive resistor of the clamping circuit. The positive transistor is coupled between the positive node of the inter-stage matching network and the negative node of the inter-stage matching network. The clamping circuit includes a negative transistor and a negative resistor coupled to the negative transistor; and The negative transistor is coupled between the positive node and the negative node of the inter-level matching network.

15. The apparatus according to claim 14, wherein: The first channel terminal of the positive transistor is coupled to the positive node of the interstage matching network, and the second channel terminal of the positive transistor is coupled to the negative node of the interstage matching network; and The first channel terminal of the negative transistor is coupled to the negative node of the interstage matching network, and the second channel terminal of the negative transistor is coupled to the positive node of the interstage matching network.

16. The apparatus according to claim 15, wherein: The first channel terminal of the positive transistor includes the collector terminal of the positive transistor, and the second channel terminal of the positive transistor includes the emitter terminal of the positive transistor; and The first channel terminal of the negative transistor includes the collector terminal of the negative transistor, and the second channel terminal of the negative transistor includes the emitter terminal of the negative transistor.

17. The apparatus according to claim 15, wherein: The positive resistor is coupled between the control terminal of the positive transistor and the negative node of the interstage matching network; and The negative resistor is coupled between the control terminal of the negative transistor and the positive node of the interstage matching network.

18. The apparatus according to claim 1, further comprising: A wireless interface device, the wireless interface device including the amplifier circuit.

19. The apparatus of claim 18, further comprising: Display screen; and One or more processors, operatively coupled to at least a portion of the display screen and the wireless interface device, the one or more processors being configured to present one or more graphic images on the display screen based on one or more wireless signals transmitted using the amplifier circuitry of the wireless interface device.

20. An apparatus comprising: An amplifier circuit, comprising an input port and an output port, includes: A driver amplifier, the driver amplifier including a driver amplifier input and a driver amplifier output, the driver amplifier input being coupled to the input port; A power amplifier, the power amplifier including a power amplifier input and a power amplifier output, the power amplifier output being coupled to the output port; Interstage matching network, the interstage matching network being coupled between the driver amplifier output and the power amplifier input; and A component for clamping the power of a signal flowing through the interstage matching network between the driver amplifier and the power amplifier using a transistor and a resistor coupled to the transistor.

21. The apparatus according to claim 20, wherein: The power amplifier includes a differential power amplifier, and the signal includes a differential signal; and The amplifier circuit also includes components for balancing the positive and negative clamping of the differential signal.

22. A method, the method comprising: Use a driver amplifier to amplify the signal to generate the first amplified signal; The first amplified signal is propagated through an inter-stage matching network; In conjunction with the propagation, a transistor and a resistor coupled to the transistor are used to clamp the first amplified signal to generate an intermediate signal; as well as A power amplifier is used to amplify the intermediate signal to generate a second amplified signal.

23. The method of claim 22, wherein the clamping comprises: Increase the balance of clamping between the positive and negative voltage swings of differential signaling.

24. The method of claim 22, wherein: The transistor includes a positive transistor, and the resistor includes a positive resistor; The positive resistor is coupled between the control terminal of the positive transistor and the first channel terminal of the positive transistor; and The clamping includes using a negative transistor and a negative resistor to clamp the first amplified signal, the negative resistor being coupled between the control terminal of the negative transistor and the second channel terminal of the positive transistor.

Images